projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| af69fb3a KK |
1 | /* |
| 2 | * see notice in hfc_multi.c | |
| 3 | */ | |
| 4 | ||
| af69fb3a KK |
5 | #define DEBUG_HFCMULTI_FIFO 0x00010000 |
| 6 | #define DEBUG_HFCMULTI_CRC 0x00020000 | |
| 7 | #define DEBUG_HFCMULTI_INIT 0x00040000 | |
| 8 | #define DEBUG_HFCMULTI_PLXSD 0x00080000 | |
| 9 | #define DEBUG_HFCMULTI_MODE 0x00100000 | |
| 10 | #define DEBUG_HFCMULTI_MSG 0x00200000 | |
| 11 | #define DEBUG_HFCMULTI_STATE 0x00400000 | |
| 8dd2f36f | 12 | #define DEBUG_HFCMULTI_FILL 0x00800000 |
| af69fb3a KK |
13 | #define DEBUG_HFCMULTI_SYNC 0x01000000 |
| 14 | #define DEBUG_HFCMULTI_DTMF 0x02000000 | |
| 15 | #define DEBUG_HFCMULTI_LOCK 0x80000000 | |
| 16 | ||
| 17 | #define PCI_ENA_REGIO 0x01 | |
| 18 | #define PCI_ENA_MEMIO 0x02 | |
| 19 | ||
| 20 | /* | |
| 21 | * NOTE: some registers are assigned multiple times due to different modes | |
| 22 | * also registers are assigned differen for HFC-4s/8s and HFC-E1 | |
| 23 | */ | |
| 24 | ||
| 25 | /* | |
| 26 | #define MAX_FRAME_SIZE 2048 | |
| 27 | */ | |
| 28 | ||
| 29 | struct hfc_chan { | |
| 30 | struct dchannel *dch; /* link if channel is a D-channel */ | |
| 31 | struct bchannel *bch; /* link if channel is a B-channel */ | |
| 32 | int port; /* the interface port this */ | |
| 33 | /* channel is associated with */ | |
| 34 | int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */ | |
| 35 | int los, ais, slip_tx, slip_rx, rdi; /* current alarms */ | |
| 36 | int jitter; | |
| 37 | u_long cfg; /* port configuration */ | |
| 38 | int sync; /* sync state (used by E1) */ | |
| 39 | u_int protocol; /* current protocol */ | |
| 40 | int slot_tx; /* current pcm slot */ | |
| 41 | int bank_tx; /* current pcm bank */ | |
| 42 | int slot_rx; | |
| 43 | int bank_rx; | |
| 44 | int conf; /* conference setting of TX slot */ | |
| 45 | int txpending; /* if there is currently data in */ | |
| 46 | /* the FIFO 0=no, 1=yes, 2=splloop */ | |
| 47 | int rx_off; /* set to turn fifo receive off */ | |
| 48 | int coeff_count; /* curren coeff block */ | |
| 49 | s32 *coeff; /* memory pointer to 8 coeff blocks */ | |
| 50 | }; | |
| 51 | ||
| 52 | ||
| 53 | struct hfcm_hw { | |
| 54 | u_char r_ctrl; | |
| 55 | u_char r_irq_ctrl; | |
| 56 | u_char r_cirm; | |
| 57 | u_char r_ram_sz; | |
| 58 | u_char r_pcm_md0; | |
| 59 | u_char r_irqmsk_misc; | |
| 60 | u_char r_dtmf; | |
| 61 | u_char r_st_sync; | |
| 62 | u_char r_sci_msk; | |
| 63 | u_char r_tx0, r_tx1; | |
| 64 | u_char a_st_ctrl0[8]; | |
| 65 | timer_t timer; | |
| 66 | }; | |
| 67 | ||
| 68 | ||
| 69 | /* for each stack these flags are used (cfg) */ | |
| 70 | #define HFC_CFG_NONCAP_TX 1 /* S/T TX interface has less capacity */ | |
| 71 | #define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */ | |
| 72 | #define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */ | |
| 73 | #define HFC_CFG_OPTICAL 4 /* the E1 interface is optical */ | |
| 74 | #define HFC_CFG_REPORT_LOS 5 /* the card should report loss of signal */ | |
| 75 | #define HFC_CFG_REPORT_AIS 6 /* the card should report alarm ind. sign. */ | |
| 76 | #define HFC_CFG_REPORT_SLIP 7 /* the card should report bit slips */ | |
| 77 | #define HFC_CFG_REPORT_RDI 8 /* the card should report remote alarm */ | |
| 78 | #define HFC_CFG_DTMF 9 /* enable DTMF-detection */ | |
| 79 | #define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */ | |
| 80 | /* use double frame instead. */ | |
| 81 | ||
| 82 | #define HFC_CHIP_EXRAM_128 0 /* external ram 128k */ | |
| 83 | #define HFC_CHIP_EXRAM_512 1 /* external ram 256k */ | |
| 84 | #define HFC_CHIP_REVISION0 2 /* old fifo handling */ | |
| 85 | #define HFC_CHIP_PCM_SLAVE 3 /* PCM is slave */ | |
| 86 | #define HFC_CHIP_PCM_MASTER 4 /* PCM is master */ | |
| 87 | #define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */ | |
| 88 | #define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */ | |
| 89 | #define HFC_CHIP_ULAW 7 /* ULAW mode */ | |
| 90 | #define HFC_CHIP_CLOCK2 8 /* double clock mode */ | |
| 91 | #define HFC_CHIP_E1CLOCK_GET 9 /* always get clock from E1 interface */ | |
| 92 | #define HFC_CHIP_E1CLOCK_PUT 10 /* always put clock from E1 interface */ | |
| 93 | #define HFC_CHIP_WATCHDOG 11 /* whether we should send signals */ | |
| 94 | /* to the watchdog */ | |
| 95 | #define HFC_CHIP_B410P 12 /* whether we have a b410p with echocan in */ | |
| 96 | /* hw */ | |
| 97 | #define HFC_CHIP_PLXSD 13 /* whether we have a Speech-Design PLX */ | |
| 98 | ||
| 99 | #define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */ | |
| 100 | #define HFC_IO_MODE_REGIO 0x01 /* PCI io access */ | |
| 101 | #define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */ | |
| 102 | ||
| 103 | /* table entry in the PCI devices list */ | |
| 104 | struct hm_map { | |
| 105 | char *vendor_name; | |
| 106 | char *card_name; | |
| 107 | int type; | |
| 108 | int ports; | |
| 109 | int clock2; | |
| 110 | int leds; | |
| 111 | int opticalsupport; | |
| 112 | int dip_type; | |
| 113 | int io_mode; | |
| 114 | }; | |
| 115 | ||
| 116 | struct hfc_multi { | |
| 117 | struct list_head list; | |
| 118 | struct hm_map *mtyp; | |
| 119 | int id; | |
| 120 | int pcm; /* id of pcm bus */ | |
| 121 | int type; | |
| 122 | int ports; | |
| 123 | ||
| 124 | u_int irq; /* irq used by card */ | |
| 125 | u_int irqcnt; | |
| 126 | struct pci_dev *pci_dev; | |
| 127 | int io_mode; /* selects mode */ | |
| 128 | #ifdef HFC_REGISTER_DEBUG | |
| 129 | void (*HFC_outb)(struct hfc_multi *hc, u_char reg, | |
| 130 | u_char val, const char *function, int line); | |
| 131 | void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg, | |
| 132 | u_char val, const char *function, int line); | |
| 133 | u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg, | |
| 134 | const char *function, int line); | |
| 135 | u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg, | |
| 136 | const char *function, int line); | |
| 137 | u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg, | |
| 138 | const char *function, int line); | |
| 139 | u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg, | |
| 140 | const char *function, int line); | |
| 141 | void (*HFC_wait)(struct hfc_multi *hc, | |
| 142 | const char *function, int line); | |
| 143 | void (*HFC_wait_nodebug)(struct hfc_multi *hc, | |
| 144 | const char *function, int line); | |
| 145 | #else | |
| 146 | void (*HFC_outb)(struct hfc_multi *hc, u_char reg, | |
| 147 | u_char val); | |
| 148 | void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg, | |
| 149 | u_char val); | |
| 150 | u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg); | |
| 151 | u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg); | |
| 152 | u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg); | |
| 153 | u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg); | |
| 154 | void (*HFC_wait)(struct hfc_multi *hc); | |
| 155 | void (*HFC_wait_nodebug)(struct hfc_multi *hc); | |
| 156 | #endif | |
| 157 | void (*read_fifo)(struct hfc_multi *hc, u_char *data, | |
| 158 | int len); | |
| 159 | void (*write_fifo)(struct hfc_multi *hc, u_char *data, | |
| 160 | int len); | |
| 161 | u_long pci_origmembase, plx_origmembase, dsp_origmembase; | |
| c31655fc HE |
162 | void __iomem *pci_membase; /* PCI memory */ |
| 163 | void __iomem *plx_membase; /* PLX memory */ | |
| af69fb3a KK |
164 | u_char *dsp_membase; /* DSP on PLX */ |
| 165 | u_long pci_iobase; /* PCI IO */ | |
| 166 | struct hfcm_hw hw; /* remember data of write-only-registers */ | |
| 167 | ||
| 168 | u_long chip; /* chip configuration */ | |
| 169 | int masterclk; /* port that provides master clock -1=off */ | |
| 8dd2f36f AE |
170 | unsigned char silence;/* silence byte */ |
| 171 | unsigned char silence_data[128];/* silence block */ | |
| af69fb3a KK |
172 | int dtmf; /* flag that dtmf is currently in process */ |
| 173 | int Flen; /* F-buffer size */ | |
| 174 | int Zlen; /* Z-buffer size (must be int for calculation)*/ | |
| 175 | int max_trans; /* maximum transparent fifo fill */ | |
| 176 | int Zmin; /* Z-buffer offset */ | |
| 177 | int DTMFbase; /* base address of DTMF coefficients */ | |
| 178 | ||
| 179 | u_int slots; /* number of PCM slots */ | |
| 180 | u_int leds; /* type of leds */ | |
| 181 | u_int ledcount; /* used to animate leds */ | |
| 182 | u_long ledstate; /* save last state of leds */ | |
| 183 | int opticalsupport; /* has the e1 board */ | |
| 184 | /* an optical Interface */ | |
| 185 | int dslot; /* channel # of d-channel (E1) default 16 */ | |
| 186 | ||
| 187 | u_long wdcount; /* every 500 ms we need to */ | |
| 188 | /* send the watchdog a signal */ | |
| 189 | u_char wdbyte; /* watchdog toggle byte */ | |
| 190 | u_int activity[8]; /* if there is any action on this */ | |
| 191 | /* port (will be cleared after */ | |
| 192 | /* showing led-states) */ | |
| 193 | int e1_state; /* keep track of last state */ | |
| 194 | int e1_getclock; /* if sync is retrieved from interface */ | |
| 195 | int syncronized; /* keep track of existing sync interface */ | |
| 196 | int e1_resync; /* resync jobs */ | |
| 197 | ||
| 198 | spinlock_t lock; /* the lock */ | |
| 199 | ||
| 3bd69ad1 AE |
200 | struct mISDNclock *iclock; /* isdn clock support */ |
| 201 | int iclock_on; | |
| 202 | ||
| af69fb3a KK |
203 | /* |
| 204 | * the channel index is counted from 0, regardless where the channel | |
| 205 | * is located on the hfc-channel. | |
| 206 | * the bch->channel is equvalent to the hfc-channel | |
| 207 | */ | |
| 208 | struct hfc_chan chan[32]; | |
| 209 | u_char created[8]; /* what port is created */ | |
| 210 | signed char slot_owner[256]; /* owner channel of slot */ | |
| 211 | }; | |
| 212 | ||
| 213 | /* PLX GPIOs */ | |
| 214 | #define PLX_GPIO4_DIR_BIT 13 | |
| 215 | #define PLX_GPIO4_BIT 14 | |
| 216 | #define PLX_GPIO5_DIR_BIT 16 | |
| 217 | #define PLX_GPIO5_BIT 17 | |
| 218 | #define PLX_GPIO6_DIR_BIT 19 | |
| 219 | #define PLX_GPIO6_BIT 20 | |
| 220 | #define PLX_GPIO7_DIR_BIT 22 | |
| 221 | #define PLX_GPIO7_BIT 23 | |
| 222 | #define PLX_GPIO8_DIR_BIT 25 | |
| 223 | #define PLX_GPIO8_BIT 26 | |
| 224 | ||
| 225 | #define PLX_GPIO4 (1 << PLX_GPIO4_BIT) | |
| 226 | #define PLX_GPIO5 (1 << PLX_GPIO5_BIT) | |
| 227 | #define PLX_GPIO6 (1 << PLX_GPIO6_BIT) | |
| 228 | #define PLX_GPIO7 (1 << PLX_GPIO7_BIT) | |
| 229 | #define PLX_GPIO8 (1 << PLX_GPIO8_BIT) | |
| 230 | ||
| 231 | #define PLX_GPIO4_DIR (1 << PLX_GPIO4_DIR_BIT) | |
| 232 | #define PLX_GPIO5_DIR (1 << PLX_GPIO5_DIR_BIT) | |
| 233 | #define PLX_GPIO6_DIR (1 << PLX_GPIO6_DIR_BIT) | |
| 234 | #define PLX_GPIO7_DIR (1 << PLX_GPIO7_DIR_BIT) | |
| 235 | #define PLX_GPIO8_DIR (1 << PLX_GPIO8_DIR_BIT) | |
| 236 | ||
| 237 | #define PLX_TERM_ON PLX_GPIO7 | |
| 238 | #define PLX_SLAVE_EN_N PLX_GPIO5 | |
| 239 | #define PLX_MASTER_EN PLX_GPIO6 | |
| 240 | #define PLX_SYNC_O_EN PLX_GPIO4 | |
| 241 | #define PLX_DSP_RES_N PLX_GPIO8 | |
| 242 | /* GPIO4..8 Enable & Set to OUT, SLAVE_EN_N = 1 */ | |
| 243 | #define PLX_GPIOC_INIT (PLX_GPIO4_DIR | PLX_GPIO5_DIR | PLX_GPIO6_DIR \ | |
| 244 | | PLX_GPIO7_DIR | PLX_GPIO8_DIR | PLX_SLAVE_EN_N) | |
| 245 | ||
| 246 | /* PLX Interrupt Control/STATUS */ | |
| 247 | #define PLX_INTCSR_LINTI1_ENABLE 0x01 | |
| 248 | #define PLX_INTCSR_LINTI1_STATUS 0x04 | |
| 249 | #define PLX_INTCSR_LINTI2_ENABLE 0x08 | |
| 250 | #define PLX_INTCSR_LINTI2_STATUS 0x20 | |
| 251 | #define PLX_INTCSR_PCIINT_ENABLE 0x40 | |
| 252 | ||
| 253 | /* PLX Registers */ | |
| 254 | #define PLX_INTCSR 0x4c | |
| 255 | #define PLX_CNTRL 0x50 | |
| 256 | #define PLX_GPIOC 0x54 | |
| 257 | ||
| 258 | ||
| 259 | /* | |
| 260 | * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1 | |
| 261 | */ | |
| 262 | ||
| 263 | /* write only registers */ | |
| 264 | #define R_CIRM 0x00 | |
| 265 | #define R_CTRL 0x01 | |
| 266 | #define R_BRG_PCM_CFG 0x02 | |
| 267 | #define R_RAM_ADDR0 0x08 | |
| 268 | #define R_RAM_ADDR1 0x09 | |
| 269 | #define R_RAM_ADDR2 0x0A | |
| 270 | #define R_FIRST_FIFO 0x0B | |
| 271 | #define R_RAM_SZ 0x0C | |
| 272 | #define R_FIFO_MD 0x0D | |
| 273 | #define R_INC_RES_FIFO 0x0E | |
| 274 | #define R_FSM_IDX 0x0F | |
| 275 | #define R_FIFO 0x0F | |
| 276 | #define R_SLOT 0x10 | |
| 277 | #define R_IRQMSK_MISC 0x11 | |
| 278 | #define R_SCI_MSK 0x12 | |
| 279 | #define R_IRQ_CTRL 0x13 | |
| 280 | #define R_PCM_MD0 0x14 | |
| 281 | #define R_PCM_MD1 0x15 | |
| 282 | #define R_PCM_MD2 0x15 | |
| 283 | #define R_SH0H 0x15 | |
| 284 | #define R_SH1H 0x15 | |
| 285 | #define R_SH0L 0x15 | |
| 286 | #define R_SH1L 0x15 | |
| 287 | #define R_SL_SEL0 0x15 | |
| 288 | #define R_SL_SEL1 0x15 | |
| 289 | #define R_SL_SEL2 0x15 | |
| 290 | #define R_SL_SEL3 0x15 | |
| 291 | #define R_SL_SEL4 0x15 | |
| 292 | #define R_SL_SEL5 0x15 | |
| 293 | #define R_SL_SEL6 0x15 | |
| 294 | #define R_SL_SEL7 0x15 | |
| 295 | #define R_ST_SEL 0x16 | |
| 296 | #define R_ST_SYNC 0x17 | |
| 297 | #define R_CONF_EN 0x18 | |
| 298 | #define R_TI_WD 0x1A | |
| 299 | #define R_BERT_WD_MD 0x1B | |
| 300 | #define R_DTMF 0x1C | |
| 301 | #define R_DTMF_N 0x1D | |
| 302 | #define R_E1_WR_STA 0x20 | |
| 303 | #define R_E1_RD_STA 0x20 | |
| 304 | #define R_LOS0 0x22 | |
| 305 | #define R_LOS1 0x23 | |
| 306 | #define R_RX0 0x24 | |
| 307 | #define R_RX_FR0 0x25 | |
| 308 | #define R_RX_FR1 0x26 | |
| 309 | #define R_TX0 0x28 | |
| 310 | #define R_TX1 0x29 | |
| 311 | #define R_TX_FR0 0x2C | |
| 312 | ||
| 313 | #define R_TX_FR1 0x2D | |
| 314 | #define R_TX_FR2 0x2E | |
| 315 | #define R_JATT_ATT 0x2F /* undocumented */ | |
| 316 | #define A_ST_RD_STATE 0x30 | |
| 317 | #define A_ST_WR_STATE 0x30 | |
| 318 | #define R_RX_OFF 0x30 | |
| 319 | #define A_ST_CTRL0 0x31 | |
| 320 | #define R_SYNC_OUT 0x31 | |
| 321 | #define A_ST_CTRL1 0x32 | |
| 322 | #define A_ST_CTRL2 0x33 | |
| 323 | #define A_ST_SQ_WR 0x34 | |
| 324 | #define R_TX_OFF 0x34 | |
| 325 | #define R_SYNC_CTRL 0x35 | |
| 326 | #define A_ST_CLK_DLY 0x37 | |
| 327 | #define R_PWM0 0x38 | |
| 328 | #define R_PWM1 0x39 | |
| 329 | #define A_ST_B1_TX 0x3C | |
| 330 | #define A_ST_B2_TX 0x3D | |
| 331 | #define A_ST_D_TX 0x3E | |
| 332 | #define R_GPIO_OUT0 0x40 | |
| 333 | #define R_GPIO_OUT1 0x41 | |
| 334 | #define R_GPIO_EN0 0x42 | |
| 335 | #define R_GPIO_EN1 0x43 | |
| 336 | #define R_GPIO_SEL 0x44 | |
| 337 | #define R_BRG_CTRL 0x45 | |
| 338 | #define R_PWM_MD 0x46 | |
| 339 | #define R_BRG_MD 0x47 | |
| 340 | #define R_BRG_TIM0 0x48 | |
| 341 | #define R_BRG_TIM1 0x49 | |
| 342 | #define R_BRG_TIM2 0x4A | |
| 343 | #define R_BRG_TIM3 0x4B | |
| 344 | #define R_BRG_TIM_SEL01 0x4C | |
| 345 | #define R_BRG_TIM_SEL23 0x4D | |
| 346 | #define R_BRG_TIM_SEL45 0x4E | |
| 347 | #define R_BRG_TIM_SEL67 0x4F | |
| 348 | #define A_SL_CFG 0xD0 | |
| 349 | #define A_CONF 0xD1 | |
| 350 | #define A_CH_MSK 0xF4 | |
| 351 | #define A_CON_HDLC 0xFA | |
| 352 | #define A_SUBCH_CFG 0xFB | |
| 353 | #define A_CHANNEL 0xFC | |
| 354 | #define A_FIFO_SEQ 0xFD | |
| 355 | #define A_IRQ_MSK 0xFF | |
| 356 | ||
| 357 | /* read only registers */ | |
| 358 | #define A_Z12 0x04 | |
| 359 | #define A_Z1L 0x04 | |
| 360 | #define A_Z1 0x04 | |
| 361 | #define A_Z1H 0x05 | |
| 362 | #define A_Z2L 0x06 | |
| 363 | #define A_Z2 0x06 | |
| 364 | #define A_Z2H 0x07 | |
| 365 | #define A_F1 0x0C | |
| 366 | #define A_F12 0x0C | |
| 367 | #define A_F2 0x0D | |
| 368 | #define R_IRQ_OVIEW 0x10 | |
| 369 | #define R_IRQ_MISC 0x11 | |
| 370 | #define R_IRQ_STATECH 0x12 | |
| 371 | #define R_CONF_OFLOW 0x14 | |
| 372 | #define R_RAM_USE 0x15 | |
| 373 | #define R_CHIP_ID 0x16 | |
| 374 | #define R_BERT_STA 0x17 | |
| 375 | #define R_F0_CNTL 0x18 | |
| 376 | #define R_F0_CNTH 0x19 | |
| 377 | #define R_BERT_EC 0x1A | |
| 378 | #define R_BERT_ECL 0x1A | |
| 379 | #define R_BERT_ECH 0x1B | |
| 380 | #define R_STATUS 0x1C | |
| 381 | #define R_CHIP_RV 0x1F | |
| 382 | #define R_STATE 0x20 | |
| 383 | #define R_SYNC_STA 0x24 | |
| 384 | #define R_RX_SL0_0 0x25 | |
| 385 | #define R_RX_SL0_1 0x26 | |
| 386 | #define R_RX_SL0_2 0x27 | |
| 387 | #define R_JATT_DIR 0x2b /* undocumented */ | |
| 388 | #define R_SLIP 0x2c | |
| 389 | #define A_ST_RD_STA 0x30 | |
| 390 | #define R_FAS_EC 0x30 | |
| 391 | #define R_FAS_ECL 0x30 | |
| 392 | #define R_FAS_ECH 0x31 | |
| 393 | #define R_VIO_EC 0x32 | |
| 394 | #define R_VIO_ECL 0x32 | |
| 395 | #define R_VIO_ECH 0x33 | |
| 396 | #define A_ST_SQ_RD 0x34 | |
| 397 | #define R_CRC_EC 0x34 | |
| 398 | #define R_CRC_ECL 0x34 | |
| 399 | #define R_CRC_ECH 0x35 | |
| 400 | #define R_E_EC 0x36 | |
| 401 | #define R_E_ECL 0x36 | |
| 402 | #define R_E_ECH 0x37 | |
| 403 | #define R_SA6_SA13_EC 0x38 | |
| 404 | #define R_SA6_SA13_ECL 0x38 | |
| 405 | #define R_SA6_SA13_ECH 0x39 | |
| 406 | #define R_SA6_SA23_EC 0x3A | |
| 407 | #define R_SA6_SA23_ECL 0x3A | |
| 408 | #define R_SA6_SA23_ECH 0x3B | |
| 409 | #define A_ST_B1_RX 0x3C | |
| 410 | #define A_ST_B2_RX 0x3D | |
| 411 | #define A_ST_D_RX 0x3E | |
| 412 | #define A_ST_E_RX 0x3F | |
| 413 | #define R_GPIO_IN0 0x40 | |
| 414 | #define R_GPIO_IN1 0x41 | |
| 415 | #define R_GPI_IN0 0x44 | |
| 416 | #define R_GPI_IN1 0x45 | |
| 417 | #define R_GPI_IN2 0x46 | |
| 418 | #define R_GPI_IN3 0x47 | |
| 419 | #define R_INT_DATA 0x88 | |
| 420 | #define R_IRQ_FIFO_BL0 0xC8 | |
| 421 | #define R_IRQ_FIFO_BL1 0xC9 | |
| 422 | #define R_IRQ_FIFO_BL2 0xCA | |
| 423 | #define R_IRQ_FIFO_BL3 0xCB | |
| 424 | #define R_IRQ_FIFO_BL4 0xCC | |
| 425 | #define R_IRQ_FIFO_BL5 0xCD | |
| 426 | #define R_IRQ_FIFO_BL6 0xCE | |
| 427 | #define R_IRQ_FIFO_BL7 0xCF | |
| 428 | ||
| 429 | /* read and write registers */ | |
| 430 | #define A_FIFO_DATA0 0x80 | |
| 431 | #define A_FIFO_DATA1 0x80 | |
| 432 | #define A_FIFO_DATA2 0x80 | |
| 433 | #define A_FIFO_DATA0_NOINC 0x84 | |
| 434 | #define A_FIFO_DATA1_NOINC 0x84 | |
| 435 | #define A_FIFO_DATA2_NOINC 0x84 | |
| 436 | #define R_RAM_DATA 0xC0 | |
| 437 | ||
| 438 | ||
| 439 | /* | |
| 440 | * BIT SETTING FOR HFC-4S/8S AND HFC-E1 | |
| 441 | */ | |
| 442 | ||
| 443 | /* chapter 2: universal bus interface */ | |
| 444 | /* R_CIRM */ | |
| 445 | #define V_IRQ_SEL 0x01 | |
| 446 | #define V_SRES 0x08 | |
| 447 | #define V_HFCRES 0x10 | |
| 448 | #define V_PCMRES 0x20 | |
| 449 | #define V_STRES 0x40 | |
| 450 | #define V_ETRES 0x40 | |
| 451 | #define V_RLD_EPR 0x80 | |
| 452 | /* R_CTRL */ | |
| 453 | #define V_FIFO_LPRIO 0x02 | |
| 454 | #define V_SLOW_RD 0x04 | |
| 455 | #define V_EXT_RAM 0x08 | |
| 456 | #define V_CLK_OFF 0x20 | |
| 457 | #define V_ST_CLK 0x40 | |
| 458 | /* R_RAM_ADDR0 */ | |
| 459 | #define V_RAM_ADDR2 0x01 | |
| 460 | #define V_ADDR_RES 0x40 | |
| 461 | #define V_ADDR_INC 0x80 | |
| 462 | /* R_RAM_SZ */ | |
| 463 | #define V_RAM_SZ 0x01 | |
| 464 | #define V_PWM0_16KHZ 0x10 | |
| 465 | #define V_PWM1_16KHZ 0x20 | |
| 466 | #define V_FZ_MD 0x80 | |
| 467 | /* R_CHIP_ID */ | |
| 468 | #define V_PNP_IRQ 0x01 | |
| 469 | #define V_CHIP_ID 0x10 | |
| 470 | ||
| 471 | /* chapter 3: data flow */ | |
| 472 | /* R_FIRST_FIFO */ | |
| 473 | #define V_FIRST_FIRO_DIR 0x01 | |
| 474 | #define V_FIRST_FIFO_NUM 0x02 | |
| 475 | /* R_FIFO_MD */ | |
| 476 | #define V_FIFO_MD 0x01 | |
| 477 | #define V_CSM_MD 0x04 | |
| 478 | #define V_FSM_MD 0x08 | |
| 479 | #define V_FIFO_SZ 0x10 | |
| 480 | /* R_FIFO */ | |
| 481 | #define V_FIFO_DIR 0x01 | |
| 482 | #define V_FIFO_NUM 0x02 | |
| 483 | #define V_REV 0x80 | |
| 484 | /* R_SLOT */ | |
| 485 | #define V_SL_DIR 0x01 | |
| 486 | #define V_SL_NUM 0x02 | |
| 487 | /* A_SL_CFG */ | |
| 488 | #define V_CH_DIR 0x01 | |
| 489 | #define V_CH_SEL 0x02 | |
| 490 | #define V_ROUTING 0x40 | |
| 491 | /* A_CON_HDLC */ | |
| 492 | #define V_IFF 0x01 | |
| 493 | #define V_HDLC_TRP 0x02 | |
| 494 | #define V_TRP_IRQ 0x04 | |
| 495 | #define V_DATA_FLOW 0x20 | |
| 496 | /* A_SUBCH_CFG */ | |
| 497 | #define V_BIT_CNT 0x01 | |
| 498 | #define V_START_BIT 0x08 | |
| 499 | #define V_LOOP_FIFO 0x40 | |
| 500 | #define V_INV_DATA 0x80 | |
| 501 | /* A_CHANNEL */ | |
| 502 | #define V_CH_DIR0 0x01 | |
| 503 | #define V_CH_NUM0 0x02 | |
| 504 | /* A_FIFO_SEQ */ | |
| 505 | #define V_NEXT_FIFO_DIR 0x01 | |
| 506 | #define V_NEXT_FIFO_NUM 0x02 | |
| 507 | #define V_SEQ_END 0x40 | |
| 508 | ||
| 509 | /* chapter 4: FIFO handling and HDLC controller */ | |
| 510 | /* R_INC_RES_FIFO */ | |
| 511 | #define V_INC_F 0x01 | |
| 512 | #define V_RES_F 0x02 | |
| 513 | #define V_RES_LOST 0x04 | |
| 514 | ||
| 515 | /* chapter 5: S/T interface */ | |
| 516 | /* R_SCI_MSK */ | |
| 517 | #define V_SCI_MSK_ST0 0x01 | |
| 518 | #define V_SCI_MSK_ST1 0x02 | |
| 519 | #define V_SCI_MSK_ST2 0x04 | |
| 520 | #define V_SCI_MSK_ST3 0x08 | |
| 521 | #define V_SCI_MSK_ST4 0x10 | |
| 522 | #define V_SCI_MSK_ST5 0x20 | |
| 523 | #define V_SCI_MSK_ST6 0x40 | |
| 524 | #define V_SCI_MSK_ST7 0x80 | |
| 525 | /* R_ST_SEL */ | |
| 526 | #define V_ST_SEL 0x01 | |
| 527 | #define V_MULT_ST 0x08 | |
| 528 | /* R_ST_SYNC */ | |
| 529 | #define V_SYNC_SEL 0x01 | |
| 530 | #define V_AUTO_SYNC 0x08 | |
| 531 | /* A_ST_WR_STA */ | |
| 532 | #define V_ST_SET_STA 0x01 | |
| 533 | #define V_ST_LD_STA 0x10 | |
| 534 | #define V_ST_ACT 0x20 | |
| 535 | #define V_SET_G2_G3 0x80 | |
| 536 | /* A_ST_CTRL0 */ | |
| 537 | #define V_B1_EN 0x01 | |
| 538 | #define V_B2_EN 0x02 | |
| 539 | #define V_ST_MD 0x04 | |
| 540 | #define V_D_PRIO 0x08 | |
| 541 | #define V_SQ_EN 0x10 | |
| 542 | #define V_96KHZ 0x20 | |
| 543 | #define V_TX_LI 0x40 | |
| 544 | #define V_ST_STOP 0x80 | |
| 545 | /* A_ST_CTRL1 */ | |
| 546 | #define V_G2_G3_EN 0x01 | |
| 547 | #define V_D_HI 0x04 | |
| 548 | #define V_E_IGNO 0x08 | |
| 549 | #define V_E_LO 0x10 | |
| 550 | #define V_B12_SWAP 0x80 | |
| 551 | /* A_ST_CTRL2 */ | |
| 552 | #define V_B1_RX_EN 0x01 | |
| 553 | #define V_B2_RX_EN 0x02 | |
| 554 | #define V_ST_TRIS 0x40 | |
| 555 | /* A_ST_CLK_DLY */ | |
| 556 | #define V_ST_CK_DLY 0x01 | |
| 557 | #define V_ST_SMPL 0x10 | |
| 558 | /* A_ST_D_TX */ | |
| 559 | #define V_ST_D_TX 0x40 | |
| 560 | /* R_IRQ_STATECH */ | |
| 561 | #define V_SCI_ST0 0x01 | |
| 562 | #define V_SCI_ST1 0x02 | |
| 563 | #define V_SCI_ST2 0x04 | |
| 564 | #define V_SCI_ST3 0x08 | |
| 565 | #define V_SCI_ST4 0x10 | |
| 566 | #define V_SCI_ST5 0x20 | |
| 567 | #define V_SCI_ST6 0x40 | |
| 568 | #define V_SCI_ST7 0x80 | |
| 569 | /* A_ST_RD_STA */ | |
| 570 | #define V_ST_STA 0x01 | |
| 571 | #define V_FR_SYNC_ST 0x10 | |
| 572 | #define V_TI2_EXP 0x20 | |
| 573 | #define V_INFO0 0x40 | |
| 574 | #define V_G2_G3 0x80 | |
| 575 | /* A_ST_SQ_RD */ | |
| 576 | #define V_ST_SQ 0x01 | |
| 577 | #define V_MF_RX_RDY 0x10 | |
| 578 | #define V_MF_TX_RDY 0x80 | |
| 579 | /* A_ST_D_RX */ | |
| 580 | #define V_ST_D_RX 0x40 | |
| 581 | /* A_ST_E_RX */ | |
| 582 | #define V_ST_E_RX 0x40 | |
| 583 | ||
| 584 | /* chapter 5: E1 interface */ | |
| 585 | /* R_E1_WR_STA */ | |
| 586 | /* R_E1_RD_STA */ | |
| 587 | #define V_E1_SET_STA 0x01 | |
| 588 | #define V_E1_LD_STA 0x10 | |
| 589 | /* R_RX0 */ | |
| 590 | #define V_RX_CODE 0x01 | |
| 591 | #define V_RX_FBAUD 0x04 | |
| 592 | #define V_RX_CMI 0x08 | |
| 593 | #define V_RX_INV_CMI 0x10 | |
| 594 | #define V_RX_INV_CLK 0x20 | |
| 595 | #define V_RX_INV_DATA 0x40 | |
| 596 | #define V_AIS_ITU 0x80 | |
| 597 | /* R_RX_FR0 */ | |
| 598 | #define V_NO_INSYNC 0x01 | |
| 599 | #define V_AUTO_RESYNC 0x02 | |
| 600 | #define V_AUTO_RECO 0x04 | |
| 601 | #define V_SWORD_COND 0x08 | |
| 602 | #define V_SYNC_LOSS 0x10 | |
| 603 | #define V_XCRC_SYNC 0x20 | |
| 604 | #define V_MF_RESYNC 0x40 | |
| 605 | #define V_RESYNC 0x80 | |
| 606 | /* R_RX_FR1 */ | |
| 607 | #define V_RX_MF 0x01 | |
| 608 | #define V_RX_MF_SYNC 0x02 | |
| 609 | #define V_RX_SL0_RAM 0x04 | |
| 610 | #define V_ERR_SIM 0x20 | |
| 611 | #define V_RES_NMF 0x40 | |
| 612 | /* R_TX0 */ | |
| 613 | #define V_TX_CODE 0x01 | |
| 614 | #define V_TX_FBAUD 0x04 | |
| 615 | #define V_TX_CMI_CODE 0x08 | |
| 616 | #define V_TX_INV_CMI_CODE 0x10 | |
| 617 | #define V_TX_INV_CLK 0x20 | |
| 618 | #define V_TX_INV_DATA 0x40 | |
| 619 | #define V_OUT_EN 0x80 | |
| 620 | /* R_TX1 */ | |
| 621 | #define V_INV_CLK 0x01 | |
| 622 | #define V_EXCHG_DATA_LI 0x02 | |
| 623 | #define V_AIS_OUT 0x04 | |
| 624 | #define V_ATX 0x20 | |
| 625 | #define V_NTRI 0x40 | |
| 626 | #define V_AUTO_ERR_RES 0x80 | |
| 627 | /* R_TX_FR0 */ | |
| 628 | #define V_TRP_FAS 0x01 | |
| 629 | #define V_TRP_NFAS 0x02 | |
| 630 | #define V_TRP_RAL 0x04 | |
| 631 | #define V_TRP_SA 0x08 | |
| 632 | /* R_TX_FR1 */ | |
| 633 | #define V_TX_FAS 0x01 | |
| 634 | #define V_TX_NFAS 0x02 | |
| 635 | #define V_TX_RAL 0x04 | |
| 636 | #define V_TX_SA 0x08 | |
| 637 | /* R_TX_FR2 */ | |
| 638 | #define V_TX_MF 0x01 | |
| 639 | #define V_TRP_SL0 0x02 | |
| 640 | #define V_TX_SL0_RAM 0x04 | |
| 641 | #define V_TX_E 0x10 | |
| 642 | #define V_NEG_E 0x20 | |
| 643 | #define V_XS12_ON 0x40 | |
| 644 | #define V_XS15_ON 0x80 | |
| 645 | /* R_RX_OFF */ | |
| 646 | #define V_RX_SZ 0x01 | |
| 647 | #define V_RX_INIT 0x04 | |
| 648 | /* R_SYNC_OUT */ | |
| 649 | #define V_SYNC_E1_RX 0x01 | |
| 650 | #define V_IPATS0 0x20 | |
| 651 | #define V_IPATS1 0x40 | |
| 652 | #define V_IPATS2 0x80 | |
| 653 | /* R_TX_OFF */ | |
| 654 | #define V_TX_SZ 0x01 | |
| 655 | #define V_TX_INIT 0x04 | |
| 656 | /* R_SYNC_CTRL */ | |
| 657 | #define V_EXT_CLK_SYNC 0x01 | |
| 658 | #define V_SYNC_OFFS 0x02 | |
| 659 | #define V_PCM_SYNC 0x04 | |
| 660 | #define V_NEG_CLK 0x08 | |
| 661 | #define V_HCLK 0x10 | |
| 662 | /* | |
| 663 | #define V_JATT_AUTO_DEL 0x20 | |
| 664 | #define V_JATT_AUTO 0x40 | |
| 665 | */ | |
| 666 | #define V_JATT_OFF 0x80 | |
| 667 | /* R_STATE */ | |
| 668 | #define V_E1_STA 0x01 | |
| 669 | #define V_ALT_FR_RX 0x40 | |
| 670 | #define V_ALT_FR_TX 0x80 | |
| 671 | /* R_SYNC_STA */ | |
| 672 | #define V_RX_STA 0x01 | |
| 673 | #define V_FR_SYNC_E1 0x04 | |
| 674 | #define V_SIG_LOS 0x08 | |
| 675 | #define V_MFA_STA 0x10 | |
| 676 | #define V_AIS 0x40 | |
| 677 | #define V_NO_MF_SYNC 0x80 | |
| 678 | /* R_RX_SL0_0 */ | |
| 679 | #define V_SI_FAS 0x01 | |
| 680 | #define V_SI_NFAS 0x02 | |
| 681 | #define V_A 0x04 | |
| 682 | #define V_CRC_OK 0x08 | |
| 683 | #define V_TX_E1 0x10 | |
| 684 | #define V_TX_E2 0x20 | |
| 685 | #define V_RX_E1 0x40 | |
| 686 | #define V_RX_E2 0x80 | |
| 687 | /* R_SLIP */ | |
| 688 | #define V_SLIP_RX 0x01 | |
| 689 | #define V_FOSLIP_RX 0x08 | |
| 690 | #define V_SLIP_TX 0x10 | |
| 691 | #define V_FOSLIP_TX 0x80 | |
| 692 | ||
| 693 | /* chapter 6: PCM interface */ | |
| 694 | /* R_PCM_MD0 */ | |
| 695 | #define V_PCM_MD 0x01 | |
| 696 | #define V_C4_POL 0x02 | |
| 697 | #define V_F0_NEG 0x04 | |
| 698 | #define V_F0_LEN 0x08 | |
| 699 | #define V_PCM_ADDR 0x10 | |
| 700 | /* R_SL_SEL0 */ | |
| 701 | #define V_SL_SEL0 0x01 | |
| 702 | #define V_SH_SEL0 0x80 | |
| 703 | /* R_SL_SEL1 */ | |
| 704 | #define V_SL_SEL1 0x01 | |
| 705 | #define V_SH_SEL1 0x80 | |
| 706 | /* R_SL_SEL2 */ | |
| 707 | #define V_SL_SEL2 0x01 | |
| 708 | #define V_SH_SEL2 0x80 | |
| 709 | /* R_SL_SEL3 */ | |
| 710 | #define V_SL_SEL3 0x01 | |
| 711 | #define V_SH_SEL3 0x80 | |
| 712 | /* R_SL_SEL4 */ | |
| 713 | #define V_SL_SEL4 0x01 | |
| 714 | #define V_SH_SEL4 0x80 | |
| 715 | /* R_SL_SEL5 */ | |
| 716 | #define V_SL_SEL5 0x01 | |
| 717 | #define V_SH_SEL5 0x80 | |
| 718 | /* R_SL_SEL6 */ | |
| 719 | #define V_SL_SEL6 0x01 | |
| 720 | #define V_SH_SEL6 0x80 | |
| 721 | /* R_SL_SEL7 */ | |
| 722 | #define V_SL_SEL7 0x01 | |
| 723 | #define V_SH_SEL7 0x80 | |
| 724 | /* R_PCM_MD1 */ | |
| 725 | #define V_ODEC_CON 0x01 | |
| 726 | #define V_PLL_ADJ 0x04 | |
| 727 | #define V_PCM_DR 0x10 | |
| 728 | #define V_PCM_LOOP 0x40 | |
| 729 | /* R_PCM_MD2 */ | |
| 730 | #define V_SYNC_PLL 0x02 | |
| 731 | #define V_SYNC_SRC 0x04 | |
| 732 | #define V_SYNC_OUT 0x08 | |
| 733 | #define V_ICR_FR_TIME 0x40 | |
| 734 | #define V_EN_PLL 0x80 | |
| 735 | ||
| 736 | /* chapter 7: pulse width modulation */ | |
| 737 | /* R_PWM_MD */ | |
| 738 | #define V_EXT_IRQ_EN 0x08 | |
| 739 | #define V_PWM0_MD 0x10 | |
| 740 | #define V_PWM1_MD 0x40 | |
| 741 | ||
| 742 | /* chapter 8: multiparty audio conferences */ | |
| 743 | /* R_CONF_EN */ | |
| 744 | #define V_CONF_EN 0x01 | |
| 745 | #define V_ULAW 0x80 | |
| 746 | /* A_CONF */ | |
| 747 | #define V_CONF_NUM 0x01 | |
| 748 | #define V_NOISE_SUPPR 0x08 | |
| 749 | #define V_ATT_LEV 0x20 | |
| 750 | #define V_CONF_SL 0x80 | |
| 751 | /* R_CONF_OFLOW */ | |
| 752 | #define V_CONF_OFLOW0 0x01 | |
| 753 | #define V_CONF_OFLOW1 0x02 | |
| 754 | #define V_CONF_OFLOW2 0x04 | |
| 755 | #define V_CONF_OFLOW3 0x08 | |
| 756 | #define V_CONF_OFLOW4 0x10 | |
| 757 | #define V_CONF_OFLOW5 0x20 | |
| 758 | #define V_CONF_OFLOW6 0x40 | |
| 759 | #define V_CONF_OFLOW7 0x80 | |
| 760 | ||
| 761 | /* chapter 9: DTMF contoller */ | |
| 762 | /* R_DTMF0 */ | |
| 763 | #define V_DTMF_EN 0x01 | |
| 764 | #define V_HARM_SEL 0x02 | |
| 765 | #define V_DTMF_RX_CH 0x04 | |
| 766 | #define V_DTMF_STOP 0x08 | |
| 767 | #define V_CHBL_SEL 0x10 | |
| 768 | #define V_RST_DTMF 0x40 | |
| 769 | #define V_ULAW_SEL 0x80 | |
| 770 | ||
| 771 | /* chapter 10: BERT */ | |
| 772 | /* R_BERT_WD_MD */ | |
| 773 | #define V_PAT_SEQ 0x01 | |
| 774 | #define V_BERT_ERR 0x08 | |
| 775 | #define V_AUTO_WD_RES 0x20 | |
| 776 | #define V_WD_RES 0x80 | |
| 777 | /* R_BERT_STA */ | |
| 778 | #define V_BERT_SYNC_SRC 0x01 | |
| 779 | #define V_BERT_SYNC 0x10 | |
| 780 | #define V_BERT_INV_DATA 0x20 | |
| 781 | ||
| 782 | /* chapter 11: auxiliary interface */ | |
| 783 | /* R_BRG_PCM_CFG */ | |
| 784 | #define V_BRG_EN 0x01 | |
| 785 | #define V_BRG_MD 0x02 | |
| 786 | #define V_PCM_CLK 0x20 | |
| 787 | #define V_ADDR_WRDLY 0x40 | |
| 788 | /* R_BRG_CTRL */ | |
| 789 | #define V_BRG_CS 0x01 | |
| 790 | #define V_BRG_ADDR 0x08 | |
| 791 | #define V_BRG_CS_SRC 0x80 | |
| 792 | /* R_BRG_MD */ | |
| 793 | #define V_BRG_MD0 0x01 | |
| 794 | #define V_BRG_MD1 0x02 | |
| 795 | #define V_BRG_MD2 0x04 | |
| 796 | #define V_BRG_MD3 0x08 | |
| 797 | #define V_BRG_MD4 0x10 | |
| 798 | #define V_BRG_MD5 0x20 | |
| 799 | #define V_BRG_MD6 0x40 | |
| 800 | #define V_BRG_MD7 0x80 | |
| 801 | /* R_BRG_TIM0 */ | |
| 802 | #define V_BRG_TIM0_IDLE 0x01 | |
| 803 | #define V_BRG_TIM0_CLK 0x10 | |
| 804 | /* R_BRG_TIM1 */ | |
| 805 | #define V_BRG_TIM1_IDLE 0x01 | |
| 806 | #define V_BRG_TIM1_CLK 0x10 | |
| 807 | /* R_BRG_TIM2 */ | |
| 808 | #define V_BRG_TIM2_IDLE 0x01 | |
| 809 | #define V_BRG_TIM2_CLK 0x10 | |
| 810 | /* R_BRG_TIM3 */ | |
| 811 | #define V_BRG_TIM3_IDLE 0x01 | |
| 812 | #define V_BRG_TIM3_CLK 0x10 | |
| 813 | /* R_BRG_TIM_SEL01 */ | |
| 814 | #define V_BRG_WR_SEL0 0x01 | |
| 815 | #define V_BRG_RD_SEL0 0x04 | |
| 816 | #define V_BRG_WR_SEL1 0x10 | |
| 817 | #define V_BRG_RD_SEL1 0x40 | |
| 818 | /* R_BRG_TIM_SEL23 */ | |
| 819 | #define V_BRG_WR_SEL2 0x01 | |
| 820 | #define V_BRG_RD_SEL2 0x04 | |
| 821 | #define V_BRG_WR_SEL3 0x10 | |
| 822 | #define V_BRG_RD_SEL3 0x40 | |
| 823 | /* R_BRG_TIM_SEL45 */ | |
| 824 | #define V_BRG_WR_SEL4 0x01 | |
| 825 | #define V_BRG_RD_SEL4 0x04 | |
| 826 | #define V_BRG_WR_SEL5 0x10 | |
| 827 | #define V_BRG_RD_SEL5 0x40 | |
| 828 | /* R_BRG_TIM_SEL67 */ | |
| 829 | #define V_BRG_WR_SEL6 0x01 | |
| 830 | #define V_BRG_RD_SEL6 0x04 | |
| 831 | #define V_BRG_WR_SEL7 0x10 | |
| 832 | #define V_BRG_RD_SEL7 0x40 | |
| 833 | ||
| 834 | /* chapter 12: clock, reset, interrupt, timer and watchdog */ | |
| 835 | /* R_IRQMSK_MISC */ | |
| 836 | #define V_STA_IRQMSK 0x01 | |
| 837 | #define V_TI_IRQMSK 0x02 | |
| 838 | #define V_PROC_IRQMSK 0x04 | |
| 839 | #define V_DTMF_IRQMSK 0x08 | |
| 840 | #define V_IRQ1S_MSK 0x10 | |
| 841 | #define V_SA6_IRQMSK 0x20 | |
| 842 | #define V_RX_EOMF_MSK 0x40 | |
| 843 | #define V_TX_EOMF_MSK 0x80 | |
| 844 | /* R_IRQ_CTRL */ | |
| 845 | #define V_FIFO_IRQ 0x01 | |
| 846 | #define V_GLOB_IRQ_EN 0x08 | |
| 847 | #define V_IRQ_POL 0x10 | |
| 848 | /* R_TI_WD */ | |
| 849 | #define V_EV_TS 0x01 | |
| 850 | #define V_WD_TS 0x10 | |
| 851 | /* A_IRQ_MSK */ | |
| 852 | #define V_IRQ 0x01 | |
| 853 | #define V_BERT_EN 0x02 | |
| 854 | #define V_MIX_IRQ 0x04 | |
| 855 | /* R_IRQ_OVIEW */ | |
| 856 | #define V_IRQ_FIFO_BL0 0x01 | |
| 857 | #define V_IRQ_FIFO_BL1 0x02 | |
| 858 | #define V_IRQ_FIFO_BL2 0x04 | |
| 859 | #define V_IRQ_FIFO_BL3 0x08 | |
| 860 | #define V_IRQ_FIFO_BL4 0x10 | |
| 861 | #define V_IRQ_FIFO_BL5 0x20 | |
| 862 | #define V_IRQ_FIFO_BL6 0x40 | |
| 863 | #define V_IRQ_FIFO_BL7 0x80 | |
| 864 | /* R_IRQ_MISC */ | |
| 865 | #define V_STA_IRQ 0x01 | |
| 866 | #define V_TI_IRQ 0x02 | |
| 867 | #define V_IRQ_PROC 0x04 | |
| 868 | #define V_DTMF_IRQ 0x08 | |
| 869 | #define V_IRQ1S 0x10 | |
| 870 | #define V_SA6_IRQ 0x20 | |
| 871 | #define V_RX_EOMF 0x40 | |
| 872 | #define V_TX_EOMF 0x80 | |
| 873 | /* R_STATUS */ | |
| 874 | #define V_BUSY 0x01 | |
| 875 | #define V_PROC 0x02 | |
| 876 | #define V_DTMF_STA 0x04 | |
| 877 | #define V_LOST_STA 0x08 | |
| 878 | #define V_SYNC_IN 0x10 | |
| 879 | #define V_EXT_IRQSTA 0x20 | |
| 880 | #define V_MISC_IRQSTA 0x40 | |
| 881 | #define V_FR_IRQSTA 0x80 | |
| 882 | /* R_IRQ_FIFO_BL0 */ | |
| 883 | #define V_IRQ_FIFO0_TX 0x01 | |
| 884 | #define V_IRQ_FIFO0_RX 0x02 | |
| 885 | #define V_IRQ_FIFO1_TX 0x04 | |
| 886 | #define V_IRQ_FIFO1_RX 0x08 | |
| 887 | #define V_IRQ_FIFO2_TX 0x10 | |
| 888 | #define V_IRQ_FIFO2_RX 0x20 | |
| 889 | #define V_IRQ_FIFO3_TX 0x40 | |
| 890 | #define V_IRQ_FIFO3_RX 0x80 | |
| 891 | /* R_IRQ_FIFO_BL1 */ | |
| 892 | #define V_IRQ_FIFO4_TX 0x01 | |
| 893 | #define V_IRQ_FIFO4_RX 0x02 | |
| 894 | #define V_IRQ_FIFO5_TX 0x04 | |
| 895 | #define V_IRQ_FIFO5_RX 0x08 | |
| 896 | #define V_IRQ_FIFO6_TX 0x10 | |
| 897 | #define V_IRQ_FIFO6_RX 0x20 | |
| 898 | #define V_IRQ_FIFO7_TX 0x40 | |
| 899 | #define V_IRQ_FIFO7_RX 0x80 | |
| 900 | /* R_IRQ_FIFO_BL2 */ | |
| 901 | #define V_IRQ_FIFO8_TX 0x01 | |
| 902 | #define V_IRQ_FIFO8_RX 0x02 | |
| 903 | #define V_IRQ_FIFO9_TX 0x04 | |
| 904 | #define V_IRQ_FIFO9_RX 0x08 | |
| 905 | #define V_IRQ_FIFO10_TX 0x10 | |
| 906 | #define V_IRQ_FIFO10_RX 0x20 | |
| 907 | #define V_IRQ_FIFO11_TX 0x40 | |
| 908 | #define V_IRQ_FIFO11_RX 0x80 | |
| 909 | /* R_IRQ_FIFO_BL3 */ | |
| 910 | #define V_IRQ_FIFO12_TX 0x01 | |
| 911 | #define V_IRQ_FIFO12_RX 0x02 | |
| 912 | #define V_IRQ_FIFO13_TX 0x04 | |
| 913 | #define V_IRQ_FIFO13_RX 0x08 | |
| 914 | #define V_IRQ_FIFO14_TX 0x10 | |
| 915 | #define V_IRQ_FIFO14_RX 0x20 | |
| 916 | #define V_IRQ_FIFO15_TX 0x40 | |
| 917 | #define V_IRQ_FIFO15_RX 0x80 | |
| 918 | /* R_IRQ_FIFO_BL4 */ | |
| 919 | #define V_IRQ_FIFO16_TX 0x01 | |
| 920 | #define V_IRQ_FIFO16_RX 0x02 | |
| 921 | #define V_IRQ_FIFO17_TX 0x04 | |
| 922 | #define V_IRQ_FIFO17_RX 0x08 | |
| 923 | #define V_IRQ_FIFO18_TX 0x10 | |
| 924 | #define V_IRQ_FIFO18_RX 0x20 | |
| 925 | #define V_IRQ_FIFO19_TX 0x40 | |
| 926 | #define V_IRQ_FIFO19_RX 0x80 | |
| 927 | /* R_IRQ_FIFO_BL5 */ | |
| 928 | #define V_IRQ_FIFO20_TX 0x01 | |
| 929 | #define V_IRQ_FIFO20_RX 0x02 | |
| 930 | #define V_IRQ_FIFO21_TX 0x04 | |
| 931 | #define V_IRQ_FIFO21_RX 0x08 | |
| 932 | #define V_IRQ_FIFO22_TX 0x10 | |
| 933 | #define V_IRQ_FIFO22_RX 0x20 | |
| 934 | #define V_IRQ_FIFO23_TX 0x40 | |
| 935 | #define V_IRQ_FIFO23_RX 0x80 | |
| 936 | /* R_IRQ_FIFO_BL6 */ | |
| 937 | #define V_IRQ_FIFO24_TX 0x01 | |
| 938 | #define V_IRQ_FIFO24_RX 0x02 | |
| 939 | #define V_IRQ_FIFO25_TX 0x04 | |
| 940 | #define V_IRQ_FIFO25_RX 0x08 | |
| 941 | #define V_IRQ_FIFO26_TX 0x10 | |
| 942 | #define V_IRQ_FIFO26_RX 0x20 | |
| 943 | #define V_IRQ_FIFO27_TX 0x40 | |
| 944 | #define V_IRQ_FIFO27_RX 0x80 | |
| 945 | /* R_IRQ_FIFO_BL7 */ | |
| 946 | #define V_IRQ_FIFO28_TX 0x01 | |
| 947 | #define V_IRQ_FIFO28_RX 0x02 | |
| 948 | #define V_IRQ_FIFO29_TX 0x04 | |
| 949 | #define V_IRQ_FIFO29_RX 0x08 | |
| 950 | #define V_IRQ_FIFO30_TX 0x10 | |
| 951 | #define V_IRQ_FIFO30_RX 0x20 | |
| 952 | #define V_IRQ_FIFO31_TX 0x40 | |
| 953 | #define V_IRQ_FIFO31_RX 0x80 | |
| 954 | ||
| 955 | /* chapter 13: general purpose I/O pins (GPIO) and input pins (GPI) */ | |
| 956 | /* R_GPIO_OUT0 */ | |
| 957 | #define V_GPIO_OUT0 0x01 | |
| 958 | #define V_GPIO_OUT1 0x02 | |
| 959 | #define V_GPIO_OUT2 0x04 | |
| 960 | #define V_GPIO_OUT3 0x08 | |
| 961 | #define V_GPIO_OUT4 0x10 | |
| 962 | #define V_GPIO_OUT5 0x20 | |
| 963 | #define V_GPIO_OUT6 0x40 | |
| 964 | #define V_GPIO_OUT7 0x80 | |
| 965 | /* R_GPIO_OUT1 */ | |
| 966 | #define V_GPIO_OUT8 0x01 | |
| 967 | #define V_GPIO_OUT9 0x02 | |
| 968 | #define V_GPIO_OUT10 0x04 | |
| 969 | #define V_GPIO_OUT11 0x08 | |
| 970 | #define V_GPIO_OUT12 0x10 | |
| 971 | #define V_GPIO_OUT13 0x20 | |
| 972 | #define V_GPIO_OUT14 0x40 | |
| 973 | #define V_GPIO_OUT15 0x80 | |
| 974 | /* R_GPIO_EN0 */ | |
| 975 | #define V_GPIO_EN0 0x01 | |
| 976 | #define V_GPIO_EN1 0x02 | |
| 977 | #define V_GPIO_EN2 0x04 | |
| 978 | #define V_GPIO_EN3 0x08 | |
| 979 | #define V_GPIO_EN4 0x10 | |
| 980 | #define V_GPIO_EN5 0x20 | |
| 981 | #define V_GPIO_EN6 0x40 | |
| 982 | #define V_GPIO_EN7 0x80 | |
| 983 | /* R_GPIO_EN1 */ | |
| 984 | #define V_GPIO_EN8 0x01 | |
| 985 | #define V_GPIO_EN9 0x02 | |
| 986 | #define V_GPIO_EN10 0x04 | |
| 987 | #define V_GPIO_EN11 0x08 | |
| 988 | #define V_GPIO_EN12 0x10 | |
| 989 | #define V_GPIO_EN13 0x20 | |
| 990 | #define V_GPIO_EN14 0x40 | |
| 991 | #define V_GPIO_EN15 0x80 | |
| 992 | /* R_GPIO_SEL */ | |
| 993 | #define V_GPIO_SEL0 0x01 | |
| 994 | #define V_GPIO_SEL1 0x02 | |
| 995 | #define V_GPIO_SEL2 0x04 | |
| 996 | #define V_GPIO_SEL3 0x08 | |
| 997 | #define V_GPIO_SEL4 0x10 | |
| 998 | #define V_GPIO_SEL5 0x20 | |
| 999 | #define V_GPIO_SEL6 0x40 | |
| 1000 | #define V_GPIO_SEL7 0x80 | |
| 1001 | /* R_GPIO_IN0 */ | |
| 1002 | #define V_GPIO_IN0 0x01 | |
| 1003 | #define V_GPIO_IN1 0x02 | |
| 1004 | #define V_GPIO_IN2 0x04 | |
| 1005 | #define V_GPIO_IN3 0x08 | |
| 1006 | #define V_GPIO_IN4 0x10 | |
| 1007 | #define V_GPIO_IN5 0x20 | |
| 1008 | #define V_GPIO_IN6 0x40 | |
| 1009 | #define V_GPIO_IN7 0x80 | |
| 1010 | /* R_GPIO_IN1 */ | |
| 1011 | #define V_GPIO_IN8 0x01 | |
| 1012 | #define V_GPIO_IN9 0x02 | |
| 1013 | #define V_GPIO_IN10 0x04 | |
| 1014 | #define V_GPIO_IN11 0x08 | |
| 1015 | #define V_GPIO_IN12 0x10 | |
| 1016 | #define V_GPIO_IN13 0x20 | |
| 1017 | #define V_GPIO_IN14 0x40 | |
| 1018 | #define V_GPIO_IN15 0x80 | |
| 1019 | /* R_GPI_IN0 */ | |
| 1020 | #define V_GPI_IN0 0x01 | |
| 1021 | #define V_GPI_IN1 0x02 | |
| 1022 | #define V_GPI_IN2 0x04 | |
| 1023 | #define V_GPI_IN3 0x08 | |
| 1024 | #define V_GPI_IN4 0x10 | |
| 1025 | #define V_GPI_IN5 0x20 | |
| 1026 | #define V_GPI_IN6 0x40 | |
| 1027 | #define V_GPI_IN7 0x80 | |
| 1028 | /* R_GPI_IN1 */ | |
| 1029 | #define V_GPI_IN8 0x01 | |
| 1030 | #define V_GPI_IN9 0x02 | |
| 1031 | #define V_GPI_IN10 0x04 | |
| 1032 | #define V_GPI_IN11 0x08 | |
| 1033 | #define V_GPI_IN12 0x10 | |
| 1034 | #define V_GPI_IN13 0x20 | |
| 1035 | #define V_GPI_IN14 0x40 | |
| 1036 | #define V_GPI_IN15 0x80 | |
| 1037 | /* R_GPI_IN2 */ | |
| 1038 | #define V_GPI_IN16 0x01 | |
| 1039 | #define V_GPI_IN17 0x02 | |
| 1040 | #define V_GPI_IN18 0x04 | |
| 1041 | #define V_GPI_IN19 0x08 | |
| 1042 | #define V_GPI_IN20 0x10 | |
| 1043 | #define V_GPI_IN21 0x20 | |
| 1044 | #define V_GPI_IN22 0x40 | |
| 1045 | #define V_GPI_IN23 0x80 | |
| 1046 | /* R_GPI_IN3 */ | |
| 1047 | #define V_GPI_IN24 0x01 | |
| 1048 | #define V_GPI_IN25 0x02 | |
| 1049 | #define V_GPI_IN26 0x04 | |
| 1050 | #define V_GPI_IN27 0x08 | |
| 1051 | #define V_GPI_IN28 0x10 | |
| 1052 | #define V_GPI_IN29 0x20 | |
| 1053 | #define V_GPI_IN30 0x40 | |
| 1054 | #define V_GPI_IN31 0x80 | |
| 1055 | ||
| 1056 | /* map of all registers, used for debugging */ | |
| 1057 | ||
| 1058 | #ifdef HFC_REGISTER_DEBUG | |
| 1059 | struct hfc_register_names { | |
| 1060 | char *name; | |
| 1061 | u_char reg; | |
| 1062 | } hfc_register_names[] = { | |
| 1063 | /* write registers */ | |
| 1064 | {"R_CIRM", 0x00}, | |
| 1065 | {"R_CTRL", 0x01}, | |
| 1066 | {"R_BRG_PCM_CFG ", 0x02}, | |
| 1067 | {"R_RAM_ADDR0", 0x08}, | |
| 1068 | {"R_RAM_ADDR1", 0x09}, | |
| 1069 | {"R_RAM_ADDR2", 0x0A}, | |
| 1070 | {"R_FIRST_FIFO", 0x0B}, | |
| 1071 | {"R_RAM_SZ", 0x0C}, | |
| 1072 | {"R_FIFO_MD", 0x0D}, | |
| 1073 | {"R_INC_RES_FIFO", 0x0E}, | |
| 1074 | {"R_FIFO / R_FSM_IDX", 0x0F}, | |
| 1075 | {"R_SLOT", 0x10}, | |
| 1076 | {"R_IRQMSK_MISC", 0x11}, | |
| 1077 | {"R_SCI_MSK", 0x12}, | |
| 1078 | {"R_IRQ_CTRL", 0x13}, | |
| 1079 | {"R_PCM_MD0", 0x14}, | |
| 1080 | {"R_0x15", 0x15}, | |
| 1081 | {"R_ST_SEL", 0x16}, | |
| 1082 | {"R_ST_SYNC", 0x17}, | |
| 1083 | {"R_CONF_EN", 0x18}, | |
| 1084 | {"R_TI_WD", 0x1A}, | |
| 1085 | {"R_BERT_WD_MD", 0x1B}, | |
| 1086 | {"R_DTMF", 0x1C}, | |
| 1087 | {"R_DTMF_N", 0x1D}, | |
| 1088 | {"R_E1_XX_STA", 0x20}, | |
| 1089 | {"R_LOS0", 0x22}, | |
| 1090 | {"R_LOS1", 0x23}, | |
| 1091 | {"R_RX0", 0x24}, | |
| 1092 | {"R_RX_FR0", 0x25}, | |
| 1093 | {"R_RX_FR1", 0x26}, | |
| 1094 | {"R_TX0", 0x28}, | |
| 1095 | {"R_TX1", 0x29}, | |
| 1096 | {"R_TX_FR0", 0x2C}, | |
| 1097 | {"R_TX_FR1", 0x2D}, | |
| 1098 | {"R_TX_FR2", 0x2E}, | |
| 1099 | {"R_JATT_ATT", 0x2F}, | |
| 1100 | {"A_ST_xx_STA/R_RX_OFF", 0x30}, | |
| 1101 | {"A_ST_CTRL0/R_SYNC_OUT", 0x31}, | |
| 1102 | {"A_ST_CTRL1", 0x32}, | |
| 1103 | {"A_ST_CTRL2", 0x33}, | |
| 1104 | {"A_ST_SQ_WR", 0x34}, | |
| 1105 | {"R_TX_OFF", 0x34}, | |
| 1106 | {"R_SYNC_CTRL", 0x35}, | |
| 1107 | {"A_ST_CLK_DLY", 0x37}, | |
| 1108 | {"R_PWM0", 0x38}, | |
| 1109 | {"R_PWM1", 0x39}, | |
| 1110 | {"A_ST_B1_TX", 0x3C}, | |
| 1111 | {"A_ST_B2_TX", 0x3D}, | |
| 1112 | {"A_ST_D_TX", 0x3E}, | |
| 1113 | {"R_GPIO_OUT0", 0x40}, | |
| 1114 | {"R_GPIO_OUT1", 0x41}, | |
| 1115 | {"R_GPIO_EN0", 0x42}, | |
| 1116 | {"R_GPIO_EN1", 0x43}, | |
| 1117 | {"R_GPIO_SEL", 0x44}, | |
| 1118 | {"R_BRG_CTRL", 0x45}, | |
| 1119 | {"R_PWM_MD", 0x46}, | |
| 1120 | {"R_BRG_MD", 0x47}, | |
| 1121 | {"R_BRG_TIM0", 0x48}, | |
| 1122 | {"R_BRG_TIM1", 0x49}, | |
| 1123 | {"R_BRG_TIM2", 0x4A}, | |
| 1124 | {"R_BRG_TIM3", 0x4B}, | |
| 1125 | {"R_BRG_TIM_SEL01", 0x4C}, | |
| 1126 | {"R_BRG_TIM_SEL23", 0x4D}, | |
| 1127 | {"R_BRG_TIM_SEL45", 0x4E}, | |
| 1128 | {"R_BRG_TIM_SEL67", 0x4F}, | |
| 1129 | {"A_FIFO_DATA0-2", 0x80}, | |
| 1130 | {"A_FIFO_DATA0-2_NOINC", 0x84}, | |
| 1131 | {"R_RAM_DATA", 0xC0}, | |
| 1132 | {"A_SL_CFG", 0xD0}, | |
| 1133 | {"A_CONF", 0xD1}, | |
| 1134 | {"A_CH_MSK", 0xF4}, | |
| 1135 | {"A_CON_HDLC", 0xFA}, | |
| 1136 | {"A_SUBCH_CFG", 0xFB}, | |
| 1137 | {"A_CHANNEL", 0xFC}, | |
| 1138 | {"A_FIFO_SEQ", 0xFD}, | |
| 1139 | {"A_IRQ_MSK", 0xFF}, | |
| 1140 | {NULL, 0}, | |
| 1141 | ||
| 1142 | /* read registers */ | |
| 1143 | {"A_Z1", 0x04}, | |
| 1144 | {"A_Z1H", 0x05}, | |
| 1145 | {"A_Z2", 0x06}, | |
| 1146 | {"A_Z2H", 0x07}, | |
| 1147 | {"A_F1", 0x0C}, | |
| 1148 | {"A_F2", 0x0D}, | |
| 1149 | {"R_IRQ_OVIEW", 0x10}, | |
| 1150 | {"R_IRQ_MISC", 0x11}, | |
| 1151 | {"R_IRQ_STATECH", 0x12}, | |
| 1152 | {"R_CONF_OFLOW", 0x14}, | |
| 1153 | {"R_RAM_USE", 0x15}, | |
| 1154 | {"R_CHIP_ID", 0x16}, | |
| 1155 | {"R_BERT_STA", 0x17}, | |
| 1156 | {"R_F0_CNTL", 0x18}, | |
| 1157 | {"R_F0_CNTH", 0x19}, | |
| 1158 | {"R_BERT_ECL", 0x1A}, | |
| 1159 | {"R_BERT_ECH", 0x1B}, | |
| 1160 | {"R_STATUS", 0x1C}, | |
| 1161 | {"R_CHIP_RV", 0x1F}, | |
| 1162 | {"R_STATE", 0x20}, | |
| 1163 | {"R_SYNC_STA", 0x24}, | |
| 1164 | {"R_RX_SL0_0", 0x25}, | |
| 1165 | {"R_RX_SL0_1", 0x26}, | |
| 1166 | {"R_RX_SL0_2", 0x27}, | |
| 1167 | {"R_JATT_DIR", 0x2b}, | |
| 1168 | {"R_SLIP", 0x2c}, | |
| 1169 | {"A_ST_RD_STA", 0x30}, | |
| 1170 | {"R_FAS_ECL", 0x30}, | |
| 1171 | {"R_FAS_ECH", 0x31}, | |
| 1172 | {"R_VIO_ECL", 0x32}, | |
| 1173 | {"R_VIO_ECH", 0x33}, | |
| 1174 | {"R_CRC_ECL / A_ST_SQ_RD", 0x34}, | |
| 1175 | {"R_CRC_ECH", 0x35}, | |
| 1176 | {"R_E_ECL", 0x36}, | |
| 1177 | {"R_E_ECH", 0x37}, | |
| 1178 | {"R_SA6_SA13_ECL", 0x38}, | |
| 1179 | {"R_SA6_SA13_ECH", 0x39}, | |
| 1180 | {"R_SA6_SA23_ECL", 0x3A}, | |
| 1181 | {"R_SA6_SA23_ECH", 0x3B}, | |
| 1182 | {"A_ST_B1_RX", 0x3C}, | |
| 1183 | {"A_ST_B2_RX", 0x3D}, | |
| 1184 | {"A_ST_D_RX", 0x3E}, | |
| 1185 | {"A_ST_E_RX", 0x3F}, | |
| 1186 | {"R_GPIO_IN0", 0x40}, | |
| 1187 | {"R_GPIO_IN1", 0x41}, | |
| 1188 | {"R_GPI_IN0", 0x44}, | |
| 1189 | {"R_GPI_IN1", 0x45}, | |
| 1190 | {"R_GPI_IN2", 0x46}, | |
| 1191 | {"R_GPI_IN3", 0x47}, | |
| 1192 | {"A_FIFO_DATA0-2", 0x80}, | |
| 1193 | {"A_FIFO_DATA0-2_NOINC", 0x84}, | |
| 1194 | {"R_INT_DATA", 0x88}, | |
| 1195 | {"R_RAM_DATA", 0xC0}, | |
| 1196 | {"R_IRQ_FIFO_BL0", 0xC8}, | |
| 1197 | {"R_IRQ_FIFO_BL1", 0xC9}, | |
| 1198 | {"R_IRQ_FIFO_BL2", 0xCA}, | |
| 1199 | {"R_IRQ_FIFO_BL3", 0xCB}, | |
| 1200 | {"R_IRQ_FIFO_BL4", 0xCC}, | |
| 1201 | {"R_IRQ_FIFO_BL5", 0xCD}, | |
| 1202 | {"R_IRQ_FIFO_BL6", 0xCE}, | |
| 1203 | {"R_IRQ_FIFO_BL7", 0xCF}, | |
| 1204 | }; | |
| 1205 | #endif /* HFC_REGISTER_DEBUG */ | |
| 1206 |