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de6cc651 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1700fe1a KK |
2 | /* |
3 | * specific defines for CCD's HFC 2BDS0 PCI chips | |
4 | * | |
5 | * Author Werner Cornelius (werner@isdn4linux.de) | |
6 | * | |
7 | * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de) | |
1700fe1a KK |
8 | */ |
9 | ||
10 | /* | |
11 | * thresholds for transparent B-channel mode | |
12 | * change mask and threshold simultaneously | |
13 | */ | |
14 | #define HFCPCI_BTRANS_THRESHOLD 128 | |
8dd2f36f | 15 | #define HFCPCI_FILLEMPTY 64 |
1700fe1a KK |
16 | #define HFCPCI_BTRANS_THRESMASK 0x00 |
17 | ||
18 | /* defines for PCI config */ | |
19 | #define PCI_ENA_MEMIO 0x02 | |
20 | #define PCI_ENA_MASTER 0x04 | |
21 | ||
22 | /* GCI/IOM bus monitor registers */ | |
23 | #define HCFPCI_C_I 0x08 | |
24 | #define HFCPCI_TRxR 0x0C | |
25 | #define HFCPCI_MON1_D 0x28 | |
26 | #define HFCPCI_MON2_D 0x2C | |
27 | ||
28 | /* GCI/IOM bus timeslot registers */ | |
29 | #define HFCPCI_B1_SSL 0x80 | |
30 | #define HFCPCI_B2_SSL 0x84 | |
31 | #define HFCPCI_AUX1_SSL 0x88 | |
32 | #define HFCPCI_AUX2_SSL 0x8C | |
33 | #define HFCPCI_B1_RSL 0x90 | |
34 | #define HFCPCI_B2_RSL 0x94 | |
35 | #define HFCPCI_AUX1_RSL 0x98 | |
36 | #define HFCPCI_AUX2_RSL 0x9C | |
37 | ||
38 | /* GCI/IOM bus data registers */ | |
39 | #define HFCPCI_B1_D 0xA0 | |
40 | #define HFCPCI_B2_D 0xA4 | |
41 | #define HFCPCI_AUX1_D 0xA8 | |
42 | #define HFCPCI_AUX2_D 0xAC | |
43 | ||
44 | /* GCI/IOM bus configuration registers */ | |
45 | #define HFCPCI_MST_EMOD 0xB4 | |
46 | #define HFCPCI_MST_MODE 0xB8 | |
475be4d8 | 47 | #define HFCPCI_CONNECT 0xBC |
1700fe1a KK |
48 | |
49 | ||
50 | /* Interrupt and status registers */ | |
51 | #define HFCPCI_FIFO_EN 0x44 | |
52 | #define HFCPCI_TRM 0x48 | |
53 | #define HFCPCI_B_MODE 0x4C | |
54 | #define HFCPCI_CHIP_ID 0x58 | |
55 | #define HFCPCI_CIRM 0x60 | |
56 | #define HFCPCI_CTMT 0x64 | |
57 | #define HFCPCI_INT_M1 0x68 | |
58 | #define HFCPCI_INT_M2 0x6C | |
59 | #define HFCPCI_INT_S1 0x78 | |
60 | #define HFCPCI_INT_S2 0x7C | |
61 | #define HFCPCI_STATUS 0x70 | |
62 | ||
63 | /* S/T section registers */ | |
64 | #define HFCPCI_STATES 0xC0 | |
65 | #define HFCPCI_SCTRL 0xC4 | |
66 | #define HFCPCI_SCTRL_E 0xC8 | |
67 | #define HFCPCI_SCTRL_R 0xCC | |
68 | #define HFCPCI_SQ 0xD0 | |
69 | #define HFCPCI_CLKDEL 0xDC | |
70 | #define HFCPCI_B1_REC 0xF0 | |
71 | #define HFCPCI_B1_SEND 0xF0 | |
72 | #define HFCPCI_B2_REC 0xF4 | |
73 | #define HFCPCI_B2_SEND 0xF4 | |
74 | #define HFCPCI_D_REC 0xF8 | |
75 | #define HFCPCI_D_SEND 0xF8 | |
76 | #define HFCPCI_E_REC 0xFC | |
77 | ||
78 | ||
79 | /* bits in status register (READ) */ | |
80 | #define HFCPCI_PCI_PROC 0x02 | |
81 | #define HFCPCI_NBUSY 0x04 | |
82 | #define HFCPCI_TIMER_ELAP 0x10 | |
83 | #define HFCPCI_STATINT 0x20 | |
84 | #define HFCPCI_FRAMEINT 0x40 | |
85 | #define HFCPCI_ANYINT 0x80 | |
86 | ||
87 | /* bits in CTMT (Write) */ | |
88 | #define HFCPCI_CLTIMER 0x80 | |
89 | #define HFCPCI_TIM3_125 0x04 | |
90 | #define HFCPCI_TIM25 0x10 | |
91 | #define HFCPCI_TIM50 0x14 | |
92 | #define HFCPCI_TIM400 0x18 | |
93 | #define HFCPCI_TIM800 0x1C | |
94 | #define HFCPCI_AUTO_TIMER 0x20 | |
95 | #define HFCPCI_TRANSB2 0x02 | |
96 | #define HFCPCI_TRANSB1 0x01 | |
97 | ||
98 | /* bits in CIRM (Write) */ | |
99 | #define HFCPCI_AUX_MSK 0x07 | |
100 | #define HFCPCI_RESET 0x08 | |
101 | #define HFCPCI_B1_REV 0x40 | |
102 | #define HFCPCI_B2_REV 0x80 | |
103 | ||
104 | /* bits in INT_M1 and INT_S1 */ | |
105 | #define HFCPCI_INTS_B1TRANS 0x01 | |
106 | #define HFCPCI_INTS_B2TRANS 0x02 | |
107 | #define HFCPCI_INTS_DTRANS 0x04 | |
108 | #define HFCPCI_INTS_B1REC 0x08 | |
109 | #define HFCPCI_INTS_B2REC 0x10 | |
110 | #define HFCPCI_INTS_DREC 0x20 | |
111 | #define HFCPCI_INTS_L1STATE 0x40 | |
112 | #define HFCPCI_INTS_TIMER 0x80 | |
113 | ||
114 | /* bits in INT_M2 */ | |
115 | #define HFCPCI_PROC_TRANS 0x01 | |
116 | #define HFCPCI_GCI_I_CHG 0x02 | |
117 | #define HFCPCI_GCI_MON_REC 0x04 | |
118 | #define HFCPCI_IRQ_ENABLE 0x08 | |
119 | #define HFCPCI_PMESEL 0x80 | |
120 | ||
121 | /* bits in STATES */ | |
122 | #define HFCPCI_STATE_MSK 0x0F | |
123 | #define HFCPCI_LOAD_STATE 0x10 | |
124 | #define HFCPCI_ACTIVATE 0x20 | |
125 | #define HFCPCI_DO_ACTION 0x40 | |
126 | #define HFCPCI_NT_G2_G3 0x80 | |
127 | ||
128 | /* bits in HFCD_MST_MODE */ | |
129 | #define HFCPCI_MASTER 0x01 | |
130 | #define HFCPCI_SLAVE 0x00 | |
131 | #define HFCPCI_F0IO_POSITIV 0x02 | |
132 | #define HFCPCI_F0_NEGATIV 0x04 | |
133 | #define HFCPCI_F0_2C4 0x08 | |
134 | /* remaining bits are for codecs control */ | |
135 | ||
136 | /* bits in HFCD_SCTRL */ | |
137 | #define SCTRL_B1_ENA 0x01 | |
138 | #define SCTRL_B2_ENA 0x02 | |
139 | #define SCTRL_MODE_TE 0x00 | |
140 | #define SCTRL_MODE_NT 0x04 | |
141 | #define SCTRL_LOW_PRIO 0x08 | |
142 | #define SCTRL_SQ_ENA 0x10 | |
143 | #define SCTRL_TEST 0x20 | |
144 | #define SCTRL_NONE_CAP 0x40 | |
145 | #define SCTRL_PWR_DOWN 0x80 | |
146 | ||
147 | /* bits in SCTRL_E */ | |
148 | #define HFCPCI_AUTO_AWAKE 0x01 | |
149 | #define HFCPCI_DBIT_1 0x04 | |
150 | #define HFCPCI_IGNORE_COL 0x08 | |
151 | #define HFCPCI_CHG_B1_B2 0x80 | |
152 | ||
153 | /* bits in FIFO_EN register */ | |
154 | #define HFCPCI_FIFOEN_B1 0x03 | |
155 | #define HFCPCI_FIFOEN_B2 0x0C | |
156 | #define HFCPCI_FIFOEN_DTX 0x10 | |
157 | #define HFCPCI_FIFOEN_B1TX 0x01 | |
158 | #define HFCPCI_FIFOEN_B1RX 0x02 | |
159 | #define HFCPCI_FIFOEN_B2TX 0x04 | |
160 | #define HFCPCI_FIFOEN_B2RX 0x08 | |
161 | ||
162 | ||
163 | /* definitions of fifo memory area */ | |
164 | #define MAX_D_FRAMES 15 | |
165 | #define MAX_B_FRAMES 31 | |
166 | #define B_SUB_VAL 0x200 | |
167 | #define B_FIFO_SIZE (0x2000 - B_SUB_VAL) | |
168 | #define D_FIFO_SIZE 512 | |
169 | #define D_FREG_MASK 0xF | |
170 | ||
171 | struct zt { | |
f11d32df HH |
172 | __le16 z1; /* Z1 pointer 16 Bit */ |
173 | __le16 z2; /* Z2 pointer 16 Bit */ | |
1700fe1a KK |
174 | }; |
175 | ||
176 | struct dfifo { | |
177 | u_char data[D_FIFO_SIZE]; /* FIFO data space */ | |
475be4d8 | 178 | u_char fill1[0x20A0 - D_FIFO_SIZE]; /* reserved, do not use */ |
1700fe1a | 179 | u_char f1, f2; /* f pointers */ |
475be4d8 | 180 | u_char fill2[0x20C0 - 0x20A2]; /* reserved, do not use */ |
1700fe1a | 181 | /* mask index with D_FREG_MASK for access */ |
475be4d8 JP |
182 | struct zt za[MAX_D_FRAMES + 1]; |
183 | u_char fill3[0x4000 - 0x2100]; /* align 16K */ | |
1700fe1a KK |
184 | }; |
185 | ||
186 | struct bzfifo { | |
475be4d8 | 187 | struct zt za[MAX_B_FRAMES + 1]; /* only range 0x0..0x1F allowed */ |
1700fe1a | 188 | u_char f1, f2; /* f pointers */ |
475be4d8 | 189 | u_char fill[0x2100 - 0x2082]; /* alignment */ |
1700fe1a KK |
190 | }; |
191 | ||
192 | ||
193 | union fifo_area { | |
194 | struct { | |
195 | struct dfifo d_tx; /* D-send channel */ | |
196 | struct dfifo d_rx; /* D-receive channel */ | |
197 | } d_chan; | |
198 | struct { | |
199 | u_char fill1[0x200]; | |
200 | u_char txdat_b1[B_FIFO_SIZE]; | |
201 | struct bzfifo txbz_b1; | |
202 | struct bzfifo txbz_b2; | |
203 | u_char txdat_b2[B_FIFO_SIZE]; | |
204 | u_char fill2[D_FIFO_SIZE]; | |
205 | u_char rxdat_b1[B_FIFO_SIZE]; | |
206 | struct bzfifo rxbz_b1; | |
207 | struct bzfifo rxbz_b2; | |
208 | u_char rxdat_b2[B_FIFO_SIZE]; | |
209 | } b_chans; | |
210 | u_char fill[32768]; | |
211 | }; | |
212 | ||
475be4d8 JP |
213 | #define Write_hfc(a, b, c) (writeb(c, (a->hw.pci_io) + b)) |
214 | #define Read_hfc(a, b) (readb((a->hw.pci_io) + b)) |