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1700fe1a KK |
1 | /* |
2 | * specific defines for CCD's HFC 2BDS0 PCI chips | |
3 | * | |
4 | * Author Werner Cornelius (werner@isdn4linux.de) | |
5 | * | |
6 | * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de) | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | * | |
22 | */ | |
23 | ||
24 | /* | |
25 | * thresholds for transparent B-channel mode | |
26 | * change mask and threshold simultaneously | |
27 | */ | |
28 | #define HFCPCI_BTRANS_THRESHOLD 128 | |
29 | #define HFCPCI_BTRANS_MAX 256 | |
30 | #define HFCPCI_BTRANS_THRESMASK 0x00 | |
31 | ||
32 | /* defines for PCI config */ | |
33 | #define PCI_ENA_MEMIO 0x02 | |
34 | #define PCI_ENA_MASTER 0x04 | |
35 | ||
36 | /* GCI/IOM bus monitor registers */ | |
37 | #define HCFPCI_C_I 0x08 | |
38 | #define HFCPCI_TRxR 0x0C | |
39 | #define HFCPCI_MON1_D 0x28 | |
40 | #define HFCPCI_MON2_D 0x2C | |
41 | ||
42 | /* GCI/IOM bus timeslot registers */ | |
43 | #define HFCPCI_B1_SSL 0x80 | |
44 | #define HFCPCI_B2_SSL 0x84 | |
45 | #define HFCPCI_AUX1_SSL 0x88 | |
46 | #define HFCPCI_AUX2_SSL 0x8C | |
47 | #define HFCPCI_B1_RSL 0x90 | |
48 | #define HFCPCI_B2_RSL 0x94 | |
49 | #define HFCPCI_AUX1_RSL 0x98 | |
50 | #define HFCPCI_AUX2_RSL 0x9C | |
51 | ||
52 | /* GCI/IOM bus data registers */ | |
53 | #define HFCPCI_B1_D 0xA0 | |
54 | #define HFCPCI_B2_D 0xA4 | |
55 | #define HFCPCI_AUX1_D 0xA8 | |
56 | #define HFCPCI_AUX2_D 0xAC | |
57 | ||
58 | /* GCI/IOM bus configuration registers */ | |
59 | #define HFCPCI_MST_EMOD 0xB4 | |
60 | #define HFCPCI_MST_MODE 0xB8 | |
61 | #define HFCPCI_CONNECT 0xBC | |
62 | ||
63 | ||
64 | /* Interrupt and status registers */ | |
65 | #define HFCPCI_FIFO_EN 0x44 | |
66 | #define HFCPCI_TRM 0x48 | |
67 | #define HFCPCI_B_MODE 0x4C | |
68 | #define HFCPCI_CHIP_ID 0x58 | |
69 | #define HFCPCI_CIRM 0x60 | |
70 | #define HFCPCI_CTMT 0x64 | |
71 | #define HFCPCI_INT_M1 0x68 | |
72 | #define HFCPCI_INT_M2 0x6C | |
73 | #define HFCPCI_INT_S1 0x78 | |
74 | #define HFCPCI_INT_S2 0x7C | |
75 | #define HFCPCI_STATUS 0x70 | |
76 | ||
77 | /* S/T section registers */ | |
78 | #define HFCPCI_STATES 0xC0 | |
79 | #define HFCPCI_SCTRL 0xC4 | |
80 | #define HFCPCI_SCTRL_E 0xC8 | |
81 | #define HFCPCI_SCTRL_R 0xCC | |
82 | #define HFCPCI_SQ 0xD0 | |
83 | #define HFCPCI_CLKDEL 0xDC | |
84 | #define HFCPCI_B1_REC 0xF0 | |
85 | #define HFCPCI_B1_SEND 0xF0 | |
86 | #define HFCPCI_B2_REC 0xF4 | |
87 | #define HFCPCI_B2_SEND 0xF4 | |
88 | #define HFCPCI_D_REC 0xF8 | |
89 | #define HFCPCI_D_SEND 0xF8 | |
90 | #define HFCPCI_E_REC 0xFC | |
91 | ||
92 | ||
93 | /* bits in status register (READ) */ | |
94 | #define HFCPCI_PCI_PROC 0x02 | |
95 | #define HFCPCI_NBUSY 0x04 | |
96 | #define HFCPCI_TIMER_ELAP 0x10 | |
97 | #define HFCPCI_STATINT 0x20 | |
98 | #define HFCPCI_FRAMEINT 0x40 | |
99 | #define HFCPCI_ANYINT 0x80 | |
100 | ||
101 | /* bits in CTMT (Write) */ | |
102 | #define HFCPCI_CLTIMER 0x80 | |
103 | #define HFCPCI_TIM3_125 0x04 | |
104 | #define HFCPCI_TIM25 0x10 | |
105 | #define HFCPCI_TIM50 0x14 | |
106 | #define HFCPCI_TIM400 0x18 | |
107 | #define HFCPCI_TIM800 0x1C | |
108 | #define HFCPCI_AUTO_TIMER 0x20 | |
109 | #define HFCPCI_TRANSB2 0x02 | |
110 | #define HFCPCI_TRANSB1 0x01 | |
111 | ||
112 | /* bits in CIRM (Write) */ | |
113 | #define HFCPCI_AUX_MSK 0x07 | |
114 | #define HFCPCI_RESET 0x08 | |
115 | #define HFCPCI_B1_REV 0x40 | |
116 | #define HFCPCI_B2_REV 0x80 | |
117 | ||
118 | /* bits in INT_M1 and INT_S1 */ | |
119 | #define HFCPCI_INTS_B1TRANS 0x01 | |
120 | #define HFCPCI_INTS_B2TRANS 0x02 | |
121 | #define HFCPCI_INTS_DTRANS 0x04 | |
122 | #define HFCPCI_INTS_B1REC 0x08 | |
123 | #define HFCPCI_INTS_B2REC 0x10 | |
124 | #define HFCPCI_INTS_DREC 0x20 | |
125 | #define HFCPCI_INTS_L1STATE 0x40 | |
126 | #define HFCPCI_INTS_TIMER 0x80 | |
127 | ||
128 | /* bits in INT_M2 */ | |
129 | #define HFCPCI_PROC_TRANS 0x01 | |
130 | #define HFCPCI_GCI_I_CHG 0x02 | |
131 | #define HFCPCI_GCI_MON_REC 0x04 | |
132 | #define HFCPCI_IRQ_ENABLE 0x08 | |
133 | #define HFCPCI_PMESEL 0x80 | |
134 | ||
135 | /* bits in STATES */ | |
136 | #define HFCPCI_STATE_MSK 0x0F | |
137 | #define HFCPCI_LOAD_STATE 0x10 | |
138 | #define HFCPCI_ACTIVATE 0x20 | |
139 | #define HFCPCI_DO_ACTION 0x40 | |
140 | #define HFCPCI_NT_G2_G3 0x80 | |
141 | ||
142 | /* bits in HFCD_MST_MODE */ | |
143 | #define HFCPCI_MASTER 0x01 | |
144 | #define HFCPCI_SLAVE 0x00 | |
145 | #define HFCPCI_F0IO_POSITIV 0x02 | |
146 | #define HFCPCI_F0_NEGATIV 0x04 | |
147 | #define HFCPCI_F0_2C4 0x08 | |
148 | /* remaining bits are for codecs control */ | |
149 | ||
150 | /* bits in HFCD_SCTRL */ | |
151 | #define SCTRL_B1_ENA 0x01 | |
152 | #define SCTRL_B2_ENA 0x02 | |
153 | #define SCTRL_MODE_TE 0x00 | |
154 | #define SCTRL_MODE_NT 0x04 | |
155 | #define SCTRL_LOW_PRIO 0x08 | |
156 | #define SCTRL_SQ_ENA 0x10 | |
157 | #define SCTRL_TEST 0x20 | |
158 | #define SCTRL_NONE_CAP 0x40 | |
159 | #define SCTRL_PWR_DOWN 0x80 | |
160 | ||
161 | /* bits in SCTRL_E */ | |
162 | #define HFCPCI_AUTO_AWAKE 0x01 | |
163 | #define HFCPCI_DBIT_1 0x04 | |
164 | #define HFCPCI_IGNORE_COL 0x08 | |
165 | #define HFCPCI_CHG_B1_B2 0x80 | |
166 | ||
167 | /* bits in FIFO_EN register */ | |
168 | #define HFCPCI_FIFOEN_B1 0x03 | |
169 | #define HFCPCI_FIFOEN_B2 0x0C | |
170 | #define HFCPCI_FIFOEN_DTX 0x10 | |
171 | #define HFCPCI_FIFOEN_B1TX 0x01 | |
172 | #define HFCPCI_FIFOEN_B1RX 0x02 | |
173 | #define HFCPCI_FIFOEN_B2TX 0x04 | |
174 | #define HFCPCI_FIFOEN_B2RX 0x08 | |
175 | ||
176 | ||
177 | /* definitions of fifo memory area */ | |
178 | #define MAX_D_FRAMES 15 | |
179 | #define MAX_B_FRAMES 31 | |
180 | #define B_SUB_VAL 0x200 | |
181 | #define B_FIFO_SIZE (0x2000 - B_SUB_VAL) | |
182 | #define D_FIFO_SIZE 512 | |
183 | #define D_FREG_MASK 0xF | |
184 | ||
185 | struct zt { | |
f11d32df HH |
186 | __le16 z1; /* Z1 pointer 16 Bit */ |
187 | __le16 z2; /* Z2 pointer 16 Bit */ | |
1700fe1a KK |
188 | }; |
189 | ||
190 | struct dfifo { | |
191 | u_char data[D_FIFO_SIZE]; /* FIFO data space */ | |
192 | u_char fill1[0x20A0-D_FIFO_SIZE]; /* reserved, do not use */ | |
193 | u_char f1, f2; /* f pointers */ | |
194 | u_char fill2[0x20C0-0x20A2]; /* reserved, do not use */ | |
195 | /* mask index with D_FREG_MASK for access */ | |
196 | struct zt za[MAX_D_FRAMES+1]; | |
197 | u_char fill3[0x4000-0x2100]; /* align 16K */ | |
198 | }; | |
199 | ||
200 | struct bzfifo { | |
201 | struct zt za[MAX_B_FRAMES+1]; /* only range 0x0..0x1F allowed */ | |
202 | u_char f1, f2; /* f pointers */ | |
203 | u_char fill[0x2100-0x2082]; /* alignment */ | |
204 | }; | |
205 | ||
206 | ||
207 | union fifo_area { | |
208 | struct { | |
209 | struct dfifo d_tx; /* D-send channel */ | |
210 | struct dfifo d_rx; /* D-receive channel */ | |
211 | } d_chan; | |
212 | struct { | |
213 | u_char fill1[0x200]; | |
214 | u_char txdat_b1[B_FIFO_SIZE]; | |
215 | struct bzfifo txbz_b1; | |
216 | struct bzfifo txbz_b2; | |
217 | u_char txdat_b2[B_FIFO_SIZE]; | |
218 | u_char fill2[D_FIFO_SIZE]; | |
219 | u_char rxdat_b1[B_FIFO_SIZE]; | |
220 | struct bzfifo rxbz_b1; | |
221 | struct bzfifo rxbz_b2; | |
222 | u_char rxdat_b2[B_FIFO_SIZE]; | |
223 | } b_chans; | |
224 | u_char fill[32768]; | |
225 | }; | |
226 | ||
227 | #define Write_hfc(a, b, c) (writeb(c, (a->hw.pci_io)+b)) | |
228 | #define Read_hfc(a, b) (readb((a->hw.pci_io)+b)) |