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af69fb3a KK |
1 | /* |
2 | * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards | |
3 | * | |
4 | * Author Andreas Eversberg (jolly@eversberg.eu) | |
5 | * ported to mqueue mechanism: | |
6 | * Peter Sprenger (sprengermoving-bytes.de) | |
7 | * | |
8 | * inspired by existing hfc-pci driver: | |
9 | * Copyright 1999 by Werner Cornelius (werner@isdn-development.de) | |
10 | * Copyright 2008 by Karsten Keil (kkeil@suse.de) | |
11 | * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu) | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2, or (at your option) | |
16 | * any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | * | |
28 | * Thanks to Cologne Chip AG for this great controller! | |
29 | */ | |
30 | ||
31 | /* | |
32 | * module parameters: | |
33 | * type: | |
34 | * By default (0), the card is automatically detected. | |
35 | * Or use the following combinations: | |
36 | * Bit 0-7 = 0x00001 = HFC-E1 (1 port) | |
37 | * or Bit 0-7 = 0x00004 = HFC-4S (4 ports) | |
38 | * or Bit 0-7 = 0x00008 = HFC-8S (8 ports) | |
39 | * Bit 8 = 0x00100 = uLaw (instead of aLaw) | |
40 | * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware | |
41 | * Bit 10 = spare | |
42 | * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto) | |
43 | * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto) | |
44 | * Bit 13 = spare | |
45 | * Bit 14 = 0x04000 = Use external ram (128K) | |
46 | * Bit 15 = 0x08000 = Use external ram (512K) | |
47 | * Bit 16 = 0x10000 = Use 64 timeslots instead of 32 | |
48 | * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else | |
49 | * Bit 18 = spare | |
50 | * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog) | |
51 | * (all other bits are reserved and shall be 0) | |
52 | * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM | |
53 | * bus (PCM master) | |
54 | * | |
55 | * port: (optional or required for all ports on all installed cards) | |
56 | * HFC-4S/HFC-8S only bits: | |
57 | * Bit 0 = 0x001 = Use master clock for this S/T interface | |
58 | * (ony once per chip). | |
59 | * Bit 1 = 0x002 = transmitter line setup (non capacitive mode) | |
60 | * Don't use this unless you know what you are doing! | |
61 | * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing) | |
62 | * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock | |
63 | * received from port 1 | |
64 | * | |
65 | * HFC-E1 only bits: | |
66 | * Bit 0 = 0x0001 = interface: 0=copper, 1=optical | |
67 | * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode) | |
68 | * Bit 2 = 0x0004 = Report LOS | |
69 | * Bit 3 = 0x0008 = Report AIS | |
70 | * Bit 4 = 0x0010 = Report SLIP | |
71 | * Bit 5 = 0x0020 = Report RDI | |
72 | * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame | |
73 | * mode instead. | |
74 | * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. | |
75 | * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. | |
76 | * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. | |
77 | * (E1 only) | |
78 | * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0 | |
79 | * for default. | |
80 | * (all other bits are reserved and shall be 0) | |
81 | * | |
82 | * debug: | |
83 | * NOTE: only one debug value must be given for all cards | |
84 | * enable debugging (see hfc_multi.h for debug options) | |
85 | * | |
86 | * poll: | |
87 | * NOTE: only one poll value must be given for all cards | |
88 | * Give the number of samples for each fifo process. | |
89 | * By default 128 is used. Decrease to reduce delay, increase to | |
90 | * reduce cpu load. If unsure, don't mess with it! | |
91 | * Valid is 8, 16, 32, 64, 128, 256. | |
92 | * | |
93 | * pcm: | |
94 | * NOTE: only one pcm value must be given for every card. | |
95 | * The PCM bus id tells the mISDNdsp module about the connected PCM bus. | |
96 | * By default (0), the PCM bus id is 100 for the card that is PCM master. | |
97 | * If multiple cards are PCM master (because they are not interconnected), | |
98 | * each card with PCM master will have increasing PCM id. | |
99 | * All PCM busses with the same ID are expected to be connected and have | |
100 | * common time slots slots. | |
101 | * Only one chip of the PCM bus must be master, the others slave. | |
102 | * -1 means no support of PCM bus not even. | |
103 | * Omit this value, if all cards are interconnected or none is connected. | |
104 | * If unsure, don't give this parameter. | |
105 | * | |
106 | * dslot: | |
107 | * NOTE: only one poll value must be given for every card. | |
108 | * Also this value must be given for non-E1 cards. If omitted, the E1 | |
109 | * card has D-channel on time slot 16, which is default. | |
110 | * If 1..15 or 17..31, an alternate time slot is used for D-channel. | |
111 | * In this case, the application must be able to handle this. | |
112 | * If -1 is given, the D-channel is disabled and all 31 slots can be used | |
113 | * for B-channel. (only for specific applications) | |
114 | * If you don't know how to use it, you don't need it! | |
115 | * | |
116 | * iomode: | |
117 | * NOTE: only one mode value must be given for every card. | |
118 | * -> See hfc_multi.h for HFC_IO_MODE_* values | |
119 | * By default, the IO mode is pci memory IO (MEMIO). | |
120 | * Some cards requre specific IO mode, so it cannot be changed. | |
121 | * It may be usefull to set IO mode to register io (REGIO) to solve | |
122 | * PCI bridge problems. | |
123 | * If unsure, don't give this parameter. | |
124 | * | |
125 | * clockdelay_nt: | |
126 | * NOTE: only one clockdelay_nt value must be given once for all cards. | |
127 | * Give the value of the clock control register (A_ST_CLK_DLY) | |
128 | * of the S/T interfaces in NT mode. | |
129 | * This register is needed for the TBR3 certification, so don't change it. | |
130 | * | |
131 | * clockdelay_te: | |
132 | * NOTE: only one clockdelay_te value must be given once | |
133 | * Give the value of the clock control register (A_ST_CLK_DLY) | |
134 | * of the S/T interfaces in TE mode. | |
135 | * This register is needed for the TBR3 certification, so don't change it. | |
3bd69ad1 AE |
136 | * |
137 | * clock: | |
1b36c78f | 138 | * NOTE: only one clock value must be given once |
3bd69ad1 AE |
139 | * Selects interface with clock source for mISDN and applications. |
140 | * Set to card number starting with 1. Set to -1 to disable. | |
141 | * By default, the first card is used as clock source. | |
af69fb3a KK |
142 | */ |
143 | ||
144 | /* | |
145 | * debug register access (never use this, it will flood your system log) | |
146 | * #define HFC_REGISTER_DEBUG | |
147 | */ | |
148 | ||
69e656cc | 149 | #define HFC_MULTI_VERSION "2.03" |
af69fb3a KK |
150 | |
151 | #include <linux/module.h> | |
152 | #include <linux/pci.h> | |
153 | #include <linux/delay.h> | |
154 | #include <linux/mISDNhw.h> | |
155 | #include <linux/mISDNdsp.h> | |
156 | ||
157 | /* | |
158 | #define IRQCOUNT_DEBUG | |
159 | #define IRQ_DEBUG | |
160 | */ | |
161 | ||
162 | #include "hfc_multi.h" | |
163 | #ifdef ECHOPREP | |
164 | #include "gaintab.h" | |
165 | #endif | |
166 | ||
167 | #define MAX_CARDS 8 | |
168 | #define MAX_PORTS (8 * MAX_CARDS) | |
169 | ||
170 | static LIST_HEAD(HFClist); | |
171 | static spinlock_t HFClock; /* global hfc list lock */ | |
172 | ||
173 | static void ph_state_change(struct dchannel *); | |
af69fb3a KK |
174 | |
175 | static struct hfc_multi *syncmaster; | |
5b834354 | 176 | static int plxsd_master; /* if we have a master card (yet) */ |
af69fb3a | 177 | static spinlock_t plx_lock; /* may not acquire other lock inside */ |
af69fb3a KK |
178 | |
179 | #define TYP_E1 1 | |
180 | #define TYP_4S 4 | |
181 | #define TYP_8S 8 | |
182 | ||
183 | static int poll_timer = 6; /* default = 128 samples = 16ms */ | |
184 | /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */ | |
185 | static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 }; | |
186 | #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */ | |
187 | #define CLKDEL_NT 0x6c /* CLKDEL in NT mode | |
188 | (0x60 MUST be included!) */ | |
af69fb3a KK |
189 | |
190 | #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */ | |
191 | #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */ | |
192 | #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */ | |
193 | ||
194 | /* | |
195 | * module stuff | |
196 | */ | |
197 | ||
198 | static uint type[MAX_CARDS]; | |
3bd69ad1 AE |
199 | static int pcm[MAX_CARDS]; |
200 | static int dslot[MAX_CARDS]; | |
af69fb3a KK |
201 | static uint iomode[MAX_CARDS]; |
202 | static uint port[MAX_PORTS]; | |
203 | static uint debug; | |
204 | static uint poll; | |
3bd69ad1 | 205 | static int clock; |
af69fb3a KK |
206 | static uint timer; |
207 | static uint clockdelay_te = CLKDEL_TE; | |
208 | static uint clockdelay_nt = CLKDEL_NT; | |
209 | ||
210 | static int HFC_cnt, Port_cnt, PCM_cnt = 99; | |
211 | ||
212 | MODULE_AUTHOR("Andreas Eversberg"); | |
213 | MODULE_LICENSE("GPL"); | |
69e656cc | 214 | MODULE_VERSION(HFC_MULTI_VERSION); |
af69fb3a KK |
215 | module_param(debug, uint, S_IRUGO | S_IWUSR); |
216 | module_param(poll, uint, S_IRUGO | S_IWUSR); | |
3bd69ad1 | 217 | module_param(clock, int, S_IRUGO | S_IWUSR); |
af69fb3a KK |
218 | module_param(timer, uint, S_IRUGO | S_IWUSR); |
219 | module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR); | |
220 | module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR); | |
221 | module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR); | |
3bd69ad1 AE |
222 | module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR); |
223 | module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR); | |
af69fb3a KK |
224 | module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR); |
225 | module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR); | |
226 | ||
227 | #ifdef HFC_REGISTER_DEBUG | |
228 | #define HFC_outb(hc, reg, val) \ | |
229 | (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) | |
230 | #define HFC_outb_nodebug(hc, reg, val) \ | |
231 | (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) | |
232 | #define HFC_inb(hc, reg) \ | |
233 | (hc->HFC_inb(hc, reg, __func__, __LINE__)) | |
234 | #define HFC_inb_nodebug(hc, reg) \ | |
235 | (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__)) | |
236 | #define HFC_inw(hc, reg) \ | |
237 | (hc->HFC_inw(hc, reg, __func__, __LINE__)) | |
238 | #define HFC_inw_nodebug(hc, reg) \ | |
239 | (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__)) | |
240 | #define HFC_wait(hc) \ | |
241 | (hc->HFC_wait(hc, __func__, __LINE__)) | |
242 | #define HFC_wait_nodebug(hc) \ | |
243 | (hc->HFC_wait_nodebug(hc, __func__, __LINE__)) | |
244 | #else | |
245 | #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) | |
246 | #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) | |
247 | #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg)) | |
248 | #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg)) | |
249 | #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg)) | |
250 | #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg)) | |
251 | #define HFC_wait(hc) (hc->HFC_wait(hc)) | |
252 | #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc)) | |
253 | #endif | |
254 | ||
255 | /* HFC_IO_MODE_PCIMEM */ | |
256 | static void | |
257 | #ifdef HFC_REGISTER_DEBUG | |
258 | HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, | |
259 | const char *function, int line) | |
260 | #else | |
261 | HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) | |
262 | #endif | |
263 | { | |
264 | writeb(val, (hc->pci_membase)+reg); | |
265 | } | |
266 | static u_char | |
267 | #ifdef HFC_REGISTER_DEBUG | |
268 | HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
269 | #else | |
270 | HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) | |
271 | #endif | |
272 | { | |
273 | return readb((hc->pci_membase)+reg); | |
274 | } | |
275 | static u_short | |
276 | #ifdef HFC_REGISTER_DEBUG | |
277 | HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
278 | #else | |
279 | HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) | |
280 | #endif | |
281 | { | |
282 | return readw((hc->pci_membase)+reg); | |
283 | } | |
284 | static void | |
285 | #ifdef HFC_REGISTER_DEBUG | |
286 | HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line) | |
287 | #else | |
288 | HFC_wait_pcimem(struct hfc_multi *hc) | |
289 | #endif | |
290 | { | |
291 | while (readb((hc->pci_membase)+R_STATUS) & V_BUSY); | |
292 | } | |
293 | ||
294 | /* HFC_IO_MODE_REGIO */ | |
295 | static void | |
296 | #ifdef HFC_REGISTER_DEBUG | |
297 | HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, | |
298 | const char *function, int line) | |
299 | #else | |
300 | HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) | |
301 | #endif | |
302 | { | |
303 | outb(reg, (hc->pci_iobase)+4); | |
304 | outb(val, hc->pci_iobase); | |
305 | } | |
306 | static u_char | |
307 | #ifdef HFC_REGISTER_DEBUG | |
308 | HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
309 | #else | |
310 | HFC_inb_regio(struct hfc_multi *hc, u_char reg) | |
311 | #endif | |
312 | { | |
313 | outb(reg, (hc->pci_iobase)+4); | |
314 | return inb(hc->pci_iobase); | |
315 | } | |
316 | static u_short | |
317 | #ifdef HFC_REGISTER_DEBUG | |
318 | HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
319 | #else | |
320 | HFC_inw_regio(struct hfc_multi *hc, u_char reg) | |
321 | #endif | |
322 | { | |
323 | outb(reg, (hc->pci_iobase)+4); | |
324 | return inw(hc->pci_iobase); | |
325 | } | |
326 | static void | |
327 | #ifdef HFC_REGISTER_DEBUG | |
328 | HFC_wait_regio(struct hfc_multi *hc, const char *function, int line) | |
329 | #else | |
330 | HFC_wait_regio(struct hfc_multi *hc) | |
331 | #endif | |
332 | { | |
333 | outb(R_STATUS, (hc->pci_iobase)+4); | |
334 | while (inb(hc->pci_iobase) & V_BUSY); | |
335 | } | |
336 | ||
337 | #ifdef HFC_REGISTER_DEBUG | |
338 | static void | |
339 | HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, | |
340 | const char *function, int line) | |
341 | { | |
342 | char regname[256] = "", bits[9] = "xxxxxxxx"; | |
343 | int i; | |
344 | ||
345 | i = -1; | |
346 | while (hfc_register_names[++i].name) { | |
347 | if (hfc_register_names[i].reg == reg) | |
348 | strcat(regname, hfc_register_names[i].name); | |
349 | } | |
350 | if (regname[0] == '\0') | |
351 | strcpy(regname, "register"); | |
352 | ||
353 | bits[7] = '0'+(!!(val&1)); | |
354 | bits[6] = '0'+(!!(val&2)); | |
355 | bits[5] = '0'+(!!(val&4)); | |
356 | bits[4] = '0'+(!!(val&8)); | |
357 | bits[3] = '0'+(!!(val&16)); | |
358 | bits[2] = '0'+(!!(val&32)); | |
359 | bits[1] = '0'+(!!(val&64)); | |
360 | bits[0] = '0'+(!!(val&128)); | |
361 | printk(KERN_DEBUG | |
362 | "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n", | |
363 | hc->id, reg, regname, val, bits, function, line); | |
364 | HFC_outb_nodebug(hc, reg, val); | |
365 | } | |
366 | static u_char | |
367 | HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
368 | { | |
369 | char regname[256] = "", bits[9] = "xxxxxxxx"; | |
370 | u_char val = HFC_inb_nodebug(hc, reg); | |
371 | int i; | |
372 | ||
373 | i = 0; | |
374 | while (hfc_register_names[i++].name) | |
375 | ; | |
376 | while (hfc_register_names[++i].name) { | |
377 | if (hfc_register_names[i].reg == reg) | |
378 | strcat(regname, hfc_register_names[i].name); | |
379 | } | |
380 | if (regname[0] == '\0') | |
381 | strcpy(regname, "register"); | |
382 | ||
383 | bits[7] = '0'+(!!(val&1)); | |
384 | bits[6] = '0'+(!!(val&2)); | |
385 | bits[5] = '0'+(!!(val&4)); | |
386 | bits[4] = '0'+(!!(val&8)); | |
387 | bits[3] = '0'+(!!(val&16)); | |
388 | bits[2] = '0'+(!!(val&32)); | |
389 | bits[1] = '0'+(!!(val&64)); | |
390 | bits[0] = '0'+(!!(val&128)); | |
391 | printk(KERN_DEBUG | |
392 | "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n", | |
393 | hc->id, reg, regname, val, bits, function, line); | |
394 | return val; | |
395 | } | |
396 | static u_short | |
397 | HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
398 | { | |
399 | char regname[256] = ""; | |
400 | u_short val = HFC_inw_nodebug(hc, reg); | |
401 | int i; | |
402 | ||
403 | i = 0; | |
404 | while (hfc_register_names[i++].name) | |
405 | ; | |
406 | while (hfc_register_names[++i].name) { | |
407 | if (hfc_register_names[i].reg == reg) | |
408 | strcat(regname, hfc_register_names[i].name); | |
409 | } | |
410 | if (regname[0] == '\0') | |
411 | strcpy(regname, "register"); | |
412 | ||
413 | printk(KERN_DEBUG | |
414 | "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n", | |
415 | hc->id, reg, regname, val, function, line); | |
416 | return val; | |
417 | } | |
418 | static void | |
419 | HFC_wait_debug(struct hfc_multi *hc, const char *function, int line) | |
420 | { | |
421 | printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n", | |
422 | hc->id, function, line); | |
423 | HFC_wait_nodebug(hc); | |
424 | } | |
425 | #endif | |
426 | ||
427 | /* write fifo data (REGIO) */ | |
5b834354 | 428 | static void |
af69fb3a KK |
429 | write_fifo_regio(struct hfc_multi *hc, u_char *data, int len) |
430 | { | |
431 | outb(A_FIFO_DATA0, (hc->pci_iobase)+4); | |
432 | while (len>>2) { | |
b3e0aeeb | 433 | outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase); |
af69fb3a KK |
434 | data += 4; |
435 | len -= 4; | |
436 | } | |
437 | while (len>>1) { | |
b3e0aeeb | 438 | outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase); |
af69fb3a KK |
439 | data += 2; |
440 | len -= 2; | |
441 | } | |
442 | while (len) { | |
443 | outb(*data, hc->pci_iobase); | |
444 | data++; | |
445 | len--; | |
446 | } | |
447 | } | |
448 | /* write fifo data (PCIMEM) */ | |
5b834354 | 449 | static void |
af69fb3a KK |
450 | write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) |
451 | { | |
452 | while (len>>2) { | |
b3e0aeeb KK |
453 | writel(cpu_to_le32(*(u32 *)data), |
454 | hc->pci_membase + A_FIFO_DATA0); | |
af69fb3a KK |
455 | data += 4; |
456 | len -= 4; | |
457 | } | |
458 | while (len>>1) { | |
b3e0aeeb KK |
459 | writew(cpu_to_le16(*(u16 *)data), |
460 | hc->pci_membase + A_FIFO_DATA0); | |
af69fb3a KK |
461 | data += 2; |
462 | len -= 2; | |
463 | } | |
464 | while (len) { | |
b3e0aeeb | 465 | writeb(*data, hc->pci_membase + A_FIFO_DATA0); |
af69fb3a KK |
466 | data++; |
467 | len--; | |
468 | } | |
469 | } | |
470 | /* read fifo data (REGIO) */ | |
5b834354 | 471 | static void |
af69fb3a KK |
472 | read_fifo_regio(struct hfc_multi *hc, u_char *data, int len) |
473 | { | |
474 | outb(A_FIFO_DATA0, (hc->pci_iobase)+4); | |
475 | while (len>>2) { | |
b3e0aeeb | 476 | *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase)); |
af69fb3a KK |
477 | data += 4; |
478 | len -= 4; | |
479 | } | |
480 | while (len>>1) { | |
b3e0aeeb | 481 | *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase)); |
af69fb3a KK |
482 | data += 2; |
483 | len -= 2; | |
484 | } | |
485 | while (len) { | |
486 | *data = inb(hc->pci_iobase); | |
487 | data++; | |
488 | len--; | |
489 | } | |
490 | } | |
491 | ||
492 | /* read fifo data (PCIMEM) */ | |
5b834354 | 493 | static void |
af69fb3a KK |
494 | read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) |
495 | { | |
496 | while (len>>2) { | |
497 | *(u32 *)data = | |
b3e0aeeb | 498 | le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0)); |
af69fb3a KK |
499 | data += 4; |
500 | len -= 4; | |
501 | } | |
502 | while (len>>1) { | |
503 | *(u16 *)data = | |
b3e0aeeb | 504 | le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0)); |
af69fb3a KK |
505 | data += 2; |
506 | len -= 2; | |
507 | } | |
508 | while (len) { | |
b3e0aeeb | 509 | *data = readb(hc->pci_membase + A_FIFO_DATA0); |
af69fb3a KK |
510 | data++; |
511 | len--; | |
512 | } | |
513 | } | |
514 | ||
515 | ||
516 | static void | |
517 | enable_hwirq(struct hfc_multi *hc) | |
518 | { | |
519 | hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN; | |
520 | HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); | |
521 | } | |
522 | ||
523 | static void | |
524 | disable_hwirq(struct hfc_multi *hc) | |
525 | { | |
526 | hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN); | |
527 | HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); | |
528 | } | |
529 | ||
530 | #define NUM_EC 2 | |
531 | #define MAX_TDM_CHAN 32 | |
532 | ||
533 | ||
534 | inline void | |
535 | enablepcibridge(struct hfc_multi *c) | |
536 | { | |
537 | HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */ | |
538 | } | |
539 | ||
540 | inline void | |
541 | disablepcibridge(struct hfc_multi *c) | |
542 | { | |
543 | HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */ | |
544 | } | |
545 | ||
546 | inline unsigned char | |
547 | readpcibridge(struct hfc_multi *hc, unsigned char address) | |
548 | { | |
549 | unsigned short cipv; | |
550 | unsigned char data; | |
551 | ||
552 | if (!hc->pci_iobase) | |
553 | return 0; | |
554 | ||
555 | /* slow down a PCI read access by 1 PCI clock cycle */ | |
556 | HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/ | |
557 | ||
558 | if (address == 0) | |
559 | cipv = 0x4000; | |
560 | else | |
561 | cipv = 0x5800; | |
562 | ||
563 | /* select local bridge port address by writing to CIP port */ | |
564 | /* data = HFC_inb(c, cipv); * was _io before */ | |
565 | outw(cipv, hc->pci_iobase + 4); | |
566 | data = inb(hc->pci_iobase); | |
567 | ||
568 | /* restore R_CTRL for normal PCI read cycle speed */ | |
569 | HFC_outb(hc, R_CTRL, 0x0); /* was _io before */ | |
570 | ||
571 | return data; | |
572 | } | |
573 | ||
574 | inline void | |
575 | writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data) | |
576 | { | |
577 | unsigned short cipv; | |
578 | unsigned int datav; | |
579 | ||
580 | if (!hc->pci_iobase) | |
581 | return; | |
582 | ||
583 | if (address == 0) | |
584 | cipv = 0x4000; | |
585 | else | |
586 | cipv = 0x5800; | |
587 | ||
588 | /* select local bridge port address by writing to CIP port */ | |
589 | outw(cipv, hc->pci_iobase + 4); | |
590 | /* define a 32 bit dword with 4 identical bytes for write sequence */ | |
591 | datav = data | ((__u32) data << 8) | ((__u32) data << 16) | | |
592 | ((__u32) data << 24); | |
593 | ||
594 | /* | |
595 | * write this 32 bit dword to the bridge data port | |
596 | * this will initiate a write sequence of up to 4 writes to the same | |
597 | * address on the local bus interface the number of write accesses | |
598 | * is undefined but >=1 and depends on the next PCI transaction | |
599 | * during write sequence on the local bus | |
600 | */ | |
601 | outl(datav, hc->pci_iobase); | |
602 | } | |
603 | ||
604 | inline void | |
605 | cpld_set_reg(struct hfc_multi *hc, unsigned char reg) | |
606 | { | |
607 | /* Do data pin read low byte */ | |
608 | HFC_outb(hc, R_GPIO_OUT1, reg); | |
609 | } | |
610 | ||
611 | inline void | |
612 | cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) | |
613 | { | |
614 | cpld_set_reg(hc, reg); | |
615 | ||
616 | enablepcibridge(hc); | |
617 | writepcibridge(hc, 1, val); | |
618 | disablepcibridge(hc); | |
619 | ||
620 | return; | |
621 | } | |
622 | ||
623 | inline unsigned char | |
624 | cpld_read_reg(struct hfc_multi *hc, unsigned char reg) | |
625 | { | |
626 | unsigned char bytein; | |
627 | ||
628 | cpld_set_reg(hc, reg); | |
629 | ||
630 | /* Do data pin read low byte */ | |
631 | HFC_outb(hc, R_GPIO_OUT1, reg); | |
632 | ||
633 | enablepcibridge(hc); | |
634 | bytein = readpcibridge(hc, 1); | |
635 | disablepcibridge(hc); | |
636 | ||
637 | return bytein; | |
638 | } | |
639 | ||
640 | inline void | |
641 | vpm_write_address(struct hfc_multi *hc, unsigned short addr) | |
642 | { | |
643 | cpld_write_reg(hc, 0, 0xff & addr); | |
644 | cpld_write_reg(hc, 1, 0x01 & (addr >> 8)); | |
645 | } | |
646 | ||
647 | inline unsigned short | |
648 | vpm_read_address(struct hfc_multi *c) | |
649 | { | |
650 | unsigned short addr; | |
651 | unsigned short highbit; | |
652 | ||
653 | addr = cpld_read_reg(c, 0); | |
654 | highbit = cpld_read_reg(c, 1); | |
655 | ||
656 | addr = addr | (highbit << 8); | |
657 | ||
658 | return addr & 0x1ff; | |
659 | } | |
660 | ||
661 | inline unsigned char | |
662 | vpm_in(struct hfc_multi *c, int which, unsigned short addr) | |
663 | { | |
664 | unsigned char res; | |
665 | ||
666 | vpm_write_address(c, addr); | |
667 | ||
668 | if (!which) | |
669 | cpld_set_reg(c, 2); | |
670 | else | |
671 | cpld_set_reg(c, 3); | |
672 | ||
673 | enablepcibridge(c); | |
674 | res = readpcibridge(c, 1); | |
675 | disablepcibridge(c); | |
676 | ||
677 | cpld_set_reg(c, 0); | |
678 | ||
679 | return res; | |
680 | } | |
681 | ||
682 | inline void | |
683 | vpm_out(struct hfc_multi *c, int which, unsigned short addr, | |
684 | unsigned char data) | |
685 | { | |
686 | vpm_write_address(c, addr); | |
687 | ||
688 | enablepcibridge(c); | |
689 | ||
690 | if (!which) | |
691 | cpld_set_reg(c, 2); | |
692 | else | |
693 | cpld_set_reg(c, 3); | |
694 | ||
695 | writepcibridge(c, 1, data); | |
696 | ||
697 | cpld_set_reg(c, 0); | |
698 | ||
699 | disablepcibridge(c); | |
700 | ||
701 | { | |
702 | unsigned char regin; | |
703 | regin = vpm_in(c, which, addr); | |
704 | if (regin != data) | |
705 | printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back " | |
706 | "0x%x\n", data, addr, regin); | |
707 | } | |
708 | ||
709 | } | |
710 | ||
711 | ||
5b834354 | 712 | static void |
af69fb3a KK |
713 | vpm_init(struct hfc_multi *wc) |
714 | { | |
715 | unsigned char reg; | |
716 | unsigned int mask; | |
717 | unsigned int i, x, y; | |
718 | unsigned int ver; | |
719 | ||
720 | for (x = 0; x < NUM_EC; x++) { | |
721 | /* Setup GPIO's */ | |
722 | if (!x) { | |
723 | ver = vpm_in(wc, x, 0x1a0); | |
724 | printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver); | |
725 | } | |
726 | ||
727 | for (y = 0; y < 4; y++) { | |
728 | vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */ | |
729 | vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */ | |
730 | vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */ | |
731 | } | |
732 | ||
733 | /* Setup TDM path - sets fsync and tdm_clk as inputs */ | |
734 | reg = vpm_in(wc, x, 0x1a3); /* misc_con */ | |
735 | vpm_out(wc, x, 0x1a3, reg & ~2); | |
736 | ||
737 | /* Setup Echo length (256 taps) */ | |
738 | vpm_out(wc, x, 0x022, 1); | |
739 | vpm_out(wc, x, 0x023, 0xff); | |
740 | ||
741 | /* Setup timeslots */ | |
742 | vpm_out(wc, x, 0x02f, 0x00); | |
743 | mask = 0x02020202 << (x * 4); | |
744 | ||
745 | /* Setup the tdm channel masks for all chips */ | |
746 | for (i = 0; i < 4; i++) | |
747 | vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff); | |
748 | ||
749 | /* Setup convergence rate */ | |
750 | printk(KERN_DEBUG "VPM: A-law mode\n"); | |
751 | reg = 0x00 | 0x10 | 0x01; | |
752 | vpm_out(wc, x, 0x20, reg); | |
753 | printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg); | |
754 | /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */ | |
755 | ||
756 | vpm_out(wc, x, 0x24, 0x02); | |
757 | reg = vpm_in(wc, x, 0x24); | |
758 | printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg); | |
759 | ||
760 | /* Initialize echo cans */ | |
761 | for (i = 0; i < MAX_TDM_CHAN; i++) { | |
762 | if (mask & (0x00000001 << i)) | |
763 | vpm_out(wc, x, i, 0x00); | |
764 | } | |
765 | ||
766 | /* | |
767 | * ARM arch at least disallows a udelay of | |
768 | * more than 2ms... it gives a fake "__bad_udelay" | |
769 | * reference at link-time. | |
770 | * long delays in kernel code are pretty sucky anyway | |
771 | * for now work around it using 5 x 2ms instead of 1 x 10ms | |
772 | */ | |
773 | ||
774 | udelay(2000); | |
775 | udelay(2000); | |
776 | udelay(2000); | |
777 | udelay(2000); | |
778 | udelay(2000); | |
779 | ||
780 | /* Put in bypass mode */ | |
781 | for (i = 0; i < MAX_TDM_CHAN; i++) { | |
782 | if (mask & (0x00000001 << i)) | |
783 | vpm_out(wc, x, i, 0x01); | |
784 | } | |
785 | ||
786 | /* Enable bypass */ | |
787 | for (i = 0; i < MAX_TDM_CHAN; i++) { | |
788 | if (mask & (0x00000001 << i)) | |
789 | vpm_out(wc, x, 0x78 + i, 0x01); | |
790 | } | |
791 | ||
792 | } | |
793 | } | |
794 | ||
047ce8f2 | 795 | #ifdef UNUSED |
5b834354 | 796 | static void |
af69fb3a KK |
797 | vpm_check(struct hfc_multi *hctmp) |
798 | { | |
799 | unsigned char gpi2; | |
800 | ||
801 | gpi2 = HFC_inb(hctmp, R_GPI_IN2); | |
802 | ||
803 | if ((gpi2 & 0x3) != 0x3) | |
804 | printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2); | |
805 | } | |
047ce8f2 | 806 | #endif /* UNUSED */ |
af69fb3a KK |
807 | |
808 | ||
809 | /* | |
810 | * Interface to enable/disable the HW Echocan | |
811 | * | |
812 | * these functions are called within a spin_lock_irqsave on | |
813 | * the channel instance lock, so we are not disturbed by irqs | |
814 | * | |
815 | * we can later easily change the interface to make other | |
816 | * things configurable, for now we configure the taps | |
817 | * | |
818 | */ | |
819 | ||
5b834354 | 820 | static void |
af69fb3a KK |
821 | vpm_echocan_on(struct hfc_multi *hc, int ch, int taps) |
822 | { | |
823 | unsigned int timeslot; | |
824 | unsigned int unit; | |
825 | struct bchannel *bch = hc->chan[ch].bch; | |
826 | #ifdef TXADJ | |
827 | int txadj = -4; | |
828 | struct sk_buff *skb; | |
829 | #endif | |
830 | if (hc->chan[ch].protocol != ISDN_P_B_RAW) | |
831 | return; | |
832 | ||
833 | if (!bch) | |
834 | return; | |
835 | ||
836 | #ifdef TXADJ | |
837 | skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, | |
838 | sizeof(int), &txadj, GFP_ATOMIC); | |
839 | if (skb) | |
840 | recv_Bchannel_skb(bch, skb); | |
841 | #endif | |
842 | ||
843 | timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; | |
844 | unit = ch % 4; | |
845 | ||
846 | printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n", | |
847 | taps, timeslot); | |
848 | ||
849 | vpm_out(hc, unit, timeslot, 0x7e); | |
850 | } | |
851 | ||
5b834354 | 852 | static void |
af69fb3a KK |
853 | vpm_echocan_off(struct hfc_multi *hc, int ch) |
854 | { | |
855 | unsigned int timeslot; | |
856 | unsigned int unit; | |
857 | struct bchannel *bch = hc->chan[ch].bch; | |
858 | #ifdef TXADJ | |
859 | int txadj = 0; | |
860 | struct sk_buff *skb; | |
861 | #endif | |
862 | ||
863 | if (hc->chan[ch].protocol != ISDN_P_B_RAW) | |
864 | return; | |
865 | ||
866 | if (!bch) | |
867 | return; | |
868 | ||
869 | #ifdef TXADJ | |
870 | skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, | |
871 | sizeof(int), &txadj, GFP_ATOMIC); | |
872 | if (skb) | |
873 | recv_Bchannel_skb(bch, skb); | |
874 | #endif | |
875 | ||
876 | timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; | |
877 | unit = ch % 4; | |
878 | ||
879 | printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n", | |
880 | timeslot); | |
881 | /* FILLME */ | |
882 | vpm_out(hc, unit, timeslot, 0x01); | |
883 | } | |
884 | ||
885 | ||
886 | /* | |
887 | * Speech Design resync feature | |
888 | * NOTE: This is called sometimes outside interrupt handler. | |
889 | * We must lock irqsave, so no other interrupt (other card) will occurr! | |
890 | * Also multiple interrupts may nest, so must lock each access (lists, card)! | |
891 | */ | |
892 | static inline void | |
893 | hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) | |
894 | { | |
bcf91745 | 895 | struct hfc_multi *hc, *next, *pcmmaster = NULL; |
c31655fc HE |
896 | void __iomem *plx_acc_32; |
897 | u_int pv; | |
af69fb3a KK |
898 | u_long flags; |
899 | ||
900 | spin_lock_irqsave(&HFClock, flags); | |
901 | spin_lock(&plx_lock); /* must be locked inside other locks */ | |
902 | ||
903 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
904 | printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n", | |
905 | __func__, syncmaster); | |
906 | ||
907 | /* select new master */ | |
908 | if (newmaster) { | |
909 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
910 | printk(KERN_DEBUG "using provided controller\n"); | |
911 | } else { | |
912 | list_for_each_entry_safe(hc, next, &HFClist, list) { | |
913 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
914 | if (hc->syncronized) { | |
915 | newmaster = hc; | |
916 | break; | |
917 | } | |
918 | } | |
919 | } | |
920 | } | |
921 | ||
922 | /* Disable sync of all cards */ | |
923 | list_for_each_entry_safe(hc, next, &HFClist, list) { | |
924 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
c31655fc | 925 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
926 | pv = readl(plx_acc_32); |
927 | pv &= ~PLX_SYNC_O_EN; | |
928 | writel(pv, plx_acc_32); | |
929 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { | |
930 | pcmmaster = hc; | |
931 | if (hc->type == 1) { | |
932 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
933 | printk(KERN_DEBUG | |
934 | "Schedule SYNC_I\n"); | |
935 | hc->e1_resync |= 1; /* get SYNC_I */ | |
936 | } | |
937 | } | |
938 | } | |
939 | } | |
940 | ||
941 | if (newmaster) { | |
942 | hc = newmaster; | |
943 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
944 | printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " | |
945 | "interface.\n", hc->id, hc); | |
946 | /* Enable new sync master */ | |
c31655fc | 947 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
948 | pv = readl(plx_acc_32); |
949 | pv |= PLX_SYNC_O_EN; | |
950 | writel(pv, plx_acc_32); | |
951 | /* switch to jatt PLL, if not disabled by RX_SYNC */ | |
952 | if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) { | |
953 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
954 | printk(KERN_DEBUG "Schedule jatt PLL\n"); | |
955 | hc->e1_resync |= 2; /* switch to jatt */ | |
956 | } | |
957 | } else { | |
958 | if (pcmmaster) { | |
959 | hc = pcmmaster; | |
960 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
961 | printk(KERN_DEBUG | |
962 | "id=%d (0x%p) = PCM master syncronized " | |
963 | "with QUARTZ\n", hc->id, hc); | |
964 | if (hc->type == 1) { | |
965 | /* Use the crystal clock for the PCM | |
966 | master card */ | |
967 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
968 | printk(KERN_DEBUG | |
969 | "Schedule QUARTZ for HFC-E1\n"); | |
970 | hc->e1_resync |= 4; /* switch quartz */ | |
971 | } else { | |
972 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
973 | printk(KERN_DEBUG | |
974 | "QUARTZ is automatically " | |
975 | "enabled by HFC-%dS\n", hc->type); | |
976 | } | |
c31655fc | 977 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
978 | pv = readl(plx_acc_32); |
979 | pv |= PLX_SYNC_O_EN; | |
980 | writel(pv, plx_acc_32); | |
981 | } else | |
982 | if (!rm) | |
983 | printk(KERN_ERR "%s no pcm master, this MUST " | |
984 | "not happen!\n", __func__); | |
985 | } | |
986 | syncmaster = newmaster; | |
987 | ||
988 | spin_unlock(&plx_lock); | |
989 | spin_unlock_irqrestore(&HFClock, flags); | |
990 | } | |
991 | ||
992 | /* This must be called AND hc must be locked irqsave!!! */ | |
993 | inline void | |
994 | plxsd_checksync(struct hfc_multi *hc, int rm) | |
995 | { | |
996 | if (hc->syncronized) { | |
997 | if (syncmaster == NULL) { | |
998 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
999 | printk(KERN_WARNING "%s: GOT sync on card %d" | |
1000 | " (id=%d)\n", __func__, hc->id + 1, | |
1001 | hc->id); | |
1002 | hfcmulti_resync(hc, hc, rm); | |
1003 | } | |
1004 | } else { | |
1005 | if (syncmaster == hc) { | |
1006 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1007 | printk(KERN_WARNING "%s: LOST sync on card %d" | |
1008 | " (id=%d)\n", __func__, hc->id + 1, | |
1009 | hc->id); | |
1010 | hfcmulti_resync(hc, NULL, rm); | |
1011 | } | |
1012 | } | |
1013 | } | |
1014 | ||
1015 | ||
1016 | /* | |
1017 | * free hardware resources used by driver | |
1018 | */ | |
1019 | static void | |
1020 | release_io_hfcmulti(struct hfc_multi *hc) | |
1021 | { | |
c31655fc HE |
1022 | void __iomem *plx_acc_32; |
1023 | u_int pv; | |
af69fb3a KK |
1024 | u_long plx_flags; |
1025 | ||
1026 | if (debug & DEBUG_HFCMULTI_INIT) | |
1027 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
1028 | ||
1029 | /* soft reset also masks all interrupts */ | |
1030 | hc->hw.r_cirm |= V_SRES; | |
1031 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1032 | udelay(1000); | |
1033 | hc->hw.r_cirm &= ~V_SRES; | |
1034 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1035 | udelay(1000); /* instead of 'wait' that may cause locking */ | |
1036 | ||
1037 | /* release Speech Design card, if PLX was initialized */ | |
1038 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) { | |
1039 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1040 | printk(KERN_DEBUG "%s: release PLXSD card %d\n", | |
1041 | __func__, hc->id + 1); | |
1042 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 1043 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
1044 | writel(PLX_GPIOC_INIT, plx_acc_32); |
1045 | pv = readl(plx_acc_32); | |
1046 | /* Termination off */ | |
1047 | pv &= ~PLX_TERM_ON; | |
1048 | /* Disconnect the PCM */ | |
1049 | pv |= PLX_SLAVE_EN_N; | |
1050 | pv &= ~PLX_MASTER_EN; | |
1051 | pv &= ~PLX_SYNC_O_EN; | |
1052 | /* Put the DSP in Reset */ | |
1053 | pv &= ~PLX_DSP_RES_N; | |
1054 | writel(pv, plx_acc_32); | |
1055 | if (debug & DEBUG_HFCMULTI_INIT) | |
1056 | printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n", | |
1057 | __func__, pv); | |
1058 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1059 | } | |
1060 | ||
1061 | /* disable memory mapped ports / io ports */ | |
1062 | test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ | |
1063 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); | |
1064 | if (hc->pci_membase) | |
c31655fc | 1065 | iounmap(hc->pci_membase); |
af69fb3a | 1066 | if (hc->plx_membase) |
c31655fc | 1067 | iounmap(hc->plx_membase); |
af69fb3a KK |
1068 | if (hc->pci_iobase) |
1069 | release_region(hc->pci_iobase, 8); | |
1070 | ||
1071 | if (hc->pci_dev) { | |
1072 | pci_disable_device(hc->pci_dev); | |
1073 | pci_set_drvdata(hc->pci_dev, NULL); | |
1074 | } | |
1075 | if (debug & DEBUG_HFCMULTI_INIT) | |
1076 | printk(KERN_DEBUG "%s: done\n", __func__); | |
1077 | } | |
1078 | ||
1079 | /* | |
1080 | * function called to reset the HFC chip. A complete software reset of chip | |
1081 | * and fifos is done. All configuration of the chip is done. | |
1082 | */ | |
1083 | ||
1084 | static int | |
1085 | init_chip(struct hfc_multi *hc) | |
1086 | { | |
1087 | u_long flags, val, val2 = 0, rev; | |
1088 | int i, err = 0; | |
1089 | u_char r_conf_en, rval; | |
c31655fc HE |
1090 | void __iomem *plx_acc_32; |
1091 | u_int pv; | |
af69fb3a KK |
1092 | u_long plx_flags, hfc_flags; |
1093 | int plx_count; | |
1094 | struct hfc_multi *pos, *next, *plx_last_hc; | |
1095 | ||
1096 | spin_lock_irqsave(&hc->lock, flags); | |
1097 | /* reset all registers */ | |
1098 | memset(&hc->hw, 0, sizeof(struct hfcm_hw)); | |
1099 | ||
1100 | /* revision check */ | |
1101 | if (debug & DEBUG_HFCMULTI_INIT) | |
1102 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
1103 | val = HFC_inb(hc, R_CHIP_ID)>>4; | |
1104 | if (val != 0x8 && val != 0xc && val != 0xe) { | |
1105 | printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val); | |
1106 | err = -EIO; | |
1107 | goto out; | |
1108 | } | |
1109 | rev = HFC_inb(hc, R_CHIP_RV); | |
1110 | printk(KERN_INFO | |
1111 | "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n", | |
1112 | val, rev, (rev == 0) ? " (old FIFO handling)" : ""); | |
1113 | if (rev == 0) { | |
1114 | test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip); | |
1115 | printk(KERN_WARNING | |
1116 | "HFC_multi: NOTE: Your chip is revision 0, " | |
1117 | "ask Cologne Chip for update. Newer chips " | |
1118 | "have a better FIFO handling. Old chips " | |
1119 | "still work but may have slightly lower " | |
1120 | "HDLC transmit performance.\n"); | |
1121 | } | |
1122 | if (rev > 1) { | |
1123 | printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't " | |
1124 | "consider chip revision = %ld. The chip / " | |
1125 | "bridge may not work.\n", rev); | |
1126 | } | |
1127 | ||
1128 | /* set s-ram size */ | |
1129 | hc->Flen = 0x10; | |
1130 | hc->Zmin = 0x80; | |
1131 | hc->Zlen = 384; | |
1132 | hc->DTMFbase = 0x1000; | |
1133 | if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) { | |
1134 | if (debug & DEBUG_HFCMULTI_INIT) | |
1135 | printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n", | |
1136 | __func__); | |
1137 | hc->hw.r_ctrl |= V_EXT_RAM; | |
1138 | hc->hw.r_ram_sz = 1; | |
1139 | hc->Flen = 0x20; | |
1140 | hc->Zmin = 0xc0; | |
1141 | hc->Zlen = 1856; | |
1142 | hc->DTMFbase = 0x2000; | |
1143 | } | |
1144 | if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) { | |
1145 | if (debug & DEBUG_HFCMULTI_INIT) | |
1146 | printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n", | |
1147 | __func__); | |
1148 | hc->hw.r_ctrl |= V_EXT_RAM; | |
1149 | hc->hw.r_ram_sz = 2; | |
1150 | hc->Flen = 0x20; | |
1151 | hc->Zmin = 0xc0; | |
1152 | hc->Zlen = 8000; | |
1153 | hc->DTMFbase = 0x2000; | |
1154 | } | |
1155 | hc->max_trans = poll << 1; | |
1156 | if (hc->max_trans > hc->Zlen) | |
1157 | hc->max_trans = hc->Zlen; | |
1158 | ||
1159 | /* Speech Design PLX bridge */ | |
1160 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1161 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1162 | printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", | |
1163 | __func__, hc->id + 1); | |
1164 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 1165 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
1166 | writel(PLX_GPIOC_INIT, plx_acc_32); |
1167 | pv = readl(plx_acc_32); | |
1168 | /* The first and the last cards are terminating the PCM bus */ | |
1169 | pv |= PLX_TERM_ON; /* hc is currently the last */ | |
1170 | /* Disconnect the PCM */ | |
1171 | pv |= PLX_SLAVE_EN_N; | |
1172 | pv &= ~PLX_MASTER_EN; | |
1173 | pv &= ~PLX_SYNC_O_EN; | |
1174 | /* Put the DSP in Reset */ | |
1175 | pv &= ~PLX_DSP_RES_N; | |
1176 | writel(pv, plx_acc_32); | |
1177 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1178 | if (debug & DEBUG_HFCMULTI_INIT) | |
1179 | printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n", | |
1180 | __func__, pv); | |
1181 | /* | |
1182 | * If we are the 3rd PLXSD card or higher, we must turn | |
1183 | * termination of last PLXSD card off. | |
1184 | */ | |
1185 | spin_lock_irqsave(&HFClock, hfc_flags); | |
1186 | plx_count = 0; | |
1187 | plx_last_hc = NULL; | |
1188 | list_for_each_entry_safe(pos, next, &HFClist, list) { | |
1189 | if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) { | |
1190 | plx_count++; | |
1191 | if (pos != hc) | |
1192 | plx_last_hc = pos; | |
1193 | } | |
1194 | } | |
1195 | if (plx_count >= 3) { | |
1196 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1197 | printk(KERN_DEBUG "%s: card %d is between, so " | |
1198 | "we disable termination\n", | |
1199 | __func__, plx_last_hc->id + 1); | |
1200 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 1201 | plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
1202 | pv = readl(plx_acc_32); |
1203 | pv &= ~PLX_TERM_ON; | |
1204 | writel(pv, plx_acc_32); | |
1205 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1206 | if (debug & DEBUG_HFCMULTI_INIT) | |
1207 | printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n", | |
1208 | __func__, pv); | |
1209 | } | |
1210 | spin_unlock_irqrestore(&HFClock, hfc_flags); | |
1211 | hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ | |
1212 | } | |
1213 | ||
1214 | /* we only want the real Z2 read-pointer for revision > 0 */ | |
1215 | if (!test_bit(HFC_CHIP_REVISION0, &hc->chip)) | |
1216 | hc->hw.r_ram_sz |= V_FZ_MD; | |
1217 | ||
1218 | /* select pcm mode */ | |
1219 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
1220 | if (debug & DEBUG_HFCMULTI_INIT) | |
1221 | printk(KERN_DEBUG "%s: setting PCM into slave mode\n", | |
1222 | __func__); | |
1223 | } else | |
1224 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) { | |
1225 | if (debug & DEBUG_HFCMULTI_INIT) | |
1226 | printk(KERN_DEBUG "%s: setting PCM into master mode\n", | |
1227 | __func__); | |
1228 | hc->hw.r_pcm_md0 |= V_PCM_MD; | |
1229 | } else { | |
1230 | if (debug & DEBUG_HFCMULTI_INIT) | |
1231 | printk(KERN_DEBUG "%s: performing PCM auto detect\n", | |
1232 | __func__); | |
1233 | } | |
1234 | ||
1235 | /* soft reset */ | |
1236 | HFC_outb(hc, R_CTRL, hc->hw.r_ctrl); | |
1237 | HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); | |
1238 | HFC_outb(hc, R_FIFO_MD, 0); | |
1239 | hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR; | |
1240 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1241 | udelay(100); | |
1242 | hc->hw.r_cirm = 0; | |
1243 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1244 | udelay(100); | |
1245 | HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); | |
1246 | ||
1247 | /* Speech Design PLX bridge pcm and sync mode */ | |
1248 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1249 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 1250 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
1251 | pv = readl(plx_acc_32); |
1252 | /* Connect PCM */ | |
1253 | if (hc->hw.r_pcm_md0 & V_PCM_MD) { | |
1254 | pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; | |
1255 | pv |= PLX_SYNC_O_EN; | |
1256 | if (debug & DEBUG_HFCMULTI_INIT) | |
1257 | printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n", | |
1258 | __func__, pv); | |
1259 | } else { | |
1260 | pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N); | |
1261 | pv &= ~PLX_SYNC_O_EN; | |
1262 | if (debug & DEBUG_HFCMULTI_INIT) | |
1263 | printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n", | |
1264 | __func__, pv); | |
1265 | } | |
1266 | writel(pv, plx_acc_32); | |
1267 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1268 | } | |
1269 | ||
1270 | /* PCM setup */ | |
1271 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90); | |
1272 | if (hc->slots == 32) | |
1273 | HFC_outb(hc, R_PCM_MD1, 0x00); | |
1274 | if (hc->slots == 64) | |
1275 | HFC_outb(hc, R_PCM_MD1, 0x10); | |
1276 | if (hc->slots == 128) | |
1277 | HFC_outb(hc, R_PCM_MD1, 0x20); | |
1278 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0); | |
1279 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) | |
1280 | HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */ | |
1281 | else | |
1282 | HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */ | |
1283 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); | |
1284 | for (i = 0; i < 256; i++) { | |
1285 | HFC_outb_nodebug(hc, R_SLOT, i); | |
1286 | HFC_outb_nodebug(hc, A_SL_CFG, 0); | |
1287 | HFC_outb_nodebug(hc, A_CONF, 0); | |
1288 | hc->slot_owner[i] = -1; | |
1289 | } | |
1290 | ||
1291 | /* set clock speed */ | |
1292 | if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) { | |
1293 | if (debug & DEBUG_HFCMULTI_INIT) | |
1294 | printk(KERN_DEBUG | |
1295 | "%s: setting double clock\n", __func__); | |
1296 | HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); | |
1297 | } | |
1298 | ||
1299 | /* B410P GPIO */ | |
1300 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) { | |
1301 | printk(KERN_NOTICE "Setting GPIOs\n"); | |
1302 | HFC_outb(hc, R_GPIO_SEL, 0x30); | |
1303 | HFC_outb(hc, R_GPIO_EN1, 0x3); | |
1304 | udelay(1000); | |
1305 | printk(KERN_NOTICE "calling vpm_init\n"); | |
1306 | vpm_init(hc); | |
1307 | } | |
1308 | ||
1309 | /* check if R_F0_CNT counts (8 kHz frame count) */ | |
1310 | val = HFC_inb(hc, R_F0_CNTL); | |
1311 | val += HFC_inb(hc, R_F0_CNTH) << 8; | |
1312 | if (debug & DEBUG_HFCMULTI_INIT) | |
1313 | printk(KERN_DEBUG | |
1314 | "HFC_multi F0_CNT %ld after reset\n", val); | |
1315 | spin_unlock_irqrestore(&hc->lock, flags); | |
1316 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1317 | schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */ | |
1318 | spin_lock_irqsave(&hc->lock, flags); | |
1319 | val2 = HFC_inb(hc, R_F0_CNTL); | |
1320 | val2 += HFC_inb(hc, R_F0_CNTH) << 8; | |
1321 | if (debug & DEBUG_HFCMULTI_INIT) | |
1322 | printk(KERN_DEBUG | |
1323 | "HFC_multi F0_CNT %ld after 10 ms (1st try)\n", | |
1324 | val2); | |
1325 | if (val2 >= val+8) { /* 1 ms */ | |
1326 | /* it counts, so we keep the pcm mode */ | |
1327 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) | |
1328 | printk(KERN_INFO "controller is PCM bus MASTER\n"); | |
1329 | else | |
1330 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) | |
1331 | printk(KERN_INFO "controller is PCM bus SLAVE\n"); | |
1332 | else { | |
1333 | test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
1334 | printk(KERN_INFO "controller is PCM bus SLAVE " | |
1335 | "(auto detected)\n"); | |
1336 | } | |
1337 | } else { | |
1338 | /* does not count */ | |
1339 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { | |
1340 | controller_fail: | |
1341 | printk(KERN_ERR "HFC_multi ERROR, getting no 125us " | |
1342 | "pulse. Seems that controller fails.\n"); | |
1343 | err = -EIO; | |
1344 | goto out; | |
1345 | } | |
1346 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
1347 | printk(KERN_INFO "controller is PCM bus SLAVE " | |
1348 | "(ignoring missing PCM clock)\n"); | |
1349 | } else { | |
1350 | /* only one pcm master */ | |
1351 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) | |
1352 | && plxsd_master) { | |
1353 | printk(KERN_ERR "HFC_multi ERROR, no clock " | |
1354 | "on another Speech Design card found. " | |
1355 | "Please be sure to connect PCM cable.\n"); | |
1356 | err = -EIO; | |
1357 | goto out; | |
1358 | } | |
1359 | /* retry with master clock */ | |
1360 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1361 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 1362 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
1363 | pv = readl(plx_acc_32); |
1364 | pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; | |
1365 | pv |= PLX_SYNC_O_EN; | |
1366 | writel(pv, plx_acc_32); | |
1367 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1368 | if (debug & DEBUG_HFCMULTI_INIT) | |
1369 | printk(KERN_WARNING "%s: master: PLX_GPIO" | |
1370 | "=%x\n", __func__, pv); | |
1371 | } | |
1372 | hc->hw.r_pcm_md0 |= V_PCM_MD; | |
1373 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); | |
1374 | spin_unlock_irqrestore(&hc->lock, flags); | |
1375 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1376 | schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */ | |
1377 | spin_lock_irqsave(&hc->lock, flags); | |
1378 | val2 = HFC_inb(hc, R_F0_CNTL); | |
1379 | val2 += HFC_inb(hc, R_F0_CNTH) << 8; | |
1380 | if (debug & DEBUG_HFCMULTI_INIT) | |
1381 | printk(KERN_DEBUG "HFC_multi F0_CNT %ld after " | |
1382 | "10 ms (2nd try)\n", val2); | |
1383 | if (val2 >= val+8) { /* 1 ms */ | |
1384 | test_and_set_bit(HFC_CHIP_PCM_MASTER, | |
1385 | &hc->chip); | |
1386 | printk(KERN_INFO "controller is PCM bus MASTER " | |
1387 | "(auto detected)\n"); | |
1388 | } else | |
1389 | goto controller_fail; | |
1390 | } | |
1391 | } | |
1392 | ||
1393 | /* Release the DSP Reset */ | |
1394 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1395 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) | |
1396 | plxsd_master = 1; | |
1397 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 1398 | plx_acc_32 = hc->plx_membase + PLX_GPIOC; |
af69fb3a KK |
1399 | pv = readl(plx_acc_32); |
1400 | pv |= PLX_DSP_RES_N; | |
1401 | writel(pv, plx_acc_32); | |
1402 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1403 | if (debug & DEBUG_HFCMULTI_INIT) | |
1404 | printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n", | |
1405 | __func__, pv); | |
1406 | } | |
1407 | ||
1408 | /* pcm id */ | |
1409 | if (hc->pcm) | |
1410 | printk(KERN_INFO "controller has given PCM BUS ID %d\n", | |
1411 | hc->pcm); | |
1412 | else { | |
1413 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) | |
1414 | || test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1415 | PCM_cnt++; /* SD has proprietary bridging */ | |
1416 | } | |
1417 | hc->pcm = PCM_cnt; | |
1418 | printk(KERN_INFO "controller has PCM BUS ID %d " | |
1419 | "(auto selected)\n", hc->pcm); | |
1420 | } | |
1421 | ||
1422 | /* set up timer */ | |
1423 | HFC_outb(hc, R_TI_WD, poll_timer); | |
1424 | hc->hw.r_irqmsk_misc |= V_TI_IRQMSK; | |
1425 | ||
af69fb3a KK |
1426 | /* set E1 state machine IRQ */ |
1427 | if (hc->type == 1) | |
1428 | hc->hw.r_irqmsk_misc |= V_STA_IRQMSK; | |
1429 | ||
1430 | /* set DTMF detection */ | |
1431 | if (test_bit(HFC_CHIP_DTMF, &hc->chip)) { | |
1432 | if (debug & DEBUG_HFCMULTI_INIT) | |
1433 | printk(KERN_DEBUG "%s: enabling DTMF detection " | |
1434 | "for all B-channel\n", __func__); | |
1435 | hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP; | |
1436 | if (test_bit(HFC_CHIP_ULAW, &hc->chip)) | |
1437 | hc->hw.r_dtmf |= V_ULAW_SEL; | |
1438 | HFC_outb(hc, R_DTMF_N, 102 - 1); | |
1439 | hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK; | |
1440 | } | |
1441 | ||
1442 | /* conference engine */ | |
1443 | if (test_bit(HFC_CHIP_ULAW, &hc->chip)) | |
1444 | r_conf_en = V_CONF_EN | V_ULAW; | |
1445 | else | |
1446 | r_conf_en = V_CONF_EN; | |
1447 | HFC_outb(hc, R_CONF_EN, r_conf_en); | |
1448 | ||
1449 | /* setting leds */ | |
1450 | switch (hc->leds) { | |
1451 | case 1: /* HFC-E1 OEM */ | |
1452 | if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) | |
1453 | HFC_outb(hc, R_GPIO_SEL, 0x32); | |
1454 | else | |
1455 | HFC_outb(hc, R_GPIO_SEL, 0x30); | |
1456 | ||
1457 | HFC_outb(hc, R_GPIO_EN1, 0x0f); | |
1458 | HFC_outb(hc, R_GPIO_OUT1, 0x00); | |
1459 | ||
1460 | HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); | |
1461 | break; | |
1462 | ||
1463 | case 2: /* HFC-4S OEM */ | |
1464 | case 3: | |
1465 | HFC_outb(hc, R_GPIO_SEL, 0xf0); | |
1466 | HFC_outb(hc, R_GPIO_EN1, 0xff); | |
1467 | HFC_outb(hc, R_GPIO_OUT1, 0x00); | |
1468 | break; | |
1469 | } | |
1470 | ||
1471 | /* set master clock */ | |
1472 | if (hc->masterclk >= 0) { | |
1473 | if (debug & DEBUG_HFCMULTI_INIT) | |
1474 | printk(KERN_DEBUG "%s: setting ST master clock " | |
1475 | "to port %d (0..%d)\n", | |
1476 | __func__, hc->masterclk, hc->ports-1); | |
1477 | hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC; | |
1478 | HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); | |
1479 | } | |
1480 | ||
1481 | /* setting misc irq */ | |
1482 | HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc); | |
1483 | if (debug & DEBUG_HFCMULTI_INIT) | |
1484 | printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n", | |
1485 | hc->hw.r_irqmsk_misc); | |
1486 | ||
1487 | /* RAM access test */ | |
1488 | HFC_outb(hc, R_RAM_ADDR0, 0); | |
1489 | HFC_outb(hc, R_RAM_ADDR1, 0); | |
1490 | HFC_outb(hc, R_RAM_ADDR2, 0); | |
1491 | for (i = 0; i < 256; i++) { | |
1492 | HFC_outb_nodebug(hc, R_RAM_ADDR0, i); | |
1493 | HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff)); | |
1494 | } | |
1495 | for (i = 0; i < 256; i++) { | |
1496 | HFC_outb_nodebug(hc, R_RAM_ADDR0, i); | |
1497 | HFC_inb_nodebug(hc, R_RAM_DATA); | |
1498 | rval = HFC_inb_nodebug(hc, R_INT_DATA); | |
1499 | if (rval != ((i * 3) & 0xff)) { | |
1500 | printk(KERN_DEBUG | |
1501 | "addr:%x val:%x should:%x\n", i, rval, | |
1502 | (i * 3) & 0xff); | |
1503 | err++; | |
1504 | } | |
1505 | } | |
1506 | if (err) { | |
1507 | printk(KERN_DEBUG "aborting - %d RAM access errors\n", err); | |
1508 | err = -EIO; | |
1509 | goto out; | |
1510 | } | |
1511 | ||
1512 | if (debug & DEBUG_HFCMULTI_INIT) | |
1513 | printk(KERN_DEBUG "%s: done\n", __func__); | |
1514 | out: | |
1515 | spin_unlock_irqrestore(&hc->lock, flags); | |
1516 | return err; | |
1517 | } | |
1518 | ||
1519 | ||
1520 | /* | |
1521 | * control the watchdog | |
1522 | */ | |
1523 | static void | |
1524 | hfcmulti_watchdog(struct hfc_multi *hc) | |
1525 | { | |
1526 | hc->wdcount++; | |
1527 | ||
1528 | if (hc->wdcount > 10) { | |
1529 | hc->wdcount = 0; | |
1530 | hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ? | |
1531 | V_GPIO_OUT3 : V_GPIO_OUT2; | |
1532 | ||
1533 | /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */ | |
1534 | HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); | |
1535 | HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte); | |
1536 | } | |
1537 | } | |
1538 | ||
1539 | ||
1540 | ||
1541 | /* | |
1542 | * output leds | |
1543 | */ | |
1544 | static void | |
1545 | hfcmulti_leds(struct hfc_multi *hc) | |
1546 | { | |
1547 | unsigned long lled; | |
1548 | unsigned long leddw; | |
1549 | int i, state, active, leds; | |
1550 | struct dchannel *dch; | |
1551 | int led[4]; | |
1552 | ||
1553 | hc->ledcount += poll; | |
1554 | if (hc->ledcount > 4096) { | |
1555 | hc->ledcount -= 4096; | |
1556 | hc->ledstate = 0xAFFEAFFE; | |
1557 | } | |
1558 | ||
1559 | switch (hc->leds) { | |
1560 | case 1: /* HFC-E1 OEM */ | |
1561 | /* 2 red blinking: NT mode deactivate | |
1562 | * 2 red steady: TE mode deactivate | |
1563 | * left green: L1 active | |
1564 | * left red: frame sync, but no L1 | |
1565 | * right green: L2 active | |
1566 | */ | |
1567 | if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */ | |
1568 | if (hc->chan[hc->dslot].dch->dev.D.protocol | |
1569 | != ISDN_P_NT_E1) { | |
1570 | led[0] = 1; | |
1571 | led[1] = 1; | |
1572 | } else if (hc->ledcount>>11) { | |
1573 | led[0] = 1; | |
1574 | led[1] = 1; | |
1575 | } else { | |
1576 | led[0] = 0; | |
1577 | led[1] = 0; | |
1578 | } | |
1579 | led[2] = 0; | |
1580 | led[3] = 0; | |
1581 | } else { /* with frame sync */ | |
1582 | /* TODO make it work */ | |
1583 | led[0] = 0; | |
1584 | led[1] = 0; | |
1585 | led[2] = 0; | |
1586 | led[3] = 1; | |
1587 | } | |
1588 | leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF; | |
1589 | /* leds are inverted */ | |
1590 | if (leds != (int)hc->ledstate) { | |
1591 | HFC_outb_nodebug(hc, R_GPIO_OUT1, leds); | |
1592 | hc->ledstate = leds; | |
1593 | } | |
1594 | break; | |
1595 | ||
1596 | case 2: /* HFC-4S OEM */ | |
1597 | /* red blinking = PH_DEACTIVATE NT Mode | |
1598 | * red steady = PH_DEACTIVATE TE Mode | |
1599 | * green steady = PH_ACTIVATE | |
1600 | */ | |
1601 | for (i = 0; i < 4; i++) { | |
1602 | state = 0; | |
1603 | active = -1; | |
1604 | dch = hc->chan[(i << 2) | 2].dch; | |
1605 | if (dch) { | |
1606 | state = dch->state; | |
1607 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
1608 | active = 3; | |
1609 | else | |
1610 | active = 7; | |
1611 | } | |
1612 | if (state) { | |
1613 | if (state == active) { | |
1614 | led[i] = 1; /* led green */ | |
1615 | } else | |
1616 | if (dch->dev.D.protocol == ISDN_P_TE_S0) | |
1617 | /* TE mode: led red */ | |
1618 | led[i] = 2; | |
1619 | else | |
1620 | if (hc->ledcount>>11) | |
1621 | /* led red */ | |
1622 | led[i] = 2; | |
1623 | else | |
1624 | /* led off */ | |
1625 | led[i] = 0; | |
1626 | } else | |
1627 | led[i] = 0; /* led off */ | |
1628 | } | |
1629 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) { | |
1630 | leds = 0; | |
1631 | for (i = 0; i < 4; i++) { | |
1632 | if (led[i] == 1) { | |
1633 | /*green*/ | |
1634 | leds |= (0x2 << (i * 2)); | |
1635 | } else if (led[i] == 2) { | |
1636 | /*red*/ | |
1637 | leds |= (0x1 << (i * 2)); | |
1638 | } | |
1639 | } | |
1640 | if (leds != (int)hc->ledstate) { | |
1641 | vpm_out(hc, 0, 0x1a8 + 3, leds); | |
1642 | hc->ledstate = leds; | |
1643 | } | |
1644 | } else { | |
1645 | leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) | | |
1646 | ((led[0] > 0) << 2) | ((led[2] > 0) << 3) | | |
1647 | ((led[3] & 1) << 4) | ((led[1] & 1) << 5) | | |
1648 | ((led[0] & 1) << 6) | ((led[2] & 1) << 7); | |
1649 | if (leds != (int)hc->ledstate) { | |
1650 | HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F); | |
1651 | HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4); | |
1652 | hc->ledstate = leds; | |
1653 | } | |
1654 | } | |
1655 | break; | |
1656 | ||
1657 | case 3: /* HFC 1S/2S Beronet */ | |
1658 | /* red blinking = PH_DEACTIVATE NT Mode | |
1659 | * red steady = PH_DEACTIVATE TE Mode | |
1660 | * green steady = PH_ACTIVATE | |
1661 | */ | |
1662 | for (i = 0; i < 2; i++) { | |
1663 | state = 0; | |
1664 | active = -1; | |
1665 | dch = hc->chan[(i << 2) | 2].dch; | |
1666 | if (dch) { | |
1667 | state = dch->state; | |
1668 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
1669 | active = 3; | |
1670 | else | |
1671 | active = 7; | |
1672 | } | |
1673 | if (state) { | |
1674 | if (state == active) { | |
1675 | led[i] = 1; /* led green */ | |
1676 | } else | |
1677 | if (dch->dev.D.protocol == ISDN_P_TE_S0) | |
1678 | /* TE mode: led red */ | |
1679 | led[i] = 2; | |
1680 | else | |
1681 | if (hc->ledcount >> 11) | |
1682 | /* led red */ | |
1683 | led[i] = 2; | |
1684 | else | |
1685 | /* led off */ | |
1686 | led[i] = 0; | |
1687 | } else | |
1688 | led[i] = 0; /* led off */ | |
1689 | } | |
1690 | ||
1691 | ||
1692 | leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2) | |
1693 | | ((led[1]&1)<<3); | |
1694 | if (leds != (int)hc->ledstate) { | |
1695 | HFC_outb_nodebug(hc, R_GPIO_EN1, | |
1696 | ((led[0] > 0) << 2) | ((led[1] > 0) << 3)); | |
1697 | HFC_outb_nodebug(hc, R_GPIO_OUT1, | |
1698 | ((led[0] & 1) << 2) | ((led[1] & 1) << 3)); | |
1699 | hc->ledstate = leds; | |
1700 | } | |
1701 | break; | |
1702 | case 8: /* HFC 8S+ Beronet */ | |
1703 | lled = 0; | |
1704 | ||
1705 | for (i = 0; i < 8; i++) { | |
1706 | state = 0; | |
1707 | active = -1; | |
1708 | dch = hc->chan[(i << 2) | 2].dch; | |
1709 | if (dch) { | |
1710 | state = dch->state; | |
1711 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
1712 | active = 3; | |
1713 | else | |
1714 | active = 7; | |
1715 | } | |
1716 | if (state) { | |
1717 | if (state == active) { | |
1718 | lled |= 0 << i; | |
1719 | } else | |
1720 | if (hc->ledcount >> 11) | |
1721 | lled |= 0 << i; | |
1722 | else | |
1723 | lled |= 1 << i; | |
1724 | } else | |
1725 | lled |= 1 << i; | |
1726 | } | |
1727 | leddw = lled << 24 | lled << 16 | lled << 8 | lled; | |
1728 | if (leddw != hc->ledstate) { | |
1729 | /* HFC_outb(hc, R_BRG_PCM_CFG, 1); | |
1730 | HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */ | |
1731 | /* was _io before */ | |
1732 | HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); | |
1733 | outw(0x4000, hc->pci_iobase + 4); | |
1734 | outl(leddw, hc->pci_iobase); | |
1735 | HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK); | |
1736 | hc->ledstate = leddw; | |
1737 | } | |
1738 | break; | |
1739 | } | |
1740 | } | |
1741 | /* | |
1742 | * read dtmf coefficients | |
1743 | */ | |
1744 | ||
1745 | static void | |
1746 | hfcmulti_dtmf(struct hfc_multi *hc) | |
1747 | { | |
1748 | s32 *coeff; | |
1749 | u_int mantissa; | |
1750 | int co, ch; | |
1751 | struct bchannel *bch = NULL; | |
1752 | u8 exponent; | |
1753 | int dtmf = 0; | |
1754 | int addr; | |
1755 | u16 w_float; | |
1756 | struct sk_buff *skb; | |
1757 | struct mISDNhead *hh; | |
1758 | ||
1759 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1760 | printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__); | |
1761 | for (ch = 0; ch <= 31; ch++) { | |
1762 | /* only process enabled B-channels */ | |
1763 | bch = hc->chan[ch].bch; | |
1764 | if (!bch) | |
1765 | continue; | |
1766 | if (!hc->created[hc->chan[ch].port]) | |
1767 | continue; | |
1768 | if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
1769 | continue; | |
1770 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1771 | printk(KERN_DEBUG "%s: dtmf channel %d:", | |
1772 | __func__, ch); | |
1773 | coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]); | |
1774 | dtmf = 1; | |
1775 | for (co = 0; co < 8; co++) { | |
1776 | /* read W(n-1) coefficient */ | |
1777 | addr = hc->DTMFbase + ((co<<7) | (ch<<2)); | |
1778 | HFC_outb_nodebug(hc, R_RAM_ADDR0, addr); | |
1779 | HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8); | |
1780 | HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16) | |
1781 | | V_ADDR_INC); | |
1782 | w_float = HFC_inb_nodebug(hc, R_RAM_DATA); | |
1783 | w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); | |
1784 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1785 | printk(" %04x", w_float); | |
1786 | ||
1787 | /* decode float (see chip doc) */ | |
1788 | mantissa = w_float & 0x0fff; | |
1789 | if (w_float & 0x8000) | |
1790 | mantissa |= 0xfffff000; | |
1791 | exponent = (w_float>>12) & 0x7; | |
1792 | if (exponent) { | |
1793 | mantissa ^= 0x1000; | |
1794 | mantissa <<= (exponent-1); | |
1795 | } | |
1796 | ||
1797 | /* store coefficient */ | |
1798 | coeff[co<<1] = mantissa; | |
1799 | ||
1800 | /* read W(n) coefficient */ | |
1801 | w_float = HFC_inb_nodebug(hc, R_RAM_DATA); | |
1802 | w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); | |
1803 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1804 | printk(" %04x", w_float); | |
1805 | ||
1806 | /* decode float (see chip doc) */ | |
1807 | mantissa = w_float & 0x0fff; | |
1808 | if (w_float & 0x8000) | |
1809 | mantissa |= 0xfffff000; | |
1810 | exponent = (w_float>>12) & 0x7; | |
1811 | if (exponent) { | |
1812 | mantissa ^= 0x1000; | |
1813 | mantissa <<= (exponent-1); | |
1814 | } | |
1815 | ||
1816 | /* store coefficient */ | |
1817 | coeff[(co<<1)|1] = mantissa; | |
1818 | } | |
1819 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1820 | printk("%s: DTMF ready %08x %08x %08x %08x " | |
1821 | "%08x %08x %08x %08x\n", __func__, | |
1822 | coeff[0], coeff[1], coeff[2], coeff[3], | |
1823 | coeff[4], coeff[5], coeff[6], coeff[7]); | |
1824 | hc->chan[ch].coeff_count++; | |
1825 | if (hc->chan[ch].coeff_count == 8) { | |
1826 | hc->chan[ch].coeff_count = 0; | |
1827 | skb = mI_alloc_skb(512, GFP_ATOMIC); | |
1828 | if (!skb) { | |
1829 | printk(KERN_WARNING "%s: No memory for skb\n", | |
1830 | __func__); | |
1831 | continue; | |
1832 | } | |
1833 | hh = mISDN_HEAD_P(skb); | |
1834 | hh->prim = PH_CONTROL_IND; | |
1835 | hh->id = DTMF_HFC_COEF; | |
1836 | memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512); | |
1837 | recv_Bchannel_skb(bch, skb); | |
1838 | } | |
1839 | } | |
1840 | ||
1841 | /* restart DTMF processing */ | |
1842 | hc->dtmf = dtmf; | |
1843 | if (dtmf) | |
1844 | HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF); | |
1845 | } | |
1846 | ||
1847 | ||
1848 | /* | |
1849 | * fill fifo as much as possible | |
1850 | */ | |
1851 | ||
1852 | static void | |
1853 | hfcmulti_tx(struct hfc_multi *hc, int ch) | |
1854 | { | |
1855 | int i, ii, temp, len = 0; | |
1856 | int Zspace, z1, z2; /* must be int for calculation */ | |
1857 | int Fspace, f1, f2; | |
1858 | u_char *d; | |
1859 | int *txpending, slot_tx; | |
1860 | struct bchannel *bch; | |
1861 | struct dchannel *dch; | |
1862 | struct sk_buff **sp = NULL; | |
1863 | int *idxp; | |
1864 | ||
1865 | bch = hc->chan[ch].bch; | |
1866 | dch = hc->chan[ch].dch; | |
1867 | if ((!dch) && (!bch)) | |
1868 | return; | |
1869 | ||
1870 | txpending = &hc->chan[ch].txpending; | |
1871 | slot_tx = hc->chan[ch].slot_tx; | |
1872 | if (dch) { | |
1873 | if (!test_bit(FLG_ACTIVE, &dch->Flags)) | |
1874 | return; | |
1875 | sp = &dch->tx_skb; | |
1876 | idxp = &dch->tx_idx; | |
1877 | } else { | |
1878 | if (!test_bit(FLG_ACTIVE, &bch->Flags)) | |
1879 | return; | |
1880 | sp = &bch->tx_skb; | |
1881 | idxp = &bch->tx_idx; | |
1882 | } | |
1883 | if (*sp) | |
1884 | len = (*sp)->len; | |
1885 | ||
1886 | if ((!len) && *txpending != 1) | |
1887 | return; /* no data */ | |
1888 | ||
1889 | if (test_bit(HFC_CHIP_B410P, &hc->chip) && | |
1890 | (hc->chan[ch].protocol == ISDN_P_B_RAW) && | |
1891 | (hc->chan[ch].slot_rx < 0) && | |
1892 | (hc->chan[ch].slot_tx < 0)) | |
1893 | HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1)); | |
1894 | else | |
1895 | HFC_outb_nodebug(hc, R_FIFO, ch << 1); | |
1896 | HFC_wait_nodebug(hc); | |
1897 | ||
1898 | if (*txpending == 2) { | |
1899 | /* reset fifo */ | |
1900 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); | |
1901 | HFC_wait_nodebug(hc); | |
1902 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
1903 | *txpending = 1; | |
1904 | } | |
1905 | next_frame: | |
1906 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
1907 | f1 = HFC_inb_nodebug(hc, A_F1); | |
1908 | f2 = HFC_inb_nodebug(hc, A_F2); | |
1909 | while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) { | |
1910 | if (debug & DEBUG_HFCMULTI_FIFO) | |
1911 | printk(KERN_DEBUG | |
1912 | "%s(card %d): reread f2 because %d!=%d\n", | |
1913 | __func__, hc->id + 1, temp, f2); | |
1914 | f2 = temp; /* repeat until F2 is equal */ | |
1915 | } | |
1916 | Fspace = f2 - f1 - 1; | |
1917 | if (Fspace < 0) | |
1918 | Fspace += hc->Flen; | |
1919 | /* | |
1920 | * Old FIFO handling doesn't give us the current Z2 read | |
1921 | * pointer, so we cannot send the next frame before the fifo | |
1922 | * is empty. It makes no difference except for a slightly | |
1923 | * lower performance. | |
1924 | */ | |
1925 | if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) { | |
1926 | if (f1 != f2) | |
1927 | Fspace = 0; | |
1928 | else | |
1929 | Fspace = 1; | |
1930 | } | |
1931 | /* one frame only for ST D-channels, to allow resending */ | |
1932 | if (hc->type != 1 && dch) { | |
1933 | if (f1 != f2) | |
1934 | Fspace = 0; | |
1935 | } | |
1936 | /* F-counter full condition */ | |
1937 | if (Fspace == 0) | |
1938 | return; | |
1939 | } | |
1940 | z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; | |
1941 | z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; | |
1942 | while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) { | |
1943 | if (debug & DEBUG_HFCMULTI_FIFO) | |
1944 | printk(KERN_DEBUG "%s(card %d): reread z2 because " | |
1945 | "%d!=%d\n", __func__, hc->id + 1, temp, z2); | |
1946 | z2 = temp; /* repeat unti Z2 is equal */ | |
1947 | } | |
1948 | Zspace = z2 - z1; | |
1949 | if (Zspace <= 0) | |
1950 | Zspace += hc->Zlen; | |
1951 | Zspace -= 4; /* keep not too full, so pointers will not overrun */ | |
1952 | /* fill transparent data only to maxinum transparent load (minus 4) */ | |
1953 | if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
1954 | Zspace = Zspace - hc->Zlen + hc->max_trans; | |
1955 | if (Zspace <= 0) /* no space of 4 bytes */ | |
1956 | return; | |
1957 | ||
1958 | /* if no data */ | |
1959 | if (!len) { | |
1960 | if (z1 == z2) { /* empty */ | |
1961 | /* if done with FIFO audio data during PCM connection */ | |
1962 | if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && | |
1963 | *txpending && slot_tx >= 0) { | |
1964 | if (debug & DEBUG_HFCMULTI_MODE) | |
1965 | printk(KERN_DEBUG | |
1966 | "%s: reconnecting PCM due to no " | |
1967 | "more FIFO data: channel %d " | |
1968 | "slot_tx %d\n", | |
1969 | __func__, ch, slot_tx); | |
1970 | /* connect slot */ | |
1971 | HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | | |
1972 | V_HDLC_TRP | V_IFF); | |
1973 | HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); | |
1974 | HFC_wait_nodebug(hc); | |
1975 | HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | | |
1976 | V_HDLC_TRP | V_IFF); | |
1977 | HFC_outb_nodebug(hc, R_FIFO, ch<<1); | |
1978 | HFC_wait_nodebug(hc); | |
1979 | } | |
1980 | *txpending = 0; | |
1981 | } | |
1982 | return; /* no data */ | |
1983 | } | |
1984 | ||
8dd2f36f AE |
1985 | /* "fill fifo if empty" feature */ |
1986 | if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags) | |
1987 | && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) { | |
1988 | if (debug & DEBUG_HFCMULTI_FILL) | |
1989 | printk(KERN_DEBUG "%s: buffer empty, so we have " | |
1990 | "underrun\n", __func__); | |
1991 | /* fill buffer, to prevent future underrun */ | |
1992 | hc->write_fifo(hc, hc->silence_data, poll >> 1); | |
1993 | Zspace -= (poll >> 1); | |
1994 | } | |
1995 | ||
af69fb3a KK |
1996 | /* if audio data and connected slot */ |
1997 | if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending) | |
1998 | && slot_tx >= 0) { | |
1999 | if (debug & DEBUG_HFCMULTI_MODE) | |
2000 | printk(KERN_DEBUG "%s: disconnecting PCM due to " | |
2001 | "FIFO data: channel %d slot_tx %d\n", | |
2002 | __func__, ch, slot_tx); | |
2003 | /* disconnect slot */ | |
2004 | HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF); | |
2005 | HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); | |
2006 | HFC_wait_nodebug(hc); | |
2007 | HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF); | |
2008 | HFC_outb_nodebug(hc, R_FIFO, ch<<1); | |
2009 | HFC_wait_nodebug(hc); | |
2010 | } | |
2011 | *txpending = 1; | |
2012 | ||
2013 | /* show activity */ | |
2014 | hc->activity[hc->chan[ch].port] = 1; | |
2015 | ||
2016 | /* fill fifo to what we have left */ | |
2017 | ii = len; | |
2018 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) | |
2019 | temp = 1; | |
2020 | else | |
2021 | temp = 0; | |
2022 | i = *idxp; | |
2023 | d = (*sp)->data + i; | |
2024 | if (ii - i > Zspace) | |
2025 | ii = Zspace + i; | |
2026 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2027 | printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space " | |
2028 | "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n", | |
2029 | __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i, | |
2030 | temp ? "HDLC":"TRANS"); | |
2031 | ||
af69fb3a KK |
2032 | /* Have to prep the audio data */ |
2033 | hc->write_fifo(hc, d, ii - i); | |
2034 | *idxp = ii; | |
2035 | ||
2036 | /* if not all data has been written */ | |
2037 | if (ii != len) { | |
2038 | /* NOTE: fifo is started by the calling function */ | |
2039 | return; | |
2040 | } | |
2041 | ||
2042 | /* if all data has been written, terminate frame */ | |
2043 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
2044 | /* increment f-counter */ | |
2045 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); | |
2046 | HFC_wait_nodebug(hc); | |
2047 | } | |
2048 | ||
2049 | /* send confirm, since get_net_bframe will not do it with trans */ | |
2050 | if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
2051 | confirm_Bsend(bch); | |
2052 | ||
2053 | /* check for next frame */ | |
2054 | dev_kfree_skb(*sp); | |
2055 | if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */ | |
2056 | len = (*sp)->len; | |
2057 | goto next_frame; | |
2058 | } | |
2059 | if (dch && get_next_dframe(dch)) { | |
2060 | len = (*sp)->len; | |
2061 | goto next_frame; | |
2062 | } | |
2063 | ||
2064 | /* | |
2065 | * now we have no more data, so in case of transparent, | |
2066 | * we set the last byte in fifo to 'silence' in case we will get | |
2067 | * no more data at all. this prevents sending an undefined value. | |
2068 | */ | |
2069 | if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
8dd2f36f | 2070 | HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); |
af69fb3a KK |
2071 | } |
2072 | ||
2073 | ||
2074 | /* NOTE: only called if E1 card is in active state */ | |
2075 | static void | |
2076 | hfcmulti_rx(struct hfc_multi *hc, int ch) | |
2077 | { | |
2078 | int temp; | |
2079 | int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */ | |
2080 | int f1 = 0, f2 = 0; /* = 0, to make GCC happy */ | |
2081 | int again = 0; | |
2082 | struct bchannel *bch; | |
2083 | struct dchannel *dch; | |
2084 | struct sk_buff *skb, **sp = NULL; | |
2085 | int maxlen; | |
2086 | ||
2087 | bch = hc->chan[ch].bch; | |
2088 | dch = hc->chan[ch].dch; | |
2089 | if ((!dch) && (!bch)) | |
2090 | return; | |
2091 | if (dch) { | |
2092 | if (!test_bit(FLG_ACTIVE, &dch->Flags)) | |
2093 | return; | |
2094 | sp = &dch->rx_skb; | |
2095 | maxlen = dch->maxlen; | |
2096 | } else { | |
2097 | if (!test_bit(FLG_ACTIVE, &bch->Flags)) | |
2098 | return; | |
2099 | sp = &bch->rx_skb; | |
2100 | maxlen = bch->maxlen; | |
2101 | } | |
2102 | next_frame: | |
2103 | /* on first AND before getting next valid frame, R_FIFO must be written | |
2104 | to. */ | |
2105 | if (test_bit(HFC_CHIP_B410P, &hc->chip) && | |
2106 | (hc->chan[ch].protocol == ISDN_P_B_RAW) && | |
2107 | (hc->chan[ch].slot_rx < 0) && | |
2108 | (hc->chan[ch].slot_tx < 0)) | |
2109 | HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1); | |
2110 | else | |
2111 | HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1); | |
2112 | HFC_wait_nodebug(hc); | |
2113 | ||
2114 | /* ignore if rx is off BUT change fifo (above) to start pending TX */ | |
2115 | if (hc->chan[ch].rx_off) | |
2116 | return; | |
2117 | ||
2118 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
2119 | f1 = HFC_inb_nodebug(hc, A_F1); | |
2120 | while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) { | |
2121 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2122 | printk(KERN_DEBUG | |
2123 | "%s(card %d): reread f1 because %d!=%d\n", | |
2124 | __func__, hc->id + 1, temp, f1); | |
2125 | f1 = temp; /* repeat until F1 is equal */ | |
2126 | } | |
2127 | f2 = HFC_inb_nodebug(hc, A_F2); | |
2128 | } | |
2129 | z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; | |
2130 | while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) { | |
2131 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2132 | printk(KERN_DEBUG "%s(card %d): reread z2 because " | |
2133 | "%d!=%d\n", __func__, hc->id + 1, temp, z2); | |
2134 | z1 = temp; /* repeat until Z1 is equal */ | |
2135 | } | |
2136 | z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; | |
2137 | Zsize = z1 - z2; | |
2138 | if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2) | |
2139 | /* complete hdlc frame */ | |
2140 | Zsize++; | |
2141 | if (Zsize < 0) | |
2142 | Zsize += hc->Zlen; | |
2143 | /* if buffer is empty */ | |
2144 | if (Zsize <= 0) | |
2145 | return; | |
2146 | ||
2147 | if (*sp == NULL) { | |
2148 | *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC); | |
2149 | if (*sp == NULL) { | |
2150 | printk(KERN_DEBUG "%s: No mem for rx_skb\n", | |
2151 | __func__); | |
2152 | return; | |
2153 | } | |
2154 | } | |
2155 | /* show activity */ | |
2156 | hc->activity[hc->chan[ch].port] = 1; | |
2157 | ||
2158 | /* empty fifo with what we have */ | |
2159 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
2160 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2161 | printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d " | |
2162 | "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) " | |
2163 | "got=%d (again %d)\n", __func__, hc->id + 1, ch, | |
2164 | Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE", | |
2165 | f1, f2, Zsize + (*sp)->len, again); | |
2166 | /* HDLC */ | |
2167 | if ((Zsize + (*sp)->len) > (maxlen + 3)) { | |
2168 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2169 | printk(KERN_DEBUG | |
2170 | "%s(card %d): hdlc-frame too large.\n", | |
2171 | __func__, hc->id + 1); | |
2172 | skb_trim(*sp, 0); | |
2173 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); | |
2174 | HFC_wait_nodebug(hc); | |
2175 | return; | |
2176 | } | |
2177 | ||
2178 | hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); | |
2179 | ||
2180 | if (f1 != f2) { | |
2181 | /* increment Z2,F2-counter */ | |
2182 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); | |
2183 | HFC_wait_nodebug(hc); | |
2184 | /* check size */ | |
2185 | if ((*sp)->len < 4) { | |
2186 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2187 | printk(KERN_DEBUG | |
2188 | "%s(card %d): Frame below minimum " | |
2189 | "size\n", __func__, hc->id + 1); | |
2190 | skb_trim(*sp, 0); | |
2191 | goto next_frame; | |
2192 | } | |
2193 | /* there is at least one complete frame, check crc */ | |
2194 | if ((*sp)->data[(*sp)->len - 1]) { | |
2195 | if (debug & DEBUG_HFCMULTI_CRC) | |
2196 | printk(KERN_DEBUG | |
2197 | "%s: CRC-error\n", __func__); | |
2198 | skb_trim(*sp, 0); | |
2199 | goto next_frame; | |
2200 | } | |
2201 | skb_trim(*sp, (*sp)->len - 3); | |
2202 | if ((*sp)->len < MISDN_COPY_SIZE) { | |
2203 | skb = *sp; | |
2204 | *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); | |
2205 | if (*sp) { | |
2206 | memcpy(skb_put(*sp, skb->len), | |
2207 | skb->data, skb->len); | |
2208 | skb_trim(skb, 0); | |
2209 | } else { | |
2210 | printk(KERN_DEBUG "%s: No mem\n", | |
2211 | __func__); | |
2212 | *sp = skb; | |
2213 | skb = NULL; | |
2214 | } | |
2215 | } else { | |
2216 | skb = NULL; | |
2217 | } | |
2218 | if (debug & DEBUG_HFCMULTI_FIFO) { | |
2219 | printk(KERN_DEBUG "%s(card %d):", | |
2220 | __func__, hc->id + 1); | |
2221 | temp = 0; | |
2222 | while (temp < (*sp)->len) | |
2223 | printk(" %02x", (*sp)->data[temp++]); | |
2224 | printk("\n"); | |
2225 | } | |
2226 | if (dch) | |
2227 | recv_Dchannel(dch); | |
2228 | else | |
2229 | recv_Bchannel(bch); | |
2230 | *sp = skb; | |
2231 | again++; | |
2232 | goto next_frame; | |
2233 | } | |
2234 | /* there is an incomplete frame */ | |
2235 | } else { | |
2236 | /* transparent */ | |
2237 | if (Zsize > skb_tailroom(*sp)) | |
2238 | Zsize = skb_tailroom(*sp); | |
2239 | hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); | |
2240 | if (((*sp)->len) < MISDN_COPY_SIZE) { | |
2241 | skb = *sp; | |
2242 | *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); | |
2243 | if (*sp) { | |
2244 | memcpy(skb_put(*sp, skb->len), | |
2245 | skb->data, skb->len); | |
2246 | skb_trim(skb, 0); | |
2247 | } else { | |
2248 | printk(KERN_DEBUG "%s: No mem\n", __func__); | |
2249 | *sp = skb; | |
2250 | skb = NULL; | |
2251 | } | |
2252 | } else { | |
2253 | skb = NULL; | |
2254 | } | |
2255 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2256 | printk(KERN_DEBUG | |
2257 | "%s(card %d): fifo(%d) reading %d bytes " | |
2258 | "(z1=%04x, z2=%04x) TRANS\n", | |
2259 | __func__, hc->id + 1, ch, Zsize, z1, z2); | |
2260 | /* only bch is transparent */ | |
2261 | recv_Bchannel(bch); | |
2262 | *sp = skb; | |
2263 | } | |
2264 | } | |
2265 | ||
2266 | ||
2267 | /* | |
2268 | * Interrupt handler | |
2269 | */ | |
2270 | static void | |
2271 | signal_state_up(struct dchannel *dch, int info, char *msg) | |
2272 | { | |
2273 | struct sk_buff *skb; | |
2274 | int id, data = info; | |
2275 | ||
2276 | if (debug & DEBUG_HFCMULTI_STATE) | |
2277 | printk(KERN_DEBUG "%s: %s\n", __func__, msg); | |
2278 | ||
2279 | id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */ | |
2280 | ||
2281 | skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data, | |
2282 | GFP_ATOMIC); | |
2283 | if (!skb) | |
2284 | return; | |
2285 | recv_Dchannel_skb(dch, skb); | |
2286 | } | |
2287 | ||
2288 | static inline void | |
2289 | handle_timer_irq(struct hfc_multi *hc) | |
2290 | { | |
2291 | int ch, temp; | |
2292 | struct dchannel *dch; | |
2293 | u_long flags; | |
2294 | ||
2295 | /* process queued resync jobs */ | |
2296 | if (hc->e1_resync) { | |
2297 | /* lock, so e1_resync gets not changed */ | |
2298 | spin_lock_irqsave(&HFClock, flags); | |
2299 | if (hc->e1_resync & 1) { | |
2300 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
2301 | printk(KERN_DEBUG "Enable SYNC_I\n"); | |
2302 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC); | |
2303 | /* disable JATT, if RX_SYNC is set */ | |
2304 | if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) | |
2305 | HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); | |
2306 | } | |
2307 | if (hc->e1_resync & 2) { | |
2308 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
2309 | printk(KERN_DEBUG "Enable jatt PLL\n"); | |
2310 | HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); | |
2311 | } | |
2312 | if (hc->e1_resync & 4) { | |
2313 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
2314 | printk(KERN_DEBUG | |
2315 | "Enable QUARTZ for HFC-E1\n"); | |
2316 | /* set jatt to quartz */ | |
2317 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | |
2318 | | V_JATT_OFF); | |
2319 | /* switch to JATT, in case it is not already */ | |
2320 | HFC_outb(hc, R_SYNC_OUT, 0); | |
2321 | } | |
2322 | hc->e1_resync = 0; | |
2323 | spin_unlock_irqrestore(&HFClock, flags); | |
2324 | } | |
2325 | ||
2326 | if (hc->type != 1 || hc->e1_state == 1) | |
2327 | for (ch = 0; ch <= 31; ch++) { | |
2328 | if (hc->created[hc->chan[ch].port]) { | |
2329 | hfcmulti_tx(hc, ch); | |
2330 | /* fifo is started when switching to rx-fifo */ | |
2331 | hfcmulti_rx(hc, ch); | |
2332 | if (hc->chan[ch].dch && | |
2333 | hc->chan[ch].nt_timer > -1) { | |
2334 | dch = hc->chan[ch].dch; | |
2335 | if (!(--hc->chan[ch].nt_timer)) { | |
2336 | schedule_event(dch, | |
2337 | FLG_PHCHANGE); | |
2338 | if (debug & | |
2339 | DEBUG_HFCMULTI_STATE) | |
2340 | printk(KERN_DEBUG | |
2341 | "%s: nt_timer at " | |
2342 | "state %x\n", | |
2343 | __func__, | |
2344 | dch->state); | |
2345 | } | |
2346 | } | |
2347 | } | |
2348 | } | |
2349 | if (hc->type == 1 && hc->created[0]) { | |
2350 | dch = hc->chan[hc->dslot].dch; | |
2351 | if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { | |
2352 | /* LOS */ | |
2353 | temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS; | |
2354 | if (!temp && hc->chan[hc->dslot].los) | |
2355 | signal_state_up(dch, L1_SIGNAL_LOS_ON, | |
2356 | "LOS detected"); | |
2357 | if (temp && !hc->chan[hc->dslot].los) | |
2358 | signal_state_up(dch, L1_SIGNAL_LOS_OFF, | |
2359 | "LOS gone"); | |
2360 | hc->chan[hc->dslot].los = temp; | |
2361 | } | |
2362 | if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) { | |
2363 | /* AIS */ | |
2364 | temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS; | |
2365 | if (!temp && hc->chan[hc->dslot].ais) | |
2366 | signal_state_up(dch, L1_SIGNAL_AIS_ON, | |
2367 | "AIS detected"); | |
2368 | if (temp && !hc->chan[hc->dslot].ais) | |
2369 | signal_state_up(dch, L1_SIGNAL_AIS_OFF, | |
2370 | "AIS gone"); | |
2371 | hc->chan[hc->dslot].ais = temp; | |
2372 | } | |
2373 | if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) { | |
2374 | /* SLIP */ | |
2375 | temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX; | |
2376 | if (!temp && hc->chan[hc->dslot].slip_rx) | |
2377 | signal_state_up(dch, L1_SIGNAL_SLIP_RX, | |
2378 | " bit SLIP detected RX"); | |
2379 | hc->chan[hc->dslot].slip_rx = temp; | |
2380 | temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX; | |
2381 | if (!temp && hc->chan[hc->dslot].slip_tx) | |
2382 | signal_state_up(dch, L1_SIGNAL_SLIP_TX, | |
2383 | " bit SLIP detected TX"); | |
2384 | hc->chan[hc->dslot].slip_tx = temp; | |
2385 | } | |
2386 | if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) { | |
2387 | /* RDI */ | |
2388 | temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A; | |
2389 | if (!temp && hc->chan[hc->dslot].rdi) | |
2390 | signal_state_up(dch, L1_SIGNAL_RDI_ON, | |
2391 | "RDI detected"); | |
2392 | if (temp && !hc->chan[hc->dslot].rdi) | |
2393 | signal_state_up(dch, L1_SIGNAL_RDI_OFF, | |
2394 | "RDI gone"); | |
2395 | hc->chan[hc->dslot].rdi = temp; | |
2396 | } | |
2397 | temp = HFC_inb_nodebug(hc, R_JATT_DIR); | |
2398 | switch (hc->chan[hc->dslot].sync) { | |
2399 | case 0: | |
2400 | if ((temp & 0x60) == 0x60) { | |
2401 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2402 | printk(KERN_DEBUG | |
2403 | "%s: (id=%d) E1 now " | |
2404 | "in clock sync\n", | |
2405 | __func__, hc->id); | |
2406 | HFC_outb(hc, R_RX_OFF, | |
2407 | hc->chan[hc->dslot].jitter | V_RX_INIT); | |
2408 | HFC_outb(hc, R_TX_OFF, | |
2409 | hc->chan[hc->dslot].jitter | V_RX_INIT); | |
2410 | hc->chan[hc->dslot].sync = 1; | |
2411 | goto check_framesync; | |
2412 | } | |
2413 | break; | |
2414 | case 1: | |
2415 | if ((temp & 0x60) != 0x60) { | |
2416 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2417 | printk(KERN_DEBUG | |
2418 | "%s: (id=%d) E1 " | |
2419 | "lost clock sync\n", | |
2420 | __func__, hc->id); | |
2421 | hc->chan[hc->dslot].sync = 0; | |
2422 | break; | |
2423 | } | |
2424 | check_framesync: | |
2425 | temp = HFC_inb_nodebug(hc, R_SYNC_STA); | |
2426 | if (temp == 0x27) { | |
2427 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2428 | printk(KERN_DEBUG | |
2429 | "%s: (id=%d) E1 " | |
2430 | "now in frame sync\n", | |
2431 | __func__, hc->id); | |
2432 | hc->chan[hc->dslot].sync = 2; | |
2433 | } | |
2434 | break; | |
2435 | case 2: | |
2436 | if ((temp & 0x60) != 0x60) { | |
2437 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2438 | printk(KERN_DEBUG | |
2439 | "%s: (id=%d) E1 lost " | |
2440 | "clock & frame sync\n", | |
2441 | __func__, hc->id); | |
2442 | hc->chan[hc->dslot].sync = 0; | |
2443 | break; | |
2444 | } | |
2445 | temp = HFC_inb_nodebug(hc, R_SYNC_STA); | |
2446 | if (temp != 0x27) { | |
2447 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2448 | printk(KERN_DEBUG | |
2449 | "%s: (id=%d) E1 " | |
2450 | "lost frame sync\n", | |
2451 | __func__, hc->id); | |
2452 | hc->chan[hc->dslot].sync = 1; | |
2453 | } | |
2454 | break; | |
2455 | } | |
2456 | } | |
2457 | ||
2458 | if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) | |
2459 | hfcmulti_watchdog(hc); | |
2460 | ||
2461 | if (hc->leds) | |
2462 | hfcmulti_leds(hc); | |
2463 | } | |
2464 | ||
2465 | static void | |
2466 | ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech) | |
2467 | { | |
2468 | struct dchannel *dch; | |
2469 | int ch; | |
2470 | int active; | |
2471 | u_char st_status, temp; | |
2472 | ||
2473 | /* state machine */ | |
2474 | for (ch = 0; ch <= 31; ch++) { | |
2475 | if (hc->chan[ch].dch) { | |
2476 | dch = hc->chan[ch].dch; | |
2477 | if (r_irq_statech & 1) { | |
2478 | HFC_outb_nodebug(hc, R_ST_SEL, | |
2479 | hc->chan[ch].port); | |
2480 | /* undocumented: delay after R_ST_SEL */ | |
2481 | udelay(1); | |
2482 | /* undocumented: status changes during read */ | |
2483 | st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE); | |
2484 | while (st_status != (temp = | |
2485 | HFC_inb_nodebug(hc, A_ST_RD_STATE))) { | |
2486 | if (debug & DEBUG_HFCMULTI_STATE) | |
2487 | printk(KERN_DEBUG "%s: reread " | |
2488 | "STATE because %d!=%d\n", | |
2489 | __func__, temp, | |
2490 | st_status); | |
2491 | st_status = temp; /* repeat */ | |
2492 | } | |
2493 | ||
2494 | /* Speech Design TE-sync indication */ | |
2495 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && | |
2496 | dch->dev.D.protocol == ISDN_P_TE_S0) { | |
2497 | if (st_status & V_FR_SYNC_ST) | |
2498 | hc->syncronized |= | |
2499 | (1 << hc->chan[ch].port); | |
2500 | else | |
2501 | hc->syncronized &= | |
2502 | ~(1 << hc->chan[ch].port); | |
2503 | } | |
2504 | dch->state = st_status & 0x0f; | |
2505 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
2506 | active = 3; | |
2507 | else | |
2508 | active = 7; | |
2509 | if (dch->state == active) { | |
2510 | HFC_outb_nodebug(hc, R_FIFO, | |
2511 | (ch << 1) | 1); | |
2512 | HFC_wait_nodebug(hc); | |
2513 | HFC_outb_nodebug(hc, | |
2514 | R_INC_RES_FIFO, V_RES_F); | |
2515 | HFC_wait_nodebug(hc); | |
2516 | dch->tx_idx = 0; | |
2517 | } | |
2518 | schedule_event(dch, FLG_PHCHANGE); | |
2519 | if (debug & DEBUG_HFCMULTI_STATE) | |
2520 | printk(KERN_DEBUG | |
2521 | "%s: S/T newstate %x port %d\n", | |
2522 | __func__, dch->state, | |
2523 | hc->chan[ch].port); | |
2524 | } | |
2525 | r_irq_statech >>= 1; | |
2526 | } | |
2527 | } | |
2528 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) | |
2529 | plxsd_checksync(hc, 0); | |
2530 | } | |
2531 | ||
2532 | static void | |
2533 | fifo_irq(struct hfc_multi *hc, int block) | |
2534 | { | |
2535 | int ch, j; | |
2536 | struct dchannel *dch; | |
2537 | struct bchannel *bch; | |
2538 | u_char r_irq_fifo_bl; | |
2539 | ||
2540 | r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block); | |
2541 | j = 0; | |
2542 | while (j < 8) { | |
2543 | ch = (block << 2) + (j >> 1); | |
2544 | dch = hc->chan[ch].dch; | |
2545 | bch = hc->chan[ch].bch; | |
2546 | if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) { | |
2547 | j += 2; | |
2548 | continue; | |
2549 | } | |
2550 | if (dch && (r_irq_fifo_bl & (1 << j)) && | |
2551 | test_bit(FLG_ACTIVE, &dch->Flags)) { | |
2552 | hfcmulti_tx(hc, ch); | |
2553 | /* start fifo */ | |
2554 | HFC_outb_nodebug(hc, R_FIFO, 0); | |
2555 | HFC_wait_nodebug(hc); | |
2556 | } | |
2557 | if (bch && (r_irq_fifo_bl & (1 << j)) && | |
2558 | test_bit(FLG_ACTIVE, &bch->Flags)) { | |
2559 | hfcmulti_tx(hc, ch); | |
2560 | /* start fifo */ | |
2561 | HFC_outb_nodebug(hc, R_FIFO, 0); | |
2562 | HFC_wait_nodebug(hc); | |
2563 | } | |
2564 | j++; | |
2565 | if (dch && (r_irq_fifo_bl & (1 << j)) && | |
2566 | test_bit(FLG_ACTIVE, &dch->Flags)) { | |
2567 | hfcmulti_rx(hc, ch); | |
2568 | } | |
2569 | if (bch && (r_irq_fifo_bl & (1 << j)) && | |
2570 | test_bit(FLG_ACTIVE, &bch->Flags)) { | |
2571 | hfcmulti_rx(hc, ch); | |
2572 | } | |
2573 | j++; | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | #ifdef IRQ_DEBUG | |
2578 | int irqsem; | |
2579 | #endif | |
2580 | static irqreturn_t | |
2581 | hfcmulti_interrupt(int intno, void *dev_id) | |
2582 | { | |
2583 | #ifdef IRQCOUNT_DEBUG | |
2584 | static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0, | |
2585 | iq5 = 0, iq6 = 0, iqcnt = 0; | |
2586 | #endif | |
af69fb3a KK |
2587 | struct hfc_multi *hc = dev_id; |
2588 | struct dchannel *dch; | |
2589 | u_char r_irq_statech, status, r_irq_misc, r_irq_oview; | |
2590 | int i; | |
c31655fc HE |
2591 | void __iomem *plx_acc; |
2592 | u_short wval; | |
af69fb3a KK |
2593 | u_char e1_syncsta, temp; |
2594 | u_long flags; | |
2595 | ||
2596 | if (!hc) { | |
2597 | printk(KERN_ERR "HFC-multi: Spurious interrupt!\n"); | |
2598 | return IRQ_NONE; | |
2599 | } | |
2600 | ||
2601 | spin_lock(&hc->lock); | |
2602 | ||
2603 | #ifdef IRQ_DEBUG | |
2604 | if (irqsem) | |
2605 | printk(KERN_ERR "irq for card %d during irq from " | |
2606 | "card %d, this is no bug.\n", hc->id + 1, irqsem); | |
2607 | irqsem = hc->id + 1; | |
2608 | #endif | |
2609 | ||
2610 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
2611 | spin_lock_irqsave(&plx_lock, flags); | |
c31655fc | 2612 | plx_acc = hc->plx_membase + PLX_INTCSR; |
af69fb3a KK |
2613 | wval = readw(plx_acc); |
2614 | spin_unlock_irqrestore(&plx_lock, flags); | |
2615 | if (!(wval & PLX_INTCSR_LINTI1_STATUS)) | |
2616 | goto irq_notforus; | |
2617 | } | |
2618 | ||
2619 | status = HFC_inb_nodebug(hc, R_STATUS); | |
2620 | r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH); | |
2621 | #ifdef IRQCOUNT_DEBUG | |
2622 | if (r_irq_statech) | |
2623 | iq1++; | |
2624 | if (status & V_DTMF_STA) | |
2625 | iq2++; | |
2626 | if (status & V_LOST_STA) | |
2627 | iq3++; | |
2628 | if (status & V_EXT_IRQSTA) | |
2629 | iq4++; | |
2630 | if (status & V_MISC_IRQSTA) | |
2631 | iq5++; | |
2632 | if (status & V_FR_IRQSTA) | |
2633 | iq6++; | |
2634 | if (iqcnt++ > 5000) { | |
2635 | printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n", | |
2636 | iq1, iq2, iq3, iq4, iq5, iq6); | |
2637 | iqcnt = 0; | |
2638 | } | |
2639 | #endif | |
3bd69ad1 | 2640 | |
af69fb3a KK |
2641 | if (!r_irq_statech && |
2642 | !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA | | |
2643 | V_MISC_IRQSTA | V_FR_IRQSTA))) { | |
2644 | /* irq is not for us */ | |
2645 | goto irq_notforus; | |
2646 | } | |
2647 | hc->irqcnt++; | |
2648 | if (r_irq_statech) { | |
2649 | if (hc->type != 1) | |
2650 | ph_state_irq(hc, r_irq_statech); | |
2651 | } | |
2652 | if (status & V_EXT_IRQSTA) | |
2653 | ; /* external IRQ */ | |
2654 | if (status & V_LOST_STA) { | |
2655 | /* LOST IRQ */ | |
2656 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */ | |
2657 | } | |
2658 | if (status & V_MISC_IRQSTA) { | |
2659 | /* misc IRQ */ | |
2660 | r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC); | |
9e6115f2 | 2661 | r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */ |
af69fb3a KK |
2662 | if (r_irq_misc & V_STA_IRQ) { |
2663 | if (hc->type == 1) { | |
2664 | /* state machine */ | |
2665 | dch = hc->chan[hc->dslot].dch; | |
2666 | e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA); | |
2667 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) | |
2668 | && hc->e1_getclock) { | |
2669 | if (e1_syncsta & V_FR_SYNC_E1) | |
2670 | hc->syncronized = 1; | |
2671 | else | |
2672 | hc->syncronized = 0; | |
2673 | } | |
2674 | /* undocumented: status changes during read */ | |
2675 | dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA); | |
2676 | while (dch->state != (temp = | |
2677 | HFC_inb_nodebug(hc, R_E1_RD_STA))) { | |
2678 | if (debug & DEBUG_HFCMULTI_STATE) | |
2679 | printk(KERN_DEBUG "%s: reread " | |
2680 | "STATE because %d!=%d\n", | |
2681 | __func__, temp, | |
2682 | dch->state); | |
2683 | dch->state = temp; /* repeat */ | |
2684 | } | |
2685 | dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA) | |
2686 | & 0x7; | |
2687 | schedule_event(dch, FLG_PHCHANGE); | |
2688 | if (debug & DEBUG_HFCMULTI_STATE) | |
2689 | printk(KERN_DEBUG | |
2690 | "%s: E1 (id=%d) newstate %x\n", | |
2691 | __func__, hc->id, dch->state); | |
2692 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) | |
2693 | plxsd_checksync(hc, 0); | |
2694 | } | |
2695 | } | |
3bd69ad1 AE |
2696 | if (r_irq_misc & V_TI_IRQ) { |
2697 | if (hc->iclock_on) | |
2698 | mISDN_clock_update(hc->iclock, poll, NULL); | |
af69fb3a | 2699 | handle_timer_irq(hc); |
3bd69ad1 | 2700 | } |
af69fb3a KK |
2701 | |
2702 | if (r_irq_misc & V_DTMF_IRQ) { | |
af69fb3a KK |
2703 | hfcmulti_dtmf(hc); |
2704 | } | |
af69fb3a | 2705 | if (r_irq_misc & V_IRQ_PROC) { |
69e656cc KK |
2706 | static int irq_proc_cnt; |
2707 | if (!irq_proc_cnt++) | |
2708 | printk(KERN_WARNING "%s: got V_IRQ_PROC -" | |
2709 | " this should not happen\n", __func__); | |
af69fb3a KK |
2710 | } |
2711 | ||
2712 | } | |
2713 | if (status & V_FR_IRQSTA) { | |
2714 | /* FIFO IRQ */ | |
2715 | r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW); | |
2716 | for (i = 0; i < 8; i++) { | |
2717 | if (r_irq_oview & (1 << i)) | |
2718 | fifo_irq(hc, i); | |
2719 | } | |
2720 | } | |
2721 | ||
2722 | #ifdef IRQ_DEBUG | |
2723 | irqsem = 0; | |
2724 | #endif | |
2725 | spin_unlock(&hc->lock); | |
2726 | return IRQ_HANDLED; | |
2727 | ||
2728 | irq_notforus: | |
2729 | #ifdef IRQ_DEBUG | |
2730 | irqsem = 0; | |
2731 | #endif | |
2732 | spin_unlock(&hc->lock); | |
2733 | return IRQ_NONE; | |
2734 | } | |
2735 | ||
2736 | ||
2737 | /* | |
2738 | * timer callback for D-chan busy resolution. Currently no function | |
2739 | */ | |
2740 | ||
2741 | static void | |
2742 | hfcmulti_dbusy_timer(struct hfc_multi *hc) | |
2743 | { | |
2744 | } | |
2745 | ||
2746 | ||
2747 | /* | |
2748 | * activate/deactivate hardware for selected channels and mode | |
2749 | * | |
2750 | * configure B-channel with the given protocol | |
2751 | * ch eqals to the HFC-channel (0-31) | |
2752 | * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31 | |
2753 | * for S/T, 1-31 for E1) | |
2754 | * the hdlc interrupts will be set/unset | |
2755 | */ | |
2756 | static int | |
2757 | mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx, | |
2758 | int bank_tx, int slot_rx, int bank_rx) | |
2759 | { | |
2760 | int flow_tx = 0, flow_rx = 0, routing = 0; | |
2761 | int oslot_tx, oslot_rx; | |
2762 | int conf; | |
2763 | ||
2764 | if (ch < 0 || ch > 31) | |
2765 | return EINVAL; | |
2766 | oslot_tx = hc->chan[ch].slot_tx; | |
2767 | oslot_rx = hc->chan[ch].slot_rx; | |
2768 | conf = hc->chan[ch].conf; | |
2769 | ||
2770 | if (debug & DEBUG_HFCMULTI_MODE) | |
2771 | printk(KERN_DEBUG | |
2772 | "%s: card %d channel %d protocol %x slot old=%d new=%d " | |
2773 | "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n", | |
2774 | __func__, hc->id, ch, protocol, oslot_tx, slot_tx, | |
2775 | bank_tx, oslot_rx, slot_rx, bank_rx); | |
2776 | ||
2777 | if (oslot_tx >= 0 && slot_tx != oslot_tx) { | |
2778 | /* remove from slot */ | |
2779 | if (debug & DEBUG_HFCMULTI_MODE) | |
2780 | printk(KERN_DEBUG "%s: remove from slot %d (TX)\n", | |
2781 | __func__, oslot_tx); | |
2782 | if (hc->slot_owner[oslot_tx<<1] == ch) { | |
2783 | HFC_outb(hc, R_SLOT, oslot_tx << 1); | |
2784 | HFC_outb(hc, A_SL_CFG, 0); | |
2785 | HFC_outb(hc, A_CONF, 0); | |
2786 | hc->slot_owner[oslot_tx<<1] = -1; | |
2787 | } else { | |
2788 | if (debug & DEBUG_HFCMULTI_MODE) | |
2789 | printk(KERN_DEBUG | |
2790 | "%s: we are not owner of this tx slot " | |
2791 | "anymore, channel %d is.\n", | |
2792 | __func__, hc->slot_owner[oslot_tx<<1]); | |
2793 | } | |
2794 | } | |
2795 | ||
2796 | if (oslot_rx >= 0 && slot_rx != oslot_rx) { | |
2797 | /* remove from slot */ | |
2798 | if (debug & DEBUG_HFCMULTI_MODE) | |
2799 | printk(KERN_DEBUG | |
2800 | "%s: remove from slot %d (RX)\n", | |
2801 | __func__, oslot_rx); | |
2802 | if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) { | |
2803 | HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR); | |
2804 | HFC_outb(hc, A_SL_CFG, 0); | |
2805 | hc->slot_owner[(oslot_rx << 1) | 1] = -1; | |
2806 | } else { | |
2807 | if (debug & DEBUG_HFCMULTI_MODE) | |
2808 | printk(KERN_DEBUG | |
2809 | "%s: we are not owner of this rx slot " | |
2810 | "anymore, channel %d is.\n", | |
2811 | __func__, | |
2812 | hc->slot_owner[(oslot_rx << 1) | 1]); | |
2813 | } | |
2814 | } | |
2815 | ||
2816 | if (slot_tx < 0) { | |
2817 | flow_tx = 0x80; /* FIFO->ST */ | |
2818 | /* disable pcm slot */ | |
2819 | hc->chan[ch].slot_tx = -1; | |
2820 | hc->chan[ch].bank_tx = 0; | |
2821 | } else { | |
2822 | /* set pcm slot */ | |
2823 | if (hc->chan[ch].txpending) | |
2824 | flow_tx = 0x80; /* FIFO->ST */ | |
2825 | else | |
2826 | flow_tx = 0xc0; /* PCM->ST */ | |
2827 | /* put on slot */ | |
2828 | routing = bank_tx ? 0xc0 : 0x80; | |
2829 | if (conf >= 0 || bank_tx > 1) | |
2830 | routing = 0x40; /* loop */ | |
2831 | if (debug & DEBUG_HFCMULTI_MODE) | |
2832 | printk(KERN_DEBUG "%s: put channel %d to slot %d bank" | |
2833 | " %d flow %02x routing %02x conf %d (TX)\n", | |
2834 | __func__, ch, slot_tx, bank_tx, | |
2835 | flow_tx, routing, conf); | |
2836 | HFC_outb(hc, R_SLOT, slot_tx << 1); | |
2837 | HFC_outb(hc, A_SL_CFG, (ch<<1) | routing); | |
2838 | HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL)); | |
2839 | hc->slot_owner[slot_tx << 1] = ch; | |
2840 | hc->chan[ch].slot_tx = slot_tx; | |
2841 | hc->chan[ch].bank_tx = bank_tx; | |
2842 | } | |
2843 | if (slot_rx < 0) { | |
2844 | /* disable pcm slot */ | |
2845 | flow_rx = 0x80; /* ST->FIFO */ | |
2846 | hc->chan[ch].slot_rx = -1; | |
2847 | hc->chan[ch].bank_rx = 0; | |
2848 | } else { | |
2849 | /* set pcm slot */ | |
2850 | if (hc->chan[ch].txpending) | |
2851 | flow_rx = 0x80; /* ST->FIFO */ | |
2852 | else | |
2853 | flow_rx = 0xc0; /* ST->(FIFO,PCM) */ | |
2854 | /* put on slot */ | |
2855 | routing = bank_rx?0x80:0xc0; /* reversed */ | |
2856 | if (conf >= 0 || bank_rx > 1) | |
2857 | routing = 0x40; /* loop */ | |
2858 | if (debug & DEBUG_HFCMULTI_MODE) | |
2859 | printk(KERN_DEBUG "%s: put channel %d to slot %d bank" | |
2860 | " %d flow %02x routing %02x conf %d (RX)\n", | |
2861 | __func__, ch, slot_rx, bank_rx, | |
2862 | flow_rx, routing, conf); | |
2863 | HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR); | |
2864 | HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing); | |
2865 | hc->slot_owner[(slot_rx<<1)|1] = ch; | |
2866 | hc->chan[ch].slot_rx = slot_rx; | |
2867 | hc->chan[ch].bank_rx = bank_rx; | |
2868 | } | |
2869 | ||
2870 | switch (protocol) { | |
2871 | case (ISDN_P_NONE): | |
2872 | /* disable TX fifo */ | |
2873 | HFC_outb(hc, R_FIFO, ch << 1); | |
2874 | HFC_wait(hc); | |
2875 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF); | |
2876 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2877 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2878 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2879 | HFC_wait(hc); | |
2880 | /* disable RX fifo */ | |
2881 | HFC_outb(hc, R_FIFO, (ch<<1)|1); | |
2882 | HFC_wait(hc); | |
2883 | HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00); | |
2884 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2885 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2886 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2887 | HFC_wait(hc); | |
2888 | if (hc->chan[ch].bch && hc->type != 1) { | |
2889 | hc->hw.a_st_ctrl0[hc->chan[ch].port] &= | |
2890 | ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN; | |
2891 | HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); | |
2892 | /* undocumented: delay after R_ST_SEL */ | |
2893 | udelay(1); | |
2894 | HFC_outb(hc, A_ST_CTRL0, | |
2895 | hc->hw.a_st_ctrl0[hc->chan[ch].port]); | |
2896 | } | |
2897 | if (hc->chan[ch].bch) { | |
2898 | test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); | |
2899 | test_and_clear_bit(FLG_TRANSPARENT, | |
2900 | &hc->chan[ch].bch->Flags); | |
2901 | } | |
2902 | break; | |
2903 | case (ISDN_P_B_RAW): /* B-channel */ | |
2904 | ||
2905 | if (test_bit(HFC_CHIP_B410P, &hc->chip) && | |
2906 | (hc->chan[ch].slot_rx < 0) && | |
2907 | (hc->chan[ch].slot_tx < 0)) { | |
2908 | ||
2909 | printk(KERN_DEBUG | |
2910 | "Setting B-channel %d to echo cancelable " | |
2911 | "state on PCM slot %d\n", ch, | |
2912 | ((ch / 4) * 8) + ((ch % 4) * 4) + 1); | |
2913 | printk(KERN_DEBUG | |
2914 | "Enabling pass through for channel\n"); | |
2915 | vpm_out(hc, ch, ((ch / 4) * 8) + | |
2916 | ((ch % 4) * 4) + 1, 0x01); | |
2917 | /* rx path */ | |
2918 | /* S/T -> PCM */ | |
2919 | HFC_outb(hc, R_FIFO, (ch << 1)); | |
2920 | HFC_wait(hc); | |
2921 | HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); | |
2922 | HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + | |
2923 | ((ch % 4) * 4) + 1) << 1); | |
2924 | HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1)); | |
2925 | ||
2926 | /* PCM -> FIFO */ | |
2927 | HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1); | |
2928 | HFC_wait(hc); | |
2929 | HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); | |
2930 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2931 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2932 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2933 | HFC_wait(hc); | |
2934 | HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + | |
2935 | ((ch % 4) * 4) + 1) << 1) | 1); | |
2936 | HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1); | |
2937 | ||
2938 | /* tx path */ | |
2939 | /* PCM -> S/T */ | |
2940 | HFC_outb(hc, R_FIFO, (ch << 1) | 1); | |
2941 | HFC_wait(hc); | |
2942 | HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); | |
2943 | HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + | |
2944 | ((ch % 4) * 4)) << 1) | 1); | |
2945 | HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1); | |
2946 | ||
2947 | /* FIFO -> PCM */ | |
2948 | HFC_outb(hc, R_FIFO, 0x20 | (ch << 1)); | |
2949 | HFC_wait(hc); | |
2950 | HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); | |
2951 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2952 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2953 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2954 | HFC_wait(hc); | |
2955 | /* tx silence */ | |
8dd2f36f | 2956 | HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); |
af69fb3a KK |
2957 | HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + |
2958 | ((ch % 4) * 4)) << 1); | |
2959 | HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1)); | |
2960 | } else { | |
2961 | /* enable TX fifo */ | |
2962 | HFC_outb(hc, R_FIFO, ch << 1); | |
2963 | HFC_wait(hc); | |
2964 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | | |
2965 | V_HDLC_TRP | V_IFF); | |
2966 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2967 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2968 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2969 | HFC_wait(hc); | |
2970 | /* tx silence */ | |
8dd2f36f | 2971 | HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence); |
af69fb3a KK |
2972 | /* enable RX fifo */ |
2973 | HFC_outb(hc, R_FIFO, (ch<<1)|1); | |
2974 | HFC_wait(hc); | |
2975 | HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP); | |
2976 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2977 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2978 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2979 | HFC_wait(hc); | |
2980 | } | |
2981 | if (hc->type != 1) { | |
2982 | hc->hw.a_st_ctrl0[hc->chan[ch].port] |= | |
2983 | ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; | |
2984 | HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); | |
2985 | /* undocumented: delay after R_ST_SEL */ | |
2986 | udelay(1); | |
2987 | HFC_outb(hc, A_ST_CTRL0, | |
2988 | hc->hw.a_st_ctrl0[hc->chan[ch].port]); | |
2989 | } | |
2990 | if (hc->chan[ch].bch) | |
2991 | test_and_set_bit(FLG_TRANSPARENT, | |
2992 | &hc->chan[ch].bch->Flags); | |
2993 | break; | |
2994 | case (ISDN_P_B_HDLC): /* B-channel */ | |
2995 | case (ISDN_P_TE_S0): /* D-channel */ | |
2996 | case (ISDN_P_NT_S0): | |
2997 | case (ISDN_P_TE_E1): | |
2998 | case (ISDN_P_NT_E1): | |
2999 | /* enable TX fifo */ | |
3000 | HFC_outb(hc, R_FIFO, ch<<1); | |
3001 | HFC_wait(hc); | |
3002 | if (hc->type == 1 || hc->chan[ch].bch) { | |
3003 | /* E1 or B-channel */ | |
3004 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04); | |
3005 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
3006 | } else { | |
3007 | /* D-Channel without HDLC fill flags */ | |
3008 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF); | |
3009 | HFC_outb(hc, A_SUBCH_CFG, 2); | |
3010 | } | |
3011 | HFC_outb(hc, A_IRQ_MSK, V_IRQ); | |
3012 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
3013 | HFC_wait(hc); | |
3014 | /* enable RX fifo */ | |
3015 | HFC_outb(hc, R_FIFO, (ch<<1)|1); | |
3016 | HFC_wait(hc); | |
3017 | HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04); | |
3018 | if (hc->type == 1 || hc->chan[ch].bch) | |
3019 | HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */ | |
3020 | else | |
3021 | HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */ | |
3022 | HFC_outb(hc, A_IRQ_MSK, V_IRQ); | |
3023 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
3024 | HFC_wait(hc); | |
3025 | if (hc->chan[ch].bch) { | |
3026 | test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); | |
3027 | if (hc->type != 1) { | |
3028 | hc->hw.a_st_ctrl0[hc->chan[ch].port] |= | |
3029 | ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN; | |
3030 | HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); | |
3031 | /* undocumented: delay after R_ST_SEL */ | |
3032 | udelay(1); | |
3033 | HFC_outb(hc, A_ST_CTRL0, | |
3034 | hc->hw.a_st_ctrl0[hc->chan[ch].port]); | |
3035 | } | |
3036 | } | |
3037 | break; | |
3038 | default: | |
3039 | printk(KERN_DEBUG "%s: protocol not known %x\n", | |
3040 | __func__, protocol); | |
3041 | hc->chan[ch].protocol = ISDN_P_NONE; | |
3042 | return -ENOPROTOOPT; | |
3043 | } | |
3044 | hc->chan[ch].protocol = protocol; | |
3045 | return 0; | |
3046 | } | |
3047 | ||
3048 | ||
3049 | /* | |
3050 | * connect/disconnect PCM | |
3051 | */ | |
3052 | ||
3053 | static void | |
3054 | hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx, | |
3055 | int slot_rx, int bank_rx) | |
3056 | { | |
3057 | if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) { | |
3058 | /* disable PCM */ | |
3059 | mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0); | |
3060 | return; | |
3061 | } | |
3062 | ||
3063 | /* enable pcm */ | |
3064 | mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx, | |
3065 | slot_rx, bank_rx); | |
3066 | } | |
3067 | ||
3068 | /* | |
3069 | * set/disable conference | |
3070 | */ | |
3071 | ||
3072 | static void | |
3073 | hfcmulti_conf(struct hfc_multi *hc, int ch, int num) | |
3074 | { | |
3075 | if (num >= 0 && num <= 7) | |
3076 | hc->chan[ch].conf = num; | |
3077 | else | |
3078 | hc->chan[ch].conf = -1; | |
3079 | mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx, | |
3080 | hc->chan[ch].bank_tx, hc->chan[ch].slot_rx, | |
3081 | hc->chan[ch].bank_rx); | |
3082 | } | |
3083 | ||
3084 | ||
3085 | /* | |
3086 | * set/disable sample loop | |
3087 | */ | |
3088 | ||
3089 | /* NOTE: this function is experimental and therefore disabled */ | |
3090 | ||
3091 | /* | |
3092 | * Layer 1 callback function | |
3093 | */ | |
3094 | static int | |
3095 | hfcm_l1callback(struct dchannel *dch, u_int cmd) | |
3096 | { | |
3097 | struct hfc_multi *hc = dch->hw; | |
3098 | u_long flags; | |
3099 | ||
3100 | switch (cmd) { | |
3101 | case INFO3_P8: | |
3102 | case INFO3_P10: | |
3103 | break; | |
3104 | case HW_RESET_REQ: | |
3105 | /* start activation */ | |
3106 | spin_lock_irqsave(&hc->lock, flags); | |
3107 | if (hc->type == 1) { | |
3108 | if (debug & DEBUG_HFCMULTI_MSG) | |
3109 | printk(KERN_DEBUG | |
3110 | "%s: HW_RESET_REQ no BRI\n", | |
3111 | __func__); | |
3112 | } else { | |
3113 | HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); | |
3114 | /* undocumented: delay after R_ST_SEL */ | |
3115 | udelay(1); | |
3116 | HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */ | |
3117 | udelay(6); /* wait at least 5,21us */ | |
3118 | HFC_outb(hc, A_ST_WR_STATE, 3); | |
3119 | HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3)); | |
3120 | /* activate */ | |
3121 | } | |
3122 | spin_unlock_irqrestore(&hc->lock, flags); | |
3123 | l1_event(dch->l1, HW_POWERUP_IND); | |
3124 | break; | |
3125 | case HW_DEACT_REQ: | |
3126 | /* start deactivation */ | |
3127 | spin_lock_irqsave(&hc->lock, flags); | |
3128 | if (hc->type == 1) { | |
3129 | if (debug & DEBUG_HFCMULTI_MSG) | |
3130 | printk(KERN_DEBUG | |
3131 | "%s: HW_DEACT_REQ no BRI\n", | |
3132 | __func__); | |
3133 | } else { | |
3134 | HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); | |
3135 | /* undocumented: delay after R_ST_SEL */ | |
3136 | udelay(1); | |
3137 | HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2); | |
3138 | /* deactivate */ | |
3139 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
3140 | hc->syncronized &= | |
3141 | ~(1 << hc->chan[dch->slot].port); | |
3142 | plxsd_checksync(hc, 0); | |
3143 | } | |
3144 | } | |
3145 | skb_queue_purge(&dch->squeue); | |
3146 | if (dch->tx_skb) { | |
3147 | dev_kfree_skb(dch->tx_skb); | |
3148 | dch->tx_skb = NULL; | |
3149 | } | |
3150 | dch->tx_idx = 0; | |
3151 | if (dch->rx_skb) { | |
3152 | dev_kfree_skb(dch->rx_skb); | |
3153 | dch->rx_skb = NULL; | |
3154 | } | |
3155 | test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); | |
3156 | if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) | |
3157 | del_timer(&dch->timer); | |
3158 | spin_unlock_irqrestore(&hc->lock, flags); | |
3159 | break; | |
3160 | case HW_POWERUP_REQ: | |
3161 | spin_lock_irqsave(&hc->lock, flags); | |
3162 | if (hc->type == 1) { | |
3163 | if (debug & DEBUG_HFCMULTI_MSG) | |
3164 | printk(KERN_DEBUG | |
3165 | "%s: HW_POWERUP_REQ no BRI\n", | |
3166 | __func__); | |
3167 | } else { | |
3168 | HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); | |
3169 | /* undocumented: delay after R_ST_SEL */ | |
3170 | udelay(1); | |
3171 | HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */ | |
3172 | udelay(6); /* wait at least 5,21us */ | |
3173 | HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */ | |
3174 | } | |
3175 | spin_unlock_irqrestore(&hc->lock, flags); | |
3176 | break; | |
3177 | case PH_ACTIVATE_IND: | |
3178 | test_and_set_bit(FLG_ACTIVE, &dch->Flags); | |
3179 | _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, | |
3180 | GFP_ATOMIC); | |
3181 | break; | |
3182 | case PH_DEACTIVATE_IND: | |
3183 | test_and_clear_bit(FLG_ACTIVE, &dch->Flags); | |
3184 | _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, | |
3185 | GFP_ATOMIC); | |
3186 | break; | |
3187 | default: | |
3188 | if (dch->debug & DEBUG_HW) | |
3189 | printk(KERN_DEBUG "%s: unknown command %x\n", | |
3190 | __func__, cmd); | |
3191 | return -1; | |
3192 | } | |
3193 | return 0; | |
3194 | } | |
3195 | ||
3196 | /* | |
3197 | * Layer2 -> Layer 1 Transfer | |
3198 | */ | |
3199 | ||
3200 | static int | |
3201 | handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb) | |
3202 | { | |
3203 | struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); | |
3204 | struct dchannel *dch = container_of(dev, struct dchannel, dev); | |
3205 | struct hfc_multi *hc = dch->hw; | |
3206 | struct mISDNhead *hh = mISDN_HEAD_P(skb); | |
3207 | int ret = -EINVAL; | |
3208 | unsigned int id; | |
3209 | u_long flags; | |
3210 | ||
3211 | switch (hh->prim) { | |
3212 | case PH_DATA_REQ: | |
3213 | if (skb->len < 1) | |
3214 | break; | |
3215 | spin_lock_irqsave(&hc->lock, flags); | |
3216 | ret = dchannel_senddata(dch, skb); | |
3217 | if (ret > 0) { /* direct TX */ | |
3218 | id = hh->id; /* skb can be freed */ | |
3219 | hfcmulti_tx(hc, dch->slot); | |
3220 | ret = 0; | |
3221 | /* start fifo */ | |
3222 | HFC_outb(hc, R_FIFO, 0); | |
3223 | HFC_wait(hc); | |
3224 | spin_unlock_irqrestore(&hc->lock, flags); | |
3225 | queue_ch_frame(ch, PH_DATA_CNF, id, NULL); | |
3226 | } else | |
3227 | spin_unlock_irqrestore(&hc->lock, flags); | |
3228 | return ret; | |
3229 | case PH_ACTIVATE_REQ: | |
3230 | if (dch->dev.D.protocol != ISDN_P_TE_S0) { | |
3231 | spin_lock_irqsave(&hc->lock, flags); | |
3232 | ret = 0; | |
3233 | if (debug & DEBUG_HFCMULTI_MSG) | |
3234 | printk(KERN_DEBUG | |
3235 | "%s: PH_ACTIVATE port %d (0..%d)\n", | |
3236 | __func__, hc->chan[dch->slot].port, | |
3237 | hc->ports-1); | |
3238 | /* start activation */ | |
3239 | if (hc->type == 1) { | |
3240 | ph_state_change(dch); | |
3241 | if (debug & DEBUG_HFCMULTI_STATE) | |
3242 | printk(KERN_DEBUG | |
3243 | "%s: E1 report state %x \n", | |
3244 | __func__, dch->state); | |
3245 | } else { | |
3246 | HFC_outb(hc, R_ST_SEL, | |
3247 | hc->chan[dch->slot].port); | |
3248 | /* undocumented: delay after R_ST_SEL */ | |
3249 | udelay(1); | |
3250 | HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1); | |
3251 | /* G1 */ | |
3252 | udelay(6); /* wait at least 5,21us */ | |
3253 | HFC_outb(hc, A_ST_WR_STATE, 1); | |
3254 | HFC_outb(hc, A_ST_WR_STATE, 1 | | |
3255 | (V_ST_ACT*3)); /* activate */ | |
3256 | dch->state = 1; | |
3257 | } | |
3258 | spin_unlock_irqrestore(&hc->lock, flags); | |
3259 | } else | |
3260 | ret = l1_event(dch->l1, hh->prim); | |
3261 | break; | |
3262 | case PH_DEACTIVATE_REQ: | |
3263 | test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); | |
3264 | if (dch->dev.D.protocol != ISDN_P_TE_S0) { | |
3265 | spin_lock_irqsave(&hc->lock, flags); | |
3266 | if (debug & DEBUG_HFCMULTI_MSG) | |
3267 | printk(KERN_DEBUG | |
3268 | "%s: PH_DEACTIVATE port %d (0..%d)\n", | |
3269 | __func__, hc->chan[dch->slot].port, | |
3270 | hc->ports-1); | |
3271 | /* start deactivation */ | |
3272 | if (hc->type == 1) { | |
3273 | if (debug & DEBUG_HFCMULTI_MSG) | |
3274 | printk(KERN_DEBUG | |
3275 | "%s: PH_DEACTIVATE no BRI\n", | |
3276 | __func__); | |
3277 | } else { | |
3278 | HFC_outb(hc, R_ST_SEL, | |
3279 | hc->chan[dch->slot].port); | |
3280 | /* undocumented: delay after R_ST_SEL */ | |
3281 | udelay(1); | |
3282 | HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); | |
3283 | /* deactivate */ | |
3284 | dch->state = 1; | |
3285 | } | |
3286 | skb_queue_purge(&dch->squeue); | |
3287 | if (dch->tx_skb) { | |
3288 | dev_kfree_skb(dch->tx_skb); | |
3289 | dch->tx_skb = NULL; | |
3290 | } | |
3291 | dch->tx_idx = 0; | |
3292 | if (dch->rx_skb) { | |
3293 | dev_kfree_skb(dch->rx_skb); | |
3294 | dch->rx_skb = NULL; | |
3295 | } | |
3296 | test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); | |
3297 | if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) | |
3298 | del_timer(&dch->timer); | |
3299 | #ifdef FIXME | |
3300 | if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags)) | |
3301 | dchannel_sched_event(&hc->dch, D_CLEARBUSY); | |
3302 | #endif | |
3303 | ret = 0; | |
3304 | spin_unlock_irqrestore(&hc->lock, flags); | |
3305 | } else | |
3306 | ret = l1_event(dch->l1, hh->prim); | |
3307 | break; | |
3308 | } | |
3309 | if (!ret) | |
3310 | dev_kfree_skb(skb); | |
3311 | return ret; | |
3312 | } | |
3313 | ||
3314 | static void | |
3315 | deactivate_bchannel(struct bchannel *bch) | |
3316 | { | |
3317 | struct hfc_multi *hc = bch->hw; | |
3318 | u_long flags; | |
3319 | ||
3320 | spin_lock_irqsave(&hc->lock, flags); | |
3321 | if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) { | |
3322 | dev_kfree_skb(bch->next_skb); | |
3323 | bch->next_skb = NULL; | |
3324 | } | |
3325 | if (bch->tx_skb) { | |
3326 | dev_kfree_skb(bch->tx_skb); | |
3327 | bch->tx_skb = NULL; | |
3328 | } | |
3329 | bch->tx_idx = 0; | |
3330 | if (bch->rx_skb) { | |
3331 | dev_kfree_skb(bch->rx_skb); | |
3332 | bch->rx_skb = NULL; | |
3333 | } | |
3334 | hc->chan[bch->slot].coeff_count = 0; | |
3335 | test_and_clear_bit(FLG_ACTIVE, &bch->Flags); | |
3336 | test_and_clear_bit(FLG_TX_BUSY, &bch->Flags); | |
3337 | hc->chan[bch->slot].rx_off = 0; | |
3338 | hc->chan[bch->slot].conf = -1; | |
3339 | mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0); | |
3340 | spin_unlock_irqrestore(&hc->lock, flags); | |
3341 | } | |
3342 | ||
3343 | static int | |
3344 | handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb) | |
3345 | { | |
3346 | struct bchannel *bch = container_of(ch, struct bchannel, ch); | |
3347 | struct hfc_multi *hc = bch->hw; | |
3348 | int ret = -EINVAL; | |
3349 | struct mISDNhead *hh = mISDN_HEAD_P(skb); | |
3350 | unsigned int id; | |
3351 | u_long flags; | |
3352 | ||
3353 | switch (hh->prim) { | |
3354 | case PH_DATA_REQ: | |
3355 | if (!skb->len) | |
3356 | break; | |
3357 | spin_lock_irqsave(&hc->lock, flags); | |
3358 | ret = bchannel_senddata(bch, skb); | |
3359 | if (ret > 0) { /* direct TX */ | |
3360 | id = hh->id; /* skb can be freed */ | |
3361 | hfcmulti_tx(hc, bch->slot); | |
3362 | ret = 0; | |
3363 | /* start fifo */ | |
3364 | HFC_outb_nodebug(hc, R_FIFO, 0); | |
3365 | HFC_wait_nodebug(hc); | |
3366 | if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) { | |
3367 | spin_unlock_irqrestore(&hc->lock, flags); | |
3368 | queue_ch_frame(ch, PH_DATA_CNF, id, NULL); | |
3369 | } else | |
3370 | spin_unlock_irqrestore(&hc->lock, flags); | |
3371 | } else | |
3372 | spin_unlock_irqrestore(&hc->lock, flags); | |
3373 | return ret; | |
3374 | case PH_ACTIVATE_REQ: | |
3375 | if (debug & DEBUG_HFCMULTI_MSG) | |
3376 | printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n", | |
3377 | __func__, bch->slot); | |
3378 | spin_lock_irqsave(&hc->lock, flags); | |
3379 | /* activate B-channel if not already activated */ | |
3380 | if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { | |
3381 | hc->chan[bch->slot].txpending = 0; | |
3382 | ret = mode_hfcmulti(hc, bch->slot, | |
3383 | ch->protocol, | |
3384 | hc->chan[bch->slot].slot_tx, | |
3385 | hc->chan[bch->slot].bank_tx, | |
3386 | hc->chan[bch->slot].slot_rx, | |
3387 | hc->chan[bch->slot].bank_rx); | |
3388 | if (!ret) { | |
3389 | if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf | |
3390 | && test_bit(HFC_CHIP_DTMF, &hc->chip)) { | |
3391 | /* start decoder */ | |
3392 | hc->dtmf = 1; | |
3393 | if (debug & DEBUG_HFCMULTI_DTMF) | |
3394 | printk(KERN_DEBUG | |
3395 | "%s: start dtmf decoder\n", | |
3396 | __func__); | |
3397 | HFC_outb(hc, R_DTMF, hc->hw.r_dtmf | | |
3398 | V_RST_DTMF); | |
3399 | } | |
3400 | } | |
3401 | } else | |
3402 | ret = 0; | |
3403 | spin_unlock_irqrestore(&hc->lock, flags); | |
3404 | if (!ret) | |
3405 | _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL, | |
3406 | GFP_KERNEL); | |
3407 | break; | |
3408 | case PH_CONTROL_REQ: | |
3409 | spin_lock_irqsave(&hc->lock, flags); | |
3410 | switch (hh->id) { | |
3411 | case HFC_SPL_LOOP_ON: /* set sample loop */ | |
3412 | if (debug & DEBUG_HFCMULTI_MSG) | |
3413 | printk(KERN_DEBUG | |
3414 | "%s: HFC_SPL_LOOP_ON (len = %d)\n", | |
3415 | __func__, skb->len); | |
3416 | ret = 0; | |
3417 | break; | |
3418 | case HFC_SPL_LOOP_OFF: /* set silence */ | |
3419 | if (debug & DEBUG_HFCMULTI_MSG) | |
3420 | printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n", | |
3421 | __func__); | |
3422 | ret = 0; | |
3423 | break; | |
3424 | default: | |
3425 | printk(KERN_ERR | |
3426 | "%s: unknown PH_CONTROL_REQ info %x\n", | |
3427 | __func__, hh->id); | |
3428 | ret = -EINVAL; | |
3429 | } | |
3430 | spin_unlock_irqrestore(&hc->lock, flags); | |
3431 | break; | |
3432 | case PH_DEACTIVATE_REQ: | |
3433 | deactivate_bchannel(bch); /* locked there */ | |
3434 | _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL, | |
3435 | GFP_KERNEL); | |
3436 | ret = 0; | |
3437 | break; | |
3438 | } | |
3439 | if (!ret) | |
3440 | dev_kfree_skb(skb); | |
3441 | return ret; | |
3442 | } | |
3443 | ||
3444 | /* | |
3445 | * bchannel control function | |
3446 | */ | |
3447 | static int | |
3448 | channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) | |
3449 | { | |
3450 | int ret = 0; | |
3451 | struct dsp_features *features = | |
3452 | (struct dsp_features *)(*((u_long *)&cq->p1)); | |
3453 | struct hfc_multi *hc = bch->hw; | |
3454 | int slot_tx; | |
3455 | int bank_tx; | |
3456 | int slot_rx; | |
3457 | int bank_rx; | |
3458 | int num; | |
3459 | ||
3460 | switch (cq->op) { | |
3461 | case MISDN_CTRL_GETOP: | |
3462 | cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP | |
8dd2f36f | 3463 | | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY; |
af69fb3a KK |
3464 | break; |
3465 | case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */ | |
3466 | hc->chan[bch->slot].rx_off = !!cq->p1; | |
3467 | if (!hc->chan[bch->slot].rx_off) { | |
3468 | /* reset fifo on rx on */ | |
3469 | HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1); | |
3470 | HFC_wait_nodebug(hc); | |
3471 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); | |
3472 | HFC_wait_nodebug(hc); | |
3473 | } | |
3474 | if (debug & DEBUG_HFCMULTI_MSG) | |
3475 | printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n", | |
3476 | __func__, bch->nr, hc->chan[bch->slot].rx_off); | |
3477 | break; | |
8dd2f36f AE |
3478 | case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */ |
3479 | test_and_set_bit(FLG_FILLEMPTY, &bch->Flags); | |
3480 | if (debug & DEBUG_HFCMULTI_MSG) | |
3481 | printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d " | |
3482 | "off=%d)\n", __func__, bch->nr, !!cq->p1); | |
3483 | break; | |
af69fb3a KK |
3484 | case MISDN_CTRL_HW_FEATURES: /* fill features structure */ |
3485 | if (debug & DEBUG_HFCMULTI_MSG) | |
3486 | printk(KERN_DEBUG "%s: HW_FEATURE request\n", | |
3487 | __func__); | |
3488 | /* create confirm */ | |
3489 | features->hfc_id = hc->id; | |
3490 | if (test_bit(HFC_CHIP_DTMF, &hc->chip)) | |
3491 | features->hfc_dtmf = 1; | |
3492 | features->hfc_loops = 0; | |
3493 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) { | |
3494 | features->hfc_echocanhw = 1; | |
3495 | } else { | |
3496 | features->pcm_id = hc->pcm; | |
3497 | features->pcm_slots = hc->slots; | |
3498 | features->pcm_banks = 2; | |
3499 | } | |
3500 | break; | |
3501 | case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */ | |
3502 | slot_tx = cq->p1 & 0xff; | |
3503 | bank_tx = cq->p1 >> 8; | |
3504 | slot_rx = cq->p2 & 0xff; | |
3505 | bank_rx = cq->p2 >> 8; | |
3506 | if (debug & DEBUG_HFCMULTI_MSG) | |
3507 | printk(KERN_DEBUG | |
3508 | "%s: HFC_PCM_CONN slot %d bank %d (TX) " | |
3509 | "slot %d bank %d (RX)\n", | |
3510 | __func__, slot_tx, bank_tx, | |
3511 | slot_rx, bank_rx); | |
3512 | if (slot_tx < hc->slots && bank_tx <= 2 && | |
3513 | slot_rx < hc->slots && bank_rx <= 2) | |
3514 | hfcmulti_pcm(hc, bch->slot, | |
3515 | slot_tx, bank_tx, slot_rx, bank_rx); | |
3516 | else { | |
3517 | printk(KERN_WARNING | |
3518 | "%s: HFC_PCM_CONN slot %d bank %d (TX) " | |
3519 | "slot %d bank %d (RX) out of range\n", | |
3520 | __func__, slot_tx, bank_tx, | |
3521 | slot_rx, bank_rx); | |
3522 | ret = -EINVAL; | |
3523 | } | |
3524 | break; | |
3525 | case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */ | |
3526 | if (debug & DEBUG_HFCMULTI_MSG) | |
3527 | printk(KERN_DEBUG "%s: HFC_PCM_DISC\n", | |
3528 | __func__); | |
3529 | hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0); | |
3530 | break; | |
3531 | case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */ | |
3532 | num = cq->p1 & 0xff; | |
3533 | if (debug & DEBUG_HFCMULTI_MSG) | |
3534 | printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n", | |
3535 | __func__, num); | |
3536 | if (num <= 7) | |
3537 | hfcmulti_conf(hc, bch->slot, num); | |
3538 | else { | |
3539 | printk(KERN_WARNING | |
3540 | "%s: HW_CONF_JOIN conf %d out of range\n", | |
3541 | __func__, num); | |
3542 | ret = -EINVAL; | |
3543 | } | |
3544 | break; | |
3545 | case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */ | |
3546 | if (debug & DEBUG_HFCMULTI_MSG) | |
3547 | printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__); | |
3548 | hfcmulti_conf(hc, bch->slot, -1); | |
3549 | break; | |
3550 | case MISDN_CTRL_HFC_ECHOCAN_ON: | |
3551 | if (debug & DEBUG_HFCMULTI_MSG) | |
3552 | printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__); | |
3553 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) | |
3554 | vpm_echocan_on(hc, bch->slot, cq->p1); | |
3555 | else | |
3556 | ret = -EINVAL; | |
3557 | break; | |
3558 | ||
3559 | case MISDN_CTRL_HFC_ECHOCAN_OFF: | |
3560 | if (debug & DEBUG_HFCMULTI_MSG) | |
3561 | printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n", | |
3562 | __func__); | |
3563 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) | |
3564 | vpm_echocan_off(hc, bch->slot); | |
3565 | else | |
3566 | ret = -EINVAL; | |
3567 | break; | |
3568 | default: | |
3569 | printk(KERN_WARNING "%s: unknown Op %x\n", | |
3570 | __func__, cq->op); | |
3571 | ret = -EINVAL; | |
3572 | break; | |
3573 | } | |
3574 | return ret; | |
3575 | } | |
3576 | ||
3577 | static int | |
3578 | hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) | |
3579 | { | |
3580 | struct bchannel *bch = container_of(ch, struct bchannel, ch); | |
3581 | struct hfc_multi *hc = bch->hw; | |
3582 | int err = -EINVAL; | |
3583 | u_long flags; | |
3584 | ||
3585 | if (bch->debug & DEBUG_HW) | |
3586 | printk(KERN_DEBUG "%s: cmd:%x %p\n", | |
3587 | __func__, cmd, arg); | |
3588 | switch (cmd) { | |
3589 | case CLOSE_CHANNEL: | |
3590 | test_and_clear_bit(FLG_OPEN, &bch->Flags); | |
3591 | if (test_bit(FLG_ACTIVE, &bch->Flags)) | |
3592 | deactivate_bchannel(bch); /* locked there */ | |
3593 | ch->protocol = ISDN_P_NONE; | |
3594 | ch->peer = NULL; | |
3595 | module_put(THIS_MODULE); | |
3596 | err = 0; | |
3597 | break; | |
3598 | case CONTROL_CHANNEL: | |
3599 | spin_lock_irqsave(&hc->lock, flags); | |
3600 | err = channel_bctrl(bch, arg); | |
3601 | spin_unlock_irqrestore(&hc->lock, flags); | |
3602 | break; | |
3603 | default: | |
3604 | printk(KERN_WARNING "%s: unknown prim(%x)\n", | |
3605 | __func__, cmd); | |
3606 | } | |
3607 | return err; | |
3608 | } | |
3609 | ||
3610 | /* | |
3611 | * handle D-channel events | |
3612 | * | |
3613 | * handle state change event | |
3614 | */ | |
3615 | static void | |
3616 | ph_state_change(struct dchannel *dch) | |
3617 | { | |
20b78804 | 3618 | struct hfc_multi *hc; |
af69fb3a KK |
3619 | int ch, i; |
3620 | ||
3621 | if (!dch) { | |
3622 | printk(KERN_WARNING "%s: ERROR given dch is NULL\n", | |
3623 | __func__); | |
3624 | return; | |
3625 | } | |
20b78804 | 3626 | hc = dch->hw; |
af69fb3a KK |
3627 | ch = dch->slot; |
3628 | ||
3629 | if (hc->type == 1) { | |
3630 | if (dch->dev.D.protocol == ISDN_P_TE_E1) { | |
3631 | if (debug & DEBUG_HFCMULTI_STATE) | |
3632 | printk(KERN_DEBUG | |
3633 | "%s: E1 TE (id=%d) newstate %x\n", | |
3634 | __func__, hc->id, dch->state); | |
3635 | } else { | |
3636 | if (debug & DEBUG_HFCMULTI_STATE) | |
3637 | printk(KERN_DEBUG | |
3638 | "%s: E1 NT (id=%d) newstate %x\n", | |
3639 | __func__, hc->id, dch->state); | |
3640 | } | |
3641 | switch (dch->state) { | |
3642 | case (1): | |
3643 | if (hc->e1_state != 1) { | |
3644 | for (i = 1; i <= 31; i++) { | |
3645 | /* reset fifos on e1 activation */ | |
3646 | HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1); | |
3647 | HFC_wait_nodebug(hc); | |
3648 | HFC_outb_nodebug(hc, | |
3649 | R_INC_RES_FIFO, V_RES_F); | |
3650 | HFC_wait_nodebug(hc); | |
3651 | } | |
3652 | } | |
3653 | test_and_set_bit(FLG_ACTIVE, &dch->Flags); | |
3654 | _queue_data(&dch->dev.D, PH_ACTIVATE_IND, | |
3655 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3656 | break; | |
3657 | ||
3658 | default: | |
3659 | if (hc->e1_state != 1) | |
3660 | return; | |
3661 | test_and_clear_bit(FLG_ACTIVE, &dch->Flags); | |
3662 | _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, | |
3663 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3664 | } | |
3665 | hc->e1_state = dch->state; | |
3666 | } else { | |
3667 | if (dch->dev.D.protocol == ISDN_P_TE_S0) { | |
3668 | if (debug & DEBUG_HFCMULTI_STATE) | |
3669 | printk(KERN_DEBUG | |
3670 | "%s: S/T TE newstate %x\n", | |
3671 | __func__, dch->state); | |
3672 | switch (dch->state) { | |
3673 | case (0): | |
3674 | l1_event(dch->l1, HW_RESET_IND); | |
3675 | break; | |
3676 | case (3): | |
3677 | l1_event(dch->l1, HW_DEACT_IND); | |
3678 | break; | |
3679 | case (5): | |
3680 | case (8): | |
3681 | l1_event(dch->l1, ANYSIGNAL); | |
3682 | break; | |
3683 | case (6): | |
3684 | l1_event(dch->l1, INFO2); | |
3685 | break; | |
3686 | case (7): | |
3687 | l1_event(dch->l1, INFO4_P8); | |
3688 | break; | |
3689 | } | |
3690 | } else { | |
3691 | if (debug & DEBUG_HFCMULTI_STATE) | |
3692 | printk(KERN_DEBUG "%s: S/T NT newstate %x\n", | |
3693 | __func__, dch->state); | |
3694 | switch (dch->state) { | |
3695 | case (2): | |
3696 | if (hc->chan[ch].nt_timer == 0) { | |
3697 | hc->chan[ch].nt_timer = -1; | |
3698 | HFC_outb(hc, R_ST_SEL, | |
3699 | hc->chan[ch].port); | |
3700 | /* undocumented: delay after R_ST_SEL */ | |
3701 | udelay(1); | |
3702 | HFC_outb(hc, A_ST_WR_STATE, 4 | | |
3703 | V_ST_LD_STA); /* G4 */ | |
3704 | udelay(6); /* wait at least 5,21us */ | |
3705 | HFC_outb(hc, A_ST_WR_STATE, 4); | |
3706 | dch->state = 4; | |
3707 | } else { | |
3708 | /* one extra count for the next event */ | |
3709 | hc->chan[ch].nt_timer = | |
3710 | nt_t1_count[poll_timer] + 1; | |
3711 | HFC_outb(hc, R_ST_SEL, | |
3712 | hc->chan[ch].port); | |
3713 | /* undocumented: delay after R_ST_SEL */ | |
3714 | udelay(1); | |
3715 | /* allow G2 -> G3 transition */ | |
3716 | HFC_outb(hc, A_ST_WR_STATE, 2 | | |
3717 | V_SET_G2_G3); | |
3718 | } | |
3719 | break; | |
3720 | case (1): | |
3721 | hc->chan[ch].nt_timer = -1; | |
3722 | test_and_clear_bit(FLG_ACTIVE, &dch->Flags); | |
3723 | _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, | |
3724 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3725 | break; | |
3726 | case (4): | |
3727 | hc->chan[ch].nt_timer = -1; | |
3728 | break; | |
3729 | case (3): | |
3730 | hc->chan[ch].nt_timer = -1; | |
3731 | test_and_set_bit(FLG_ACTIVE, &dch->Flags); | |
3732 | _queue_data(&dch->dev.D, PH_ACTIVATE_IND, | |
3733 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3734 | break; | |
3735 | } | |
3736 | } | |
3737 | } | |
3738 | } | |
3739 | ||
3740 | /* | |
3741 | * called for card mode init message | |
3742 | */ | |
3743 | ||
3744 | static void | |
3745 | hfcmulti_initmode(struct dchannel *dch) | |
3746 | { | |
3747 | struct hfc_multi *hc = dch->hw; | |
3748 | u_char a_st_wr_state, r_e1_wr_sta; | |
3749 | int i, pt; | |
3750 | ||
3751 | if (debug & DEBUG_HFCMULTI_INIT) | |
3752 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
3753 | ||
3754 | if (hc->type == 1) { | |
3755 | hc->chan[hc->dslot].slot_tx = -1; | |
3756 | hc->chan[hc->dslot].slot_rx = -1; | |
3757 | hc->chan[hc->dslot].conf = -1; | |
3758 | if (hc->dslot) { | |
3759 | mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol, | |
3760 | -1, 0, -1, 0); | |
3761 | dch->timer.function = (void *) hfcmulti_dbusy_timer; | |
3762 | dch->timer.data = (long) dch; | |
3763 | init_timer(&dch->timer); | |
3764 | } | |
3765 | for (i = 1; i <= 31; i++) { | |
3766 | if (i == hc->dslot) | |
3767 | continue; | |
3768 | hc->chan[i].slot_tx = -1; | |
3769 | hc->chan[i].slot_rx = -1; | |
3770 | hc->chan[i].conf = -1; | |
3771 | mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0); | |
3772 | } | |
3773 | /* E1 */ | |
3774 | if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { | |
3775 | HFC_outb(hc, R_LOS0, 255); /* 2 ms */ | |
3776 | HFC_outb(hc, R_LOS1, 255); /* 512 ms */ | |
3777 | } | |
3778 | if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) { | |
3779 | HFC_outb(hc, R_RX0, 0); | |
3780 | hc->hw.r_tx0 = 0 | V_OUT_EN; | |
3781 | } else { | |
3782 | HFC_outb(hc, R_RX0, 1); | |
3783 | hc->hw.r_tx0 = 1 | V_OUT_EN; | |
3784 | } | |
3785 | hc->hw.r_tx1 = V_ATX | V_NTRI; | |
3786 | HFC_outb(hc, R_TX0, hc->hw.r_tx0); | |
3787 | HFC_outb(hc, R_TX1, hc->hw.r_tx1); | |
3788 | HFC_outb(hc, R_TX_FR0, 0x00); | |
3789 | HFC_outb(hc, R_TX_FR1, 0xf8); | |
3790 | ||
3791 | if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) | |
3792 | HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E); | |
3793 | ||
3794 | HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0); | |
3795 | ||
3796 | if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) | |
3797 | HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC); | |
3798 | ||
3799 | if (dch->dev.D.protocol == ISDN_P_NT_E1) { | |
3800 | if (debug & DEBUG_HFCMULTI_INIT) | |
3801 | printk(KERN_DEBUG "%s: E1 port is NT-mode\n", | |
3802 | __func__); | |
3803 | r_e1_wr_sta = 0; /* G0 */ | |
3804 | hc->e1_getclock = 0; | |
3805 | } else { | |
3806 | if (debug & DEBUG_HFCMULTI_INIT) | |
3807 | printk(KERN_DEBUG "%s: E1 port is TE-mode\n", | |
3808 | __func__); | |
3809 | r_e1_wr_sta = 0; /* F0 */ | |
3810 | hc->e1_getclock = 1; | |
3811 | } | |
3812 | if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) | |
3813 | HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); | |
3814 | else | |
3815 | HFC_outb(hc, R_SYNC_OUT, 0); | |
3816 | if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip)) | |
3817 | hc->e1_getclock = 1; | |
3818 | if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip)) | |
3819 | hc->e1_getclock = 0; | |
3820 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
3821 | /* SLAVE (clock master) */ | |
3822 | if (debug & DEBUG_HFCMULTI_INIT) | |
3823 | printk(KERN_DEBUG | |
3824 | "%s: E1 port is clock master " | |
3825 | "(clock from PCM)\n", __func__); | |
3826 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC); | |
3827 | } else { | |
3828 | if (hc->e1_getclock) { | |
3829 | /* MASTER (clock slave) */ | |
3830 | if (debug & DEBUG_HFCMULTI_INIT) | |
3831 | printk(KERN_DEBUG | |
3832 | "%s: E1 port is clock slave " | |
3833 | "(clock to PCM)\n", __func__); | |
3834 | HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); | |
3835 | } else { | |
3836 | /* MASTER (clock master) */ | |
3837 | if (debug & DEBUG_HFCMULTI_INIT) | |
3838 | printk(KERN_DEBUG "%s: E1 port is " | |
3839 | "clock master " | |
3840 | "(clock from QUARTZ)\n", | |
3841 | __func__); | |
3842 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | | |
3843 | V_PCM_SYNC | V_JATT_OFF); | |
3844 | HFC_outb(hc, R_SYNC_OUT, 0); | |
3845 | } | |
3846 | } | |
3847 | HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */ | |
3848 | HFC_outb(hc, R_PWM_MD, V_PWM0_MD); | |
3849 | HFC_outb(hc, R_PWM0, 0x50); | |
3850 | HFC_outb(hc, R_PWM1, 0xff); | |
3851 | /* state machine setup */ | |
3852 | HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA); | |
3853 | udelay(6); /* wait at least 5,21us */ | |
3854 | HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta); | |
3855 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
3856 | hc->syncronized = 0; | |
3857 | plxsd_checksync(hc, 0); | |
3858 | } | |
3859 | } else { | |
3860 | i = dch->slot; | |
3861 | hc->chan[i].slot_tx = -1; | |
3862 | hc->chan[i].slot_rx = -1; | |
3863 | hc->chan[i].conf = -1; | |
3864 | mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0); | |
3865 | dch->timer.function = (void *)hfcmulti_dbusy_timer; | |
3866 | dch->timer.data = (long) dch; | |
3867 | init_timer(&dch->timer); | |
3868 | hc->chan[i - 2].slot_tx = -1; | |
3869 | hc->chan[i - 2].slot_rx = -1; | |
3870 | hc->chan[i - 2].conf = -1; | |
3871 | mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0); | |
3872 | hc->chan[i - 1].slot_tx = -1; | |
3873 | hc->chan[i - 1].slot_rx = -1; | |
3874 | hc->chan[i - 1].conf = -1; | |
3875 | mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0); | |
3876 | /* ST */ | |
3877 | pt = hc->chan[i].port; | |
3878 | /* select interface */ | |
3879 | HFC_outb(hc, R_ST_SEL, pt); | |
3880 | /* undocumented: delay after R_ST_SEL */ | |
3881 | udelay(1); | |
3882 | if (dch->dev.D.protocol == ISDN_P_NT_S0) { | |
3883 | if (debug & DEBUG_HFCMULTI_INIT) | |
3884 | printk(KERN_DEBUG | |
3885 | "%s: ST port %d is NT-mode\n", | |
3886 | __func__, pt); | |
3887 | /* clock delay */ | |
3888 | HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt); | |
3889 | a_st_wr_state = 1; /* G1 */ | |
3890 | hc->hw.a_st_ctrl0[pt] = V_ST_MD; | |
3891 | } else { | |
3892 | if (debug & DEBUG_HFCMULTI_INIT) | |
3893 | printk(KERN_DEBUG | |
3894 | "%s: ST port %d is TE-mode\n", | |
3895 | __func__, pt); | |
3896 | /* clock delay */ | |
3897 | HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te); | |
3898 | a_st_wr_state = 2; /* F2 */ | |
3899 | hc->hw.a_st_ctrl0[pt] = 0; | |
3900 | } | |
3901 | if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg)) | |
3902 | hc->hw.a_st_ctrl0[pt] |= V_TX_LI; | |
3903 | /* line setup */ | |
3904 | HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]); | |
3905 | /* disable E-channel */ | |
3906 | if ((dch->dev.D.protocol == ISDN_P_NT_S0) || | |
3907 | test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg)) | |
3908 | HFC_outb(hc, A_ST_CTRL1, V_E_IGNO); | |
3909 | else | |
3910 | HFC_outb(hc, A_ST_CTRL1, 0); | |
3911 | /* enable B-channel receive */ | |
3912 | HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN); | |
3913 | /* state machine setup */ | |
3914 | HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA); | |
3915 | udelay(6); /* wait at least 5,21us */ | |
3916 | HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state); | |
3917 | hc->hw.r_sci_msk |= 1 << pt; | |
3918 | /* state machine interrupts */ | |
3919 | HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk); | |
3920 | /* unset sync on port */ | |
3921 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
3922 | hc->syncronized &= | |
3923 | ~(1 << hc->chan[dch->slot].port); | |
3924 | plxsd_checksync(hc, 0); | |
3925 | } | |
3926 | } | |
3927 | if (debug & DEBUG_HFCMULTI_INIT) | |
3928 | printk("%s: done\n", __func__); | |
3929 | } | |
3930 | ||
3931 | ||
3932 | static int | |
3933 | open_dchannel(struct hfc_multi *hc, struct dchannel *dch, | |
3934 | struct channel_req *rq) | |
3935 | { | |
3936 | int err = 0; | |
3937 | u_long flags; | |
3938 | ||
3939 | if (debug & DEBUG_HW_OPEN) | |
3940 | printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__, | |
3941 | dch->dev.id, __builtin_return_address(0)); | |
3942 | if (rq->protocol == ISDN_P_NONE) | |
3943 | return -EINVAL; | |
3944 | if ((dch->dev.D.protocol != ISDN_P_NONE) && | |
3945 | (dch->dev.D.protocol != rq->protocol)) { | |
3946 | if (debug & DEBUG_HFCMULTI_MODE) | |
3947 | printk(KERN_WARNING "%s: change protocol %x to %x\n", | |
3948 | __func__, dch->dev.D.protocol, rq->protocol); | |
3949 | } | |
3950 | if ((dch->dev.D.protocol == ISDN_P_TE_S0) | |
3951 | && (rq->protocol != ISDN_P_TE_S0)) | |
3952 | l1_event(dch->l1, CLOSE_CHANNEL); | |
3953 | if (dch->dev.D.protocol != rq->protocol) { | |
3954 | if (rq->protocol == ISDN_P_TE_S0) { | |
3955 | err = create_l1(dch, hfcm_l1callback); | |
3956 | if (err) | |
3957 | return err; | |
3958 | } | |
3959 | dch->dev.D.protocol = rq->protocol; | |
3960 | spin_lock_irqsave(&hc->lock, flags); | |
3961 | hfcmulti_initmode(dch); | |
3962 | spin_unlock_irqrestore(&hc->lock, flags); | |
3963 | } | |
3964 | ||
3965 | if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) || | |
3966 | ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) || | |
3967 | ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) || | |
3968 | ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) { | |
3969 | _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY, | |
3970 | 0, NULL, GFP_KERNEL); | |
3971 | } | |
3972 | rq->ch = &dch->dev.D; | |
3973 | if (!try_module_get(THIS_MODULE)) | |
3974 | printk(KERN_WARNING "%s:cannot get module\n", __func__); | |
3975 | return 0; | |
3976 | } | |
3977 | ||
3978 | static int | |
3979 | open_bchannel(struct hfc_multi *hc, struct dchannel *dch, | |
3980 | struct channel_req *rq) | |
3981 | { | |
3982 | struct bchannel *bch; | |
3983 | int ch; | |
3984 | ||
ff4cc1de | 3985 | if (!test_channelmap(rq->adr.channel, dch->dev.channelmap)) |
af69fb3a KK |
3986 | return -EINVAL; |
3987 | if (rq->protocol == ISDN_P_NONE) | |
3988 | return -EINVAL; | |
3989 | if (hc->type == 1) | |
3990 | ch = rq->adr.channel; | |
3991 | else | |
3992 | ch = (rq->adr.channel - 1) + (dch->slot - 2); | |
3993 | bch = hc->chan[ch].bch; | |
3994 | if (!bch) { | |
3995 | printk(KERN_ERR "%s:internal error ch %d has no bch\n", | |
3996 | __func__, ch); | |
3997 | return -EINVAL; | |
3998 | } | |
3999 | if (test_and_set_bit(FLG_OPEN, &bch->Flags)) | |
4000 | return -EBUSY; /* b-channel can be only open once */ | |
8dd2f36f | 4001 | test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags); |
af69fb3a KK |
4002 | bch->ch.protocol = rq->protocol; |
4003 | hc->chan[ch].rx_off = 0; | |
4004 | rq->ch = &bch->ch; | |
4005 | if (!try_module_get(THIS_MODULE)) | |
4006 | printk(KERN_WARNING "%s:cannot get module\n", __func__); | |
4007 | return 0; | |
4008 | } | |
4009 | ||
4010 | /* | |
4011 | * device control function | |
4012 | */ | |
4013 | static int | |
4014 | channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq) | |
4015 | { | |
4016 | int ret = 0; | |
4017 | ||
4018 | switch (cq->op) { | |
4019 | case MISDN_CTRL_GETOP: | |
4020 | cq->op = 0; | |
4021 | break; | |
4022 | default: | |
4023 | printk(KERN_WARNING "%s: unknown Op %x\n", | |
4024 | __func__, cq->op); | |
4025 | ret = -EINVAL; | |
4026 | break; | |
4027 | } | |
4028 | return ret; | |
4029 | } | |
4030 | ||
4031 | static int | |
4032 | hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg) | |
4033 | { | |
4034 | struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); | |
4035 | struct dchannel *dch = container_of(dev, struct dchannel, dev); | |
4036 | struct hfc_multi *hc = dch->hw; | |
4037 | struct channel_req *rq; | |
4038 | int err = 0; | |
4039 | u_long flags; | |
4040 | ||
4041 | if (dch->debug & DEBUG_HW) | |
4042 | printk(KERN_DEBUG "%s: cmd:%x %p\n", | |
4043 | __func__, cmd, arg); | |
4044 | switch (cmd) { | |
4045 | case OPEN_CHANNEL: | |
4046 | rq = arg; | |
4047 | switch (rq->protocol) { | |
4048 | case ISDN_P_TE_S0: | |
4049 | case ISDN_P_NT_S0: | |
4050 | if (hc->type == 1) { | |
4051 | err = -EINVAL; | |
4052 | break; | |
4053 | } | |
4054 | err = open_dchannel(hc, dch, rq); /* locked there */ | |
4055 | break; | |
4056 | case ISDN_P_TE_E1: | |
4057 | case ISDN_P_NT_E1: | |
4058 | if (hc->type != 1) { | |
4059 | err = -EINVAL; | |
4060 | break; | |
4061 | } | |
4062 | err = open_dchannel(hc, dch, rq); /* locked there */ | |
4063 | break; | |
4064 | default: | |
4065 | spin_lock_irqsave(&hc->lock, flags); | |
4066 | err = open_bchannel(hc, dch, rq); | |
4067 | spin_unlock_irqrestore(&hc->lock, flags); | |
4068 | } | |
4069 | break; | |
4070 | case CLOSE_CHANNEL: | |
4071 | if (debug & DEBUG_HW_OPEN) | |
4072 | printk(KERN_DEBUG "%s: dev(%d) close from %p\n", | |
4073 | __func__, dch->dev.id, | |
4074 | __builtin_return_address(0)); | |
4075 | module_put(THIS_MODULE); | |
4076 | break; | |
4077 | case CONTROL_CHANNEL: | |
4078 | spin_lock_irqsave(&hc->lock, flags); | |
4079 | err = channel_dctrl(dch, arg); | |
4080 | spin_unlock_irqrestore(&hc->lock, flags); | |
4081 | break; | |
4082 | default: | |
4083 | if (dch->debug & DEBUG_HW) | |
4084 | printk(KERN_DEBUG "%s: unknown command %x\n", | |
4085 | __func__, cmd); | |
4086 | err = -EINVAL; | |
4087 | } | |
4088 | return err; | |
4089 | } | |
4090 | ||
3bd69ad1 AE |
4091 | static int |
4092 | clockctl(void *priv, int enable) | |
4093 | { | |
4094 | struct hfc_multi *hc = priv; | |
4095 | ||
4096 | hc->iclock_on = enable; | |
4097 | return 0; | |
4098 | } | |
4099 | ||
af69fb3a KK |
4100 | /* |
4101 | * initialize the card | |
4102 | */ | |
4103 | ||
4104 | /* | |
4105 | * start timer irq, wait some time and check if we have interrupts. | |
4106 | * if not, reset chip and try again. | |
4107 | */ | |
4108 | static int | |
4109 | init_card(struct hfc_multi *hc) | |
4110 | { | |
4111 | int err = -EIO; | |
4112 | u_long flags; | |
c31655fc | 4113 | void __iomem *plx_acc; |
af69fb3a KK |
4114 | u_long plx_flags; |
4115 | ||
4116 | if (debug & DEBUG_HFCMULTI_INIT) | |
4117 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
4118 | ||
4119 | spin_lock_irqsave(&hc->lock, flags); | |
4120 | /* set interrupts but leave global interrupt disabled */ | |
4121 | hc->hw.r_irq_ctrl = V_FIFO_IRQ; | |
4122 | disable_hwirq(hc); | |
4123 | spin_unlock_irqrestore(&hc->lock, flags); | |
4124 | ||
4125 | if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED, | |
4126 | "HFC-multi", hc)) { | |
4127 | printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n", | |
4128 | hc->pci_dev->irq); | |
4129 | return -EIO; | |
4130 | } | |
4131 | hc->irq = hc->pci_dev->irq; | |
4132 | ||
4133 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4134 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 4135 | plx_acc = hc->plx_membase + PLX_INTCSR; |
af69fb3a KK |
4136 | writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), |
4137 | plx_acc); /* enable PCI & LINT1 irq */ | |
4138 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
4139 | } | |
4140 | ||
4141 | if (debug & DEBUG_HFCMULTI_INIT) | |
4142 | printk(KERN_DEBUG "%s: IRQ %d count %d\n", | |
4143 | __func__, hc->irq, hc->irqcnt); | |
4144 | err = init_chip(hc); | |
4145 | if (err) | |
4146 | goto error; | |
4147 | /* | |
4148 | * Finally enable IRQ output | |
4149 | * this is only allowed, if an IRQ routine is allready | |
4150 | * established for this HFC, so don't do that earlier | |
4151 | */ | |
4152 | spin_lock_irqsave(&hc->lock, flags); | |
4153 | enable_hwirq(hc); | |
4154 | spin_unlock_irqrestore(&hc->lock, flags); | |
4155 | /* printk(KERN_DEBUG "no master irq set!!!\n"); */ | |
4156 | set_current_state(TASK_UNINTERRUPTIBLE); | |
4157 | schedule_timeout((100*HZ)/1000); /* Timeout 100ms */ | |
4158 | /* turn IRQ off until chip is completely initialized */ | |
4159 | spin_lock_irqsave(&hc->lock, flags); | |
4160 | disable_hwirq(hc); | |
4161 | spin_unlock_irqrestore(&hc->lock, flags); | |
4162 | if (debug & DEBUG_HFCMULTI_INIT) | |
4163 | printk(KERN_DEBUG "%s: IRQ %d count %d\n", | |
4164 | __func__, hc->irq, hc->irqcnt); | |
4165 | if (hc->irqcnt) { | |
4166 | if (debug & DEBUG_HFCMULTI_INIT) | |
4167 | printk(KERN_DEBUG "%s: done\n", __func__); | |
4168 | ||
4169 | return 0; | |
4170 | } | |
4171 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
4172 | printk(KERN_INFO "ignoring missing interrupts\n"); | |
4173 | return 0; | |
4174 | } | |
4175 | ||
4176 | printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n", | |
4177 | hc->irq); | |
4178 | ||
4179 | err = -EIO; | |
4180 | ||
4181 | error: | |
4182 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4183 | spin_lock_irqsave(&plx_lock, plx_flags); | |
c31655fc | 4184 | plx_acc = hc->plx_membase + PLX_INTCSR; |
af69fb3a KK |
4185 | writew(0x00, plx_acc); /*disable IRQs*/ |
4186 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
4187 | } | |
4188 | ||
4189 | if (debug & DEBUG_HFCMULTI_INIT) | |
4190 | printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq); | |
4191 | if (hc->irq) { | |
4192 | free_irq(hc->irq, hc); | |
4193 | hc->irq = 0; | |
4194 | } | |
4195 | ||
4196 | if (debug & DEBUG_HFCMULTI_INIT) | |
4197 | printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err); | |
4198 | return err; | |
4199 | } | |
4200 | ||
4201 | /* | |
4202 | * find pci device and set it up | |
4203 | */ | |
4204 | ||
4205 | static int | |
4206 | setup_pci(struct hfc_multi *hc, struct pci_dev *pdev, | |
4207 | const struct pci_device_id *ent) | |
4208 | { | |
4209 | struct hm_map *m = (struct hm_map *)ent->driver_data; | |
4210 | ||
4211 | printk(KERN_INFO | |
4212 | "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n", | |
4213 | m->vendor_name, m->card_name, m->clock2 ? "double" : "normal"); | |
4214 | ||
4215 | hc->pci_dev = pdev; | |
4216 | if (m->clock2) | |
4217 | test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip); | |
4218 | ||
4219 | if (ent->device == 0xB410) { | |
4220 | test_and_set_bit(HFC_CHIP_B410P, &hc->chip); | |
4221 | test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); | |
4222 | test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
4223 | hc->slots = 32; | |
4224 | } | |
4225 | ||
4226 | if (hc->pci_dev->irq <= 0) { | |
4227 | printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n"); | |
4228 | return -EIO; | |
4229 | } | |
4230 | if (pci_enable_device(hc->pci_dev)) { | |
4231 | printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n"); | |
4232 | return -EIO; | |
4233 | } | |
4234 | hc->leds = m->leds; | |
4235 | hc->ledstate = 0xAFFEAFFE; | |
4236 | hc->opticalsupport = m->opticalsupport; | |
4237 | ||
4238 | /* set memory access methods */ | |
4239 | if (m->io_mode) /* use mode from card config */ | |
4240 | hc->io_mode = m->io_mode; | |
4241 | switch (hc->io_mode) { | |
4242 | case HFC_IO_MODE_PLXSD: | |
4243 | test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip); | |
4244 | hc->slots = 128; /* required */ | |
4245 | /* fall through */ | |
4246 | case HFC_IO_MODE_PCIMEM: | |
4247 | hc->HFC_outb = HFC_outb_pcimem; | |
4248 | hc->HFC_inb = HFC_inb_pcimem; | |
4249 | hc->HFC_inw = HFC_inw_pcimem; | |
4250 | hc->HFC_wait = HFC_wait_pcimem; | |
4251 | hc->read_fifo = read_fifo_pcimem; | |
4252 | hc->write_fifo = write_fifo_pcimem; | |
4253 | break; | |
4254 | case HFC_IO_MODE_REGIO: | |
4255 | hc->HFC_outb = HFC_outb_regio; | |
4256 | hc->HFC_inb = HFC_inb_regio; | |
4257 | hc->HFC_inw = HFC_inw_regio; | |
4258 | hc->HFC_wait = HFC_wait_regio; | |
4259 | hc->read_fifo = read_fifo_regio; | |
4260 | hc->write_fifo = write_fifo_regio; | |
4261 | break; | |
4262 | default: | |
4263 | printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); | |
4264 | pci_disable_device(hc->pci_dev); | |
4265 | return -EIO; | |
4266 | } | |
4267 | hc->HFC_outb_nodebug = hc->HFC_outb; | |
4268 | hc->HFC_inb_nodebug = hc->HFC_inb; | |
4269 | hc->HFC_inw_nodebug = hc->HFC_inw; | |
4270 | hc->HFC_wait_nodebug = hc->HFC_wait; | |
4271 | #ifdef HFC_REGISTER_DEBUG | |
4272 | hc->HFC_outb = HFC_outb_debug; | |
4273 | hc->HFC_inb = HFC_inb_debug; | |
4274 | hc->HFC_inw = HFC_inw_debug; | |
4275 | hc->HFC_wait = HFC_wait_debug; | |
4276 | #endif | |
4277 | hc->pci_iobase = 0; | |
4278 | hc->pci_membase = NULL; | |
4279 | hc->plx_membase = NULL; | |
4280 | ||
4281 | switch (hc->io_mode) { | |
4282 | case HFC_IO_MODE_PLXSD: | |
4283 | hc->plx_origmembase = hc->pci_dev->resource[0].start; | |
4284 | /* MEMBASE 1 is PLX PCI Bridge */ | |
4285 | ||
4286 | if (!hc->plx_origmembase) { | |
4287 | printk(KERN_WARNING | |
4288 | "HFC-multi: No IO-Memory for PCI PLX bridge found\n"); | |
4289 | pci_disable_device(hc->pci_dev); | |
4290 | return -EIO; | |
4291 | } | |
4292 | ||
4293 | hc->plx_membase = ioremap(hc->plx_origmembase, 0x80); | |
4294 | if (!hc->plx_membase) { | |
4295 | printk(KERN_WARNING | |
4296 | "HFC-multi: failed to remap plx address space. " | |
4297 | "(internal error)\n"); | |
4298 | pci_disable_device(hc->pci_dev); | |
4299 | return -EIO; | |
4300 | } | |
4301 | printk(KERN_INFO | |
4302 | "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n", | |
4303 | (u_long)hc->plx_membase, hc->plx_origmembase); | |
4304 | ||
4305 | hc->pci_origmembase = hc->pci_dev->resource[2].start; | |
4306 | /* MEMBASE 1 is PLX PCI Bridge */ | |
4307 | if (!hc->pci_origmembase) { | |
4308 | printk(KERN_WARNING | |
4309 | "HFC-multi: No IO-Memory for PCI card found\n"); | |
4310 | pci_disable_device(hc->pci_dev); | |
4311 | return -EIO; | |
4312 | } | |
4313 | ||
4314 | hc->pci_membase = ioremap(hc->pci_origmembase, 0x400); | |
4315 | if (!hc->pci_membase) { | |
4316 | printk(KERN_WARNING "HFC-multi: failed to remap io " | |
4317 | "address space. (internal error)\n"); | |
4318 | pci_disable_device(hc->pci_dev); | |
4319 | return -EIO; | |
4320 | } | |
4321 | ||
4322 | printk(KERN_INFO | |
4323 | "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d " | |
4324 | "leds-type %d\n", | |
4325 | hc->id, (u_long)hc->pci_membase, hc->pci_origmembase, | |
4326 | hc->pci_dev->irq, HZ, hc->leds); | |
4327 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); | |
4328 | break; | |
4329 | case HFC_IO_MODE_PCIMEM: | |
4330 | hc->pci_origmembase = hc->pci_dev->resource[1].start; | |
4331 | if (!hc->pci_origmembase) { | |
4332 | printk(KERN_WARNING | |
4333 | "HFC-multi: No IO-Memory for PCI card found\n"); | |
4334 | pci_disable_device(hc->pci_dev); | |
4335 | return -EIO; | |
4336 | } | |
4337 | ||
4338 | hc->pci_membase = ioremap(hc->pci_origmembase, 256); | |
4339 | if (!hc->pci_membase) { | |
4340 | printk(KERN_WARNING | |
4341 | "HFC-multi: failed to remap io address space. " | |
4342 | "(internal error)\n"); | |
4343 | pci_disable_device(hc->pci_dev); | |
4344 | return -EIO; | |
4345 | } | |
4346 | printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d " | |
4347 | "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase, | |
4348 | hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds); | |
4349 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); | |
4350 | break; | |
4351 | case HFC_IO_MODE_REGIO: | |
4352 | hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start; | |
4353 | if (!hc->pci_iobase) { | |
4354 | printk(KERN_WARNING | |
4355 | "HFC-multi: No IO for PCI card found\n"); | |
4356 | pci_disable_device(hc->pci_dev); | |
4357 | return -EIO; | |
4358 | } | |
4359 | ||
4360 | if (!request_region(hc->pci_iobase, 8, "hfcmulti")) { | |
4361 | printk(KERN_WARNING "HFC-multi: failed to request " | |
4362 | "address space at 0x%08lx (internal error)\n", | |
4363 | hc->pci_iobase); | |
4364 | pci_disable_device(hc->pci_dev); | |
4365 | return -EIO; | |
4366 | } | |
4367 | ||
4368 | printk(KERN_INFO | |
4369 | "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n", | |
4370 | m->vendor_name, m->card_name, (u_int) hc->pci_iobase, | |
4371 | hc->pci_dev->irq, HZ, hc->leds); | |
4372 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO); | |
4373 | break; | |
4374 | default: | |
4375 | printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); | |
4376 | pci_disable_device(hc->pci_dev); | |
4377 | return -EIO; | |
4378 | } | |
4379 | ||
4380 | pci_set_drvdata(hc->pci_dev, hc); | |
4381 | ||
4382 | /* At this point the needed PCI config is done */ | |
4383 | /* fifos are still not enabled */ | |
4384 | return 0; | |
4385 | } | |
4386 | ||
4387 | ||
4388 | /* | |
4389 | * remove port | |
4390 | */ | |
4391 | ||
4392 | static void | |
4393 | release_port(struct hfc_multi *hc, struct dchannel *dch) | |
4394 | { | |
4395 | int pt, ci, i = 0; | |
4396 | u_long flags; | |
4397 | struct bchannel *pb; | |
4398 | ||
4399 | ci = dch->slot; | |
4400 | pt = hc->chan[ci].port; | |
4401 | ||
4402 | if (debug & DEBUG_HFCMULTI_INIT) | |
4403 | printk(KERN_DEBUG "%s: entered for port %d\n", | |
4404 | __func__, pt + 1); | |
4405 | ||
4406 | if (pt >= hc->ports) { | |
4407 | printk(KERN_WARNING "%s: ERROR port out of range (%d).\n", | |
4408 | __func__, pt + 1); | |
4409 | return; | |
4410 | } | |
4411 | ||
4412 | if (debug & DEBUG_HFCMULTI_INIT) | |
4413 | printk(KERN_DEBUG "%s: releasing port=%d\n", | |
4414 | __func__, pt + 1); | |
4415 | ||
4416 | if (dch->dev.D.protocol == ISDN_P_TE_S0) | |
4417 | l1_event(dch->l1, CLOSE_CHANNEL); | |
4418 | ||
4419 | hc->chan[ci].dch = NULL; | |
4420 | ||
4421 | if (hc->created[pt]) { | |
4422 | hc->created[pt] = 0; | |
4423 | mISDN_unregister_device(&dch->dev); | |
4424 | } | |
4425 | ||
4426 | spin_lock_irqsave(&hc->lock, flags); | |
4427 | ||
4428 | if (dch->timer.function) { | |
4429 | del_timer(&dch->timer); | |
4430 | dch->timer.function = NULL; | |
4431 | } | |
4432 | ||
4433 | if (hc->type == 1) { /* E1 */ | |
4434 | /* remove sync */ | |
4435 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4436 | hc->syncronized = 0; | |
4437 | plxsd_checksync(hc, 1); | |
4438 | } | |
4439 | /* free channels */ | |
4440 | for (i = 0; i <= 31; i++) { | |
4441 | if (hc->chan[i].bch) { | |
4442 | if (debug & DEBUG_HFCMULTI_INIT) | |
4443 | printk(KERN_DEBUG | |
4444 | "%s: free port %d channel %d\n", | |
4445 | __func__, hc->chan[i].port+1, i); | |
4446 | pb = hc->chan[i].bch; | |
4447 | hc->chan[i].bch = NULL; | |
4448 | spin_unlock_irqrestore(&hc->lock, flags); | |
4449 | mISDN_freebchannel(pb); | |
4450 | kfree(pb); | |
4451 | kfree(hc->chan[i].coeff); | |
4452 | spin_lock_irqsave(&hc->lock, flags); | |
4453 | } | |
4454 | } | |
4455 | } else { | |
4456 | /* remove sync */ | |
4457 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4458 | hc->syncronized &= | |
4459 | ~(1 << hc->chan[ci].port); | |
4460 | plxsd_checksync(hc, 1); | |
4461 | } | |
4462 | /* free channels */ | |
4463 | if (hc->chan[ci - 2].bch) { | |
4464 | if (debug & DEBUG_HFCMULTI_INIT) | |
4465 | printk(KERN_DEBUG | |
4466 | "%s: free port %d channel %d\n", | |
4467 | __func__, hc->chan[ci - 2].port+1, | |
4468 | ci - 2); | |
4469 | pb = hc->chan[ci - 2].bch; | |
4470 | hc->chan[ci - 2].bch = NULL; | |
4471 | spin_unlock_irqrestore(&hc->lock, flags); | |
4472 | mISDN_freebchannel(pb); | |
4473 | kfree(pb); | |
4474 | kfree(hc->chan[ci - 2].coeff); | |
4475 | spin_lock_irqsave(&hc->lock, flags); | |
4476 | } | |
4477 | if (hc->chan[ci - 1].bch) { | |
4478 | if (debug & DEBUG_HFCMULTI_INIT) | |
4479 | printk(KERN_DEBUG | |
4480 | "%s: free port %d channel %d\n", | |
4481 | __func__, hc->chan[ci - 1].port+1, | |
4482 | ci - 1); | |
4483 | pb = hc->chan[ci - 1].bch; | |
4484 | hc->chan[ci - 1].bch = NULL; | |
4485 | spin_unlock_irqrestore(&hc->lock, flags); | |
4486 | mISDN_freebchannel(pb); | |
4487 | kfree(pb); | |
4488 | kfree(hc->chan[ci - 1].coeff); | |
4489 | spin_lock_irqsave(&hc->lock, flags); | |
4490 | } | |
4491 | } | |
4492 | ||
4493 | spin_unlock_irqrestore(&hc->lock, flags); | |
4494 | ||
4495 | if (debug & DEBUG_HFCMULTI_INIT) | |
4496 | printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt); | |
4497 | mISDN_freedchannel(dch); | |
4498 | kfree(dch); | |
4499 | ||
4500 | if (debug & DEBUG_HFCMULTI_INIT) | |
4501 | printk(KERN_DEBUG "%s: done!\n", __func__); | |
4502 | } | |
4503 | ||
4504 | static void | |
4505 | release_card(struct hfc_multi *hc) | |
4506 | { | |
4507 | u_long flags; | |
4508 | int ch; | |
4509 | ||
4510 | if (debug & DEBUG_HFCMULTI_INIT) | |
4511 | printk(KERN_WARNING "%s: release card (%d) entered\n", | |
4512 | __func__, hc->id); | |
4513 | ||
3bd69ad1 AE |
4514 | /* unregister clock source */ |
4515 | if (hc->iclock) | |
4516 | mISDN_unregister_clock(hc->iclock); | |
4517 | ||
4518 | /* disable irq */ | |
af69fb3a KK |
4519 | spin_lock_irqsave(&hc->lock, flags); |
4520 | disable_hwirq(hc); | |
4521 | spin_unlock_irqrestore(&hc->lock, flags); | |
af69fb3a KK |
4522 | udelay(1000); |
4523 | ||
4524 | /* dimm leds */ | |
4525 | if (hc->leds) | |
4526 | hfcmulti_leds(hc); | |
4527 | ||
4528 | /* disable D-channels & B-channels */ | |
4529 | if (debug & DEBUG_HFCMULTI_INIT) | |
4530 | printk(KERN_DEBUG "%s: disable all channels (d and b)\n", | |
4531 | __func__); | |
4532 | for (ch = 0; ch <= 31; ch++) { | |
4533 | if (hc->chan[ch].dch) | |
4534 | release_port(hc, hc->chan[ch].dch); | |
4535 | } | |
4536 | ||
4537 | /* release hardware & irq */ | |
4538 | if (hc->irq) { | |
4539 | if (debug & DEBUG_HFCMULTI_INIT) | |
4540 | printk(KERN_WARNING "%s: free irq %d\n", | |
4541 | __func__, hc->irq); | |
4542 | free_irq(hc->irq, hc); | |
4543 | hc->irq = 0; | |
4544 | ||
4545 | } | |
4546 | release_io_hfcmulti(hc); | |
4547 | ||
4548 | if (debug & DEBUG_HFCMULTI_INIT) | |
4549 | printk(KERN_WARNING "%s: remove instance from list\n", | |
4550 | __func__); | |
4551 | list_del(&hc->list); | |
4552 | ||
4553 | if (debug & DEBUG_HFCMULTI_INIT) | |
4554 | printk(KERN_WARNING "%s: delete instance\n", __func__); | |
4555 | if (hc == syncmaster) | |
4556 | syncmaster = NULL; | |
4557 | kfree(hc); | |
4558 | if (debug & DEBUG_HFCMULTI_INIT) | |
4559 | printk(KERN_WARNING "%s: card successfully removed\n", | |
4560 | __func__); | |
4561 | } | |
4562 | ||
4563 | static int | |
4564 | init_e1_port(struct hfc_multi *hc, struct hm_map *m) | |
4565 | { | |
4566 | struct dchannel *dch; | |
4567 | struct bchannel *bch; | |
4568 | int ch, ret = 0; | |
4569 | char name[MISDN_MAX_IDLEN]; | |
4570 | ||
4571 | dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); | |
4572 | if (!dch) | |
4573 | return -ENOMEM; | |
4574 | dch->debug = debug; | |
4575 | mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); | |
4576 | dch->hw = hc; | |
4577 | dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1); | |
4578 | dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | | |
4579 | (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); | |
4580 | dch->dev.D.send = handle_dmsg; | |
4581 | dch->dev.D.ctrl = hfcm_dctrl; | |
4582 | dch->dev.nrbchan = (hc->dslot)?30:31; | |
4583 | dch->slot = hc->dslot; | |
4584 | hc->chan[hc->dslot].dch = dch; | |
4585 | hc->chan[hc->dslot].port = 0; | |
4586 | hc->chan[hc->dslot].nt_timer = -1; | |
4587 | for (ch = 1; ch <= 31; ch++) { | |
4588 | if (ch == hc->dslot) /* skip dchannel */ | |
4589 | continue; | |
4590 | bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); | |
4591 | if (!bch) { | |
4592 | printk(KERN_ERR "%s: no memory for bchannel\n", | |
4593 | __func__); | |
4594 | ret = -ENOMEM; | |
4595 | goto free_chan; | |
4596 | } | |
4597 | hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL); | |
4598 | if (!hc->chan[ch].coeff) { | |
4599 | printk(KERN_ERR "%s: no memory for coeffs\n", | |
4600 | __func__); | |
4601 | ret = -ENOMEM; | |
4602 | goto free_chan; | |
4603 | } | |
4604 | bch->nr = ch; | |
4605 | bch->slot = ch; | |
4606 | bch->debug = debug; | |
4607 | mISDN_initbchannel(bch, MAX_DATA_MEM); | |
4608 | bch->hw = hc; | |
4609 | bch->ch.send = handle_bmsg; | |
4610 | bch->ch.ctrl = hfcm_bctrl; | |
4611 | bch->ch.nr = ch; | |
4612 | list_add(&bch->ch.list, &dch->dev.bchannels); | |
4613 | hc->chan[ch].bch = bch; | |
4614 | hc->chan[ch].port = 0; | |
ff4cc1de | 4615 | set_channelmap(bch->nr, dch->dev.channelmap); |
af69fb3a KK |
4616 | } |
4617 | /* set optical line type */ | |
4618 | if (port[Port_cnt] & 0x001) { | |
4619 | if (!m->opticalsupport) { | |
4620 | printk(KERN_INFO | |
4621 | "This board has no optical " | |
4622 | "support\n"); | |
4623 | } else { | |
4624 | if (debug & DEBUG_HFCMULTI_INIT) | |
4625 | printk(KERN_DEBUG | |
4626 | "%s: PORT set optical " | |
4627 | "interfacs: card(%d) " | |
4628 | "port(%d)\n", | |
4629 | __func__, | |
4630 | HFC_cnt + 1, 1); | |
4631 | test_and_set_bit(HFC_CFG_OPTICAL, | |
4632 | &hc->chan[hc->dslot].cfg); | |
4633 | } | |
4634 | } | |
4635 | /* set LOS report */ | |
4636 | if (port[Port_cnt] & 0x004) { | |
4637 | if (debug & DEBUG_HFCMULTI_INIT) | |
4638 | printk(KERN_DEBUG "%s: PORT set " | |
4639 | "LOS report: card(%d) port(%d)\n", | |
4640 | __func__, HFC_cnt + 1, 1); | |
4641 | test_and_set_bit(HFC_CFG_REPORT_LOS, | |
4642 | &hc->chan[hc->dslot].cfg); | |
4643 | } | |
4644 | /* set AIS report */ | |
4645 | if (port[Port_cnt] & 0x008) { | |
4646 | if (debug & DEBUG_HFCMULTI_INIT) | |
4647 | printk(KERN_DEBUG "%s: PORT set " | |
4648 | "AIS report: card(%d) port(%d)\n", | |
4649 | __func__, HFC_cnt + 1, 1); | |
4650 | test_and_set_bit(HFC_CFG_REPORT_AIS, | |
4651 | &hc->chan[hc->dslot].cfg); | |
4652 | } | |
4653 | /* set SLIP report */ | |
4654 | if (port[Port_cnt] & 0x010) { | |
4655 | if (debug & DEBUG_HFCMULTI_INIT) | |
4656 | printk(KERN_DEBUG | |
4657 | "%s: PORT set SLIP report: " | |
4658 | "card(%d) port(%d)\n", | |
4659 | __func__, HFC_cnt + 1, 1); | |
4660 | test_and_set_bit(HFC_CFG_REPORT_SLIP, | |
4661 | &hc->chan[hc->dslot].cfg); | |
4662 | } | |
4663 | /* set RDI report */ | |
4664 | if (port[Port_cnt] & 0x020) { | |
4665 | if (debug & DEBUG_HFCMULTI_INIT) | |
4666 | printk(KERN_DEBUG | |
4667 | "%s: PORT set RDI report: " | |
4668 | "card(%d) port(%d)\n", | |
4669 | __func__, HFC_cnt + 1, 1); | |
4670 | test_and_set_bit(HFC_CFG_REPORT_RDI, | |
4671 | &hc->chan[hc->dslot].cfg); | |
4672 | } | |
4673 | /* set CRC-4 Mode */ | |
4674 | if (!(port[Port_cnt] & 0x100)) { | |
4675 | if (debug & DEBUG_HFCMULTI_INIT) | |
4676 | printk(KERN_DEBUG "%s: PORT turn on CRC4 report:" | |
4677 | " card(%d) port(%d)\n", | |
4678 | __func__, HFC_cnt + 1, 1); | |
4679 | test_and_set_bit(HFC_CFG_CRC4, | |
4680 | &hc->chan[hc->dslot].cfg); | |
4681 | } else { | |
4682 | if (debug & DEBUG_HFCMULTI_INIT) | |
4683 | printk(KERN_DEBUG "%s: PORT turn off CRC4" | |
4684 | " report: card(%d) port(%d)\n", | |
4685 | __func__, HFC_cnt + 1, 1); | |
4686 | } | |
4687 | /* set forced clock */ | |
4688 | if (port[Port_cnt] & 0x0200) { | |
4689 | if (debug & DEBUG_HFCMULTI_INIT) | |
4690 | printk(KERN_DEBUG "%s: PORT force getting clock from " | |
4691 | "E1: card(%d) port(%d)\n", | |
4692 | __func__, HFC_cnt + 1, 1); | |
4693 | test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip); | |
4694 | } else | |
4695 | if (port[Port_cnt] & 0x0400) { | |
4696 | if (debug & DEBUG_HFCMULTI_INIT) | |
4697 | printk(KERN_DEBUG "%s: PORT force putting clock to " | |
4698 | "E1: card(%d) port(%d)\n", | |
4699 | __func__, HFC_cnt + 1, 1); | |
4700 | test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip); | |
4701 | } | |
4702 | /* set JATT PLL */ | |
4703 | if (port[Port_cnt] & 0x0800) { | |
4704 | if (debug & DEBUG_HFCMULTI_INIT) | |
4705 | printk(KERN_DEBUG "%s: PORT disable JATT PLL on " | |
4706 | "E1: card(%d) port(%d)\n", | |
4707 | __func__, HFC_cnt + 1, 1); | |
4708 | test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip); | |
4709 | } | |
4710 | /* set elastic jitter buffer */ | |
4711 | if (port[Port_cnt] & 0x3000) { | |
4712 | hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3; | |
4713 | if (debug & DEBUG_HFCMULTI_INIT) | |
4714 | printk(KERN_DEBUG | |
4715 | "%s: PORT set elastic " | |
4716 | "buffer to %d: card(%d) port(%d)\n", | |
4717 | __func__, hc->chan[hc->dslot].jitter, | |
4718 | HFC_cnt + 1, 1); | |
4719 | } else | |
4720 | hc->chan[hc->dslot].jitter = 2; /* default */ | |
4721 | snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1); | |
b36b654a | 4722 | ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); |
af69fb3a KK |
4723 | if (ret) |
4724 | goto free_chan; | |
4725 | hc->created[0] = 1; | |
4726 | return ret; | |
4727 | free_chan: | |
4728 | release_port(hc, dch); | |
4729 | return ret; | |
4730 | } | |
4731 | ||
4732 | static int | |
4733 | init_multi_port(struct hfc_multi *hc, int pt) | |
4734 | { | |
4735 | struct dchannel *dch; | |
4736 | struct bchannel *bch; | |
4737 | int ch, i, ret = 0; | |
4738 | char name[MISDN_MAX_IDLEN]; | |
4739 | ||
4740 | dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); | |
4741 | if (!dch) | |
4742 | return -ENOMEM; | |
4743 | dch->debug = debug; | |
4744 | mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); | |
4745 | dch->hw = hc; | |
4746 | dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0); | |
4747 | dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | | |
4748 | (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); | |
4749 | dch->dev.D.send = handle_dmsg; | |
4750 | dch->dev.D.ctrl = hfcm_dctrl; | |
4751 | dch->dev.nrbchan = 2; | |
4752 | i = pt << 2; | |
4753 | dch->slot = i + 2; | |
4754 | hc->chan[i + 2].dch = dch; | |
4755 | hc->chan[i + 2].port = pt; | |
4756 | hc->chan[i + 2].nt_timer = -1; | |
4757 | for (ch = 0; ch < dch->dev.nrbchan; ch++) { | |
4758 | bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); | |
4759 | if (!bch) { | |
4760 | printk(KERN_ERR "%s: no memory for bchannel\n", | |
4761 | __func__); | |
4762 | ret = -ENOMEM; | |
4763 | goto free_chan; | |
4764 | } | |
4765 | hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL); | |
4766 | if (!hc->chan[i + ch].coeff) { | |
4767 | printk(KERN_ERR "%s: no memory for coeffs\n", | |
4768 | __func__); | |
4769 | ret = -ENOMEM; | |
4770 | goto free_chan; | |
4771 | } | |
4772 | bch->nr = ch + 1; | |
4773 | bch->slot = i + ch; | |
4774 | bch->debug = debug; | |
4775 | mISDN_initbchannel(bch, MAX_DATA_MEM); | |
4776 | bch->hw = hc; | |
4777 | bch->ch.send = handle_bmsg; | |
4778 | bch->ch.ctrl = hfcm_bctrl; | |
4779 | bch->ch.nr = ch + 1; | |
4780 | list_add(&bch->ch.list, &dch->dev.bchannels); | |
4781 | hc->chan[i + ch].bch = bch; | |
4782 | hc->chan[i + ch].port = pt; | |
ff4cc1de | 4783 | set_channelmap(bch->nr, dch->dev.channelmap); |
af69fb3a KK |
4784 | } |
4785 | /* set master clock */ | |
4786 | if (port[Port_cnt] & 0x001) { | |
4787 | if (debug & DEBUG_HFCMULTI_INIT) | |
4788 | printk(KERN_DEBUG | |
4789 | "%s: PROTOCOL set master clock: " | |
4790 | "card(%d) port(%d)\n", | |
4791 | __func__, HFC_cnt + 1, pt + 1); | |
4792 | if (dch->dev.D.protocol != ISDN_P_TE_S0) { | |
4793 | printk(KERN_ERR "Error: Master clock " | |
4794 | "for port(%d) of card(%d) is only" | |
4795 | " possible with TE-mode\n", | |
4796 | pt + 1, HFC_cnt + 1); | |
4797 | ret = -EINVAL; | |
4798 | goto free_chan; | |
4799 | } | |
4800 | if (hc->masterclk >= 0) { | |
4801 | printk(KERN_ERR "Error: Master clock " | |
4802 | "for port(%d) of card(%d) already " | |
4803 | "defined for port(%d)\n", | |
4804 | pt + 1, HFC_cnt + 1, hc->masterclk+1); | |
4805 | ret = -EINVAL; | |
4806 | goto free_chan; | |
4807 | } | |
4808 | hc->masterclk = pt; | |
4809 | } | |
4810 | /* set transmitter line to non capacitive */ | |
4811 | if (port[Port_cnt] & 0x002) { | |
4812 | if (debug & DEBUG_HFCMULTI_INIT) | |
4813 | printk(KERN_DEBUG | |
4814 | "%s: PROTOCOL set non capacitive " | |
4815 | "transmitter: card(%d) port(%d)\n", | |
4816 | __func__, HFC_cnt + 1, pt + 1); | |
4817 | test_and_set_bit(HFC_CFG_NONCAP_TX, | |
4818 | &hc->chan[i + 2].cfg); | |
4819 | } | |
4820 | /* disable E-channel */ | |
4821 | if (port[Port_cnt] & 0x004) { | |
4822 | if (debug & DEBUG_HFCMULTI_INIT) | |
4823 | printk(KERN_DEBUG | |
4824 | "%s: PROTOCOL disable E-channel: " | |
4825 | "card(%d) port(%d)\n", | |
4826 | __func__, HFC_cnt + 1, pt + 1); | |
4827 | test_and_set_bit(HFC_CFG_DIS_ECHANNEL, | |
4828 | &hc->chan[i + 2].cfg); | |
4829 | } | |
b36b654a | 4830 | snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d", |
af69fb3a | 4831 | hc->type, HFC_cnt + 1, pt + 1); |
b36b654a | 4832 | ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name); |
af69fb3a KK |
4833 | if (ret) |
4834 | goto free_chan; | |
4835 | hc->created[pt] = 1; | |
4836 | return ret; | |
4837 | free_chan: | |
4838 | release_port(hc, dch); | |
4839 | return ret; | |
4840 | } | |
4841 | ||
4842 | static int | |
4843 | hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent) | |
4844 | { | |
4845 | struct hm_map *m = (struct hm_map *)ent->driver_data; | |
4846 | int ret_err = 0; | |
4847 | int pt; | |
4848 | struct hfc_multi *hc; | |
4849 | u_long flags; | |
4850 | u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */ | |
8dd2f36f | 4851 | int i; |
af69fb3a KK |
4852 | |
4853 | if (HFC_cnt >= MAX_CARDS) { | |
4854 | printk(KERN_ERR "too many cards (max=%d).\n", | |
4855 | MAX_CARDS); | |
4856 | return -EINVAL; | |
4857 | } | |
4858 | if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) { | |
4859 | printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but " | |
4860 | "type[%d] %d was supplied as module parameter\n", | |
4861 | m->vendor_name, m->card_name, m->type, HFC_cnt, | |
4862 | type[HFC_cnt] & 0xff); | |
4863 | printk(KERN_WARNING "HFC-MULTI: Load module without parameters " | |
4864 | "first, to see cards and their types."); | |
4865 | return -EINVAL; | |
4866 | } | |
4867 | if (debug & DEBUG_HFCMULTI_INIT) | |
4868 | printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n", | |
4869 | __func__, m->vendor_name, m->card_name, m->type, | |
4870 | type[HFC_cnt]); | |
4871 | ||
4872 | /* allocate card+fifo structure */ | |
4873 | hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL); | |
4874 | if (!hc) { | |
4875 | printk(KERN_ERR "No kmem for HFC-Multi card\n"); | |
4876 | return -ENOMEM; | |
4877 | } | |
4878 | spin_lock_init(&hc->lock); | |
4879 | hc->mtyp = m; | |
4880 | hc->type = m->type; | |
4881 | hc->ports = m->ports; | |
4882 | hc->id = HFC_cnt; | |
4883 | hc->pcm = pcm[HFC_cnt]; | |
4884 | hc->io_mode = iomode[HFC_cnt]; | |
8dd2f36f | 4885 | if (dslot[HFC_cnt] < 0 && hc->type == 1) { |
af69fb3a KK |
4886 | hc->dslot = 0; |
4887 | printk(KERN_INFO "HFC-E1 card has disabled D-channel, but " | |
4888 | "31 B-channels\n"); | |
8dd2f36f | 4889 | } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) { |
af69fb3a KK |
4890 | hc->dslot = dslot[HFC_cnt]; |
4891 | printk(KERN_INFO "HFC-E1 card has alternating D-channel on " | |
4892 | "time slot %d\n", dslot[HFC_cnt]); | |
4893 | } else | |
4894 | hc->dslot = 16; | |
4895 | ||
4896 | /* set chip specific features */ | |
4897 | hc->masterclk = -1; | |
4898 | if (type[HFC_cnt] & 0x100) { | |
4899 | test_and_set_bit(HFC_CHIP_ULAW, &hc->chip); | |
8dd2f36f | 4900 | hc->silence = 0xff; /* ulaw silence */ |
af69fb3a | 4901 | } else |
8dd2f36f AE |
4902 | hc->silence = 0x2a; /* alaw silence */ |
4903 | if ((poll >> 1) > sizeof(hc->silence_data)) { | |
4904 | printk(KERN_ERR "HFCMULTI error: silence_data too small, " | |
4905 | "please fix\n"); | |
4906 | return -EINVAL; | |
4907 | } | |
4908 | for (i = 0; i < (poll >> 1); i++) | |
4909 | hc->silence_data[i] = hc->silence; | |
4910 | ||
af69fb3a KK |
4911 | if (!(type[HFC_cnt] & 0x200)) |
4912 | test_and_set_bit(HFC_CHIP_DTMF, &hc->chip); | |
4913 | ||
4914 | if (type[HFC_cnt] & 0x800) | |
4915 | test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
4916 | if (type[HFC_cnt] & 0x1000) { | |
4917 | test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); | |
4918 | test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
4919 | } | |
4920 | if (type[HFC_cnt] & 0x4000) | |
4921 | test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip); | |
4922 | if (type[HFC_cnt] & 0x8000) | |
4923 | test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip); | |
4924 | hc->slots = 32; | |
4925 | if (type[HFC_cnt] & 0x10000) | |
4926 | hc->slots = 64; | |
4927 | if (type[HFC_cnt] & 0x20000) | |
4928 | hc->slots = 128; | |
4929 | if (type[HFC_cnt] & 0x80000) { | |
4930 | test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip); | |
4931 | hc->wdcount = 0; | |
4932 | hc->wdbyte = V_GPIO_OUT2; | |
4933 | printk(KERN_NOTICE "Watchdog enabled\n"); | |
4934 | } | |
4935 | ||
4936 | /* setup pci, hc->slots may change due to PLXSD */ | |
4937 | ret_err = setup_pci(hc, pdev, ent); | |
4938 | if (ret_err) { | |
4939 | if (hc == syncmaster) | |
4940 | syncmaster = NULL; | |
4941 | kfree(hc); | |
4942 | return ret_err; | |
4943 | } | |
4944 | ||
4945 | /* crate channels */ | |
4946 | for (pt = 0; pt < hc->ports; pt++) { | |
4947 | if (Port_cnt >= MAX_PORTS) { | |
4948 | printk(KERN_ERR "too many ports (max=%d).\n", | |
4949 | MAX_PORTS); | |
4950 | ret_err = -EINVAL; | |
4951 | goto free_card; | |
4952 | } | |
4953 | if (hc->type == 1) | |
4954 | ret_err = init_e1_port(hc, m); | |
4955 | else | |
4956 | ret_err = init_multi_port(hc, pt); | |
4957 | if (debug & DEBUG_HFCMULTI_INIT) | |
4958 | printk(KERN_DEBUG | |
4959 | "%s: Registering D-channel, card(%d) port(%d)" | |
4960 | "result %d\n", | |
4961 | __func__, HFC_cnt + 1, pt, ret_err); | |
4962 | ||
4963 | if (ret_err) { | |
4964 | while (pt) { /* release already registered ports */ | |
4965 | pt--; | |
4966 | release_port(hc, hc->chan[(pt << 2) + 2].dch); | |
4967 | } | |
4968 | goto free_card; | |
4969 | } | |
4970 | Port_cnt++; | |
4971 | } | |
4972 | ||
4973 | /* disp switches */ | |
4974 | switch (m->dip_type) { | |
4975 | case DIP_4S: | |
4976 | /* | |
69e656cc | 4977 | * Get DIP setting for beroNet 1S/2S/4S cards |
af69fb3a KK |
4978 | * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) + |
4979 | * GPI 19/23 (R_GPI_IN2)) | |
4980 | */ | |
4981 | dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) | | |
4982 | ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) | | |
4983 | (~HFC_inb(hc, R_GPI_IN2) & 0x08); | |
4984 | ||
4985 | /* Port mode (TE/NT) jumpers */ | |
4986 | pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf); | |
4987 | ||
4988 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) | |
4989 | pmj = ~pmj & 0xf; | |
4990 | ||
4991 | printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n", | |
4992 | m->vendor_name, m->card_name, dips, pmj); | |
4993 | break; | |
4994 | case DIP_8S: | |
4995 | /* | |
69e656cc KK |
4996 | * Get DIP Setting for beroNet 8S0+ cards |
4997 | * Enable PCI auxbridge function | |
af69fb3a KK |
4998 | */ |
4999 | HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); | |
5000 | /* prepare access to auxport */ | |
5001 | outw(0x4000, hc->pci_iobase + 4); | |
5002 | /* | |
5003 | * some dummy reads are required to | |
5004 | * read valid DIP switch data | |
5005 | */ | |
5006 | dips = inb(hc->pci_iobase); | |
5007 | dips = inb(hc->pci_iobase); | |
5008 | dips = inb(hc->pci_iobase); | |
5009 | dips = ~inb(hc->pci_iobase) & 0x3F; | |
5010 | outw(0x0, hc->pci_iobase + 4); | |
5011 | /* disable PCI auxbridge function */ | |
5012 | HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); | |
5013 | printk(KERN_INFO "%s: %s DIPs(0x%x)\n", | |
5014 | m->vendor_name, m->card_name, dips); | |
5015 | break; | |
5016 | case DIP_E1: | |
5017 | /* | |
5018 | * get DIP Setting for beroNet E1 cards | |
5019 | * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0) | |
5020 | */ | |
5021 | dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4; | |
5022 | printk(KERN_INFO "%s: %s DIPs(0x%x)\n", | |
5023 | m->vendor_name, m->card_name, dips); | |
5024 | break; | |
5025 | } | |
5026 | ||
5027 | /* add to list */ | |
5028 | spin_lock_irqsave(&HFClock, flags); | |
5029 | list_add_tail(&hc->list, &HFClist); | |
5030 | spin_unlock_irqrestore(&HFClock, flags); | |
5031 | ||
3bd69ad1 AE |
5032 | /* use as clock source */ |
5033 | if (clock == HFC_cnt + 1) | |
5034 | hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc); | |
5035 | ||
af69fb3a KK |
5036 | /* initialize hardware */ |
5037 | ret_err = init_card(hc); | |
5038 | if (ret_err) { | |
5039 | printk(KERN_ERR "init card returns %d\n", ret_err); | |
5040 | release_card(hc); | |
5041 | return ret_err; | |
5042 | } | |
5043 | ||
5044 | /* start IRQ and return */ | |
5045 | spin_lock_irqsave(&hc->lock, flags); | |
5046 | enable_hwirq(hc); | |
5047 | spin_unlock_irqrestore(&hc->lock, flags); | |
5048 | return 0; | |
5049 | ||
5050 | free_card: | |
5051 | release_io_hfcmulti(hc); | |
5052 | if (hc == syncmaster) | |
5053 | syncmaster = NULL; | |
5054 | kfree(hc); | |
5055 | return ret_err; | |
5056 | } | |
5057 | ||
5058 | static void __devexit hfc_remove_pci(struct pci_dev *pdev) | |
5059 | { | |
5060 | struct hfc_multi *card = pci_get_drvdata(pdev); | |
5061 | u_long flags; | |
5062 | ||
5063 | if (debug) | |
5064 | printk(KERN_INFO "removing hfc_multi card vendor:%x " | |
5065 | "device:%x subvendor:%x subdevice:%x\n", | |
5066 | pdev->vendor, pdev->device, | |
5067 | pdev->subsystem_vendor, pdev->subsystem_device); | |
5068 | ||
5069 | if (card) { | |
5070 | spin_lock_irqsave(&HFClock, flags); | |
5071 | release_card(card); | |
5072 | spin_unlock_irqrestore(&HFClock, flags); | |
5073 | } else { | |
5074 | if (debug) | |
5075 | printk(KERN_WARNING "%s: drvdata allready removed\n", | |
5076 | __func__); | |
5077 | } | |
5078 | } | |
5079 | ||
5080 | #define VENDOR_CCD "Cologne Chip AG" | |
5081 | #define VENDOR_BN "beroNet GmbH" | |
5082 | #define VENDOR_DIG "Digium Inc." | |
5083 | #define VENDOR_JH "Junghanns.NET GmbH" | |
5084 | #define VENDOR_PRIM "PrimuX" | |
5085 | ||
5086 | static const struct hm_map hfcm_map[] = { | |
5087 | /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0}, | |
31981db0 | 5088 | /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0}, |
af69fb3a KK |
5089 | /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0}, |
5090 | /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0}, | |
5091 | /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0}, | |
5092 | /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0}, | |
31981db0 | 5093 | /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0}, |
af69fb3a KK |
5094 | /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0}, |
5095 | /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO}, | |
5096 | /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0}, | |
5097 | /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0}, | |
5098 | /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0}, | |
5099 | ||
5100 | /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0}, | |
5101 | /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S, | |
5102 | HFC_IO_MODE_REGIO}, | |
5103 | /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0}, | |
5104 | /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0}, | |
5105 | ||
5106 | /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0}, | |
5107 | /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0}, | |
5108 | /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0}, | |
5109 | ||
5110 | /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0}, | |
5111 | /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0}, | |
5112 | /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0}, | |
5113 | /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0}, | |
5114 | ||
5115 | /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0}, | |
5116 | /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0}, | |
5117 | /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0}, | |
5118 | ||
5119 | /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0, | |
5120 | HFC_IO_MODE_PLXSD}, | |
5121 | /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0, | |
5122 | HFC_IO_MODE_PLXSD}, | |
5123 | /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0}, | |
5124 | /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0}, | |
5125 | /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0}, | |
5126 | }; | |
5127 | ||
5128 | #undef H | |
5129 | #define H(x) ((unsigned long)&hfcm_map[x]) | |
5130 | static struct pci_device_id hfmultipci_ids[] __devinitdata = { | |
5131 | ||
5132 | /* Cards with HFC-4S Chip */ | |
5133 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5134 | PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */ | |
5135 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5136 | PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */ | |
5137 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5138 | PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */ | |
5139 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5140 | PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */ | |
5141 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5142 | PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */ | |
5143 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5144 | PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */ | |
5145 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5146 | PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */ | |
5147 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5148 | PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */ | |
5149 | { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, | |
5150 | PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)}, | |
5151 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5152 | PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */ | |
5153 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5154 | PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)}, | |
5155 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5156 | PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */ | |
5157 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5158 | PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */ | |
5159 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5160 | PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */ | |
5161 | ||
5162 | /* Cards with HFC-8S Chip */ | |
5163 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5164 | PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */ | |
5165 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5166 | PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */ | |
5167 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5168 | PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */ | |
5169 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
69e656cc | 5170 | PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */ |
af69fb3a KK |
5171 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, |
5172 | PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */ | |
5173 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5174 | PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */ | |
5175 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5176 | PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */ | |
5177 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5178 | PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */ | |
5179 | ||
5180 | ||
5181 | /* Cards with HFC-E1 Chip */ | |
5182 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5183 | PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */ | |
5184 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5185 | PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */ | |
5186 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5187 | PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */ | |
5188 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5189 | PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */ | |
5190 | ||
5191 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5192 | PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */ | |
5193 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5194 | PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */ | |
5195 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5196 | PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */ | |
5197 | ||
5198 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, | |
5199 | PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */ | |
5200 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, | |
5201 | PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */ | |
5202 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID, | |
5203 | 0, 0, 0}, | |
5204 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID, | |
5205 | 0, 0, 0}, | |
5206 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID, | |
5207 | 0, 0, 0}, | |
5208 | {0, } | |
5209 | }; | |
5210 | #undef H | |
5211 | ||
5212 | MODULE_DEVICE_TABLE(pci, hfmultipci_ids); | |
5213 | ||
5214 | static int | |
5215 | hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
5216 | { | |
5217 | struct hm_map *m = (struct hm_map *)ent->driver_data; | |
5218 | int ret; | |
5219 | ||
69e656cc KK |
5220 | if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && ( |
5221 | ent->device == PCI_DEVICE_ID_CCD_HFC4S || | |
5222 | ent->device == PCI_DEVICE_ID_CCD_HFC8S || | |
5223 | ent->device == PCI_DEVICE_ID_CCD_HFCE1)) { | |
5224 | printk(KERN_ERR | |
5225 | "Unknown HFC multiport controller (vendor:%x device:%x " | |
5226 | "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device, | |
5227 | ent->subvendor, ent->subdevice); | |
5228 | printk(KERN_ERR | |
5229 | "Please contact the driver maintainer for support.\n"); | |
af69fb3a KK |
5230 | return -ENODEV; |
5231 | } | |
5232 | ret = hfcmulti_init(pdev, ent); | |
5233 | if (ret) | |
5234 | return ret; | |
5235 | HFC_cnt++; | |
5236 | printk(KERN_INFO "%d devices registered\n", HFC_cnt); | |
5237 | return 0; | |
5238 | } | |
5239 | ||
5240 | static struct pci_driver hfcmultipci_driver = { | |
5241 | .name = "hfc_multi", | |
5242 | .probe = hfcmulti_probe, | |
5243 | .remove = __devexit_p(hfc_remove_pci), | |
5244 | .id_table = hfmultipci_ids, | |
5245 | }; | |
5246 | ||
5247 | static void __exit | |
5248 | HFCmulti_cleanup(void) | |
5249 | { | |
5250 | struct hfc_multi *card, *next; | |
5251 | ||
69e656cc | 5252 | /* get rid of all devices of this driver */ |
af69fb3a KK |
5253 | list_for_each_entry_safe(card, next, &HFClist, list) |
5254 | release_card(card); | |
af69fb3a KK |
5255 | pci_unregister_driver(&hfcmultipci_driver); |
5256 | } | |
5257 | ||
5258 | static int __init | |
5259 | HFCmulti_init(void) | |
5260 | { | |
5261 | int err; | |
5262 | ||
69e656cc KK |
5263 | printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION); |
5264 | ||
af69fb3a | 5265 | #ifdef IRQ_DEBUG |
69e656cc | 5266 | printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__); |
af69fb3a KK |
5267 | #endif |
5268 | ||
5269 | spin_lock_init(&HFClock); | |
5270 | spin_lock_init(&plx_lock); | |
5271 | ||
5272 | if (debug & DEBUG_HFCMULTI_INIT) | |
5273 | printk(KERN_DEBUG "%s: init entered\n", __func__); | |
5274 | ||
af69fb3a KK |
5275 | switch (poll) { |
5276 | case 0: | |
5277 | poll_timer = 6; | |
5278 | poll = 128; | |
5279 | break; | |
af69fb3a KK |
5280 | case 8: |
5281 | poll_timer = 2; | |
5282 | break; | |
5283 | case 16: | |
5284 | poll_timer = 3; | |
5285 | break; | |
5286 | case 32: | |
5287 | poll_timer = 4; | |
5288 | break; | |
5289 | case 64: | |
5290 | poll_timer = 5; | |
5291 | break; | |
5292 | case 128: | |
5293 | poll_timer = 6; | |
5294 | break; | |
5295 | case 256: | |
5296 | poll_timer = 7; | |
5297 | break; | |
5298 | default: | |
5299 | printk(KERN_ERR | |
5300 | "%s: Wrong poll value (%d).\n", __func__, poll); | |
5301 | err = -EINVAL; | |
5302 | return err; | |
5303 | ||
5304 | } | |
5305 | ||
3bd69ad1 AE |
5306 | if (!clock) |
5307 | clock = 1; | |
5308 | ||
af69fb3a KK |
5309 | err = pci_register_driver(&hfcmultipci_driver); |
5310 | if (err < 0) { | |
5311 | printk(KERN_ERR "error registering pci driver: %x\n", err); | |
af69fb3a KK |
5312 | return err; |
5313 | } | |
5314 | return 0; | |
5315 | } | |
5316 | ||
5317 | ||
5318 | module_init(HFCmulti_init); | |
5319 | module_exit(HFCmulti_cleanup); |