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mISDN: Fix skb leak in error cases
[mirror_ubuntu-artful-kernel.git] / drivers / isdn / hardware / mISDN / hfcmulti.c
CommitLineData
af69fb3a
KK		 1/*
2 * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards
3 *
4 * Author Andreas Eversberg (jolly@eversberg.eu)
5 * ported to mqueue mechanism:
6 * Peter Sprenger (sprengermoving-bytes.de)
7 *
8 * inspired by existing hfc-pci driver:
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil (kkeil@suse.de)
11 * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu)
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2, or (at your option)
16 * any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 *
27 *
28 * Thanks to Cologne Chip AG for this great controller!
29 */
30
31/*
32 * module parameters:
33 * type:
34 * By default (0), the card is automatically detected.
35 * Or use the following combinations:
36 * Bit 0-7 = 0x00001 = HFC-E1 (1 port)
37 * or Bit 0-7 = 0x00004 = HFC-4S (4 ports)
38 * or Bit 0-7 = 0x00008 = HFC-8S (8 ports)
39 * Bit 8 = 0x00100 = uLaw (instead of aLaw)
40 * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware
41 * Bit 10 = spare
42 * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto)
43 * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto)
44 * Bit 13 = spare
45 * Bit 14 = 0x04000 = Use external ram (128K)
46 * Bit 15 = 0x08000 = Use external ram (512K)
47 * Bit 16 = 0x10000 = Use 64 timeslots instead of 32
48 * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else
49 * Bit 18 = spare
50 * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog)
51 * (all other bits are reserved and shall be 0)
52 * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM
53 * bus (PCM master)
54 *
55 * port: (optional or required for all ports on all installed cards)
56 * HFC-4S/HFC-8S only bits:
57 * Bit 0 = 0x001 = Use master clock for this S/T interface
58 * (ony once per chip).
59 * Bit 1 = 0x002 = transmitter line setup (non capacitive mode)
60 * Don't use this unless you know what you are doing!
61 * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing)
62 * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock
63 * received from port 1
64 *
65 * HFC-E1 only bits:
66 * Bit 0 = 0x0001 = interface: 0=copper, 1=optical
67 * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode)
68 * Bit 2 = 0x0004 = Report LOS
69 * Bit 3 = 0x0008 = Report AIS
70 * Bit 4 = 0x0010 = Report SLIP
71 * Bit 5 = 0x0020 = Report RDI
72 * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame
73 * mode instead.
74 * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode.
75 * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode.
76 * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL.
77 * (E1 only)
78 * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0
79 * for default.
80 * (all other bits are reserved and shall be 0)
81 *
82 * debug:
83 * NOTE: only one debug value must be given for all cards
84 * enable debugging (see hfc_multi.h for debug options)
85 *
86 * poll:
87 * NOTE: only one poll value must be given for all cards
88 * Give the number of samples for each fifo process.
89 * By default 128 is used. Decrease to reduce delay, increase to
90 * reduce cpu load. If unsure, don't mess with it!
91 * Valid is 8, 16, 32, 64, 128, 256.
92 *
93 * pcm:
94 * NOTE: only one pcm value must be given for every card.
95 * The PCM bus id tells the mISDNdsp module about the connected PCM bus.
96 * By default (0), the PCM bus id is 100 for the card that is PCM master.
97 * If multiple cards are PCM master (because they are not interconnected),
98 * each card with PCM master will have increasing PCM id.
99 * All PCM busses with the same ID are expected to be connected and have
100 * common time slots slots.
101 * Only one chip of the PCM bus must be master, the others slave.
102 * -1 means no support of PCM bus not even.
103 * Omit this value, if all cards are interconnected or none is connected.
104 * If unsure, don't give this parameter.
105 *
106 * dslot:
44e09589 107 * NOTE: only one dslot value must be given for every card.
af69fb3a
KK		 108 * Also this value must be given for non-E1 cards. If omitted, the E1
109 * card has D-channel on time slot 16, which is default.
110 * If 1..15 or 17..31, an alternate time slot is used for D-channel.
111 * In this case, the application must be able to handle this.
112 * If -1 is given, the D-channel is disabled and all 31 slots can be used
113 * for B-channel. (only for specific applications)
114 * If you don't know how to use it, you don't need it!
115 *
116 * iomode:
117 * NOTE: only one mode value must be given for every card.
118 * -> See hfc_multi.h for HFC_IO_MODE_* values
119 * By default, the IO mode is pci memory IO (MEMIO).
120 * Some cards requre specific IO mode, so it cannot be changed.
121 * It may be usefull to set IO mode to register io (REGIO) to solve
122 * PCI bridge problems.
123 * If unsure, don't give this parameter.
124 *
125 * clockdelay_nt:
126 * NOTE: only one clockdelay_nt value must be given once for all cards.
127 * Give the value of the clock control register (A_ST_CLK_DLY)
128 * of the S/T interfaces in NT mode.
129 * This register is needed for the TBR3 certification, so don't change it.
130 *
131 * clockdelay_te:
132 * NOTE: only one clockdelay_te value must be given once
133 * Give the value of the clock control register (A_ST_CLK_DLY)
134 * of the S/T interfaces in TE mode.
135 * This register is needed for the TBR3 certification, so don't change it.
3bd69ad1
AE		 136 *
137 * clock:
1b36c78f 138 * NOTE: only one clock value must be given once
3bd69ad1
AE		 139 * Selects interface with clock source for mISDN and applications.
140 * Set to card number starting with 1. Set to -1 to disable.
141 * By default, the first card is used as clock source.
af69fb3a
KK		 142 */
143
144/*
145 * debug register access (never use this, it will flood your system log)
146 * #define HFC_REGISTER_DEBUG
147 */
148
69e656cc 149#define HFC_MULTI_VERSION "2.03"
af69fb3a
KK		 150
151#include <linux/module.h>
152#include <linux/pci.h>
153#include <linux/delay.h>
154#include <linux/mISDNhw.h>
155#include <linux/mISDNdsp.h>
156
157/*
158#define IRQCOUNT_DEBUG
159#define IRQ_DEBUG
160*/
161
162#include "hfc_multi.h"
163#ifdef ECHOPREP
164#include "gaintab.h"
165#endif
166
167#define MAX_CARDS 8
168#define MAX_PORTS (8 * MAX_CARDS)
169
170static LIST_HEAD(HFClist);
171static spinlock_t HFClock; /* global hfc list lock */
172
173static void ph_state_change(struct dchannel *);
af69fb3a
KK		 174
175static struct hfc_multi *syncmaster;
5b834354 176static int plxsd_master; /* if we have a master card (yet) */
af69fb3a 177static spinlock_t plx_lock; /* may not acquire other lock inside */
af69fb3a
KK		 178
179#define TYP_E1 1
180#define TYP_4S 4
181#define TYP_8S 8
182
183static int poll_timer = 6; /* default = 128 samples = 16ms */
184/* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */
185static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 };
186#define CLKDEL_TE 0x0f /* CLKDEL in TE mode */
187#define CLKDEL_NT 0x6c /* CLKDEL in NT mode
188 (0x60 MUST be included!) */
af69fb3a
KK		 189
190#define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */
191#define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */
192#define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */
193
194/*
195 * module stuff
196 */
197
198static uint type[MAX_CARDS];
3bd69ad1
AE		 199static int pcm[MAX_CARDS];
200static int dslot[MAX_CARDS];
af69fb3a
KK		 201static uint iomode[MAX_CARDS];
202static uint port[MAX_PORTS];
203static uint debug;
204static uint poll;
3bd69ad1 205static int clock;
af69fb3a
KK		 206static uint timer;
207static uint clockdelay_te = CLKDEL_TE;
208static uint clockdelay_nt = CLKDEL_NT;
209
210static int HFC_cnt, Port_cnt, PCM_cnt = 99;
211
212MODULE_AUTHOR("Andreas Eversberg");
213MODULE_LICENSE("GPL");
69e656cc 214MODULE_VERSION(HFC_MULTI_VERSION);
af69fb3a
KK		 215module_param(debug, uint, S_IRUGO | S_IWUSR);
216module_param(poll, uint, S_IRUGO | S_IWUSR);
3bd69ad1 217module_param(clock, int, S_IRUGO | S_IWUSR);
af69fb3a
KK		 218module_param(timer, uint, S_IRUGO | S_IWUSR);
219module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR);
220module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR);
221module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR);
3bd69ad1
AE		 222module_param_array(pcm, int, NULL, S_IRUGO | S_IWUSR);
223module_param_array(dslot, int, NULL, S_IRUGO | S_IWUSR);
af69fb3a
KK		 224module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR);
225module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR);
226
227#ifdef HFC_REGISTER_DEBUG
228#define HFC_outb(hc, reg, val) \
229 (hc->HFC_outb(hc, reg, val, __func__, __LINE__))
230#define HFC_outb_nodebug(hc, reg, val) \
231 (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__))
232#define HFC_inb(hc, reg) \
233 (hc->HFC_inb(hc, reg, __func__, __LINE__))
234#define HFC_inb_nodebug(hc, reg) \
235 (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__))
236#define HFC_inw(hc, reg) \
237 (hc->HFC_inw(hc, reg, __func__, __LINE__))
238#define HFC_inw_nodebug(hc, reg) \
239 (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__))
240#define HFC_wait(hc) \
241 (hc->HFC_wait(hc, __func__, __LINE__))
242#define HFC_wait_nodebug(hc) \
243 (hc->HFC_wait_nodebug(hc, __func__, __LINE__))
244#else
245#define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val))
246#define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val))
247#define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg))
248#define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg))
249#define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg))
250#define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg))
251#define HFC_wait(hc) (hc->HFC_wait(hc))
252#define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc))
253#endif
254
255/* HFC_IO_MODE_PCIMEM */
256static void
257#ifdef HFC_REGISTER_DEBUG
258HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val,
259 const char *function, int line)
260#else
261HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val)
262#endif
263{
264 writeb(val, (hc->pci_membase)+reg);
265}
266static u_char
267#ifdef HFC_REGISTER_DEBUG
268HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
269#else
270HFC_inb_pcimem(struct hfc_multi *hc, u_char reg)
271#endif
272{
273 return readb((hc->pci_membase)+reg);
274}
275static u_short
276#ifdef HFC_REGISTER_DEBUG
277HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line)
278#else
279HFC_inw_pcimem(struct hfc_multi *hc, u_char reg)
280#endif
281{
282 return readw((hc->pci_membase)+reg);
283}
284static void
285#ifdef HFC_REGISTER_DEBUG
286HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line)
287#else
288HFC_wait_pcimem(struct hfc_multi *hc)
289#endif
290{
291 while (readb((hc->pci_membase)+R_STATUS) & V_BUSY);
292}
293
294/* HFC_IO_MODE_REGIO */
295static void
296#ifdef HFC_REGISTER_DEBUG
297HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val,
298 const char *function, int line)
299#else
300HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val)
301#endif
302{
303 outb(reg, (hc->pci_iobase)+4);
304 outb(val, hc->pci_iobase);
305}
306static u_char
307#ifdef HFC_REGISTER_DEBUG
308HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
309#else
310HFC_inb_regio(struct hfc_multi *hc, u_char reg)
311#endif
312{
313 outb(reg, (hc->pci_iobase)+4);
314 return inb(hc->pci_iobase);
315}
316static u_short
317#ifdef HFC_REGISTER_DEBUG
318HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line)
319#else
320HFC_inw_regio(struct hfc_multi *hc, u_char reg)
321#endif
322{
323 outb(reg, (hc->pci_iobase)+4);
324 return inw(hc->pci_iobase);
325}
326static void
327#ifdef HFC_REGISTER_DEBUG
328HFC_wait_regio(struct hfc_multi *hc, const char *function, int line)
329#else
330HFC_wait_regio(struct hfc_multi *hc)
331#endif
332{
333 outb(R_STATUS, (hc->pci_iobase)+4);
334 while (inb(hc->pci_iobase) & V_BUSY);
335}
336
337#ifdef HFC_REGISTER_DEBUG
338static void
339HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val,
340 const char *function, int line)
341{
342 char regname[256] = "", bits[9] = "xxxxxxxx";
343 int i;
344
345 i = -1;
346 while (hfc_register_names[++i].name) {
347 if (hfc_register_names[i].reg == reg)
348 strcat(regname, hfc_register_names[i].name);
349 }
350 if (regname[0] == '\0')
351 strcpy(regname, "register");
352
353 bits[7] = '0'+(!!(val&1));
354 bits[6] = '0'+(!!(val&2));
355 bits[5] = '0'+(!!(val&4));
356 bits[4] = '0'+(!!(val&8));
357 bits[3] = '0'+(!!(val&16));
358 bits[2] = '0'+(!!(val&32));
359 bits[1] = '0'+(!!(val&64));
360 bits[0] = '0'+(!!(val&128));
361 printk(KERN_DEBUG
362 "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n",
363 hc->id, reg, regname, val, bits, function, line);
364 HFC_outb_nodebug(hc, reg, val);
365}
366static u_char
367HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
368{
369 char regname[256] = "", bits[9] = "xxxxxxxx";
370 u_char val = HFC_inb_nodebug(hc, reg);
371 int i;
372
373 i = 0;
374 while (hfc_register_names[i++].name)
375 ;
376 while (hfc_register_names[++i].name) {
377 if (hfc_register_names[i].reg == reg)
378 strcat(regname, hfc_register_names[i].name);
379 }
380 if (regname[0] == '\0')
381 strcpy(regname, "register");
382
383 bits[7] = '0'+(!!(val&1));
384 bits[6] = '0'+(!!(val&2));
385 bits[5] = '0'+(!!(val&4));
386 bits[4] = '0'+(!!(val&8));
387 bits[3] = '0'+(!!(val&16));
388 bits[2] = '0'+(!!(val&32));
389 bits[1] = '0'+(!!(val&64));
390 bits[0] = '0'+(!!(val&128));
391 printk(KERN_DEBUG
392 "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n",
393 hc->id, reg, regname, val, bits, function, line);
394 return val;
395}
396static u_short
397HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line)
398{
399 char regname[256] = "";
400 u_short val = HFC_inw_nodebug(hc, reg);
401 int i;
402
403 i = 0;
404 while (hfc_register_names[i++].name)
405 ;
406 while (hfc_register_names[++i].name) {
407 if (hfc_register_names[i].reg == reg)
408 strcat(regname, hfc_register_names[i].name);
409 }
410 if (regname[0] == '\0')
411 strcpy(regname, "register");
412
413 printk(KERN_DEBUG
414 "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n",
415 hc->id, reg, regname, val, function, line);
416 return val;
417}
418static void
419HFC_wait_debug(struct hfc_multi *hc, const char *function, int line)
420{
421 printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n",
422 hc->id, function, line);
423 HFC_wait_nodebug(hc);
424}
425#endif
426
427/* write fifo data (REGIO) */
5b834354 428static void
af69fb3a
KK		 429write_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
430{
431 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
432 while (len>>2) {
b3e0aeeb 433 outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase);
af69fb3a
KK		 434 data += 4;
435 len -= 4;
436 }
437 while (len>>1) {
b3e0aeeb 438 outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase);
af69fb3a
KK		 439 data += 2;
440 len -= 2;
441 }
442 while (len) {
443 outb(*data, hc->pci_iobase);
444 data++;
445 len--;
446 }
447}
448/* write fifo data (PCIMEM) */
5b834354 449static void
af69fb3a
KK		 450write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
451{
452 while (len>>2) {
b3e0aeeb
KK		 453 writel(cpu_to_le32(*(u32 *)data),
454 hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 455 data += 4;
456 len -= 4;
457 }
458 while (len>>1) {
b3e0aeeb
KK		 459 writew(cpu_to_le16(*(u16 *)data),
460 hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 461 data += 2;
462 len -= 2;
463 }
464 while (len) {
b3e0aeeb 465 writeb(*data, hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 466 data++;
467 len--;
468 }
469}
470/* read fifo data (REGIO) */
5b834354 471static void
af69fb3a
KK		 472read_fifo_regio(struct hfc_multi *hc, u_char *data, int len)
473{
474 outb(A_FIFO_DATA0, (hc->pci_iobase)+4);
475 while (len>>2) {
b3e0aeeb 476 *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase));
af69fb3a
KK		 477 data += 4;
478 len -= 4;
479 }
480 while (len>>1) {
b3e0aeeb 481 *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase));
af69fb3a
KK		 482 data += 2;
483 len -= 2;
484 }
485 while (len) {
486 *data = inb(hc->pci_iobase);
487 data++;
488 len--;
489 }
490}
491
492/* read fifo data (PCIMEM) */
5b834354 493static void
af69fb3a
KK		 494read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len)
495{
496 while (len>>2) {
497 *(u32 *)data =
b3e0aeeb 498 le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0));
af69fb3a
KK		 499 data += 4;
500 len -= 4;
501 }
502 while (len>>1) {
503 *(u16 *)data =
b3e0aeeb 504 le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0));
af69fb3a
KK		 505 data += 2;
506 len -= 2;
507 }
508 while (len) {
b3e0aeeb 509 *data = readb(hc->pci_membase + A_FIFO_DATA0);
af69fb3a
KK		 510 data++;
511 len--;
512 }
513}
514
515
516static void
517enable_hwirq(struct hfc_multi *hc)
518{
519 hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN;
520 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
521}
522
523static void
524disable_hwirq(struct hfc_multi *hc)
525{
526 hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN);
527 HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl);
528}
529
530#define NUM_EC 2
531#define MAX_TDM_CHAN 32
532
533
534inline void
535enablepcibridge(struct hfc_multi *c)
536{
537 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */
538}
539
540inline void
541disablepcibridge(struct hfc_multi *c)
542{
543 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */
544}
545
546inline unsigned char
547readpcibridge(struct hfc_multi *hc, unsigned char address)
548{
549 unsigned short cipv;
550 unsigned char data;
551
552 if (!hc->pci_iobase)
553 return 0;
554
555 /* slow down a PCI read access by 1 PCI clock cycle */
556 HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/
557
558 if (address == 0)
559 cipv = 0x4000;
560 else
561 cipv = 0x5800;
562
563 /* select local bridge port address by writing to CIP port */
564 /* data = HFC_inb(c, cipv); * was _io before */
565 outw(cipv, hc->pci_iobase + 4);
566 data = inb(hc->pci_iobase);
567
568 /* restore R_CTRL for normal PCI read cycle speed */
569 HFC_outb(hc, R_CTRL, 0x0); /* was _io before */
570
571 return data;
572}
573
574inline void
575writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data)
576{
577 unsigned short cipv;
578 unsigned int datav;
579
580 if (!hc->pci_iobase)
581 return;
582
583 if (address == 0)
584 cipv = 0x4000;
585 else
586 cipv = 0x5800;
587
588 /* select local bridge port address by writing to CIP port */
589 outw(cipv, hc->pci_iobase + 4);
590 /* define a 32 bit dword with 4 identical bytes for write sequence */
591 datav = data | ((__u32) data << 8) | ((__u32) data << 16) |
592 ((__u32) data << 24);
593
594 /*
595 * write this 32 bit dword to the bridge data port
596 * this will initiate a write sequence of up to 4 writes to the same
597 * address on the local bus interface the number of write accesses
598 * is undefined but >=1 and depends on the next PCI transaction
599 * during write sequence on the local bus
600 */
601 outl(datav, hc->pci_iobase);
602}
603
604inline void
605cpld_set_reg(struct hfc_multi *hc, unsigned char reg)
606{
607 /* Do data pin read low byte */
608 HFC_outb(hc, R_GPIO_OUT1, reg);
609}
610
611inline void
612cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val)
613{
614 cpld_set_reg(hc, reg);
615
616 enablepcibridge(hc);
617 writepcibridge(hc, 1, val);
618 disablepcibridge(hc);
619
620 return;
621}
622
623inline unsigned char
624cpld_read_reg(struct hfc_multi *hc, unsigned char reg)
625{
626 unsigned char bytein;
627
628 cpld_set_reg(hc, reg);
629
630 /* Do data pin read low byte */
631 HFC_outb(hc, R_GPIO_OUT1, reg);
632
633 enablepcibridge(hc);
634 bytein = readpcibridge(hc, 1);
635 disablepcibridge(hc);
636
637 return bytein;
638}
639
640inline void
641vpm_write_address(struct hfc_multi *hc, unsigned short addr)
642{
643 cpld_write_reg(hc, 0, 0xff & addr);
644 cpld_write_reg(hc, 1, 0x01 & (addr >> 8));
645}
646
647inline unsigned short
648vpm_read_address(struct hfc_multi *c)
649{
650 unsigned short addr;
651 unsigned short highbit;
652
653 addr = cpld_read_reg(c, 0);
654 highbit = cpld_read_reg(c, 1);
655
656 addr = addr | (highbit << 8);
657
658 return addr & 0x1ff;
659}
660
661inline unsigned char
662vpm_in(struct hfc_multi *c, int which, unsigned short addr)
663{
664 unsigned char res;
665
666 vpm_write_address(c, addr);
667
668 if (!which)
669 cpld_set_reg(c, 2);
670 else
671 cpld_set_reg(c, 3);
672
673 enablepcibridge(c);
674 res = readpcibridge(c, 1);
675 disablepcibridge(c);
676
677 cpld_set_reg(c, 0);
678
679 return res;
680}
681
682inline void
683vpm_out(struct hfc_multi *c, int which, unsigned short addr,
684 unsigned char data)
685{
686 vpm_write_address(c, addr);
687
688 enablepcibridge(c);
689
690 if (!which)
691 cpld_set_reg(c, 2);
692 else
693 cpld_set_reg(c, 3);
694
695 writepcibridge(c, 1, data);
696
697 cpld_set_reg(c, 0);
698
699 disablepcibridge(c);
700
701 {
702 unsigned char regin;
703 regin = vpm_in(c, which, addr);
704 if (regin != data)
705 printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back "
706 "0x%x\n", data, addr, regin);
707 }
708
709}
710
711
5b834354 712static void
af69fb3a
KK		 713vpm_init(struct hfc_multi *wc)
714{
715 unsigned char reg;
716 unsigned int mask;
717 unsigned int i, x, y;
718 unsigned int ver;
719
720 for (x = 0; x < NUM_EC; x++) {
721 /* Setup GPIO's */
722 if (!x) {
723 ver = vpm_in(wc, x, 0x1a0);
724 printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver);
725 }
726
727 for (y = 0; y < 4; y++) {
728 vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */
729 vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */
730 vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */
731 }
732
733 /* Setup TDM path - sets fsync and tdm_clk as inputs */
734 reg = vpm_in(wc, x, 0x1a3); /* misc_con */
735 vpm_out(wc, x, 0x1a3, reg & ~2);
736
737 /* Setup Echo length (256 taps) */
738 vpm_out(wc, x, 0x022, 1);
739 vpm_out(wc, x, 0x023, 0xff);
740
741 /* Setup timeslots */
742 vpm_out(wc, x, 0x02f, 0x00);
743 mask = 0x02020202 << (x * 4);
744
745 /* Setup the tdm channel masks for all chips */
746 for (i = 0; i < 4; i++)
747 vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff);
748
749 /* Setup convergence rate */
750 printk(KERN_DEBUG "VPM: A-law mode\n");
751 reg = 0x00 | 0x10 | 0x01;
752 vpm_out(wc, x, 0x20, reg);
753 printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg);
754 /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */
755
756 vpm_out(wc, x, 0x24, 0x02);
757 reg = vpm_in(wc, x, 0x24);
758 printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg);
759
760 /* Initialize echo cans */
761 for (i = 0; i < MAX_TDM_CHAN; i++) {
762 if (mask & (0x00000001 << i))
763 vpm_out(wc, x, i, 0x00);
764 }
765
766 /*
767 * ARM arch at least disallows a udelay of
768 * more than 2ms... it gives a fake "__bad_udelay"
769 * reference at link-time.
770 * long delays in kernel code are pretty sucky anyway
771 * for now work around it using 5 x 2ms instead of 1 x 10ms
772 */
773
774 udelay(2000);
775 udelay(2000);
776 udelay(2000);
777 udelay(2000);
778 udelay(2000);
779
780 /* Put in bypass mode */
781 for (i = 0; i < MAX_TDM_CHAN; i++) {
782 if (mask & (0x00000001 << i))
783 vpm_out(wc, x, i, 0x01);
784 }
785
786 /* Enable bypass */
787 for (i = 0; i < MAX_TDM_CHAN; i++) {
788 if (mask & (0x00000001 << i))
789 vpm_out(wc, x, 0x78 + i, 0x01);
790 }
791
792 }
793}
794
047ce8f2 795#ifdef UNUSED
5b834354 796static void
af69fb3a
KK		 797vpm_check(struct hfc_multi *hctmp)
798{
799 unsigned char gpi2;
800
801 gpi2 = HFC_inb(hctmp, R_GPI_IN2);
802
803 if ((gpi2 & 0x3) != 0x3)
804 printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2);
805}
047ce8f2 806#endif /* UNUSED */
af69fb3a
KK		 807
808
809/*
810 * Interface to enable/disable the HW Echocan
811 *
812 * these functions are called within a spin_lock_irqsave on
813 * the channel instance lock, so we are not disturbed by irqs
814 *
815 * we can later easily change the interface to make other
816 * things configurable, for now we configure the taps
817 *
818 */
819
5b834354 820static void
af69fb3a
KK		 821vpm_echocan_on(struct hfc_multi *hc, int ch, int taps)
822{
823 unsigned int timeslot;
824 unsigned int unit;
825 struct bchannel *bch = hc->chan[ch].bch;
826#ifdef TXADJ
827 int txadj = -4;
828 struct sk_buff *skb;
829#endif
830 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
831 return;
832
833 if (!bch)
834 return;
835
836#ifdef TXADJ
837 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
838 sizeof(int), &txadj, GFP_ATOMIC);
839 if (skb)
840 recv_Bchannel_skb(bch, skb);
841#endif
842
843 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
844 unit = ch % 4;
845
846 printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n",
847 taps, timeslot);
848
849 vpm_out(hc, unit, timeslot, 0x7e);
850}
851
5b834354 852static void
af69fb3a
KK		 853vpm_echocan_off(struct hfc_multi *hc, int ch)
854{
855 unsigned int timeslot;
856 unsigned int unit;
857 struct bchannel *bch = hc->chan[ch].bch;
858#ifdef TXADJ
859 int txadj = 0;
860 struct sk_buff *skb;
861#endif
862
863 if (hc->chan[ch].protocol != ISDN_P_B_RAW)
864 return;
865
866 if (!bch)
867 return;
868
869#ifdef TXADJ
870 skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX,
871 sizeof(int), &txadj, GFP_ATOMIC);
872 if (skb)
873 recv_Bchannel_skb(bch, skb);
874#endif
875
876 timeslot = ((ch/4)*8) + ((ch%4)*4) + 1;
877 unit = ch % 4;
878
879 printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n",
880 timeslot);
881 /* FILLME */
882 vpm_out(hc, unit, timeslot, 0x01);
883}
884
885
886/*
887 * Speech Design resync feature
888 * NOTE: This is called sometimes outside interrupt handler.
889 * We must lock irqsave, so no other interrupt (other card) will occurr!
890 * Also multiple interrupts may nest, so must lock each access (lists, card)!
891 */
892static inline void
893hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm)
894{
bcf91745 895 struct hfc_multi *hc, *next, *pcmmaster = NULL;
c31655fc
HE		 896 void __iomem *plx_acc_32;
897 u_int pv;
af69fb3a
KK		 898 u_long flags;
899
900 spin_lock_irqsave(&HFClock, flags);
901 spin_lock(&plx_lock); /* must be locked inside other locks */
902
903 if (debug & DEBUG_HFCMULTI_PLXSD)
904 printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n",
905 __func__, syncmaster);
906
907 /* select new master */
908 if (newmaster) {
909 if (debug & DEBUG_HFCMULTI_PLXSD)
910 printk(KERN_DEBUG "using provided controller\n");
911 } else {
912 list_for_each_entry_safe(hc, next, &HFClist, list) {
913 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
914 if (hc->syncronized) {
915 newmaster = hc;
916 break;
917 }
918 }
919 }
920 }
921
922 /* Disable sync of all cards */
923 list_for_each_entry_safe(hc, next, &HFClist, list) {
924 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
c31655fc 925 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 926 pv = readl(plx_acc_32);
927 pv &= ~PLX_SYNC_O_EN;
928 writel(pv, plx_acc_32);
929 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
930 pcmmaster = hc;
931 if (hc->type == 1) {
932 if (debug & DEBUG_HFCMULTI_PLXSD)
933 printk(KERN_DEBUG
934 "Schedule SYNC_I\n");
935 hc->e1_resync |= 1; /* get SYNC_I */
936 }
937 }
938 }
939 }
940
941 if (newmaster) {
942 hc = newmaster;
943 if (debug & DEBUG_HFCMULTI_PLXSD)
944 printk(KERN_DEBUG "id=%d (0x%p) = syncronized with "
945 "interface.\n", hc->id, hc);
946 /* Enable new sync master */
c31655fc 947 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 948 pv = readl(plx_acc_32);
949 pv |= PLX_SYNC_O_EN;
950 writel(pv, plx_acc_32);
951 /* switch to jatt PLL, if not disabled by RX_SYNC */
952 if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) {
953 if (debug & DEBUG_HFCMULTI_PLXSD)
954 printk(KERN_DEBUG "Schedule jatt PLL\n");
955 hc->e1_resync |= 2; /* switch to jatt */
956 }
957 } else {
958 if (pcmmaster) {
959 hc = pcmmaster;
960 if (debug & DEBUG_HFCMULTI_PLXSD)
961 printk(KERN_DEBUG
962 "id=%d (0x%p) = PCM master syncronized "
963 "with QUARTZ\n", hc->id, hc);
964 if (hc->type == 1) {
965 /* Use the crystal clock for the PCM
966 master card */
967 if (debug & DEBUG_HFCMULTI_PLXSD)
968 printk(KERN_DEBUG
969 "Schedule QUARTZ for HFC-E1\n");
970 hc->e1_resync |= 4; /* switch quartz */
971 } else {
972 if (debug & DEBUG_HFCMULTI_PLXSD)
973 printk(KERN_DEBUG
974 "QUARTZ is automatically "
975 "enabled by HFC-%dS\n", hc->type);
976 }
c31655fc 977 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 978 pv = readl(plx_acc_32);
979 pv |= PLX_SYNC_O_EN;
980 writel(pv, plx_acc_32);
981 } else
982 if (!rm)
983 printk(KERN_ERR "%s no pcm master, this MUST "
984 "not happen!\n", __func__);
985 }
986 syncmaster = newmaster;
987
988 spin_unlock(&plx_lock);
989 spin_unlock_irqrestore(&HFClock, flags);
990}
991
992/* This must be called AND hc must be locked irqsave!!! */
993inline void
994plxsd_checksync(struct hfc_multi *hc, int rm)
995{
996 if (hc->syncronized) {
997 if (syncmaster == NULL) {
998 if (debug & DEBUG_HFCMULTI_PLXSD)
999 printk(KERN_WARNING "%s: GOT sync on card %d"
1000 " (id=%d)\n", __func__, hc->id + 1,
1001 hc->id);
1002 hfcmulti_resync(hc, hc, rm);
1003 }
1004 } else {
1005 if (syncmaster == hc) {
1006 if (debug & DEBUG_HFCMULTI_PLXSD)
1007 printk(KERN_WARNING "%s: LOST sync on card %d"
1008 " (id=%d)\n", __func__, hc->id + 1,
1009 hc->id);
1010 hfcmulti_resync(hc, NULL, rm);
1011 }
1012 }
1013}
1014
1015
1016/*
1017 * free hardware resources used by driver
1018 */
1019static void
1020release_io_hfcmulti(struct hfc_multi *hc)
1021{
c31655fc
HE		 1022 void __iomem *plx_acc_32;
1023 u_int pv;
af69fb3a
KK		 1024 u_long plx_flags;
1025
1026 if (debug & DEBUG_HFCMULTI_INIT)
1027 printk(KERN_DEBUG "%s: entered\n", __func__);
1028
1029 /* soft reset also masks all interrupts */
1030 hc->hw.r_cirm |= V_SRES;
1031 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1032 udelay(1000);
1033 hc->hw.r_cirm &= ~V_SRES;
1034 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1035 udelay(1000); /* instead of 'wait' that may cause locking */
1036
1037 /* release Speech Design card, if PLX was initialized */
1038 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) {
1039 if (debug & DEBUG_HFCMULTI_PLXSD)
1040 printk(KERN_DEBUG "%s: release PLXSD card %d\n",
1041 __func__, hc->id + 1);
1042 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1043 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1044 writel(PLX_GPIOC_INIT, plx_acc_32);
1045 pv = readl(plx_acc_32);
1046 /* Termination off */
1047 pv &= ~PLX_TERM_ON;
1048 /* Disconnect the PCM */
1049 pv |= PLX_SLAVE_EN_N;
1050 pv &= ~PLX_MASTER_EN;
1051 pv &= ~PLX_SYNC_O_EN;
1052 /* Put the DSP in Reset */
1053 pv &= ~PLX_DSP_RES_N;
1054 writel(pv, plx_acc_32);
1055 if (debug & DEBUG_HFCMULTI_INIT)
1056 printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n",
1057 __func__, pv);
1058 spin_unlock_irqrestore(&plx_lock, plx_flags);
1059 }
1060
1061 /* disable memory mapped ports / io ports */
1062 test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */
1063 pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0);
1064 if (hc->pci_membase)
c31655fc 1065 iounmap(hc->pci_membase);
af69fb3a 1066 if (hc->plx_membase)
c31655fc 1067 iounmap(hc->plx_membase);
af69fb3a
KK		 1068 if (hc->pci_iobase)
1069 release_region(hc->pci_iobase, 8);
1070
1071 if (hc->pci_dev) {
1072 pci_disable_device(hc->pci_dev);
1073 pci_set_drvdata(hc->pci_dev, NULL);
1074 }
1075 if (debug & DEBUG_HFCMULTI_INIT)
1076 printk(KERN_DEBUG "%s: done\n", __func__);
1077}
1078
1079/*
1080 * function called to reset the HFC chip. A complete software reset of chip
1081 * and fifos is done. All configuration of the chip is done.
1082 */
1083
1084static int
1085init_chip(struct hfc_multi *hc)
1086{
1087 u_long flags, val, val2 = 0, rev;
1088 int i, err = 0;
1089 u_char r_conf_en, rval;
c31655fc
HE		 1090 void __iomem *plx_acc_32;
1091 u_int pv;
af69fb3a
KK		 1092 u_long plx_flags, hfc_flags;
1093 int plx_count;
1094 struct hfc_multi *pos, *next, *plx_last_hc;
1095
1096 spin_lock_irqsave(&hc->lock, flags);
1097 /* reset all registers */
1098 memset(&hc->hw, 0, sizeof(struct hfcm_hw));
1099
1100 /* revision check */
1101 if (debug & DEBUG_HFCMULTI_INIT)
1102 printk(KERN_DEBUG "%s: entered\n", __func__);
1103 val = HFC_inb(hc, R_CHIP_ID)>>4;
1104 if (val != 0x8 && val != 0xc && val != 0xe) {
1105 printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val);
1106 err = -EIO;
1107 goto out;
1108 }
1109 rev = HFC_inb(hc, R_CHIP_RV);
1110 printk(KERN_INFO
1111 "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n",
1112 val, rev, (rev == 0) ? " (old FIFO handling)" : "");
1113 if (rev == 0) {
1114 test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip);
1115 printk(KERN_WARNING
1116 "HFC_multi: NOTE: Your chip is revision 0, "
1117 "ask Cologne Chip for update. Newer chips "
1118 "have a better FIFO handling. Old chips "
1119 "still work but may have slightly lower "
1120 "HDLC transmit performance.\n");
1121 }
1122 if (rev > 1) {
1123 printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't "
1124 "consider chip revision = %ld. The chip / "
1125 "bridge may not work.\n", rev);
1126 }
1127
1128 /* set s-ram size */
1129 hc->Flen = 0x10;
1130 hc->Zmin = 0x80;
1131 hc->Zlen = 384;
1132 hc->DTMFbase = 0x1000;
1133 if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) {
1134 if (debug & DEBUG_HFCMULTI_INIT)
1135 printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n",
1136 __func__);
1137 hc->hw.r_ctrl |= V_EXT_RAM;
1138 hc->hw.r_ram_sz = 1;
1139 hc->Flen = 0x20;
1140 hc->Zmin = 0xc0;
1141 hc->Zlen = 1856;
1142 hc->DTMFbase = 0x2000;
1143 }
1144 if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) {
1145 if (debug & DEBUG_HFCMULTI_INIT)
1146 printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n",
1147 __func__);
1148 hc->hw.r_ctrl |= V_EXT_RAM;
1149 hc->hw.r_ram_sz = 2;
1150 hc->Flen = 0x20;
1151 hc->Zmin = 0xc0;
1152 hc->Zlen = 8000;
1153 hc->DTMFbase = 0x2000;
1154 }
1155 hc->max_trans = poll << 1;
1156 if (hc->max_trans > hc->Zlen)
1157 hc->max_trans = hc->Zlen;
1158
1159 /* Speech Design PLX bridge */
1160 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1161 if (debug & DEBUG_HFCMULTI_PLXSD)
1162 printk(KERN_DEBUG "%s: initializing PLXSD card %d\n",
1163 __func__, hc->id + 1);
1164 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1165 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1166 writel(PLX_GPIOC_INIT, plx_acc_32);
1167 pv = readl(plx_acc_32);
1168 /* The first and the last cards are terminating the PCM bus */
1169 pv |= PLX_TERM_ON; /* hc is currently the last */
1170 /* Disconnect the PCM */
1171 pv |= PLX_SLAVE_EN_N;
1172 pv &= ~PLX_MASTER_EN;
1173 pv &= ~PLX_SYNC_O_EN;
1174 /* Put the DSP in Reset */
1175 pv &= ~PLX_DSP_RES_N;
1176 writel(pv, plx_acc_32);
1177 spin_unlock_irqrestore(&plx_lock, plx_flags);
1178 if (debug & DEBUG_HFCMULTI_INIT)
1179 printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n",
1180 __func__, pv);
1181 /*
1182 * If we are the 3rd PLXSD card or higher, we must turn
1183 * termination of last PLXSD card off.
1184 */
1185 spin_lock_irqsave(&HFClock, hfc_flags);
1186 plx_count = 0;
1187 plx_last_hc = NULL;
1188 list_for_each_entry_safe(pos, next, &HFClist, list) {
1189 if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) {
1190 plx_count++;
1191 if (pos != hc)
1192 plx_last_hc = pos;
1193 }
1194 }
1195 if (plx_count >= 3) {
1196 if (debug & DEBUG_HFCMULTI_PLXSD)
1197 printk(KERN_DEBUG "%s: card %d is between, so "
1198 "we disable termination\n",
1199 __func__, plx_last_hc->id + 1);
1200 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1201 plx_acc_32 = plx_last_hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1202 pv = readl(plx_acc_32);
1203 pv &= ~PLX_TERM_ON;
1204 writel(pv, plx_acc_32);
1205 spin_unlock_irqrestore(&plx_lock, plx_flags);
1206 if (debug & DEBUG_HFCMULTI_INIT)
1207 printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n",
1208 __func__, pv);
1209 }
1210 spin_unlock_irqrestore(&HFClock, hfc_flags);
1211 hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */
1212 }
1213
1214 /* we only want the real Z2 read-pointer for revision > 0 */
1215 if (!test_bit(HFC_CHIP_REVISION0, &hc->chip))
1216 hc->hw.r_ram_sz |= V_FZ_MD;
1217
1218 /* select pcm mode */
1219 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1220 if (debug & DEBUG_HFCMULTI_INIT)
1221 printk(KERN_DEBUG "%s: setting PCM into slave mode\n",
1222 __func__);
1223 } else
1224 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) {
1225 if (debug & DEBUG_HFCMULTI_INIT)
1226 printk(KERN_DEBUG "%s: setting PCM into master mode\n",
1227 __func__);
1228 hc->hw.r_pcm_md0 |= V_PCM_MD;
1229 } else {
1230 if (debug & DEBUG_HFCMULTI_INIT)
1231 printk(KERN_DEBUG "%s: performing PCM auto detect\n",
1232 __func__);
1233 }
1234
1235 /* soft reset */
1236 HFC_outb(hc, R_CTRL, hc->hw.r_ctrl);
1237 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1238 HFC_outb(hc, R_FIFO_MD, 0);
1239 hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR;
1240 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1241 udelay(100);
1242 hc->hw.r_cirm = 0;
1243 HFC_outb(hc, R_CIRM, hc->hw.r_cirm);
1244 udelay(100);
1245 HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz);
1246
1247 /* Speech Design PLX bridge pcm and sync mode */
1248 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1249 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1250 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1251 pv = readl(plx_acc_32);
1252 /* Connect PCM */
1253 if (hc->hw.r_pcm_md0 & V_PCM_MD) {
1254 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1255 pv |= PLX_SYNC_O_EN;
1256 if (debug & DEBUG_HFCMULTI_INIT)
1257 printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n",
1258 __func__, pv);
1259 } else {
1260 pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N);
1261 pv &= ~PLX_SYNC_O_EN;
1262 if (debug & DEBUG_HFCMULTI_INIT)
1263 printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n",
1264 __func__, pv);
1265 }
1266 writel(pv, plx_acc_32);
1267 spin_unlock_irqrestore(&plx_lock, plx_flags);
1268 }
1269
1270 /* PCM setup */
1271 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90);
1272 if (hc->slots == 32)
1273 HFC_outb(hc, R_PCM_MD1, 0x00);
1274 if (hc->slots == 64)
1275 HFC_outb(hc, R_PCM_MD1, 0x10);
1276 if (hc->slots == 128)
1277 HFC_outb(hc, R_PCM_MD1, 0x20);
1278 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0);
1279 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
1280 HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */
1281 else
1282 HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */
1283 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1284 for (i = 0; i < 256; i++) {
1285 HFC_outb_nodebug(hc, R_SLOT, i);
1286 HFC_outb_nodebug(hc, A_SL_CFG, 0);
1287 HFC_outb_nodebug(hc, A_CONF, 0);
1288 hc->slot_owner[i] = -1;
1289 }
1290
1291 /* set clock speed */
1292 if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) {
1293 if (debug & DEBUG_HFCMULTI_INIT)
1294 printk(KERN_DEBUG
1295 "%s: setting double clock\n", __func__);
1296 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1297 }
1298
1299 /* B410P GPIO */
1300 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1301 printk(KERN_NOTICE "Setting GPIOs\n");
1302 HFC_outb(hc, R_GPIO_SEL, 0x30);
1303 HFC_outb(hc, R_GPIO_EN1, 0x3);
1304 udelay(1000);
1305 printk(KERN_NOTICE "calling vpm_init\n");
1306 vpm_init(hc);
1307 }
1308
1309 /* check if R_F0_CNT counts (8 kHz frame count) */
1310 val = HFC_inb(hc, R_F0_CNTL);
1311 val += HFC_inb(hc, R_F0_CNTH) << 8;
1312 if (debug & DEBUG_HFCMULTI_INIT)
1313 printk(KERN_DEBUG
1314 "HFC_multi F0_CNT %ld after reset\n", val);
1315 spin_unlock_irqrestore(&hc->lock, flags);
1316 set_current_state(TASK_UNINTERRUPTIBLE);
1317 schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */
1318 spin_lock_irqsave(&hc->lock, flags);
1319 val2 = HFC_inb(hc, R_F0_CNTL);
1320 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1321 if (debug & DEBUG_HFCMULTI_INIT)
1322 printk(KERN_DEBUG
1323 "HFC_multi F0_CNT %ld after 10 ms (1st try)\n",
1324 val2);
1325 if (val2 >= val+8) { /* 1 ms */
1326 /* it counts, so we keep the pcm mode */
1327 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1328 printk(KERN_INFO "controller is PCM bus MASTER\n");
1329 else
1330 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip))
1331 printk(KERN_INFO "controller is PCM bus SLAVE\n");
1332 else {
1333 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
1334 printk(KERN_INFO "controller is PCM bus SLAVE "
1335 "(auto detected)\n");
1336 }
1337 } else {
1338 /* does not count */
1339 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) {
1340controller_fail:
1341 printk(KERN_ERR "HFC_multi ERROR, getting no 125us "
1342 "pulse. Seems that controller fails.\n");
1343 err = -EIO;
1344 goto out;
1345 }
1346 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
1347 printk(KERN_INFO "controller is PCM bus SLAVE "
1348 "(ignoring missing PCM clock)\n");
1349 } else {
1350 /* only one pcm master */
1351 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
1352 && plxsd_master) {
1353 printk(KERN_ERR "HFC_multi ERROR, no clock "
1354 "on another Speech Design card found. "
1355 "Please be sure to connect PCM cable.\n");
1356 err = -EIO;
1357 goto out;
1358 }
1359 /* retry with master clock */
1360 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1361 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1362 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1363 pv = readl(plx_acc_32);
1364 pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N;
1365 pv |= PLX_SYNC_O_EN;
1366 writel(pv, plx_acc_32);
1367 spin_unlock_irqrestore(&plx_lock, plx_flags);
1368 if (debug & DEBUG_HFCMULTI_INIT)
1369 printk(KERN_WARNING "%s: master: PLX_GPIO"
1370 "=%x\n", __func__, pv);
1371 }
1372 hc->hw.r_pcm_md0 |= V_PCM_MD;
1373 HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00);
1374 spin_unlock_irqrestore(&hc->lock, flags);
1375 set_current_state(TASK_UNINTERRUPTIBLE);
1376 schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */
1377 spin_lock_irqsave(&hc->lock, flags);
1378 val2 = HFC_inb(hc, R_F0_CNTL);
1379 val2 += HFC_inb(hc, R_F0_CNTH) << 8;
1380 if (debug & DEBUG_HFCMULTI_INIT)
1381 printk(KERN_DEBUG "HFC_multi F0_CNT %ld after "
1382 "10 ms (2nd try)\n", val2);
1383 if (val2 >= val+8) { /* 1 ms */
1384 test_and_set_bit(HFC_CHIP_PCM_MASTER,
1385 &hc->chip);
1386 printk(KERN_INFO "controller is PCM bus MASTER "
1387 "(auto detected)\n");
1388 } else
1389 goto controller_fail;
1390 }
1391 }
1392
1393 /* Release the DSP Reset */
1394 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1395 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip))
1396 plxsd_master = 1;
1397 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 1398 plx_acc_32 = hc->plx_membase + PLX_GPIOC;
af69fb3a
KK		 1399 pv = readl(plx_acc_32);
1400 pv |= PLX_DSP_RES_N;
1401 writel(pv, plx_acc_32);
1402 spin_unlock_irqrestore(&plx_lock, plx_flags);
1403 if (debug & DEBUG_HFCMULTI_INIT)
1404 printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n",
1405 __func__, pv);
1406 }
1407
1408 /* pcm id */
1409 if (hc->pcm)
1410 printk(KERN_INFO "controller has given PCM BUS ID %d\n",
1411 hc->pcm);
1412 else {
1413 if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)
1414 || test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
1415 PCM_cnt++; /* SD has proprietary bridging */
1416 }
1417 hc->pcm = PCM_cnt;
1418 printk(KERN_INFO "controller has PCM BUS ID %d "
1419 "(auto selected)\n", hc->pcm);
1420 }
1421
1422 /* set up timer */
1423 HFC_outb(hc, R_TI_WD, poll_timer);
1424 hc->hw.r_irqmsk_misc |= V_TI_IRQMSK;
1425
af69fb3a
KK		 1426 /* set E1 state machine IRQ */
1427 if (hc->type == 1)
1428 hc->hw.r_irqmsk_misc |= V_STA_IRQMSK;
1429
1430 /* set DTMF detection */
1431 if (test_bit(HFC_CHIP_DTMF, &hc->chip)) {
1432 if (debug & DEBUG_HFCMULTI_INIT)
1433 printk(KERN_DEBUG "%s: enabling DTMF detection "
1434 "for all B-channel\n", __func__);
1435 hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP;
1436 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1437 hc->hw.r_dtmf |= V_ULAW_SEL;
1438 HFC_outb(hc, R_DTMF_N, 102 - 1);
1439 hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK;
1440 }
1441
1442 /* conference engine */
1443 if (test_bit(HFC_CHIP_ULAW, &hc->chip))
1444 r_conf_en = V_CONF_EN | V_ULAW;
1445 else
1446 r_conf_en = V_CONF_EN;
1447 HFC_outb(hc, R_CONF_EN, r_conf_en);
1448
1449 /* setting leds */
1450 switch (hc->leds) {
1451 case 1: /* HFC-E1 OEM */
1452 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
1453 HFC_outb(hc, R_GPIO_SEL, 0x32);
1454 else
1455 HFC_outb(hc, R_GPIO_SEL, 0x30);
1456
1457 HFC_outb(hc, R_GPIO_EN1, 0x0f);
1458 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1459
1460 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1461 break;
1462
1463 case 2: /* HFC-4S OEM */
1464 case 3:
1465 HFC_outb(hc, R_GPIO_SEL, 0xf0);
1466 HFC_outb(hc, R_GPIO_EN1, 0xff);
1467 HFC_outb(hc, R_GPIO_OUT1, 0x00);
1468 break;
1469 }
1470
1471 /* set master clock */
1472 if (hc->masterclk >= 0) {
1473 if (debug & DEBUG_HFCMULTI_INIT)
1474 printk(KERN_DEBUG "%s: setting ST master clock "
1475 "to port %d (0..%d)\n",
1476 __func__, hc->masterclk, hc->ports-1);
1477 hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC;
1478 HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync);
1479 }
1480
1481 /* setting misc irq */
1482 HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc);
1483 if (debug & DEBUG_HFCMULTI_INIT)
1484 printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n",
1485 hc->hw.r_irqmsk_misc);
1486
1487 /* RAM access test */
1488 HFC_outb(hc, R_RAM_ADDR0, 0);
1489 HFC_outb(hc, R_RAM_ADDR1, 0);
1490 HFC_outb(hc, R_RAM_ADDR2, 0);
1491 for (i = 0; i < 256; i++) {
1492 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1493 HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff));
1494 }
1495 for (i = 0; i < 256; i++) {
1496 HFC_outb_nodebug(hc, R_RAM_ADDR0, i);
1497 HFC_inb_nodebug(hc, R_RAM_DATA);
1498 rval = HFC_inb_nodebug(hc, R_INT_DATA);
1499 if (rval != ((i * 3) & 0xff)) {
1500 printk(KERN_DEBUG
1501 "addr:%x val:%x should:%x\n", i, rval,
1502 (i * 3) & 0xff);
1503 err++;
1504 }
1505 }
1506 if (err) {
1507 printk(KERN_DEBUG "aborting - %d RAM access errors\n", err);
1508 err = -EIO;
1509 goto out;
1510 }
1511
1512 if (debug & DEBUG_HFCMULTI_INIT)
1513 printk(KERN_DEBUG "%s: done\n", __func__);
1514out:
1515 spin_unlock_irqrestore(&hc->lock, flags);
1516 return err;
1517}
1518
1519
1520/*
1521 * control the watchdog
1522 */
1523static void
1524hfcmulti_watchdog(struct hfc_multi *hc)
1525{
1526 hc->wdcount++;
1527
1528 if (hc->wdcount > 10) {
1529 hc->wdcount = 0;
1530 hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ?
1531 V_GPIO_OUT3 : V_GPIO_OUT2;
1532
1533 /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */
1534 HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3);
1535 HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte);
1536 }
1537}
1538
1539
1540
1541/*
1542 * output leds
1543 */
1544static void
1545hfcmulti_leds(struct hfc_multi *hc)
1546{
1547 unsigned long lled;
1548 unsigned long leddw;
1549 int i, state, active, leds;
1550 struct dchannel *dch;
1551 int led[4];
1552
1553 hc->ledcount += poll;
1554 if (hc->ledcount > 4096) {
1555 hc->ledcount -= 4096;
1556 hc->ledstate = 0xAFFEAFFE;
1557 }
1558
1559 switch (hc->leds) {
1560 case 1: /* HFC-E1 OEM */
1561 /* 2 red blinking: NT mode deactivate
1562 * 2 red steady: TE mode deactivate
1563 * left green: L1 active
1564 * left red: frame sync, but no L1
1565 * right green: L2 active
1566 */
1567 if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */
1568 if (hc->chan[hc->dslot].dch->dev.D.protocol
1569 != ISDN_P_NT_E1) {
1570 led[0] = 1;
1571 led[1] = 1;
1572 } else if (hc->ledcount>>11) {
1573 led[0] = 1;
1574 led[1] = 1;
1575 } else {
1576 led[0] = 0;
1577 led[1] = 0;
1578 }
1579 led[2] = 0;
1580 led[3] = 0;
1581 } else { /* with frame sync */
1582 /* TODO make it work */
1583 led[0] = 0;
1584 led[1] = 0;
1585 led[2] = 0;
1586 led[3] = 1;
1587 }
1588 leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF;
1589 /* leds are inverted */
1590 if (leds != (int)hc->ledstate) {
1591 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds);
1592 hc->ledstate = leds;
1593 }
1594 break;
1595
1596 case 2: /* HFC-4S OEM */
1597 /* red blinking = PH_DEACTIVATE NT Mode
1598 * red steady = PH_DEACTIVATE TE Mode
1599 * green steady = PH_ACTIVATE
1600 */
1601 for (i = 0; i < 4; i++) {
1602 state = 0;
1603 active = -1;
1604 dch = hc->chan[(i << 2) | 2].dch;
1605 if (dch) {
1606 state = dch->state;
1607 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1608 active = 3;
1609 else
1610 active = 7;
1611 }
1612 if (state) {
1613 if (state == active) {
1614 led[i] = 1; /* led green */
1615 } else
1616 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1617 /* TE mode: led red */
1618 led[i] = 2;
1619 else
1620 if (hc->ledcount>>11)
1621 /* led red */
1622 led[i] = 2;
1623 else
1624 /* led off */
1625 led[i] = 0;
1626 } else
1627 led[i] = 0; /* led off */
1628 }
1629 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
1630 leds = 0;
1631 for (i = 0; i < 4; i++) {
1632 if (led[i] == 1) {
1633 /*green*/
1634 leds |= (0x2 << (i * 2));
1635 } else if (led[i] == 2) {
1636 /*red*/
1637 leds |= (0x1 << (i * 2));
1638 }
1639 }
1640 if (leds != (int)hc->ledstate) {
1641 vpm_out(hc, 0, 0x1a8 + 3, leds);
1642 hc->ledstate = leds;
1643 }
1644 } else {
1645 leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) |
1646 ((led[0] > 0) << 2) | ((led[2] > 0) << 3) |
1647 ((led[3] & 1) << 4) | ((led[1] & 1) << 5) |
1648 ((led[0] & 1) << 6) | ((led[2] & 1) << 7);
1649 if (leds != (int)hc->ledstate) {
1650 HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F);
1651 HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4);
1652 hc->ledstate = leds;
1653 }
1654 }
1655 break;
1656
1657 case 3: /* HFC 1S/2S Beronet */
1658 /* red blinking = PH_DEACTIVATE NT Mode
1659 * red steady = PH_DEACTIVATE TE Mode
1660 * green steady = PH_ACTIVATE
1661 */
1662 for (i = 0; i < 2; i++) {
1663 state = 0;
1664 active = -1;
1665 dch = hc->chan[(i << 2) | 2].dch;
1666 if (dch) {
1667 state = dch->state;
1668 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1669 active = 3;
1670 else
1671 active = 7;
1672 }
1673 if (state) {
1674 if (state == active) {
1675 led[i] = 1; /* led green */
1676 } else
1677 if (dch->dev.D.protocol == ISDN_P_TE_S0)
1678 /* TE mode: led red */
1679 led[i] = 2;
1680 else
1681 if (hc->ledcount >> 11)
1682 /* led red */
1683 led[i] = 2;
1684 else
1685 /* led off */
1686 led[i] = 0;
1687 } else
1688 led[i] = 0; /* led off */
1689 }
1690
1691
1692 leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2)
1693 | ((led[1]&1)<<3);
1694 if (leds != (int)hc->ledstate) {
1695 HFC_outb_nodebug(hc, R_GPIO_EN1,
1696 ((led[0] > 0) << 2) | ((led[1] > 0) << 3));
1697 HFC_outb_nodebug(hc, R_GPIO_OUT1,
1698 ((led[0] & 1) << 2) | ((led[1] & 1) << 3));
1699 hc->ledstate = leds;
1700 }
1701 break;
1702 case 8: /* HFC 8S+ Beronet */
1703 lled = 0;
1704
1705 for (i = 0; i < 8; i++) {
1706 state = 0;
1707 active = -1;
1708 dch = hc->chan[(i << 2) | 2].dch;
1709 if (dch) {
1710 state = dch->state;
1711 if (dch->dev.D.protocol == ISDN_P_NT_S0)
1712 active = 3;
1713 else
1714 active = 7;
1715 }
1716 if (state) {
1717 if (state == active) {
1718 lled |= 0 << i;
1719 } else
1720 if (hc->ledcount >> 11)
1721 lled |= 0 << i;
1722 else
1723 lled |= 1 << i;
1724 } else
1725 lled |= 1 << i;
1726 }
1727 leddw = lled << 24 | lled << 16 | lled << 8 | lled;
1728 if (leddw != hc->ledstate) {
1729 /* HFC_outb(hc, R_BRG_PCM_CFG, 1);
1730 HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */
1731 /* was _io before */
1732 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
1733 outw(0x4000, hc->pci_iobase + 4);
1734 outl(leddw, hc->pci_iobase);
1735 HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK);
1736 hc->ledstate = leddw;
1737 }
1738 break;
1739 }
1740}
1741/*
1742 * read dtmf coefficients
1743 */
1744
1745static void
1746hfcmulti_dtmf(struct hfc_multi *hc)
1747{
1748 s32 *coeff;
1749 u_int mantissa;
1750 int co, ch;
1751 struct bchannel *bch = NULL;
1752 u8 exponent;
1753 int dtmf = 0;
1754 int addr;
1755 u16 w_float;
1756 struct sk_buff *skb;
1757 struct mISDNhead *hh;
1758
1759 if (debug & DEBUG_HFCMULTI_DTMF)
1760 printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__);
1761 for (ch = 0; ch <= 31; ch++) {
1762 /* only process enabled B-channels */
1763 bch = hc->chan[ch].bch;
1764 if (!bch)
1765 continue;
1766 if (!hc->created[hc->chan[ch].port])
1767 continue;
1768 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1769 continue;
1770 if (debug & DEBUG_HFCMULTI_DTMF)
1771 printk(KERN_DEBUG "%s: dtmf channel %d:",
1772 __func__, ch);
1773 coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]);
1774 dtmf = 1;
1775 for (co = 0; co < 8; co++) {
1776 /* read W(n-1) coefficient */
1777 addr = hc->DTMFbase + ((co<<7) | (ch<<2));
1778 HFC_outb_nodebug(hc, R_RAM_ADDR0, addr);
1779 HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8);
1780 HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16)
1781 | V_ADDR_INC);
1782 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1783 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1784 if (debug & DEBUG_HFCMULTI_DTMF)
1785 printk(" %04x", w_float);
1786
1787 /* decode float (see chip doc) */
1788 mantissa = w_float & 0x0fff;
1789 if (w_float & 0x8000)
1790 mantissa |= 0xfffff000;
1791 exponent = (w_float>>12) & 0x7;
1792 if (exponent) {
1793 mantissa ^= 0x1000;
1794 mantissa <<= (exponent-1);
1795 }
1796
1797 /* store coefficient */
1798 coeff[co<<1] = mantissa;
1799
1800 /* read W(n) coefficient */
1801 w_float = HFC_inb_nodebug(hc, R_RAM_DATA);
1802 w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8);
1803 if (debug & DEBUG_HFCMULTI_DTMF)
1804 printk(" %04x", w_float);
1805
1806 /* decode float (see chip doc) */
1807 mantissa = w_float & 0x0fff;
1808 if (w_float & 0x8000)
1809 mantissa |= 0xfffff000;
1810 exponent = (w_float>>12) & 0x7;
1811 if (exponent) {
1812 mantissa ^= 0x1000;
1813 mantissa <<= (exponent-1);
1814 }
1815
1816 /* store coefficient */
1817 coeff[(co<<1)|1] = mantissa;
1818 }
1819 if (debug & DEBUG_HFCMULTI_DTMF)
b5df5a5c
AE		 1820 printk(" DTMF ready %08x %08x %08x %08x "
1821 "%08x %08x %08x %08x\n",
af69fb3a
KK		 1822 coeff[0], coeff[1], coeff[2], coeff[3],
1823 coeff[4], coeff[5], coeff[6], coeff[7]);
1824 hc->chan[ch].coeff_count++;
1825 if (hc->chan[ch].coeff_count == 8) {
1826 hc->chan[ch].coeff_count = 0;
1827 skb = mI_alloc_skb(512, GFP_ATOMIC);
1828 if (!skb) {
1829 printk(KERN_WARNING "%s: No memory for skb\n",
1830 __func__);
1831 continue;
1832 }
1833 hh = mISDN_HEAD_P(skb);
1834 hh->prim = PH_CONTROL_IND;
1835 hh->id = DTMF_HFC_COEF;
1836 memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512);
1837 recv_Bchannel_skb(bch, skb);
1838 }
1839 }
1840
1841 /* restart DTMF processing */
1842 hc->dtmf = dtmf;
1843 if (dtmf)
1844 HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF);
1845}
1846
1847
1848/*
1849 * fill fifo as much as possible
1850 */
1851
1852static void
1853hfcmulti_tx(struct hfc_multi *hc, int ch)
1854{
1855 int i, ii, temp, len = 0;
1856 int Zspace, z1, z2; /* must be int for calculation */
1857 int Fspace, f1, f2;
1858 u_char *d;
1859 int *txpending, slot_tx;
1860 struct bchannel *bch;
1861 struct dchannel *dch;
1862 struct sk_buff **sp = NULL;
1863 int *idxp;
1864
1865 bch = hc->chan[ch].bch;
1866 dch = hc->chan[ch].dch;
1867 if ((!dch) && (!bch))
1868 return;
1869
1870 txpending = &hc->chan[ch].txpending;
1871 slot_tx = hc->chan[ch].slot_tx;
1872 if (dch) {
1873 if (!test_bit(FLG_ACTIVE, &dch->Flags))
1874 return;
1875 sp = &dch->tx_skb;
1876 idxp = &dch->tx_idx;
1877 } else {
1878 if (!test_bit(FLG_ACTIVE, &bch->Flags))
1879 return;
1880 sp = &bch->tx_skb;
1881 idxp = &bch->tx_idx;
1882 }
1883 if (*sp)
1884 len = (*sp)->len;
1885
1886 if ((!len) && *txpending != 1)
1887 return; /* no data */
1888
1889 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
1890 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
1891 (hc->chan[ch].slot_rx < 0) &&
1892 (hc->chan[ch].slot_tx < 0))
1893 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1));
1894 else
1895 HFC_outb_nodebug(hc, R_FIFO, ch << 1);
1896 HFC_wait_nodebug(hc);
1897
1898 if (*txpending == 2) {
1899 /* reset fifo */
1900 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
1901 HFC_wait_nodebug(hc);
1902 HFC_outb(hc, A_SUBCH_CFG, 0);
1903 *txpending = 1;
1904 }
1905next_frame:
1906 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
1907 f1 = HFC_inb_nodebug(hc, A_F1);
1908 f2 = HFC_inb_nodebug(hc, A_F2);
1909 while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) {
1910 if (debug & DEBUG_HFCMULTI_FIFO)
1911 printk(KERN_DEBUG
1912 "%s(card %d): reread f2 because %d!=%d\n",
1913 __func__, hc->id + 1, temp, f2);
1914 f2 = temp; /* repeat until F2 is equal */
1915 }
1916 Fspace = f2 - f1 - 1;
1917 if (Fspace < 0)
1918 Fspace += hc->Flen;
1919 /*
1920 * Old FIFO handling doesn't give us the current Z2 read
1921 * pointer, so we cannot send the next frame before the fifo
1922 * is empty. It makes no difference except for a slightly
1923 * lower performance.
1924 */
1925 if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) {
1926 if (f1 != f2)
1927 Fspace = 0;
1928 else
1929 Fspace = 1;
1930 }
1931 /* one frame only for ST D-channels, to allow resending */
1932 if (hc->type != 1 && dch) {
1933 if (f1 != f2)
1934 Fspace = 0;
1935 }
1936 /* F-counter full condition */
1937 if (Fspace == 0)
1938 return;
1939 }
1940 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
1941 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
1942 while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) {
1943 if (debug & DEBUG_HFCMULTI_FIFO)
1944 printk(KERN_DEBUG "%s(card %d): reread z2 because "
1945 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
1946 z2 = temp; /* repeat unti Z2 is equal */
1947 }
7cfa153d
AE		 1948 hc->chan[ch].Zfill = z1 - z2;
1949 if (hc->chan[ch].Zfill < 0)
1950 hc->chan[ch].Zfill += hc->Zlen;
af69fb3a
KK		 1951 Zspace = z2 - z1;
1952 if (Zspace <= 0)
1953 Zspace += hc->Zlen;
1954 Zspace -= 4; /* keep not too full, so pointers will not overrun */
1955 /* fill transparent data only to maxinum transparent load (minus 4) */
1956 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
1957 Zspace = Zspace - hc->Zlen + hc->max_trans;
1958 if (Zspace <= 0) /* no space of 4 bytes */
1959 return;
1960
1961 /* if no data */
1962 if (!len) {
1963 if (z1 == z2) { /* empty */
1964 /* if done with FIFO audio data during PCM connection */
1965 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) &&
1966 *txpending && slot_tx >= 0) {
1967 if (debug & DEBUG_HFCMULTI_MODE)
1968 printk(KERN_DEBUG
1969 "%s: reconnecting PCM due to no "
1970 "more FIFO data: channel %d "
1971 "slot_tx %d\n",
1972 __func__, ch, slot_tx);
1973 /* connect slot */
1974 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1975 V_HDLC_TRP | V_IFF);
1976 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
1977 HFC_wait_nodebug(hc);
1978 HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 |
1979 V_HDLC_TRP | V_IFF);
1980 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
1981 HFC_wait_nodebug(hc);
1982 }
1983 *txpending = 0;
1984 }
1985 return; /* no data */
1986 }
1987
8dd2f36f
AE		 1988 /* "fill fifo if empty" feature */
1989 if (bch && test_bit(FLG_FILLEMPTY, &bch->Flags)
1990 && !test_bit(FLG_HDLC, &bch->Flags) && z2 == z1) {
1991 if (debug & DEBUG_HFCMULTI_FILL)
1992 printk(KERN_DEBUG "%s: buffer empty, so we have "
1993 "underrun\n", __func__);
1994 /* fill buffer, to prevent future underrun */
1995 hc->write_fifo(hc, hc->silence_data, poll >> 1);
1996 Zspace -= (poll >> 1);
1997 }
1998
af69fb3a
KK		 1999 /* if audio data and connected slot */
2000 if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending)
2001 && slot_tx >= 0) {
2002 if (debug & DEBUG_HFCMULTI_MODE)
2003 printk(KERN_DEBUG "%s: disconnecting PCM due to "
2004 "FIFO data: channel %d slot_tx %d\n",
2005 __func__, ch, slot_tx);
2006 /* disconnect slot */
2007 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2008 HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1);
2009 HFC_wait_nodebug(hc);
2010 HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF);
2011 HFC_outb_nodebug(hc, R_FIFO, ch<<1);
2012 HFC_wait_nodebug(hc);
2013 }
2014 *txpending = 1;
2015
2016 /* show activity */
2017 hc->activity[hc->chan[ch].port] = 1;
2018
2019 /* fill fifo to what we have left */
2020 ii = len;
2021 if (dch || test_bit(FLG_HDLC, &bch->Flags))
2022 temp = 1;
2023 else
2024 temp = 0;
2025 i = *idxp;
2026 d = (*sp)->data + i;
2027 if (ii - i > Zspace)
2028 ii = Zspace + i;
2029 if (debug & DEBUG_HFCMULTI_FIFO)
2030 printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space "
2031 "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n",
2032 __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i,
2033 temp ? "HDLC":"TRANS");
2034
af69fb3a
KK		 2035 /* Have to prep the audio data */
2036 hc->write_fifo(hc, d, ii - i);
7cfa153d 2037 hc->chan[ch].Zfill += ii - i;
af69fb3a
KK		 2038 *idxp = ii;
2039
2040 /* if not all data has been written */
2041 if (ii != len) {
2042 /* NOTE: fifo is started by the calling function */
2043 return;
2044 }
2045
2046 /* if all data has been written, terminate frame */
2047 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2048 /* increment f-counter */
2049 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2050 HFC_wait_nodebug(hc);
2051 }
2052
2053 /* send confirm, since get_net_bframe will not do it with trans */
2054 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
2055 confirm_Bsend(bch);
2056
2057 /* check for next frame */
2058 dev_kfree_skb(*sp);
2059 if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */
2060 len = (*sp)->len;
2061 goto next_frame;
2062 }
2063 if (dch && get_next_dframe(dch)) {
2064 len = (*sp)->len;
2065 goto next_frame;
2066 }
2067
2068 /*
2069 * now we have no more data, so in case of transparent,
2070 * we set the last byte in fifo to 'silence' in case we will get
2071 * no more data at all. this prevents sending an undefined value.
2072 */
2073 if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags))
8dd2f36f 2074 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
af69fb3a
KK		 2075}
2076
2077
2078/* NOTE: only called if E1 card is in active state */
2079static void
2080hfcmulti_rx(struct hfc_multi *hc, int ch)
2081{
2082 int temp;
2083 int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */
2084 int f1 = 0, f2 = 0; /* = 0, to make GCC happy */
2085 int again = 0;
2086 struct bchannel *bch;
2087 struct dchannel *dch;
2088 struct sk_buff *skb, **sp = NULL;
2089 int maxlen;
2090
2091 bch = hc->chan[ch].bch;
2092 dch = hc->chan[ch].dch;
2093 if ((!dch) && (!bch))
2094 return;
2095 if (dch) {
2096 if (!test_bit(FLG_ACTIVE, &dch->Flags))
2097 return;
2098 sp = &dch->rx_skb;
2099 maxlen = dch->maxlen;
2100 } else {
2101 if (!test_bit(FLG_ACTIVE, &bch->Flags))
2102 return;
2103 sp = &bch->rx_skb;
2104 maxlen = bch->maxlen;
2105 }
2106next_frame:
2107 /* on first AND before getting next valid frame, R_FIFO must be written
2108 to. */
2109 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2110 (hc->chan[ch].protocol == ISDN_P_B_RAW) &&
2111 (hc->chan[ch].slot_rx < 0) &&
2112 (hc->chan[ch].slot_tx < 0))
2113 HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1);
2114 else
2115 HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1);
2116 HFC_wait_nodebug(hc);
2117
2118 /* ignore if rx is off BUT change fifo (above) to start pending TX */
2119 if (hc->chan[ch].rx_off)
2120 return;
2121
2122 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2123 f1 = HFC_inb_nodebug(hc, A_F1);
2124 while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) {
2125 if (debug & DEBUG_HFCMULTI_FIFO)
2126 printk(KERN_DEBUG
2127 "%s(card %d): reread f1 because %d!=%d\n",
2128 __func__, hc->id + 1, temp, f1);
2129 f1 = temp; /* repeat until F1 is equal */
2130 }
2131 f2 = HFC_inb_nodebug(hc, A_F2);
2132 }
2133 z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin;
2134 while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) {
2135 if (debug & DEBUG_HFCMULTI_FIFO)
2136 printk(KERN_DEBUG "%s(card %d): reread z2 because "
2137 "%d!=%d\n", __func__, hc->id + 1, temp, z2);
2138 z1 = temp; /* repeat until Z1 is equal */
2139 }
2140 z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin;
2141 Zsize = z1 - z2;
2142 if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2)
2143 /* complete hdlc frame */
2144 Zsize++;
2145 if (Zsize < 0)
2146 Zsize += hc->Zlen;
2147 /* if buffer is empty */
2148 if (Zsize <= 0)
2149 return;
2150
2151 if (*sp == NULL) {
2152 *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC);
2153 if (*sp == NULL) {
2154 printk(KERN_DEBUG "%s: No mem for rx_skb\n",
2155 __func__);
2156 return;
2157 }
2158 }
2159 /* show activity */
2160 hc->activity[hc->chan[ch].port] = 1;
2161
2162 /* empty fifo with what we have */
2163 if (dch || test_bit(FLG_HDLC, &bch->Flags)) {
2164 if (debug & DEBUG_HFCMULTI_FIFO)
2165 printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d "
2166 "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) "
2167 "got=%d (again %d)\n", __func__, hc->id + 1, ch,
2168 Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE",
2169 f1, f2, Zsize + (*sp)->len, again);
2170 /* HDLC */
2171 if ((Zsize + (*sp)->len) > (maxlen + 3)) {
2172 if (debug & DEBUG_HFCMULTI_FIFO)
2173 printk(KERN_DEBUG
2174 "%s(card %d): hdlc-frame too large.\n",
2175 __func__, hc->id + 1);
2176 skb_trim(*sp, 0);
2177 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
2178 HFC_wait_nodebug(hc);
2179 return;
2180 }
2181
2182 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2183
2184 if (f1 != f2) {
2185 /* increment Z2,F2-counter */
2186 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F);
2187 HFC_wait_nodebug(hc);
2188 /* check size */
2189 if ((*sp)->len < 4) {
2190 if (debug & DEBUG_HFCMULTI_FIFO)
2191 printk(KERN_DEBUG
2192 "%s(card %d): Frame below minimum "
2193 "size\n", __func__, hc->id + 1);
2194 skb_trim(*sp, 0);
2195 goto next_frame;
2196 }
2197 /* there is at least one complete frame, check crc */
2198 if ((*sp)->data[(*sp)->len - 1]) {
2199 if (debug & DEBUG_HFCMULTI_CRC)
2200 printk(KERN_DEBUG
2201 "%s: CRC-error\n", __func__);
2202 skb_trim(*sp, 0);
2203 goto next_frame;
2204 }
2205 skb_trim(*sp, (*sp)->len - 3);
2206 if ((*sp)->len < MISDN_COPY_SIZE) {
2207 skb = *sp;
2208 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2209 if (*sp) {
2210 memcpy(skb_put(*sp, skb->len),
2211 skb->data, skb->len);
2212 skb_trim(skb, 0);
2213 } else {
2214 printk(KERN_DEBUG "%s: No mem\n",
2215 __func__);
2216 *sp = skb;
2217 skb = NULL;
2218 }
2219 } else {
2220 skb = NULL;
2221 }
2222 if (debug & DEBUG_HFCMULTI_FIFO) {
2223 printk(KERN_DEBUG "%s(card %d):",
2224 __func__, hc->id + 1);
2225 temp = 0;
2226 while (temp < (*sp)->len)
2227 printk(" %02x", (*sp)->data[temp++]);
2228 printk("\n");
2229 }
2230 if (dch)
2231 recv_Dchannel(dch);
2232 else
7cfa153d 2233 recv_Bchannel(bch, MISDN_ID_ANY);
af69fb3a
KK		 2234 *sp = skb;
2235 again++;
2236 goto next_frame;
2237 }
2238 /* there is an incomplete frame */
2239 } else {
2240 /* transparent */
2241 if (Zsize > skb_tailroom(*sp))
2242 Zsize = skb_tailroom(*sp);
2243 hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize);
2244 if (((*sp)->len) < MISDN_COPY_SIZE) {
2245 skb = *sp;
2246 *sp = mI_alloc_skb(skb->len, GFP_ATOMIC);
2247 if (*sp) {
2248 memcpy(skb_put(*sp, skb->len),
2249 skb->data, skb->len);
2250 skb_trim(skb, 0);
2251 } else {
2252 printk(KERN_DEBUG "%s: No mem\n", __func__);
2253 *sp = skb;
2254 skb = NULL;
2255 }
2256 } else {
2257 skb = NULL;
2258 }
2259 if (debug & DEBUG_HFCMULTI_FIFO)
2260 printk(KERN_DEBUG
2261 "%s(card %d): fifo(%d) reading %d bytes "
2262 "(z1=%04x, z2=%04x) TRANS\n",
2263 __func__, hc->id + 1, ch, Zsize, z1, z2);
2264 /* only bch is transparent */
7cfa153d 2265 recv_Bchannel(bch, hc->chan[ch].Zfill);
af69fb3a
KK		 2266 *sp = skb;
2267 }
2268}
2269
2270
2271/*
2272 * Interrupt handler
2273 */
2274static void
2275signal_state_up(struct dchannel *dch, int info, char *msg)
2276{
2277 struct sk_buff *skb;
2278 int id, data = info;
2279
2280 if (debug & DEBUG_HFCMULTI_STATE)
2281 printk(KERN_DEBUG "%s: %s\n", __func__, msg);
2282
2283 id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */
2284
2285 skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data,
2286 GFP_ATOMIC);
2287 if (!skb)
2288 return;
2289 recv_Dchannel_skb(dch, skb);
2290}
2291
2292static inline void
2293handle_timer_irq(struct hfc_multi *hc)
2294{
2295 int ch, temp;
2296 struct dchannel *dch;
2297 u_long flags;
2298
2299 /* process queued resync jobs */
2300 if (hc->e1_resync) {
2301 /* lock, so e1_resync gets not changed */
2302 spin_lock_irqsave(&HFClock, flags);
2303 if (hc->e1_resync & 1) {
2304 if (debug & DEBUG_HFCMULTI_PLXSD)
2305 printk(KERN_DEBUG "Enable SYNC_I\n");
2306 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC);
2307 /* disable JATT, if RX_SYNC is set */
2308 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
2309 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
2310 }
2311 if (hc->e1_resync & 2) {
2312 if (debug & DEBUG_HFCMULTI_PLXSD)
2313 printk(KERN_DEBUG "Enable jatt PLL\n");
2314 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
2315 }
2316 if (hc->e1_resync & 4) {
2317 if (debug & DEBUG_HFCMULTI_PLXSD)
2318 printk(KERN_DEBUG
2319 "Enable QUARTZ for HFC-E1\n");
2320 /* set jatt to quartz */
2321 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC
2322 | V_JATT_OFF);
2323 /* switch to JATT, in case it is not already */
2324 HFC_outb(hc, R_SYNC_OUT, 0);
2325 }
2326 hc->e1_resync = 0;
2327 spin_unlock_irqrestore(&HFClock, flags);
2328 }
2329
2330 if (hc->type != 1 || hc->e1_state == 1)
2331 for (ch = 0; ch <= 31; ch++) {
2332 if (hc->created[hc->chan[ch].port]) {
2333 hfcmulti_tx(hc, ch);
2334 /* fifo is started when switching to rx-fifo */
2335 hfcmulti_rx(hc, ch);
2336 if (hc->chan[ch].dch &&
2337 hc->chan[ch].nt_timer > -1) {
2338 dch = hc->chan[ch].dch;
2339 if (!(--hc->chan[ch].nt_timer)) {
2340 schedule_event(dch,
2341 FLG_PHCHANGE);
2342 if (debug &
2343 DEBUG_HFCMULTI_STATE)
2344 printk(KERN_DEBUG
2345 "%s: nt_timer at "
2346 "state %x\n",
2347 __func__,
2348 dch->state);
2349 }
2350 }
2351 }
2352 }
2353 if (hc->type == 1 && hc->created[0]) {
2354 dch = hc->chan[hc->dslot].dch;
2355 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
2356 /* LOS */
2357 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS;
2358 if (!temp && hc->chan[hc->dslot].los)
2359 signal_state_up(dch, L1_SIGNAL_LOS_ON,
2360 "LOS detected");
2361 if (temp && !hc->chan[hc->dslot].los)
2362 signal_state_up(dch, L1_SIGNAL_LOS_OFF,
2363 "LOS gone");
2364 hc->chan[hc->dslot].los = temp;
2365 }
2366 if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) {
2367 /* AIS */
2368 temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS;
2369 if (!temp && hc->chan[hc->dslot].ais)
2370 signal_state_up(dch, L1_SIGNAL_AIS_ON,
2371 "AIS detected");
2372 if (temp && !hc->chan[hc->dslot].ais)
2373 signal_state_up(dch, L1_SIGNAL_AIS_OFF,
2374 "AIS gone");
2375 hc->chan[hc->dslot].ais = temp;
2376 }
2377 if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) {
2378 /* SLIP */
2379 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX;
2380 if (!temp && hc->chan[hc->dslot].slip_rx)
2381 signal_state_up(dch, L1_SIGNAL_SLIP_RX,
2382 " bit SLIP detected RX");
2383 hc->chan[hc->dslot].slip_rx = temp;
2384 temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX;
2385 if (!temp && hc->chan[hc->dslot].slip_tx)
2386 signal_state_up(dch, L1_SIGNAL_SLIP_TX,
2387 " bit SLIP detected TX");
2388 hc->chan[hc->dslot].slip_tx = temp;
2389 }
2390 if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) {
2391 /* RDI */
2392 temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A;
2393 if (!temp && hc->chan[hc->dslot].rdi)
2394 signal_state_up(dch, L1_SIGNAL_RDI_ON,
2395 "RDI detected");
2396 if (temp && !hc->chan[hc->dslot].rdi)
2397 signal_state_up(dch, L1_SIGNAL_RDI_OFF,
2398 "RDI gone");
2399 hc->chan[hc->dslot].rdi = temp;
2400 }
2401 temp = HFC_inb_nodebug(hc, R_JATT_DIR);
2402 switch (hc->chan[hc->dslot].sync) {
2403 case 0:
2404 if ((temp & 0x60) == 0x60) {
2405 if (debug & DEBUG_HFCMULTI_SYNC)
2406 printk(KERN_DEBUG
2407 "%s: (id=%d) E1 now "
2408 "in clock sync\n",
2409 __func__, hc->id);
2410 HFC_outb(hc, R_RX_OFF,
2411 hc->chan[hc->dslot].jitter | V_RX_INIT);
2412 HFC_outb(hc, R_TX_OFF,
2413 hc->chan[hc->dslot].jitter | V_RX_INIT);
2414 hc->chan[hc->dslot].sync = 1;
2415 goto check_framesync;
2416 }
2417 break;
2418 case 1:
2419 if ((temp & 0x60) != 0x60) {
2420 if (debug & DEBUG_HFCMULTI_SYNC)
2421 printk(KERN_DEBUG
2422 "%s: (id=%d) E1 "
2423 "lost clock sync\n",
2424 __func__, hc->id);
2425 hc->chan[hc->dslot].sync = 0;
2426 break;
2427 }
2428check_framesync:
2429 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2430 if (temp == 0x27) {
2431 if (debug & DEBUG_HFCMULTI_SYNC)
2432 printk(KERN_DEBUG
2433 "%s: (id=%d) E1 "
2434 "now in frame sync\n",
2435 __func__, hc->id);
2436 hc->chan[hc->dslot].sync = 2;
2437 }
2438 break;
2439 case 2:
2440 if ((temp & 0x60) != 0x60) {
2441 if (debug & DEBUG_HFCMULTI_SYNC)
2442 printk(KERN_DEBUG
2443 "%s: (id=%d) E1 lost "
2444 "clock & frame sync\n",
2445 __func__, hc->id);
2446 hc->chan[hc->dslot].sync = 0;
2447 break;
2448 }
2449 temp = HFC_inb_nodebug(hc, R_SYNC_STA);
2450 if (temp != 0x27) {
2451 if (debug & DEBUG_HFCMULTI_SYNC)
2452 printk(KERN_DEBUG
2453 "%s: (id=%d) E1 "
2454 "lost frame sync\n",
2455 __func__, hc->id);
2456 hc->chan[hc->dslot].sync = 1;
2457 }
2458 break;
2459 }
2460 }
2461
2462 if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip))
2463 hfcmulti_watchdog(hc);
2464
2465 if (hc->leds)
2466 hfcmulti_leds(hc);
2467}
2468
2469static void
2470ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech)
2471{
2472 struct dchannel *dch;
2473 int ch;
2474 int active;
2475 u_char st_status, temp;
2476
2477 /* state machine */
2478 for (ch = 0; ch <= 31; ch++) {
2479 if (hc->chan[ch].dch) {
2480 dch = hc->chan[ch].dch;
2481 if (r_irq_statech & 1) {
2482 HFC_outb_nodebug(hc, R_ST_SEL,
2483 hc->chan[ch].port);
2484 /* undocumented: delay after R_ST_SEL */
2485 udelay(1);
2486 /* undocumented: status changes during read */
2487 st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE);
2488 while (st_status != (temp =
2489 HFC_inb_nodebug(hc, A_ST_RD_STATE))) {
2490 if (debug & DEBUG_HFCMULTI_STATE)
2491 printk(KERN_DEBUG "%s: reread "
2492 "STATE because %d!=%d\n",
2493 __func__, temp,
2494 st_status);
2495 st_status = temp; /* repeat */
2496 }
2497
2498 /* Speech Design TE-sync indication */
2499 if (test_bit(HFC_CHIP_PLXSD, &hc->chip) &&
2500 dch->dev.D.protocol == ISDN_P_TE_S0) {
2501 if (st_status & V_FR_SYNC_ST)
2502 hc->syncronized |=
2503 (1 << hc->chan[ch].port);
2504 else
2505 hc->syncronized &=
2506 ~(1 << hc->chan[ch].port);
2507 }
2508 dch->state = st_status & 0x0f;
2509 if (dch->dev.D.protocol == ISDN_P_NT_S0)
2510 active = 3;
2511 else
2512 active = 7;
2513 if (dch->state == active) {
2514 HFC_outb_nodebug(hc, R_FIFO,
2515 (ch << 1) | 1);
2516 HFC_wait_nodebug(hc);
2517 HFC_outb_nodebug(hc,
2518 R_INC_RES_FIFO, V_RES_F);
2519 HFC_wait_nodebug(hc);
2520 dch->tx_idx = 0;
2521 }
2522 schedule_event(dch, FLG_PHCHANGE);
2523 if (debug & DEBUG_HFCMULTI_STATE)
2524 printk(KERN_DEBUG
2525 "%s: S/T newstate %x port %d\n",
2526 __func__, dch->state,
2527 hc->chan[ch].port);
2528 }
2529 r_irq_statech >>= 1;
2530 }
2531 }
2532 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2533 plxsd_checksync(hc, 0);
2534}
2535
2536static void
2537fifo_irq(struct hfc_multi *hc, int block)
2538{
2539 int ch, j;
2540 struct dchannel *dch;
2541 struct bchannel *bch;
2542 u_char r_irq_fifo_bl;
2543
2544 r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block);
2545 j = 0;
2546 while (j < 8) {
2547 ch = (block << 2) + (j >> 1);
2548 dch = hc->chan[ch].dch;
2549 bch = hc->chan[ch].bch;
2550 if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) {
2551 j += 2;
2552 continue;
2553 }
2554 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2555 test_bit(FLG_ACTIVE, &dch->Flags)) {
2556 hfcmulti_tx(hc, ch);
2557 /* start fifo */
2558 HFC_outb_nodebug(hc, R_FIFO, 0);
2559 HFC_wait_nodebug(hc);
2560 }
2561 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2562 test_bit(FLG_ACTIVE, &bch->Flags)) {
2563 hfcmulti_tx(hc, ch);
2564 /* start fifo */
2565 HFC_outb_nodebug(hc, R_FIFO, 0);
2566 HFC_wait_nodebug(hc);
2567 }
2568 j++;
2569 if (dch && (r_irq_fifo_bl & (1 << j)) &&
2570 test_bit(FLG_ACTIVE, &dch->Flags)) {
2571 hfcmulti_rx(hc, ch);
2572 }
2573 if (bch && (r_irq_fifo_bl & (1 << j)) &&
2574 test_bit(FLG_ACTIVE, &bch->Flags)) {
2575 hfcmulti_rx(hc, ch);
2576 }
2577 j++;
2578 }
2579}
2580
2581#ifdef IRQ_DEBUG
2582int irqsem;
2583#endif
2584static irqreturn_t
2585hfcmulti_interrupt(int intno, void *dev_id)
2586{
2587#ifdef IRQCOUNT_DEBUG
2588 static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0,
2589 iq5 = 0, iq6 = 0, iqcnt = 0;
2590#endif
af69fb3a
KK		 2591 struct hfc_multi *hc = dev_id;
2592 struct dchannel *dch;
2593 u_char r_irq_statech, status, r_irq_misc, r_irq_oview;
2594 int i;
c31655fc
HE		 2595 void __iomem *plx_acc;
2596 u_short wval;
af69fb3a
KK		 2597 u_char e1_syncsta, temp;
2598 u_long flags;
2599
2600 if (!hc) {
2601 printk(KERN_ERR "HFC-multi: Spurious interrupt!\n");
2602 return IRQ_NONE;
2603 }
2604
2605 spin_lock(&hc->lock);
2606
2607#ifdef IRQ_DEBUG
2608 if (irqsem)
2609 printk(KERN_ERR "irq for card %d during irq from "
2610 "card %d, this is no bug.\n", hc->id + 1, irqsem);
2611 irqsem = hc->id + 1;
2612#endif
2613
2614 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
2615 spin_lock_irqsave(&plx_lock, flags);
c31655fc 2616 plx_acc = hc->plx_membase + PLX_INTCSR;
af69fb3a
KK		 2617 wval = readw(plx_acc);
2618 spin_unlock_irqrestore(&plx_lock, flags);
2619 if (!(wval & PLX_INTCSR_LINTI1_STATUS))
2620 goto irq_notforus;
2621 }
2622
2623 status = HFC_inb_nodebug(hc, R_STATUS);
2624 r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH);
2625#ifdef IRQCOUNT_DEBUG
2626 if (r_irq_statech)
2627 iq1++;
2628 if (status & V_DTMF_STA)
2629 iq2++;
2630 if (status & V_LOST_STA)
2631 iq3++;
2632 if (status & V_EXT_IRQSTA)
2633 iq4++;
2634 if (status & V_MISC_IRQSTA)
2635 iq5++;
2636 if (status & V_FR_IRQSTA)
2637 iq6++;
2638 if (iqcnt++ > 5000) {
2639 printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n",
2640 iq1, iq2, iq3, iq4, iq5, iq6);
2641 iqcnt = 0;
2642 }
2643#endif
3bd69ad1 2644
af69fb3a
KK		 2645 if (!r_irq_statech &&
2646 !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA |
2647 V_MISC_IRQSTA | V_FR_IRQSTA))) {
2648 /* irq is not for us */
2649 goto irq_notforus;
2650 }
2651 hc->irqcnt++;
2652 if (r_irq_statech) {
2653 if (hc->type != 1)
2654 ph_state_irq(hc, r_irq_statech);
2655 }
2656 if (status & V_EXT_IRQSTA)
2657 ; /* external IRQ */
2658 if (status & V_LOST_STA) {
2659 /* LOST IRQ */
2660 HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */
2661 }
2662 if (status & V_MISC_IRQSTA) {
2663 /* misc IRQ */
2664 r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC);
9e6115f2 2665 r_irq_misc &= hc->hw.r_irqmsk_misc; /* ignore disabled irqs */
af69fb3a
KK		 2666 if (r_irq_misc & V_STA_IRQ) {
2667 if (hc->type == 1) {
2668 /* state machine */
2669 dch = hc->chan[hc->dslot].dch;
2670 e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA);
2671 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)
2672 && hc->e1_getclock) {
2673 if (e1_syncsta & V_FR_SYNC_E1)
2674 hc->syncronized = 1;
2675 else
2676 hc->syncronized = 0;
2677 }
2678 /* undocumented: status changes during read */
2679 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA);
2680 while (dch->state != (temp =
2681 HFC_inb_nodebug(hc, R_E1_RD_STA))) {
2682 if (debug & DEBUG_HFCMULTI_STATE)
2683 printk(KERN_DEBUG "%s: reread "
2684 "STATE because %d!=%d\n",
2685 __func__, temp,
2686 dch->state);
2687 dch->state = temp; /* repeat */
2688 }
2689 dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA)
2690 & 0x7;
2691 schedule_event(dch, FLG_PHCHANGE);
2692 if (debug & DEBUG_HFCMULTI_STATE)
2693 printk(KERN_DEBUG
2694 "%s: E1 (id=%d) newstate %x\n",
2695 __func__, hc->id, dch->state);
2696 if (test_bit(HFC_CHIP_PLXSD, &hc->chip))
2697 plxsd_checksync(hc, 0);
2698 }
2699 }
3bd69ad1
AE		 2700 if (r_irq_misc & V_TI_IRQ) {
2701 if (hc->iclock_on)
2702 mISDN_clock_update(hc->iclock, poll, NULL);
af69fb3a 2703 handle_timer_irq(hc);
3bd69ad1 2704 }
af69fb3a
KK		 2705
2706 if (r_irq_misc & V_DTMF_IRQ) {
af69fb3a
KK		 2707 hfcmulti_dtmf(hc);
2708 }
af69fb3a 2709 if (r_irq_misc & V_IRQ_PROC) {
69e656cc
KK		 2710 static int irq_proc_cnt;
2711 if (!irq_proc_cnt++)
2712 printk(KERN_WARNING "%s: got V_IRQ_PROC -"
2713 " this should not happen\n", __func__);
af69fb3a
KK		 2714 }
2715
2716 }
2717 if (status & V_FR_IRQSTA) {
2718 /* FIFO IRQ */
2719 r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW);
2720 for (i = 0; i < 8; i++) {
2721 if (r_irq_oview & (1 << i))
2722 fifo_irq(hc, i);
2723 }
2724 }
2725
2726#ifdef IRQ_DEBUG
2727 irqsem = 0;
2728#endif
2729 spin_unlock(&hc->lock);
2730 return IRQ_HANDLED;
2731
2732irq_notforus:
2733#ifdef IRQ_DEBUG
2734 irqsem = 0;
2735#endif
2736 spin_unlock(&hc->lock);
2737 return IRQ_NONE;
2738}
2739
2740
2741/*
2742 * timer callback for D-chan busy resolution. Currently no function
2743 */
2744
2745static void
2746hfcmulti_dbusy_timer(struct hfc_multi *hc)
2747{
2748}
2749
2750
2751/*
2752 * activate/deactivate hardware for selected channels and mode
2753 *
2754 * configure B-channel with the given protocol
2755 * ch eqals to the HFC-channel (0-31)
2756 * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31
2757 * for S/T, 1-31 for E1)
2758 * the hdlc interrupts will be set/unset
2759 */
2760static int
2761mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx,
2762 int bank_tx, int slot_rx, int bank_rx)
2763{
2764 int flow_tx = 0, flow_rx = 0, routing = 0;
2765 int oslot_tx, oslot_rx;
2766 int conf;
2767
2768 if (ch < 0 || ch > 31)
2769 return EINVAL;
2770 oslot_tx = hc->chan[ch].slot_tx;
2771 oslot_rx = hc->chan[ch].slot_rx;
2772 conf = hc->chan[ch].conf;
2773
2774 if (debug & DEBUG_HFCMULTI_MODE)
2775 printk(KERN_DEBUG
2776 "%s: card %d channel %d protocol %x slot old=%d new=%d "
2777 "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n",
2778 __func__, hc->id, ch, protocol, oslot_tx, slot_tx,
2779 bank_tx, oslot_rx, slot_rx, bank_rx);
2780
2781 if (oslot_tx >= 0 && slot_tx != oslot_tx) {
2782 /* remove from slot */
2783 if (debug & DEBUG_HFCMULTI_MODE)
2784 printk(KERN_DEBUG "%s: remove from slot %d (TX)\n",
2785 __func__, oslot_tx);
2786 if (hc->slot_owner[oslot_tx<<1] == ch) {
2787 HFC_outb(hc, R_SLOT, oslot_tx << 1);
2788 HFC_outb(hc, A_SL_CFG, 0);
2789 HFC_outb(hc, A_CONF, 0);
2790 hc->slot_owner[oslot_tx<<1] = -1;
2791 } else {
2792 if (debug & DEBUG_HFCMULTI_MODE)
2793 printk(KERN_DEBUG
2794 "%s: we are not owner of this tx slot "
2795 "anymore, channel %d is.\n",
2796 __func__, hc->slot_owner[oslot_tx<<1]);
2797 }
2798 }
2799
2800 if (oslot_rx >= 0 && slot_rx != oslot_rx) {
2801 /* remove from slot */
2802 if (debug & DEBUG_HFCMULTI_MODE)
2803 printk(KERN_DEBUG
2804 "%s: remove from slot %d (RX)\n",
2805 __func__, oslot_rx);
2806 if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) {
2807 HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR);
2808 HFC_outb(hc, A_SL_CFG, 0);
2809 hc->slot_owner[(oslot_rx << 1) | 1] = -1;
2810 } else {
2811 if (debug & DEBUG_HFCMULTI_MODE)
2812 printk(KERN_DEBUG
2813 "%s: we are not owner of this rx slot "
2814 "anymore, channel %d is.\n",
2815 __func__,
2816 hc->slot_owner[(oslot_rx << 1) | 1]);
2817 }
2818 }
2819
2820 if (slot_tx < 0) {
2821 flow_tx = 0x80; /* FIFO->ST */
2822 /* disable pcm slot */
2823 hc->chan[ch].slot_tx = -1;
2824 hc->chan[ch].bank_tx = 0;
2825 } else {
2826 /* set pcm slot */
2827 if (hc->chan[ch].txpending)
2828 flow_tx = 0x80; /* FIFO->ST */
2829 else
2830 flow_tx = 0xc0; /* PCM->ST */
2831 /* put on slot */
2832 routing = bank_tx ? 0xc0 : 0x80;
2833 if (conf >= 0 || bank_tx > 1)
2834 routing = 0x40; /* loop */
2835 if (debug & DEBUG_HFCMULTI_MODE)
2836 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2837 " %d flow %02x routing %02x conf %d (TX)\n",
2838 __func__, ch, slot_tx, bank_tx,
2839 flow_tx, routing, conf);
2840 HFC_outb(hc, R_SLOT, slot_tx << 1);
2841 HFC_outb(hc, A_SL_CFG, (ch<<1) | routing);
2842 HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL));
2843 hc->slot_owner[slot_tx << 1] = ch;
2844 hc->chan[ch].slot_tx = slot_tx;
2845 hc->chan[ch].bank_tx = bank_tx;
2846 }
2847 if (slot_rx < 0) {
2848 /* disable pcm slot */
2849 flow_rx = 0x80; /* ST->FIFO */
2850 hc->chan[ch].slot_rx = -1;
2851 hc->chan[ch].bank_rx = 0;
2852 } else {
2853 /* set pcm slot */
2854 if (hc->chan[ch].txpending)
2855 flow_rx = 0x80; /* ST->FIFO */
2856 else
2857 flow_rx = 0xc0; /* ST->(FIFO,PCM) */
2858 /* put on slot */
2859 routing = bank_rx?0x80:0xc0; /* reversed */
2860 if (conf >= 0 || bank_rx > 1)
2861 routing = 0x40; /* loop */
2862 if (debug & DEBUG_HFCMULTI_MODE)
2863 printk(KERN_DEBUG "%s: put channel %d to slot %d bank"
2864 " %d flow %02x routing %02x conf %d (RX)\n",
2865 __func__, ch, slot_rx, bank_rx,
2866 flow_rx, routing, conf);
2867 HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR);
2868 HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing);
2869 hc->slot_owner[(slot_rx<<1)|1] = ch;
2870 hc->chan[ch].slot_rx = slot_rx;
2871 hc->chan[ch].bank_rx = bank_rx;
2872 }
2873
2874 switch (protocol) {
2875 case (ISDN_P_NONE):
2876 /* disable TX fifo */
2877 HFC_outb(hc, R_FIFO, ch << 1);
2878 HFC_wait(hc);
2879 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF);
2880 HFC_outb(hc, A_SUBCH_CFG, 0);
2881 HFC_outb(hc, A_IRQ_MSK, 0);
2882 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2883 HFC_wait(hc);
2884 /* disable RX fifo */
2885 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2886 HFC_wait(hc);
2887 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00);
2888 HFC_outb(hc, A_SUBCH_CFG, 0);
2889 HFC_outb(hc, A_IRQ_MSK, 0);
2890 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2891 HFC_wait(hc);
2892 if (hc->chan[ch].bch && hc->type != 1) {
2893 hc->hw.a_st_ctrl0[hc->chan[ch].port] &=
2894 ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN;
2895 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2896 /* undocumented: delay after R_ST_SEL */
2897 udelay(1);
2898 HFC_outb(hc, A_ST_CTRL0,
2899 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2900 }
2901 if (hc->chan[ch].bch) {
2902 test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
2903 test_and_clear_bit(FLG_TRANSPARENT,
2904 &hc->chan[ch].bch->Flags);
2905 }
2906 break;
2907 case (ISDN_P_B_RAW): /* B-channel */
2908
2909 if (test_bit(HFC_CHIP_B410P, &hc->chip) &&
2910 (hc->chan[ch].slot_rx < 0) &&
2911 (hc->chan[ch].slot_tx < 0)) {
2912
2913 printk(KERN_DEBUG
2914 "Setting B-channel %d to echo cancelable "
2915 "state on PCM slot %d\n", ch,
2916 ((ch / 4) * 8) + ((ch % 4) * 4) + 1);
2917 printk(KERN_DEBUG
2918 "Enabling pass through for channel\n");
2919 vpm_out(hc, ch, ((ch / 4) * 8) +
2920 ((ch % 4) * 4) + 1, 0x01);
2921 /* rx path */
2922 /* S/T -> PCM */
2923 HFC_outb(hc, R_FIFO, (ch << 1));
2924 HFC_wait(hc);
2925 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2926 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2927 ((ch % 4) * 4) + 1) << 1);
2928 HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1));
2929
2930 /* PCM -> FIFO */
2931 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1);
2932 HFC_wait(hc);
2933 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2934 HFC_outb(hc, A_SUBCH_CFG, 0);
2935 HFC_outb(hc, A_IRQ_MSK, 0);
2936 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2937 HFC_wait(hc);
2938 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2939 ((ch % 4) * 4) + 1) << 1) | 1);
2940 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1);
2941
2942 /* tx path */
2943 /* PCM -> S/T */
2944 HFC_outb(hc, R_FIFO, (ch << 1) | 1);
2945 HFC_wait(hc);
2946 HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF);
2947 HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) +
2948 ((ch % 4) * 4)) << 1) | 1);
2949 HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1);
2950
2951 /* FIFO -> PCM */
2952 HFC_outb(hc, R_FIFO, 0x20 | (ch << 1));
2953 HFC_wait(hc);
2954 HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF);
2955 HFC_outb(hc, A_SUBCH_CFG, 0);
2956 HFC_outb(hc, A_IRQ_MSK, 0);
2957 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2958 HFC_wait(hc);
2959 /* tx silence */
8dd2f36f 2960 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
af69fb3a
KK		 2961 HFC_outb(hc, R_SLOT, (((ch / 4) * 8) +
2962 ((ch % 4) * 4)) << 1);
2963 HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1));
2964 } else {
2965 /* enable TX fifo */
2966 HFC_outb(hc, R_FIFO, ch << 1);
2967 HFC_wait(hc);
2968 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 |
2969 V_HDLC_TRP | V_IFF);
2970 HFC_outb(hc, A_SUBCH_CFG, 0);
2971 HFC_outb(hc, A_IRQ_MSK, 0);
2972 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2973 HFC_wait(hc);
2974 /* tx silence */
8dd2f36f 2975 HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, hc->silence);
af69fb3a
KK		 2976 /* enable RX fifo */
2977 HFC_outb(hc, R_FIFO, (ch<<1)|1);
2978 HFC_wait(hc);
2979 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP);
2980 HFC_outb(hc, A_SUBCH_CFG, 0);
2981 HFC_outb(hc, A_IRQ_MSK, 0);
2982 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
2983 HFC_wait(hc);
2984 }
2985 if (hc->type != 1) {
2986 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
2987 ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN;
2988 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
2989 /* undocumented: delay after R_ST_SEL */
2990 udelay(1);
2991 HFC_outb(hc, A_ST_CTRL0,
2992 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
2993 }
2994 if (hc->chan[ch].bch)
2995 test_and_set_bit(FLG_TRANSPARENT,
2996 &hc->chan[ch].bch->Flags);
2997 break;
2998 case (ISDN_P_B_HDLC): /* B-channel */
2999 case (ISDN_P_TE_S0): /* D-channel */
3000 case (ISDN_P_NT_S0):
3001 case (ISDN_P_TE_E1):
3002 case (ISDN_P_NT_E1):
3003 /* enable TX fifo */
3004 HFC_outb(hc, R_FIFO, ch<<1);
3005 HFC_wait(hc);
3006 if (hc->type == 1 || hc->chan[ch].bch) {
3007 /* E1 or B-channel */
3008 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04);
3009 HFC_outb(hc, A_SUBCH_CFG, 0);
3010 } else {
3011 /* D-Channel without HDLC fill flags */
3012 HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF);
3013 HFC_outb(hc, A_SUBCH_CFG, 2);
3014 }
3015 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3016 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3017 HFC_wait(hc);
3018 /* enable RX fifo */
3019 HFC_outb(hc, R_FIFO, (ch<<1)|1);
3020 HFC_wait(hc);
3021 HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04);
3022 if (hc->type == 1 || hc->chan[ch].bch)
3023 HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */
3024 else
3025 HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */
3026 HFC_outb(hc, A_IRQ_MSK, V_IRQ);
3027 HFC_outb(hc, R_INC_RES_FIFO, V_RES_F);
3028 HFC_wait(hc);
3029 if (hc->chan[ch].bch) {
3030 test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags);
3031 if (hc->type != 1) {
3032 hc->hw.a_st_ctrl0[hc->chan[ch].port] |=
3033 ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN;
3034 HFC_outb(hc, R_ST_SEL, hc->chan[ch].port);
3035 /* undocumented: delay after R_ST_SEL */
3036 udelay(1);
3037 HFC_outb(hc, A_ST_CTRL0,
3038 hc->hw.a_st_ctrl0[hc->chan[ch].port]);
3039 }
3040 }
3041 break;
3042 default:
3043 printk(KERN_DEBUG "%s: protocol not known %x\n",
3044 __func__, protocol);
3045 hc->chan[ch].protocol = ISDN_P_NONE;
3046 return -ENOPROTOOPT;
3047 }
3048 hc->chan[ch].protocol = protocol;
3049 return 0;
3050}
3051
3052
3053/*
3054 * connect/disconnect PCM
3055 */
3056
3057static void
3058hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx,
3059 int slot_rx, int bank_rx)
3060{
3061 if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) {
3062 /* disable PCM */
3063 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0);
3064 return;
3065 }
3066
3067 /* enable pcm */
3068 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx,
3069 slot_rx, bank_rx);
3070}
3071
3072/*
3073 * set/disable conference
3074 */
3075
3076static void
3077hfcmulti_conf(struct hfc_multi *hc, int ch, int num)
3078{
3079 if (num >= 0 && num <= 7)
3080 hc->chan[ch].conf = num;
3081 else
3082 hc->chan[ch].conf = -1;
3083 mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx,
3084 hc->chan[ch].bank_tx, hc->chan[ch].slot_rx,
3085 hc->chan[ch].bank_rx);
3086}
3087
3088
3089/*
3090 * set/disable sample loop
3091 */
3092
3093/* NOTE: this function is experimental and therefore disabled */
3094
3095/*
3096 * Layer 1 callback function
3097 */
3098static int
3099hfcm_l1callback(struct dchannel *dch, u_int cmd)
3100{
3101 struct hfc_multi *hc = dch->hw;
3102 u_long flags;
3103
3104 switch (cmd) {
3105 case INFO3_P8:
3106 case INFO3_P10:
3107 break;
3108 case HW_RESET_REQ:
3109 /* start activation */
3110 spin_lock_irqsave(&hc->lock, flags);
3111 if (hc->type == 1) {
3112 if (debug & DEBUG_HFCMULTI_MSG)
3113 printk(KERN_DEBUG
3114 "%s: HW_RESET_REQ no BRI\n",
3115 __func__);
3116 } else {
3117 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3118 /* undocumented: delay after R_ST_SEL */
3119 udelay(1);
3120 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */
3121 udelay(6); /* wait at least 5,21us */
3122 HFC_outb(hc, A_ST_WR_STATE, 3);
3123 HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3));
3124 /* activate */
3125 }
3126 spin_unlock_irqrestore(&hc->lock, flags);
3127 l1_event(dch->l1, HW_POWERUP_IND);
3128 break;
3129 case HW_DEACT_REQ:
3130 /* start deactivation */
3131 spin_lock_irqsave(&hc->lock, flags);
3132 if (hc->type == 1) {
3133 if (debug & DEBUG_HFCMULTI_MSG)
3134 printk(KERN_DEBUG
3135 "%s: HW_DEACT_REQ no BRI\n",
3136 __func__);
3137 } else {
3138 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3139 /* undocumented: delay after R_ST_SEL */
3140 udelay(1);
3141 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2);
3142 /* deactivate */
3143 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3144 hc->syncronized &=
3145 ~(1 << hc->chan[dch->slot].port);
3146 plxsd_checksync(hc, 0);
3147 }
3148 }
3149 skb_queue_purge(&dch->squeue);
3150 if (dch->tx_skb) {
3151 dev_kfree_skb(dch->tx_skb);
3152 dch->tx_skb = NULL;
3153 }
3154 dch->tx_idx = 0;
3155 if (dch->rx_skb) {
3156 dev_kfree_skb(dch->rx_skb);
3157 dch->rx_skb = NULL;
3158 }
3159 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3160 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3161 del_timer(&dch->timer);
3162 spin_unlock_irqrestore(&hc->lock, flags);
3163 break;
3164 case HW_POWERUP_REQ:
3165 spin_lock_irqsave(&hc->lock, flags);
3166 if (hc->type == 1) {
3167 if (debug & DEBUG_HFCMULTI_MSG)
3168 printk(KERN_DEBUG
3169 "%s: HW_POWERUP_REQ no BRI\n",
3170 __func__);
3171 } else {
3172 HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port);
3173 /* undocumented: delay after R_ST_SEL */
3174 udelay(1);
3175 HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */
3176 udelay(6); /* wait at least 5,21us */
3177 HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */
3178 }
3179 spin_unlock_irqrestore(&hc->lock, flags);
3180 break;
3181 case PH_ACTIVATE_IND:
3182 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3183 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3184 GFP_ATOMIC);
3185 break;
3186 case PH_DEACTIVATE_IND:
3187 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3188 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
3189 GFP_ATOMIC);
3190 break;
3191 default:
3192 if (dch->debug & DEBUG_HW)
3193 printk(KERN_DEBUG "%s: unknown command %x\n",
3194 __func__, cmd);
3195 return -1;
3196 }
3197 return 0;
3198}
3199
3200/*
3201 * Layer2 -> Layer 1 Transfer
3202 */
3203
3204static int
3205handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3206{
3207 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
3208 struct dchannel *dch = container_of(dev, struct dchannel, dev);
3209 struct hfc_multi *hc = dch->hw;
3210 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3211 int ret = -EINVAL;
3212 unsigned int id;
3213 u_long flags;
3214
3215 switch (hh->prim) {
3216 case PH_DATA_REQ:
3217 if (skb->len < 1)
3218 break;
3219 spin_lock_irqsave(&hc->lock, flags);
3220 ret = dchannel_senddata(dch, skb);
3221 if (ret > 0) { /* direct TX */
3222 id = hh->id; /* skb can be freed */
3223 hfcmulti_tx(hc, dch->slot);
3224 ret = 0;
3225 /* start fifo */
3226 HFC_outb(hc, R_FIFO, 0);
3227 HFC_wait(hc);
3228 spin_unlock_irqrestore(&hc->lock, flags);
3229 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3230 } else
3231 spin_unlock_irqrestore(&hc->lock, flags);
3232 return ret;
3233 case PH_ACTIVATE_REQ:
3234 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3235 spin_lock_irqsave(&hc->lock, flags);
3236 ret = 0;
3237 if (debug & DEBUG_HFCMULTI_MSG)
3238 printk(KERN_DEBUG
3239 "%s: PH_ACTIVATE port %d (0..%d)\n",
3240 __func__, hc->chan[dch->slot].port,
3241 hc->ports-1);
3242 /* start activation */
3243 if (hc->type == 1) {
3244 ph_state_change(dch);
3245 if (debug & DEBUG_HFCMULTI_STATE)
3246 printk(KERN_DEBUG
3247 "%s: E1 report state %x \n",
3248 __func__, dch->state);
3249 } else {
3250 HFC_outb(hc, R_ST_SEL,
3251 hc->chan[dch->slot].port);
3252 /* undocumented: delay after R_ST_SEL */
3253 udelay(1);
3254 HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1);
3255 /* G1 */
3256 udelay(6); /* wait at least 5,21us */
3257 HFC_outb(hc, A_ST_WR_STATE, 1);
3258 HFC_outb(hc, A_ST_WR_STATE, 1 |
3259 (V_ST_ACT*3)); /* activate */
3260 dch->state = 1;
3261 }
3262 spin_unlock_irqrestore(&hc->lock, flags);
3263 } else
3264 ret = l1_event(dch->l1, hh->prim);
3265 break;
3266 case PH_DEACTIVATE_REQ:
3267 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
3268 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
3269 spin_lock_irqsave(&hc->lock, flags);
3270 if (debug & DEBUG_HFCMULTI_MSG)
3271 printk(KERN_DEBUG
3272 "%s: PH_DEACTIVATE port %d (0..%d)\n",
3273 __func__, hc->chan[dch->slot].port,
3274 hc->ports-1);
3275 /* start deactivation */
3276 if (hc->type == 1) {
3277 if (debug & DEBUG_HFCMULTI_MSG)
3278 printk(KERN_DEBUG
3279 "%s: PH_DEACTIVATE no BRI\n",
3280 __func__);
3281 } else {
3282 HFC_outb(hc, R_ST_SEL,
3283 hc->chan[dch->slot].port);
3284 /* undocumented: delay after R_ST_SEL */
3285 udelay(1);
3286 HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2);
3287 /* deactivate */
3288 dch->state = 1;
3289 }
3290 skb_queue_purge(&dch->squeue);
3291 if (dch->tx_skb) {
3292 dev_kfree_skb(dch->tx_skb);
3293 dch->tx_skb = NULL;
3294 }
3295 dch->tx_idx = 0;
3296 if (dch->rx_skb) {
3297 dev_kfree_skb(dch->rx_skb);
3298 dch->rx_skb = NULL;
3299 }
3300 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
3301 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
3302 del_timer(&dch->timer);
3303#ifdef FIXME
3304 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
3305 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
3306#endif
3307 ret = 0;
3308 spin_unlock_irqrestore(&hc->lock, flags);
3309 } else
3310 ret = l1_event(dch->l1, hh->prim);
3311 break;
3312 }
3313 if (!ret)
3314 dev_kfree_skb(skb);
3315 return ret;
3316}
3317
3318static void
3319deactivate_bchannel(struct bchannel *bch)
3320{
3321 struct hfc_multi *hc = bch->hw;
3322 u_long flags;
3323
3324 spin_lock_irqsave(&hc->lock, flags);
3325 if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
3326 dev_kfree_skb(bch->next_skb);
3327 bch->next_skb = NULL;
3328 }
3329 if (bch->tx_skb) {
3330 dev_kfree_skb(bch->tx_skb);
3331 bch->tx_skb = NULL;
3332 }
3333 bch->tx_idx = 0;
3334 if (bch->rx_skb) {
3335 dev_kfree_skb(bch->rx_skb);
3336 bch->rx_skb = NULL;
3337 }
3338 hc->chan[bch->slot].coeff_count = 0;
3339 test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
3340 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
3341 hc->chan[bch->slot].rx_off = 0;
3342 hc->chan[bch->slot].conf = -1;
3343 mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0);
3344 spin_unlock_irqrestore(&hc->lock, flags);
3345}
3346
3347static int
3348handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb)
3349{
3350 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3351 struct hfc_multi *hc = bch->hw;
3352 int ret = -EINVAL;
3353 struct mISDNhead *hh = mISDN_HEAD_P(skb);
3354 unsigned int id;
3355 u_long flags;
3356
3357 switch (hh->prim) {
3358 case PH_DATA_REQ:
3359 if (!skb->len)
3360 break;
3361 spin_lock_irqsave(&hc->lock, flags);
3362 ret = bchannel_senddata(bch, skb);
3363 if (ret > 0) { /* direct TX */
3364 id = hh->id; /* skb can be freed */
3365 hfcmulti_tx(hc, bch->slot);
3366 ret = 0;
3367 /* start fifo */
3368 HFC_outb_nodebug(hc, R_FIFO, 0);
3369 HFC_wait_nodebug(hc);
3370 if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) {
3371 spin_unlock_irqrestore(&hc->lock, flags);
3372 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
3373 } else
3374 spin_unlock_irqrestore(&hc->lock, flags);
3375 } else
3376 spin_unlock_irqrestore(&hc->lock, flags);
3377 return ret;
3378 case PH_ACTIVATE_REQ:
3379 if (debug & DEBUG_HFCMULTI_MSG)
3380 printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n",
3381 __func__, bch->slot);
3382 spin_lock_irqsave(&hc->lock, flags);
3383 /* activate B-channel if not already activated */
3384 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) {
3385 hc->chan[bch->slot].txpending = 0;
3386 ret = mode_hfcmulti(hc, bch->slot,
3387 ch->protocol,
3388 hc->chan[bch->slot].slot_tx,
3389 hc->chan[bch->slot].bank_tx,
3390 hc->chan[bch->slot].slot_rx,
3391 hc->chan[bch->slot].bank_rx);
3392 if (!ret) {
3393 if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf
3394 && test_bit(HFC_CHIP_DTMF, &hc->chip)) {
3395 /* start decoder */
3396 hc->dtmf = 1;
3397 if (debug & DEBUG_HFCMULTI_DTMF)
3398 printk(KERN_DEBUG
3399 "%s: start dtmf decoder\n",
3400 __func__);
3401 HFC_outb(hc, R_DTMF, hc->hw.r_dtmf |
3402 V_RST_DTMF);
3403 }
3404 }
3405 } else
3406 ret = 0;
3407 spin_unlock_irqrestore(&hc->lock, flags);
3408 if (!ret)
3409 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3410 GFP_KERNEL);
3411 break;
3412 case PH_CONTROL_REQ:
3413 spin_lock_irqsave(&hc->lock, flags);
3414 switch (hh->id) {
3415 case HFC_SPL_LOOP_ON: /* set sample loop */
3416 if (debug & DEBUG_HFCMULTI_MSG)
3417 printk(KERN_DEBUG
3418 "%s: HFC_SPL_LOOP_ON (len = %d)\n",
3419 __func__, skb->len);
3420 ret = 0;
3421 break;
3422 case HFC_SPL_LOOP_OFF: /* set silence */
3423 if (debug & DEBUG_HFCMULTI_MSG)
3424 printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n",
3425 __func__);
3426 ret = 0;
3427 break;
3428 default:
3429 printk(KERN_ERR
3430 "%s: unknown PH_CONTROL_REQ info %x\n",
3431 __func__, hh->id);
3432 ret = -EINVAL;
3433 }
3434 spin_unlock_irqrestore(&hc->lock, flags);
3435 break;
3436 case PH_DEACTIVATE_REQ:
3437 deactivate_bchannel(bch); /* locked there */
3438 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL,
3439 GFP_KERNEL);
3440 ret = 0;
3441 break;
3442 }
3443 if (!ret)
3444 dev_kfree_skb(skb);
3445 return ret;
3446}
3447
3448/*
3449 * bchannel control function
3450 */
3451static int
3452channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
3453{
3454 int ret = 0;
3455 struct dsp_features *features =
3456 (struct dsp_features *)(*((u_long *)&cq->p1));
3457 struct hfc_multi *hc = bch->hw;
3458 int slot_tx;
3459 int bank_tx;
3460 int slot_rx;
3461 int bank_rx;
3462 int num;
3463
3464 switch (cq->op) {
3465 case MISDN_CTRL_GETOP:
3466 cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP
8dd2f36f 3467 | MISDN_CTRL_RX_OFF | MISDN_CTRL_FILL_EMPTY;
af69fb3a
KK		 3468 break;
3469 case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */
3470 hc->chan[bch->slot].rx_off = !!cq->p1;
3471 if (!hc->chan[bch->slot].rx_off) {
3472 /* reset fifo on rx on */
3473 HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1);
3474 HFC_wait_nodebug(hc);
3475 HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F);
3476 HFC_wait_nodebug(hc);
3477 }
3478 if (debug & DEBUG_HFCMULTI_MSG)
3479 printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n",
3480 __func__, bch->nr, hc->chan[bch->slot].rx_off);
3481 break;
8dd2f36f
AE		 3482 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
3483 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
3484 if (debug & DEBUG_HFCMULTI_MSG)
3485 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
3486 "off=%d)\n", __func__, bch->nr, !!cq->p1);
3487 break;
af69fb3a
KK		 3488 case MISDN_CTRL_HW_FEATURES: /* fill features structure */
3489 if (debug & DEBUG_HFCMULTI_MSG)
3490 printk(KERN_DEBUG "%s: HW_FEATURE request\n",
3491 __func__);
3492 /* create confirm */
3493 features->hfc_id = hc->id;
3494 if (test_bit(HFC_CHIP_DTMF, &hc->chip))
3495 features->hfc_dtmf = 1;
3496 features->hfc_loops = 0;
3497 if (test_bit(HFC_CHIP_B410P, &hc->chip)) {
3498 features->hfc_echocanhw = 1;
3499 } else {
3500 features->pcm_id = hc->pcm;
3501 features->pcm_slots = hc->slots;
3502 features->pcm_banks = 2;
3503 }
3504 break;
3505 case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */
3506 slot_tx = cq->p1 & 0xff;
3507 bank_tx = cq->p1 >> 8;
3508 slot_rx = cq->p2 & 0xff;
3509 bank_rx = cq->p2 >> 8;
3510 if (debug & DEBUG_HFCMULTI_MSG)
3511 printk(KERN_DEBUG
3512 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3513 "slot %d bank %d (RX)\n",
3514 __func__, slot_tx, bank_tx,
3515 slot_rx, bank_rx);
3516 if (slot_tx < hc->slots && bank_tx <= 2 &&
3517 slot_rx < hc->slots && bank_rx <= 2)
3518 hfcmulti_pcm(hc, bch->slot,
3519 slot_tx, bank_tx, slot_rx, bank_rx);
3520 else {
3521 printk(KERN_WARNING
3522 "%s: HFC_PCM_CONN slot %d bank %d (TX) "
3523 "slot %d bank %d (RX) out of range\n",
3524 __func__, slot_tx, bank_tx,
3525 slot_rx, bank_rx);
3526 ret = -EINVAL;
3527 }
3528 break;
3529 case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */
3530 if (debug & DEBUG_HFCMULTI_MSG)
3531 printk(KERN_DEBUG "%s: HFC_PCM_DISC\n",
3532 __func__);
3533 hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0);
3534 break;
3535 case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */
3536 num = cq->p1 & 0xff;
3537 if (debug & DEBUG_HFCMULTI_MSG)
3538 printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n",
3539 __func__, num);
3540 if (num <= 7)
3541 hfcmulti_conf(hc, bch->slot, num);
3542 else {
3543 printk(KERN_WARNING
3544 "%s: HW_CONF_JOIN conf %d out of range\n",
3545 __func__, num);
3546 ret = -EINVAL;
3547 }
3548 break;
3549 case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */
3550 if (debug & DEBUG_HFCMULTI_MSG)
3551 printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__);
3552 hfcmulti_conf(hc, bch->slot, -1);
3553 break;
3554 case MISDN_CTRL_HFC_ECHOCAN_ON:
3555 if (debug & DEBUG_HFCMULTI_MSG)
3556 printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__);
3557 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3558 vpm_echocan_on(hc, bch->slot, cq->p1);
3559 else
3560 ret = -EINVAL;
3561 break;
3562
3563 case MISDN_CTRL_HFC_ECHOCAN_OFF:
3564 if (debug & DEBUG_HFCMULTI_MSG)
3565 printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n",
3566 __func__);
3567 if (test_bit(HFC_CHIP_B410P, &hc->chip))
3568 vpm_echocan_off(hc, bch->slot);
3569 else
3570 ret = -EINVAL;
3571 break;
3572 default:
3573 printk(KERN_WARNING "%s: unknown Op %x\n",
3574 __func__, cq->op);
3575 ret = -EINVAL;
3576 break;
3577 }
3578 return ret;
3579}
3580
3581static int
3582hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
3583{
3584 struct bchannel *bch = container_of(ch, struct bchannel, ch);
3585 struct hfc_multi *hc = bch->hw;
3586 int err = -EINVAL;
3587 u_long flags;
3588
3589 if (bch->debug & DEBUG_HW)
3590 printk(KERN_DEBUG "%s: cmd:%x %p\n",
3591 __func__, cmd, arg);
3592 switch (cmd) {
3593 case CLOSE_CHANNEL:
3594 test_and_clear_bit(FLG_OPEN, &bch->Flags);
3595 if (test_bit(FLG_ACTIVE, &bch->Flags))
3596 deactivate_bchannel(bch); /* locked there */
3597 ch->protocol = ISDN_P_NONE;
3598 ch->peer = NULL;
3599 module_put(THIS_MODULE);
3600 err = 0;
3601 break;
3602 case CONTROL_CHANNEL:
3603 spin_lock_irqsave(&hc->lock, flags);
3604 err = channel_bctrl(bch, arg);
3605 spin_unlock_irqrestore(&hc->lock, flags);
3606 break;
3607 default:
3608 printk(KERN_WARNING "%s: unknown prim(%x)\n",
3609 __func__, cmd);
3610 }
3611 return err;
3612}
3613
3614/*
3615 * handle D-channel events
3616 *
3617 * handle state change event
3618 */
3619static void
3620ph_state_change(struct dchannel *dch)
3621{
20b78804 3622 struct hfc_multi *hc;
af69fb3a
KK		 3623 int ch, i;
3624
3625 if (!dch) {
3626 printk(KERN_WARNING "%s: ERROR given dch is NULL\n",
3627 __func__);
3628 return;
3629 }
20b78804 3630 hc = dch->hw;
af69fb3a
KK		 3631 ch = dch->slot;
3632
3633 if (hc->type == 1) {
3634 if (dch->dev.D.protocol == ISDN_P_TE_E1) {
3635 if (debug & DEBUG_HFCMULTI_STATE)
3636 printk(KERN_DEBUG
3637 "%s: E1 TE (id=%d) newstate %x\n",
3638 __func__, hc->id, dch->state);
3639 } else {
3640 if (debug & DEBUG_HFCMULTI_STATE)
3641 printk(KERN_DEBUG
3642 "%s: E1 NT (id=%d) newstate %x\n",
3643 __func__, hc->id, dch->state);
3644 }
3645 switch (dch->state) {
3646 case (1):
3647 if (hc->e1_state != 1) {
3648 for (i = 1; i <= 31; i++) {
3649 /* reset fifos on e1 activation */
3650 HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1);
3651 HFC_wait_nodebug(hc);
3652 HFC_outb_nodebug(hc,
3653 R_INC_RES_FIFO, V_RES_F);
3654 HFC_wait_nodebug(hc);
3655 }
3656 }
3657 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3658 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3659 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3660 break;
3661
3662 default:
3663 if (hc->e1_state != 1)
3664 return;
3665 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3666 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3667 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3668 }
3669 hc->e1_state = dch->state;
3670 } else {
3671 if (dch->dev.D.protocol == ISDN_P_TE_S0) {
3672 if (debug & DEBUG_HFCMULTI_STATE)
3673 printk(KERN_DEBUG
3674 "%s: S/T TE newstate %x\n",
3675 __func__, dch->state);
3676 switch (dch->state) {
3677 case (0):
3678 l1_event(dch->l1, HW_RESET_IND);
3679 break;
3680 case (3):
3681 l1_event(dch->l1, HW_DEACT_IND);
3682 break;
3683 case (5):
3684 case (8):
3685 l1_event(dch->l1, ANYSIGNAL);
3686 break;
3687 case (6):
3688 l1_event(dch->l1, INFO2);
3689 break;
3690 case (7):
3691 l1_event(dch->l1, INFO4_P8);
3692 break;
3693 }
3694 } else {
3695 if (debug & DEBUG_HFCMULTI_STATE)
3696 printk(KERN_DEBUG "%s: S/T NT newstate %x\n",
3697 __func__, dch->state);
3698 switch (dch->state) {
3699 case (2):
3700 if (hc->chan[ch].nt_timer == 0) {
3701 hc->chan[ch].nt_timer = -1;
3702 HFC_outb(hc, R_ST_SEL,
3703 hc->chan[ch].port);
3704 /* undocumented: delay after R_ST_SEL */
3705 udelay(1);
3706 HFC_outb(hc, A_ST_WR_STATE, 4 |
3707 V_ST_LD_STA); /* G4 */
3708 udelay(6); /* wait at least 5,21us */
3709 HFC_outb(hc, A_ST_WR_STATE, 4);
3710 dch->state = 4;
3711 } else {
3712 /* one extra count for the next event */
3713 hc->chan[ch].nt_timer =
3714 nt_t1_count[poll_timer] + 1;
3715 HFC_outb(hc, R_ST_SEL,
3716 hc->chan[ch].port);
3717 /* undocumented: delay after R_ST_SEL */
3718 udelay(1);
3719 /* allow G2 -> G3 transition */
3720 HFC_outb(hc, A_ST_WR_STATE, 2 |
3721 V_SET_G2_G3);
3722 }
3723 break;
3724 case (1):
3725 hc->chan[ch].nt_timer = -1;
3726 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
3727 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
3728 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3729 break;
3730 case (4):
3731 hc->chan[ch].nt_timer = -1;
3732 break;
3733 case (3):
3734 hc->chan[ch].nt_timer = -1;
3735 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
3736 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
3737 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
3738 break;
3739 }
3740 }
3741 }
3742}
3743
3744/*
3745 * called for card mode init message
3746 */
3747
3748static void
3749hfcmulti_initmode(struct dchannel *dch)
3750{
3751 struct hfc_multi *hc = dch->hw;
3752 u_char a_st_wr_state, r_e1_wr_sta;
3753 int i, pt;
3754
3755 if (debug & DEBUG_HFCMULTI_INIT)
3756 printk(KERN_DEBUG "%s: entered\n", __func__);
3757
3758 if (hc->type == 1) {
3759 hc->chan[hc->dslot].slot_tx = -1;
3760 hc->chan[hc->dslot].slot_rx = -1;
3761 hc->chan[hc->dslot].conf = -1;
3762 if (hc->dslot) {
3763 mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol,
3764 -1, 0, -1, 0);
3765 dch->timer.function = (void *) hfcmulti_dbusy_timer;
3766 dch->timer.data = (long) dch;
3767 init_timer(&dch->timer);
3768 }
3769 for (i = 1; i <= 31; i++) {
3770 if (i == hc->dslot)
3771 continue;
3772 hc->chan[i].slot_tx = -1;
3773 hc->chan[i].slot_rx = -1;
3774 hc->chan[i].conf = -1;
3775 mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0);
3776 }
3777 /* E1 */
3778 if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) {
3779 HFC_outb(hc, R_LOS0, 255); /* 2 ms */
3780 HFC_outb(hc, R_LOS1, 255); /* 512 ms */
3781 }
3782 if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) {
3783 HFC_outb(hc, R_RX0, 0);
3784 hc->hw.r_tx0 = 0 | V_OUT_EN;
3785 } else {
3786 HFC_outb(hc, R_RX0, 1);
3787 hc->hw.r_tx0 = 1 | V_OUT_EN;
3788 }
3789 hc->hw.r_tx1 = V_ATX | V_NTRI;
3790 HFC_outb(hc, R_TX0, hc->hw.r_tx0);
3791 HFC_outb(hc, R_TX1, hc->hw.r_tx1);
3792 HFC_outb(hc, R_TX_FR0, 0x00);
3793 HFC_outb(hc, R_TX_FR1, 0xf8);
3794
3795 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3796 HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E);
3797
3798 HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0);
3799
3800 if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg))
3801 HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC);
3802
3803 if (dch->dev.D.protocol == ISDN_P_NT_E1) {
3804 if (debug & DEBUG_HFCMULTI_INIT)
3805 printk(KERN_DEBUG "%s: E1 port is NT-mode\n",
3806 __func__);
3807 r_e1_wr_sta = 0; /* G0 */
3808 hc->e1_getclock = 0;
3809 } else {
3810 if (debug & DEBUG_HFCMULTI_INIT)
3811 printk(KERN_DEBUG "%s: E1 port is TE-mode\n",
3812 __func__);
3813 r_e1_wr_sta = 0; /* F0 */
3814 hc->e1_getclock = 1;
3815 }
3816 if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip))
3817 HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX);
3818 else
3819 HFC_outb(hc, R_SYNC_OUT, 0);
3820 if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip))
3821 hc->e1_getclock = 1;
3822 if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip))
3823 hc->e1_getclock = 0;
3824 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
3825 /* SLAVE (clock master) */
3826 if (debug & DEBUG_HFCMULTI_INIT)
3827 printk(KERN_DEBUG
3828 "%s: E1 port is clock master "
3829 "(clock from PCM)\n", __func__);
3830 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC);
3831 } else {
3832 if (hc->e1_getclock) {
3833 /* MASTER (clock slave) */
3834 if (debug & DEBUG_HFCMULTI_INIT)
3835 printk(KERN_DEBUG
3836 "%s: E1 port is clock slave "
3837 "(clock to PCM)\n", __func__);
3838 HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS);
3839 } else {
3840 /* MASTER (clock master) */
3841 if (debug & DEBUG_HFCMULTI_INIT)
3842 printk(KERN_DEBUG "%s: E1 port is "
3843 "clock master "
3844 "(clock from QUARTZ)\n",
3845 __func__);
3846 HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC |
3847 V_PCM_SYNC | V_JATT_OFF);
3848 HFC_outb(hc, R_SYNC_OUT, 0);
3849 }
3850 }
3851 HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */
3852 HFC_outb(hc, R_PWM_MD, V_PWM0_MD);
3853 HFC_outb(hc, R_PWM0, 0x50);
3854 HFC_outb(hc, R_PWM1, 0xff);
3855 /* state machine setup */
3856 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA);
3857 udelay(6); /* wait at least 5,21us */
3858 HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta);
3859 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3860 hc->syncronized = 0;
3861 plxsd_checksync(hc, 0);
3862 }
3863 } else {
3864 i = dch->slot;
3865 hc->chan[i].slot_tx = -1;
3866 hc->chan[i].slot_rx = -1;
3867 hc->chan[i].conf = -1;
3868 mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0);
3869 dch->timer.function = (void *)hfcmulti_dbusy_timer;
3870 dch->timer.data = (long) dch;
3871 init_timer(&dch->timer);
3872 hc->chan[i - 2].slot_tx = -1;
3873 hc->chan[i - 2].slot_rx = -1;
3874 hc->chan[i - 2].conf = -1;
3875 mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0);
3876 hc->chan[i - 1].slot_tx = -1;
3877 hc->chan[i - 1].slot_rx = -1;
3878 hc->chan[i - 1].conf = -1;
3879 mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0);
3880 /* ST */
3881 pt = hc->chan[i].port;
3882 /* select interface */
3883 HFC_outb(hc, R_ST_SEL, pt);
3884 /* undocumented: delay after R_ST_SEL */
3885 udelay(1);
3886 if (dch->dev.D.protocol == ISDN_P_NT_S0) {
3887 if (debug & DEBUG_HFCMULTI_INIT)
3888 printk(KERN_DEBUG
3889 "%s: ST port %d is NT-mode\n",
3890 __func__, pt);
3891 /* clock delay */
3892 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt);
3893 a_st_wr_state = 1; /* G1 */
3894 hc->hw.a_st_ctrl0[pt] = V_ST_MD;
3895 } else {
3896 if (debug & DEBUG_HFCMULTI_INIT)
3897 printk(KERN_DEBUG
3898 "%s: ST port %d is TE-mode\n",
3899 __func__, pt);
3900 /* clock delay */
3901 HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te);
3902 a_st_wr_state = 2; /* F2 */
3903 hc->hw.a_st_ctrl0[pt] = 0;
3904 }
3905 if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg))
3906 hc->hw.a_st_ctrl0[pt] |= V_TX_LI;
3907 /* line setup */
3908 HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]);
3909 /* disable E-channel */
3910 if ((dch->dev.D.protocol == ISDN_P_NT_S0) ||
3911 test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg))
3912 HFC_outb(hc, A_ST_CTRL1, V_E_IGNO);
3913 else
3914 HFC_outb(hc, A_ST_CTRL1, 0);
3915 /* enable B-channel receive */
3916 HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN);
3917 /* state machine setup */
3918 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA);
3919 udelay(6); /* wait at least 5,21us */
3920 HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state);
3921 hc->hw.r_sci_msk |= 1 << pt;
3922 /* state machine interrupts */
3923 HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk);
3924 /* unset sync on port */
3925 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
3926 hc->syncronized &=
3927 ~(1 << hc->chan[dch->slot].port);
3928 plxsd_checksync(hc, 0);
3929 }
3930 }
3931 if (debug & DEBUG_HFCMULTI_INIT)
3932 printk("%s: done\n", __func__);
3933}
3934
3935
3936static int
3937open_dchannel(struct hfc_multi *hc, struct dchannel *dch,
3938 struct channel_req *rq)
3939{
3940 int err = 0;
3941 u_long flags;
3942
3943 if (debug & DEBUG_HW_OPEN)
3944 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
3945 dch->dev.id, __builtin_return_address(0));
3946 if (rq->protocol == ISDN_P_NONE)
3947 return -EINVAL;
3948 if ((dch->dev.D.protocol != ISDN_P_NONE) &&
3949 (dch->dev.D.protocol != rq->protocol)) {
3950 if (debug & DEBUG_HFCMULTI_MODE)
3951 printk(KERN_WARNING "%s: change protocol %x to %x\n",
3952 __func__, dch->dev.D.protocol, rq->protocol);
3953 }
3954 if ((dch->dev.D.protocol == ISDN_P_TE_S0)
3955 && (rq->protocol != ISDN_P_TE_S0))
3956 l1_event(dch->l1, CLOSE_CHANNEL);
3957 if (dch->dev.D.protocol != rq->protocol) {
3958 if (rq->protocol == ISDN_P_TE_S0) {
3959 err = create_l1(dch, hfcm_l1callback);
3960 if (err)
3961 return err;
3962 }
3963 dch->dev.D.protocol = rq->protocol;
3964 spin_lock_irqsave(&hc->lock, flags);
3965 hfcmulti_initmode(dch);
3966 spin_unlock_irqrestore(&hc->lock, flags);
3967 }
3968
3969 if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) ||
3970 ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) ||
3971 ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) ||
3972 ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) {
3973 _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY,
3974 0, NULL, GFP_KERNEL);
3975 }
3976 rq->ch = &dch->dev.D;
3977 if (!try_module_get(THIS_MODULE))
3978 printk(KERN_WARNING "%s:cannot get module\n", __func__);
3979 return 0;
3980}
3981
3982static int
3983open_bchannel(struct hfc_multi *hc, struct dchannel *dch,
3984 struct channel_req *rq)
3985{
3986 struct bchannel *bch;
3987 int ch;
3988
ff4cc1de 3989 if (!test_channelmap(rq->adr.channel, dch->dev.channelmap))
af69fb3a
KK		 3990 return -EINVAL;
3991 if (rq->protocol == ISDN_P_NONE)
3992 return -EINVAL;
3993 if (hc->type == 1)
3994 ch = rq->adr.channel;
3995 else
3996 ch = (rq->adr.channel - 1) + (dch->slot - 2);
3997 bch = hc->chan[ch].bch;
3998 if (!bch) {
3999 printk(KERN_ERR "%s:internal error ch %d has no bch\n",
4000 __func__, ch);
4001 return -EINVAL;
4002 }
4003 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
4004 return -EBUSY; /* b-channel can be only open once */
8dd2f36f 4005 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
af69fb3a
KK		 4006 bch->ch.protocol = rq->protocol;
4007 hc->chan[ch].rx_off = 0;
4008 rq->ch = &bch->ch;
4009 if (!try_module_get(THIS_MODULE))
4010 printk(KERN_WARNING "%s:cannot get module\n", __func__);
4011 return 0;
4012}
4013
4014/*
4015 * device control function
4016 */
4017static int
4018channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq)
4019{
7df3bb8f 4020 struct hfc_multi *hc = dch->hw;
af69fb3a 4021 int ret = 0;
7df3bb8f 4022 int wd_mode, wd_cnt;
af69fb3a
KK		 4023
4024 switch (cq->op) {
4025 case MISDN_CTRL_GETOP:
7df3bb8f
AE		 4026 cq->op = MISDN_CTRL_HFC_OP;
4027 break;
4028 case MISDN_CTRL_HFC_WD_INIT: /* init the watchdog */
4029 wd_cnt = cq->p1 & 0xf;
4030 wd_mode = !!(cq->p1 >> 4);
4031 if (debug & DEBUG_HFCMULTI_MSG)
4032 printk(KERN_DEBUG
4033 "%s: MISDN_CTRL_HFC_WD_INIT mode %s counter 0x%x\n",
4034 __func__, wd_mode ? "AUTO" : "MANUAL", wd_cnt);
4035 /* set the watchdog timer */
4036 HFC_outb(hc, R_TI_WD, poll_timer | (wd_cnt << 4));
4037 hc->hw.r_bert_wd_md = (wd_mode ? V_AUTO_WD_RES : 0);
4038 if (hc->ctype == HFC_TYPE_XHFC)
4039 hc->hw.r_bert_wd_md |= 0x40 /* V_WD_EN */;
4040 /* init the watchdog register and reset the counter */
4041 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
4042 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4043 /* enable the watchdog output for Speech-Design */
4044 HFC_outb(hc, R_GPIO_SEL, V_GPIO_SEL7);
4045 HFC_outb(hc, R_GPIO_EN1, V_GPIO_EN15);
4046 HFC_outb(hc, R_GPIO_OUT1, 0);
4047 HFC_outb(hc, R_GPIO_OUT1, V_GPIO_OUT15);
4048 }
4049 break;
4050 case MISDN_CTRL_HFC_WD_RESET: /* reset the watchdog counter */
4051 if (debug & DEBUG_HFCMULTI_MSG)
4052 printk(KERN_DEBUG "%s: MISDN_CTRL_HFC_WD_RESET\n",
4053 __func__);
4054 HFC_outb(hc, R_BERT_WD_MD, hc->hw.r_bert_wd_md | V_WD_RES);
af69fb3a
KK		 4055 break;
4056 default:
4057 printk(KERN_WARNING "%s: unknown Op %x\n",
4058 __func__, cq->op);
4059 ret = -EINVAL;
4060 break;
4061 }
4062 return ret;
4063}
4064
4065static int
4066hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
4067{
4068 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
4069 struct dchannel *dch = container_of(dev, struct dchannel, dev);
4070 struct hfc_multi *hc = dch->hw;
4071 struct channel_req *rq;
4072 int err = 0;
4073 u_long flags;
4074
4075 if (dch->debug & DEBUG_HW)
4076 printk(KERN_DEBUG "%s: cmd:%x %p\n",
4077 __func__, cmd, arg);
4078 switch (cmd) {
4079 case OPEN_CHANNEL:
4080 rq = arg;
4081 switch (rq->protocol) {
4082 case ISDN_P_TE_S0:
4083 case ISDN_P_NT_S0:
4084 if (hc->type == 1) {
4085 err = -EINVAL;
4086 break;
4087 }
4088 err = open_dchannel(hc, dch, rq); /* locked there */
4089 break;
4090 case ISDN_P_TE_E1:
4091 case ISDN_P_NT_E1:
4092 if (hc->type != 1) {
4093 err = -EINVAL;
4094 break;
4095 }
4096 err = open_dchannel(hc, dch, rq); /* locked there */
4097 break;
4098 default:
4099 spin_lock_irqsave(&hc->lock, flags);
4100 err = open_bchannel(hc, dch, rq);
4101 spin_unlock_irqrestore(&hc->lock, flags);
4102 }
4103 break;
4104 case CLOSE_CHANNEL:
4105 if (debug & DEBUG_HW_OPEN)
4106 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
4107 __func__, dch->dev.id,
4108 __builtin_return_address(0));
4109 module_put(THIS_MODULE);
4110 break;
4111 case CONTROL_CHANNEL:
4112 spin_lock_irqsave(&hc->lock, flags);
4113 err = channel_dctrl(dch, arg);
4114 spin_unlock_irqrestore(&hc->lock, flags);
4115 break;
4116 default:
4117 if (dch->debug & DEBUG_HW)
4118 printk(KERN_DEBUG "%s: unknown command %x\n",
4119 __func__, cmd);
4120 err = -EINVAL;
4121 }
4122 return err;
4123}
4124
3bd69ad1
AE		 4125static int
4126clockctl(void *priv, int enable)
4127{
4128 struct hfc_multi *hc = priv;
4129
4130 hc->iclock_on = enable;
4131 return 0;
4132}
4133
af69fb3a
KK		 4134/*
4135 * initialize the card
4136 */
4137
4138/*
4139 * start timer irq, wait some time and check if we have interrupts.
4140 * if not, reset chip and try again.
4141 */
4142static int
4143init_card(struct hfc_multi *hc)
4144{
4145 int err = -EIO;
4146 u_long flags;
c31655fc 4147 void __iomem *plx_acc;
af69fb3a
KK		 4148 u_long plx_flags;
4149
4150 if (debug & DEBUG_HFCMULTI_INIT)
4151 printk(KERN_DEBUG "%s: entered\n", __func__);
4152
4153 spin_lock_irqsave(&hc->lock, flags);
4154 /* set interrupts but leave global interrupt disabled */
4155 hc->hw.r_irq_ctrl = V_FIFO_IRQ;
4156 disable_hwirq(hc);
4157 spin_unlock_irqrestore(&hc->lock, flags);
4158
4159 if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED,
4160 "HFC-multi", hc)) {
4161 printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n",
4162 hc->pci_dev->irq);
4163 return -EIO;
4164 }
4165 hc->irq = hc->pci_dev->irq;
4166
4167 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4168 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 4169 plx_acc = hc->plx_membase + PLX_INTCSR;
af69fb3a
KK		 4170 writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE),
4171 plx_acc); /* enable PCI & LINT1 irq */
4172 spin_unlock_irqrestore(&plx_lock, plx_flags);
4173 }
4174
4175 if (debug & DEBUG_HFCMULTI_INIT)
4176 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4177 __func__, hc->irq, hc->irqcnt);
4178 err = init_chip(hc);
4179 if (err)
4180 goto error;
4181 /*
4182 * Finally enable IRQ output
4183 * this is only allowed, if an IRQ routine is allready
4184 * established for this HFC, so don't do that earlier
4185 */
4186 spin_lock_irqsave(&hc->lock, flags);
4187 enable_hwirq(hc);
4188 spin_unlock_irqrestore(&hc->lock, flags);
4189 /* printk(KERN_DEBUG "no master irq set!!!\n"); */
4190 set_current_state(TASK_UNINTERRUPTIBLE);
4191 schedule_timeout((100*HZ)/1000); /* Timeout 100ms */
4192 /* turn IRQ off until chip is completely initialized */
4193 spin_lock_irqsave(&hc->lock, flags);
4194 disable_hwirq(hc);
4195 spin_unlock_irqrestore(&hc->lock, flags);
4196 if (debug & DEBUG_HFCMULTI_INIT)
4197 printk(KERN_DEBUG "%s: IRQ %d count %d\n",
4198 __func__, hc->irq, hc->irqcnt);
4199 if (hc->irqcnt) {
4200 if (debug & DEBUG_HFCMULTI_INIT)
4201 printk(KERN_DEBUG "%s: done\n", __func__);
4202
4203 return 0;
4204 }
4205 if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) {
4206 printk(KERN_INFO "ignoring missing interrupts\n");
4207 return 0;
4208 }
4209
4210 printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n",
4211 hc->irq);
4212
4213 err = -EIO;
4214
4215error:
4216 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4217 spin_lock_irqsave(&plx_lock, plx_flags);
c31655fc 4218 plx_acc = hc->plx_membase + PLX_INTCSR;
af69fb3a
KK		 4219 writew(0x00, plx_acc); /*disable IRQs*/
4220 spin_unlock_irqrestore(&plx_lock, plx_flags);
4221 }
4222
4223 if (debug & DEBUG_HFCMULTI_INIT)
4224 printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq);
4225 if (hc->irq) {
4226 free_irq(hc->irq, hc);
4227 hc->irq = 0;
4228 }
4229
4230 if (debug & DEBUG_HFCMULTI_INIT)
4231 printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err);
4232 return err;
4233}
4234
4235/*
4236 * find pci device and set it up
4237 */
4238
4239static int
4240setup_pci(struct hfc_multi *hc, struct pci_dev *pdev,
4241 const struct pci_device_id *ent)
4242{
4243 struct hm_map *m = (struct hm_map *)ent->driver_data;
4244
4245 printk(KERN_INFO
4246 "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n",
4247 m->vendor_name, m->card_name, m->clock2 ? "double" : "normal");
4248
4249 hc->pci_dev = pdev;
4250 if (m->clock2)
4251 test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip);
4252
4253 if (ent->device == 0xB410) {
4254 test_and_set_bit(HFC_CHIP_B410P, &hc->chip);
4255 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4256 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4257 hc->slots = 32;
4258 }
4259
4260 if (hc->pci_dev->irq <= 0) {
4261 printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n");
4262 return -EIO;
4263 }
4264 if (pci_enable_device(hc->pci_dev)) {
4265 printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n");
4266 return -EIO;
4267 }
4268 hc->leds = m->leds;
4269 hc->ledstate = 0xAFFEAFFE;
4270 hc->opticalsupport = m->opticalsupport;
4271
4272 /* set memory access methods */
4273 if (m->io_mode) /* use mode from card config */
4274 hc->io_mode = m->io_mode;
4275 switch (hc->io_mode) {
4276 case HFC_IO_MODE_PLXSD:
4277 test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip);
4278 hc->slots = 128; /* required */
4279 /* fall through */
4280 case HFC_IO_MODE_PCIMEM:
4281 hc->HFC_outb = HFC_outb_pcimem;
4282 hc->HFC_inb = HFC_inb_pcimem;
4283 hc->HFC_inw = HFC_inw_pcimem;
4284 hc->HFC_wait = HFC_wait_pcimem;
4285 hc->read_fifo = read_fifo_pcimem;
4286 hc->write_fifo = write_fifo_pcimem;
4287 break;
4288 case HFC_IO_MODE_REGIO:
4289 hc->HFC_outb = HFC_outb_regio;
4290 hc->HFC_inb = HFC_inb_regio;
4291 hc->HFC_inw = HFC_inw_regio;
4292 hc->HFC_wait = HFC_wait_regio;
4293 hc->read_fifo = read_fifo_regio;
4294 hc->write_fifo = write_fifo_regio;
4295 break;
4296 default:
4297 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4298 pci_disable_device(hc->pci_dev);
4299 return -EIO;
4300 }
4301 hc->HFC_outb_nodebug = hc->HFC_outb;
4302 hc->HFC_inb_nodebug = hc->HFC_inb;
4303 hc->HFC_inw_nodebug = hc->HFC_inw;
4304 hc->HFC_wait_nodebug = hc->HFC_wait;
4305#ifdef HFC_REGISTER_DEBUG
4306 hc->HFC_outb = HFC_outb_debug;
4307 hc->HFC_inb = HFC_inb_debug;
4308 hc->HFC_inw = HFC_inw_debug;
4309 hc->HFC_wait = HFC_wait_debug;
4310#endif
4311 hc->pci_iobase = 0;
4312 hc->pci_membase = NULL;
4313 hc->plx_membase = NULL;
4314
4315 switch (hc->io_mode) {
4316 case HFC_IO_MODE_PLXSD:
4317 hc->plx_origmembase = hc->pci_dev->resource[0].start;
4318 /* MEMBASE 1 is PLX PCI Bridge */
4319
4320 if (!hc->plx_origmembase) {
4321 printk(KERN_WARNING
4322 "HFC-multi: No IO-Memory for PCI PLX bridge found\n");
4323 pci_disable_device(hc->pci_dev);
4324 return -EIO;
4325 }
4326
4327 hc->plx_membase = ioremap(hc->plx_origmembase, 0x80);
4328 if (!hc->plx_membase) {
4329 printk(KERN_WARNING
4330 "HFC-multi: failed to remap plx address space. "
4331 "(internal error)\n");
4332 pci_disable_device(hc->pci_dev);
4333 return -EIO;
4334 }
4335 printk(KERN_INFO
4336 "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n",
4337 (u_long)hc->plx_membase, hc->plx_origmembase);
4338
4339 hc->pci_origmembase = hc->pci_dev->resource[2].start;
4340 /* MEMBASE 1 is PLX PCI Bridge */
4341 if (!hc->pci_origmembase) {
4342 printk(KERN_WARNING
4343 "HFC-multi: No IO-Memory for PCI card found\n");
4344 pci_disable_device(hc->pci_dev);
4345 return -EIO;
4346 }
4347
4348 hc->pci_membase = ioremap(hc->pci_origmembase, 0x400);
4349 if (!hc->pci_membase) {
4350 printk(KERN_WARNING "HFC-multi: failed to remap io "
4351 "address space. (internal error)\n");
4352 pci_disable_device(hc->pci_dev);
4353 return -EIO;
4354 }
4355
4356 printk(KERN_INFO
4357 "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d "
4358 "leds-type %d\n",
4359 hc->id, (u_long)hc->pci_membase, hc->pci_origmembase,
4360 hc->pci_dev->irq, HZ, hc->leds);
4361 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4362 break;
4363 case HFC_IO_MODE_PCIMEM:
4364 hc->pci_origmembase = hc->pci_dev->resource[1].start;
4365 if (!hc->pci_origmembase) {
4366 printk(KERN_WARNING
4367 "HFC-multi: No IO-Memory for PCI card found\n");
4368 pci_disable_device(hc->pci_dev);
4369 return -EIO;
4370 }
4371
4372 hc->pci_membase = ioremap(hc->pci_origmembase, 256);
4373 if (!hc->pci_membase) {
4374 printk(KERN_WARNING
4375 "HFC-multi: failed to remap io address space. "
4376 "(internal error)\n");
4377 pci_disable_device(hc->pci_dev);
4378 return -EIO;
4379 }
4380 printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d "
4381 "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase,
4382 hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds);
4383 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO);
4384 break;
4385 case HFC_IO_MODE_REGIO:
4386 hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start;
4387 if (!hc->pci_iobase) {
4388 printk(KERN_WARNING
4389 "HFC-multi: No IO for PCI card found\n");
4390 pci_disable_device(hc->pci_dev);
4391 return -EIO;
4392 }
4393
4394 if (!request_region(hc->pci_iobase, 8, "hfcmulti")) {
4395 printk(KERN_WARNING "HFC-multi: failed to request "
4396 "address space at 0x%08lx (internal error)\n",
4397 hc->pci_iobase);
4398 pci_disable_device(hc->pci_dev);
4399 return -EIO;
4400 }
4401
4402 printk(KERN_INFO
4403 "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n",
4404 m->vendor_name, m->card_name, (u_int) hc->pci_iobase,
4405 hc->pci_dev->irq, HZ, hc->leds);
4406 pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO);
4407 break;
4408 default:
4409 printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n");
4410 pci_disable_device(hc->pci_dev);
4411 return -EIO;
4412 }
4413
4414 pci_set_drvdata(hc->pci_dev, hc);
4415
4416 /* At this point the needed PCI config is done */
4417 /* fifos are still not enabled */
4418 return 0;
4419}
4420
4421
4422/*
4423 * remove port
4424 */
4425
4426static void
4427release_port(struct hfc_multi *hc, struct dchannel *dch)
4428{
4429 int pt, ci, i = 0;
4430 u_long flags;
4431 struct bchannel *pb;
4432
4433 ci = dch->slot;
4434 pt = hc->chan[ci].port;
4435
4436 if (debug & DEBUG_HFCMULTI_INIT)
4437 printk(KERN_DEBUG "%s: entered for port %d\n",
4438 __func__, pt + 1);
4439
4440 if (pt >= hc->ports) {
4441 printk(KERN_WARNING "%s: ERROR port out of range (%d).\n",
4442 __func__, pt + 1);
4443 return;
4444 }
4445
4446 if (debug & DEBUG_HFCMULTI_INIT)
4447 printk(KERN_DEBUG "%s: releasing port=%d\n",
4448 __func__, pt + 1);
4449
4450 if (dch->dev.D.protocol == ISDN_P_TE_S0)
4451 l1_event(dch->l1, CLOSE_CHANNEL);
4452
4453 hc->chan[ci].dch = NULL;
4454
4455 if (hc->created[pt]) {
4456 hc->created[pt] = 0;
4457 mISDN_unregister_device(&dch->dev);
4458 }
4459
4460 spin_lock_irqsave(&hc->lock, flags);
4461
4462 if (dch->timer.function) {
4463 del_timer(&dch->timer);
4464 dch->timer.function = NULL;
4465 }
4466
4467 if (hc->type == 1) { /* E1 */
4468 /* remove sync */
4469 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4470 hc->syncronized = 0;
4471 plxsd_checksync(hc, 1);
4472 }
4473 /* free channels */
4474 for (i = 0; i <= 31; i++) {
4475 if (hc->chan[i].bch) {
4476 if (debug & DEBUG_HFCMULTI_INIT)
4477 printk(KERN_DEBUG
4478 "%s: free port %d channel %d\n",
4479 __func__, hc->chan[i].port+1, i);
4480 pb = hc->chan[i].bch;
4481 hc->chan[i].bch = NULL;
4482 spin_unlock_irqrestore(&hc->lock, flags);
4483 mISDN_freebchannel(pb);
4484 kfree(pb);
4485 kfree(hc->chan[i].coeff);
4486 spin_lock_irqsave(&hc->lock, flags);
4487 }
4488 }
4489 } else {
4490 /* remove sync */
4491 if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) {
4492 hc->syncronized &=
4493 ~(1 << hc->chan[ci].port);
4494 plxsd_checksync(hc, 1);
4495 }
4496 /* free channels */
4497 if (hc->chan[ci - 2].bch) {
4498 if (debug & DEBUG_HFCMULTI_INIT)
4499 printk(KERN_DEBUG
4500 "%s: free port %d channel %d\n",
4501 __func__, hc->chan[ci - 2].port+1,
4502 ci - 2);
4503 pb = hc->chan[ci - 2].bch;
4504 hc->chan[ci - 2].bch = NULL;
4505 spin_unlock_irqrestore(&hc->lock, flags);
4506 mISDN_freebchannel(pb);
4507 kfree(pb);
4508 kfree(hc->chan[ci - 2].coeff);
4509 spin_lock_irqsave(&hc->lock, flags);
4510 }
4511 if (hc->chan[ci - 1].bch) {
4512 if (debug & DEBUG_HFCMULTI_INIT)
4513 printk(KERN_DEBUG
4514 "%s: free port %d channel %d\n",
4515 __func__, hc->chan[ci - 1].port+1,
4516 ci - 1);
4517 pb = hc->chan[ci - 1].bch;
4518 hc->chan[ci - 1].bch = NULL;
4519 spin_unlock_irqrestore(&hc->lock, flags);
4520 mISDN_freebchannel(pb);
4521 kfree(pb);
4522 kfree(hc->chan[ci - 1].coeff);
4523 spin_lock_irqsave(&hc->lock, flags);
4524 }
4525 }
4526
4527 spin_unlock_irqrestore(&hc->lock, flags);
4528
4529 if (debug & DEBUG_HFCMULTI_INIT)
4530 printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt);
4531 mISDN_freedchannel(dch);
4532 kfree(dch);
4533
4534 if (debug & DEBUG_HFCMULTI_INIT)
4535 printk(KERN_DEBUG "%s: done!\n", __func__);
4536}
4537
4538static void
4539release_card(struct hfc_multi *hc)
4540{
4541 u_long flags;
4542 int ch;
4543
4544 if (debug & DEBUG_HFCMULTI_INIT)
4545 printk(KERN_WARNING "%s: release card (%d) entered\n",
4546 __func__, hc->id);
4547
3bd69ad1
AE		 4548 /* unregister clock source */
4549 if (hc->iclock)
4550 mISDN_unregister_clock(hc->iclock);
4551
4552 /* disable irq */
af69fb3a
KK		 4553 spin_lock_irqsave(&hc->lock, flags);
4554 disable_hwirq(hc);
4555 spin_unlock_irqrestore(&hc->lock, flags);
af69fb3a
KK		 4556 udelay(1000);
4557
4558 /* dimm leds */
4559 if (hc->leds)
4560 hfcmulti_leds(hc);
4561
4562 /* disable D-channels & B-channels */
4563 if (debug & DEBUG_HFCMULTI_INIT)
4564 printk(KERN_DEBUG "%s: disable all channels (d and b)\n",
4565 __func__);
4566 for (ch = 0; ch <= 31; ch++) {
4567 if (hc->chan[ch].dch)
4568 release_port(hc, hc->chan[ch].dch);
4569 }
4570
4571 /* release hardware & irq */
4572 if (hc->irq) {
4573 if (debug & DEBUG_HFCMULTI_INIT)
4574 printk(KERN_WARNING "%s: free irq %d\n",
4575 __func__, hc->irq);
4576 free_irq(hc->irq, hc);
4577 hc->irq = 0;
4578
4579 }
4580 release_io_hfcmulti(hc);
4581
4582 if (debug & DEBUG_HFCMULTI_INIT)
4583 printk(KERN_WARNING "%s: remove instance from list\n",
4584 __func__);
4585 list_del(&hc->list);
4586
4587 if (debug & DEBUG_HFCMULTI_INIT)
4588 printk(KERN_WARNING "%s: delete instance\n", __func__);
4589 if (hc == syncmaster)
4590 syncmaster = NULL;
4591 kfree(hc);
4592 if (debug & DEBUG_HFCMULTI_INIT)
4593 printk(KERN_WARNING "%s: card successfully removed\n",
4594 __func__);
4595}
4596
4597static int
4598init_e1_port(struct hfc_multi *hc, struct hm_map *m)
4599{
4600 struct dchannel *dch;
4601 struct bchannel *bch;
4602 int ch, ret = 0;
4603 char name[MISDN_MAX_IDLEN];
4604
4605 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4606 if (!dch)
4607 return -ENOMEM;
4608 dch->debug = debug;
4609 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4610 dch->hw = hc;
4611 dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1);
4612 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4613 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4614 dch->dev.D.send = handle_dmsg;
4615 dch->dev.D.ctrl = hfcm_dctrl;
4616 dch->dev.nrbchan = (hc->dslot)?30:31;
4617 dch->slot = hc->dslot;
4618 hc->chan[hc->dslot].dch = dch;
4619 hc->chan[hc->dslot].port = 0;
4620 hc->chan[hc->dslot].nt_timer = -1;
4621 for (ch = 1; ch <= 31; ch++) {
4622 if (ch == hc->dslot) /* skip dchannel */
4623 continue;
4624 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4625 if (!bch) {
4626 printk(KERN_ERR "%s: no memory for bchannel\n",
4627 __func__);
4628 ret = -ENOMEM;
4629 goto free_chan;
4630 }
4631 hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL);
4632 if (!hc->chan[ch].coeff) {
4633 printk(KERN_ERR "%s: no memory for coeffs\n",
4634 __func__);
4635 ret = -ENOMEM;
23b904f3 4636 kfree(bch);
af69fb3a
KK		 4637 goto free_chan;
4638 }
4639 bch->nr = ch;
4640 bch->slot = ch;
4641 bch->debug = debug;
4642 mISDN_initbchannel(bch, MAX_DATA_MEM);
4643 bch->hw = hc;
4644 bch->ch.send = handle_bmsg;
4645 bch->ch.ctrl = hfcm_bctrl;
4646 bch->ch.nr = ch;
4647 list_add(&bch->ch.list, &dch->dev.bchannels);
4648 hc->chan[ch].bch = bch;
4649 hc->chan[ch].port = 0;
ff4cc1de 4650 set_channelmap(bch->nr, dch->dev.channelmap);
af69fb3a
KK		 4651 }
4652 /* set optical line type */
4653 if (port[Port_cnt] & 0x001) {
4654 if (!m->opticalsupport) {
4655 printk(KERN_INFO
4656 "This board has no optical "
4657 "support\n");
4658 } else {
4659 if (debug & DEBUG_HFCMULTI_INIT)
4660 printk(KERN_DEBUG
4661 "%s: PORT set optical "
4662 "interfacs: card(%d) "
4663 "port(%d)\n",
4664 __func__,
4665 HFC_cnt + 1, 1);
4666 test_and_set_bit(HFC_CFG_OPTICAL,
4667 &hc->chan[hc->dslot].cfg);
4668 }
4669 }
4670 /* set LOS report */
4671 if (port[Port_cnt] & 0x004) {
4672 if (debug & DEBUG_HFCMULTI_INIT)
4673 printk(KERN_DEBUG "%s: PORT set "
4674 "LOS report: card(%d) port(%d)\n",
4675 __func__, HFC_cnt + 1, 1);
4676 test_and_set_bit(HFC_CFG_REPORT_LOS,
4677 &hc->chan[hc->dslot].cfg);
4678 }
4679 /* set AIS report */
4680 if (port[Port_cnt] & 0x008) {
4681 if (debug & DEBUG_HFCMULTI_INIT)
4682 printk(KERN_DEBUG "%s: PORT set "
4683 "AIS report: card(%d) port(%d)\n",
4684 __func__, HFC_cnt + 1, 1);
4685 test_and_set_bit(HFC_CFG_REPORT_AIS,
4686 &hc->chan[hc->dslot].cfg);
4687 }
4688 /* set SLIP report */
4689 if (port[Port_cnt] & 0x010) {
4690 if (debug & DEBUG_HFCMULTI_INIT)
4691 printk(KERN_DEBUG
4692 "%s: PORT set SLIP report: "
4693 "card(%d) port(%d)\n",
4694 __func__, HFC_cnt + 1, 1);
4695 test_and_set_bit(HFC_CFG_REPORT_SLIP,
4696 &hc->chan[hc->dslot].cfg);
4697 }
4698 /* set RDI report */
4699 if (port[Port_cnt] & 0x020) {
4700 if (debug & DEBUG_HFCMULTI_INIT)
4701 printk(KERN_DEBUG
4702 "%s: PORT set RDI report: "
4703 "card(%d) port(%d)\n",
4704 __func__, HFC_cnt + 1, 1);
4705 test_and_set_bit(HFC_CFG_REPORT_RDI,
4706 &hc->chan[hc->dslot].cfg);
4707 }
4708 /* set CRC-4 Mode */
4709 if (!(port[Port_cnt] & 0x100)) {
4710 if (debug & DEBUG_HFCMULTI_INIT)
4711 printk(KERN_DEBUG "%s: PORT turn on CRC4 report:"
4712 " card(%d) port(%d)\n",
4713 __func__, HFC_cnt + 1, 1);
4714 test_and_set_bit(HFC_CFG_CRC4,
4715 &hc->chan[hc->dslot].cfg);
4716 } else {
4717 if (debug & DEBUG_HFCMULTI_INIT)
4718 printk(KERN_DEBUG "%s: PORT turn off CRC4"
4719 " report: card(%d) port(%d)\n",
4720 __func__, HFC_cnt + 1, 1);
4721 }
4722 /* set forced clock */
4723 if (port[Port_cnt] & 0x0200) {
4724 if (debug & DEBUG_HFCMULTI_INIT)
4725 printk(KERN_DEBUG "%s: PORT force getting clock from "
4726 "E1: card(%d) port(%d)\n",
4727 __func__, HFC_cnt + 1, 1);
4728 test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip);
4729 } else
4730 if (port[Port_cnt] & 0x0400) {
4731 if (debug & DEBUG_HFCMULTI_INIT)
4732 printk(KERN_DEBUG "%s: PORT force putting clock to "
4733 "E1: card(%d) port(%d)\n",
4734 __func__, HFC_cnt + 1, 1);
4735 test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip);
4736 }
4737 /* set JATT PLL */
4738 if (port[Port_cnt] & 0x0800) {
4739 if (debug & DEBUG_HFCMULTI_INIT)
4740 printk(KERN_DEBUG "%s: PORT disable JATT PLL on "
4741 "E1: card(%d) port(%d)\n",
4742 __func__, HFC_cnt + 1, 1);
4743 test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip);
4744 }
4745 /* set elastic jitter buffer */
4746 if (port[Port_cnt] & 0x3000) {
4747 hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3;
4748 if (debug & DEBUG_HFCMULTI_INIT)
4749 printk(KERN_DEBUG
4750 "%s: PORT set elastic "
4751 "buffer to %d: card(%d) port(%d)\n",
4752 __func__, hc->chan[hc->dslot].jitter,
4753 HFC_cnt + 1, 1);
4754 } else
4755 hc->chan[hc->dslot].jitter = 2; /* default */
4756 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1);
b36b654a 4757 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
af69fb3a
KK		 4758 if (ret)
4759 goto free_chan;
4760 hc->created[0] = 1;
4761 return ret;
4762free_chan:
4763 release_port(hc, dch);
4764 return ret;
4765}
4766
4767static int
4768init_multi_port(struct hfc_multi *hc, int pt)
4769{
4770 struct dchannel *dch;
4771 struct bchannel *bch;
4772 int ch, i, ret = 0;
4773 char name[MISDN_MAX_IDLEN];
4774
4775 dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL);
4776 if (!dch)
4777 return -ENOMEM;
4778 dch->debug = debug;
4779 mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change);
4780 dch->hw = hc;
4781 dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
4782 dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
4783 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
4784 dch->dev.D.send = handle_dmsg;
4785 dch->dev.D.ctrl = hfcm_dctrl;
4786 dch->dev.nrbchan = 2;
4787 i = pt << 2;
4788 dch->slot = i + 2;
4789 hc->chan[i + 2].dch = dch;
4790 hc->chan[i + 2].port = pt;
4791 hc->chan[i + 2].nt_timer = -1;
4792 for (ch = 0; ch < dch->dev.nrbchan; ch++) {
4793 bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL);
4794 if (!bch) {
4795 printk(KERN_ERR "%s: no memory for bchannel\n",
4796 __func__);
4797 ret = -ENOMEM;
4798 goto free_chan;
4799 }
4800 hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL);
4801 if (!hc->chan[i + ch].coeff) {
4802 printk(KERN_ERR "%s: no memory for coeffs\n",
4803 __func__);
4804 ret = -ENOMEM;
23b904f3 4805 kfree(bch);
af69fb3a
KK		 4806 goto free_chan;
4807 }
4808 bch->nr = ch + 1;
4809 bch->slot = i + ch;
4810 bch->debug = debug;
4811 mISDN_initbchannel(bch, MAX_DATA_MEM);
4812 bch->hw = hc;
4813 bch->ch.send = handle_bmsg;
4814 bch->ch.ctrl = hfcm_bctrl;
4815 bch->ch.nr = ch + 1;
4816 list_add(&bch->ch.list, &dch->dev.bchannels);
4817 hc->chan[i + ch].bch = bch;
4818 hc->chan[i + ch].port = pt;
ff4cc1de 4819 set_channelmap(bch->nr, dch->dev.channelmap);
af69fb3a
KK		 4820 }
4821 /* set master clock */
4822 if (port[Port_cnt] & 0x001) {
4823 if (debug & DEBUG_HFCMULTI_INIT)
4824 printk(KERN_DEBUG
4825 "%s: PROTOCOL set master clock: "
4826 "card(%d) port(%d)\n",
4827 __func__, HFC_cnt + 1, pt + 1);
4828 if (dch->dev.D.protocol != ISDN_P_TE_S0) {
4829 printk(KERN_ERR "Error: Master clock "
4830 "for port(%d) of card(%d) is only"
4831 " possible with TE-mode\n",
4832 pt + 1, HFC_cnt + 1);
4833 ret = -EINVAL;
4834 goto free_chan;
4835 }
4836 if (hc->masterclk >= 0) {
4837 printk(KERN_ERR "Error: Master clock "
4838 "for port(%d) of card(%d) already "
4839 "defined for port(%d)\n",
4840 pt + 1, HFC_cnt + 1, hc->masterclk+1);
4841 ret = -EINVAL;
4842 goto free_chan;
4843 }
4844 hc->masterclk = pt;
4845 }
4846 /* set transmitter line to non capacitive */
4847 if (port[Port_cnt] & 0x002) {
4848 if (debug & DEBUG_HFCMULTI_INIT)
4849 printk(KERN_DEBUG
4850 "%s: PROTOCOL set non capacitive "
4851 "transmitter: card(%d) port(%d)\n",
4852 __func__, HFC_cnt + 1, pt + 1);
4853 test_and_set_bit(HFC_CFG_NONCAP_TX,
4854 &hc->chan[i + 2].cfg);
4855 }
4856 /* disable E-channel */
4857 if (port[Port_cnt] & 0x004) {
4858 if (debug & DEBUG_HFCMULTI_INIT)
4859 printk(KERN_DEBUG
4860 "%s: PROTOCOL disable E-channel: "
4861 "card(%d) port(%d)\n",
4862 __func__, HFC_cnt + 1, pt + 1);
4863 test_and_set_bit(HFC_CFG_DIS_ECHANNEL,
4864 &hc->chan[i + 2].cfg);
4865 }
b36b654a 4866 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d-%d",
af69fb3a 4867 hc->type, HFC_cnt + 1, pt + 1);
b36b654a 4868 ret = mISDN_register_device(&dch->dev, &hc->pci_dev->dev, name);
af69fb3a
KK		 4869 if (ret)
4870 goto free_chan;
4871 hc->created[pt] = 1;
4872 return ret;
4873free_chan:
4874 release_port(hc, dch);
4875 return ret;
4876}
4877
4878static int
4879hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent)
4880{
4881 struct hm_map *m = (struct hm_map *)ent->driver_data;
4882 int ret_err = 0;
4883 int pt;
4884 struct hfc_multi *hc;
4885 u_long flags;
4886 u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */
8dd2f36f 4887 int i;
af69fb3a
KK		 4888
4889 if (HFC_cnt >= MAX_CARDS) {
4890 printk(KERN_ERR "too many cards (max=%d).\n",
4891 MAX_CARDS);
4892 return -EINVAL;
4893 }
4894 if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) {
4895 printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but "
4896 "type[%d] %d was supplied as module parameter\n",
4897 m->vendor_name, m->card_name, m->type, HFC_cnt,
4898 type[HFC_cnt] & 0xff);
4899 printk(KERN_WARNING "HFC-MULTI: Load module without parameters "
4900 "first, to see cards and their types.");
4901 return -EINVAL;
4902 }
4903 if (debug & DEBUG_HFCMULTI_INIT)
4904 printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n",
4905 __func__, m->vendor_name, m->card_name, m->type,
4906 type[HFC_cnt]);
4907
4908 /* allocate card+fifo structure */
4909 hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL);
4910 if (!hc) {
4911 printk(KERN_ERR "No kmem for HFC-Multi card\n");
4912 return -ENOMEM;
4913 }
4914 spin_lock_init(&hc->lock);
4915 hc->mtyp = m;
4916 hc->type = m->type;
4917 hc->ports = m->ports;
4918 hc->id = HFC_cnt;
4919 hc->pcm = pcm[HFC_cnt];
4920 hc->io_mode = iomode[HFC_cnt];
8dd2f36f 4921 if (dslot[HFC_cnt] < 0 && hc->type == 1) {
af69fb3a
KK		 4922 hc->dslot = 0;
4923 printk(KERN_INFO "HFC-E1 card has disabled D-channel, but "
4924 "31 B-channels\n");
8dd2f36f 4925 } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32 && hc->type == 1) {
af69fb3a
KK		 4926 hc->dslot = dslot[HFC_cnt];
4927 printk(KERN_INFO "HFC-E1 card has alternating D-channel on "
4928 "time slot %d\n", dslot[HFC_cnt]);
4929 } else
4930 hc->dslot = 16;
4931
4932 /* set chip specific features */
4933 hc->masterclk = -1;
4934 if (type[HFC_cnt] & 0x100) {
4935 test_and_set_bit(HFC_CHIP_ULAW, &hc->chip);
8dd2f36f 4936 hc->silence = 0xff; /* ulaw silence */
af69fb3a 4937 } else
8dd2f36f
AE		 4938 hc->silence = 0x2a; /* alaw silence */
4939 if ((poll >> 1) > sizeof(hc->silence_data)) {
4940 printk(KERN_ERR "HFCMULTI error: silence_data too small, "
4941 "please fix\n");
4942 return -EINVAL;
4943 }
4944 for (i = 0; i < (poll >> 1); i++)
4945 hc->silence_data[i] = hc->silence;
4946
af69fb3a
KK		 4947 if (!(type[HFC_cnt] & 0x200))
4948 test_and_set_bit(HFC_CHIP_DTMF, &hc->chip);
4949
4950 if (type[HFC_cnt] & 0x800)
4951 test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4952 if (type[HFC_cnt] & 0x1000) {
4953 test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip);
4954 test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip);
4955 }
4956 if (type[HFC_cnt] & 0x4000)
4957 test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip);
4958 if (type[HFC_cnt] & 0x8000)
4959 test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip);
4960 hc->slots = 32;
4961 if (type[HFC_cnt] & 0x10000)
4962 hc->slots = 64;
4963 if (type[HFC_cnt] & 0x20000)
4964 hc->slots = 128;
4965 if (type[HFC_cnt] & 0x80000) {
4966 test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip);
4967 hc->wdcount = 0;
4968 hc->wdbyte = V_GPIO_OUT2;
4969 printk(KERN_NOTICE "Watchdog enabled\n");
4970 }
4971
4972 /* setup pci, hc->slots may change due to PLXSD */
4973 ret_err = setup_pci(hc, pdev, ent);
4974 if (ret_err) {
4975 if (hc == syncmaster)
4976 syncmaster = NULL;
4977 kfree(hc);
4978 return ret_err;
4979 }
4980
4981 /* crate channels */
4982 for (pt = 0; pt < hc->ports; pt++) {
4983 if (Port_cnt >= MAX_PORTS) {
4984 printk(KERN_ERR "too many ports (max=%d).\n",
4985 MAX_PORTS);
4986 ret_err = -EINVAL;
4987 goto free_card;
4988 }
4989 if (hc->type == 1)
4990 ret_err = init_e1_port(hc, m);
4991 else
4992 ret_err = init_multi_port(hc, pt);
4993 if (debug & DEBUG_HFCMULTI_INIT)
4994 printk(KERN_DEBUG
4995 "%s: Registering D-channel, card(%d) port(%d)"
4996 "result %d\n",
4997 __func__, HFC_cnt + 1, pt, ret_err);
4998
4999 if (ret_err) {
5000 while (pt) { /* release already registered ports */
5001 pt--;
5002 release_port(hc, hc->chan[(pt << 2) + 2].dch);
5003 }
5004 goto free_card;
5005 }
5006 Port_cnt++;
5007 }
5008
5009 /* disp switches */
5010 switch (m->dip_type) {
5011 case DIP_4S:
5012 /*
69e656cc 5013 * Get DIP setting for beroNet 1S/2S/4S cards
af69fb3a
KK		 5014 * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) +
5015 * GPI 19/23 (R_GPI_IN2))
5016 */
5017 dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) |
5018 ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) |
5019 (~HFC_inb(hc, R_GPI_IN2) & 0x08);
5020
5021 /* Port mode (TE/NT) jumpers */
5022 pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf);
5023
5024 if (test_bit(HFC_CHIP_B410P, &hc->chip))
5025 pmj = ~pmj & 0xf;
5026
5027 printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n",
5028 m->vendor_name, m->card_name, dips, pmj);
5029 break;
5030 case DIP_8S:
5031 /*
69e656cc
KK		 5032 * Get DIP Setting for beroNet 8S0+ cards
5033 * Enable PCI auxbridge function
af69fb3a
KK		 5034 */
5035 HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK);
5036 /* prepare access to auxport */
5037 outw(0x4000, hc->pci_iobase + 4);
5038 /*
5039 * some dummy reads are required to
5040 * read valid DIP switch data
5041 */
5042 dips = inb(hc->pci_iobase);
5043 dips = inb(hc->pci_iobase);
5044 dips = inb(hc->pci_iobase);
5045 dips = ~inb(hc->pci_iobase) & 0x3F;
5046 outw(0x0, hc->pci_iobase + 4);
5047 /* disable PCI auxbridge function */
5048 HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK);
5049 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5050 m->vendor_name, m->card_name, dips);
5051 break;
5052 case DIP_E1:
5053 /*
5054 * get DIP Setting for beroNet E1 cards
5055 * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0)
5056 */
5057 dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4;
5058 printk(KERN_INFO "%s: %s DIPs(0x%x)\n",
5059 m->vendor_name, m->card_name, dips);
5060 break;
5061 }
5062
5063 /* add to list */
5064 spin_lock_irqsave(&HFClock, flags);
5065 list_add_tail(&hc->list, &HFClist);
5066 spin_unlock_irqrestore(&HFClock, flags);
5067
3bd69ad1
AE		 5068 /* use as clock source */
5069 if (clock == HFC_cnt + 1)
5070 hc->iclock = mISDN_register_clock("HFCMulti", 0, clockctl, hc);
5071
af69fb3a
KK		 5072 /* initialize hardware */
5073 ret_err = init_card(hc);
5074 if (ret_err) {
5075 printk(KERN_ERR "init card returns %d\n", ret_err);
5076 release_card(hc);
5077 return ret_err;
5078 }
5079
5080 /* start IRQ and return */
5081 spin_lock_irqsave(&hc->lock, flags);
5082 enable_hwirq(hc);
5083 spin_unlock_irqrestore(&hc->lock, flags);
5084 return 0;
5085
5086free_card:
5087 release_io_hfcmulti(hc);
5088 if (hc == syncmaster)
5089 syncmaster = NULL;
5090 kfree(hc);
5091 return ret_err;
5092}
5093
5094static void __devexit hfc_remove_pci(struct pci_dev *pdev)
5095{
5096 struct hfc_multi *card = pci_get_drvdata(pdev);
5097 u_long flags;
5098
5099 if (debug)
5100 printk(KERN_INFO "removing hfc_multi card vendor:%x "
5101 "device:%x subvendor:%x subdevice:%x\n",
5102 pdev->vendor, pdev->device,
5103 pdev->subsystem_vendor, pdev->subsystem_device);
5104
5105 if (card) {
5106 spin_lock_irqsave(&HFClock, flags);
5107 release_card(card);
5108 spin_unlock_irqrestore(&HFClock, flags);
5109 } else {
5110 if (debug)
5111 printk(KERN_WARNING "%s: drvdata allready removed\n",
5112 __func__);
5113 }
5114}
5115
5116#define VENDOR_CCD "Cologne Chip AG"
5117#define VENDOR_BN "beroNet GmbH"
5118#define VENDOR_DIG "Digium Inc."
5119#define VENDOR_JH "Junghanns.NET GmbH"
5120#define VENDOR_PRIM "PrimuX"
5121
5122static const struct hm_map hfcm_map[] = {
5123/*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0},
31981db0 5124/*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0},
af69fb3a
KK		 5125/*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0},
5126/*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0},
5127/*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0},
5128/*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0},
31981db0 5129/*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0},
af69fb3a
KK		 5130/*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0},
5131/*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO},
5132/*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0},
5133/*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0},
5134/*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0},
5135
5136/*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0},
5137/*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S,
5138 HFC_IO_MODE_REGIO},
5139/*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0},
5140/*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0},
5141
5142/*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0},
5143/*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5144/*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0},
5145
5146/*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0},
5147/*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0},
5148/*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5149/*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0},
5150
5151/*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0},
5152/*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0},
5153/*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0},
5154
5155/*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0,
5156 HFC_IO_MODE_PLXSD},
5157/*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0,
5158 HFC_IO_MODE_PLXSD},
5159/*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0},
5160/*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0},
5161/*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0},
5162};
5163
5164#undef H
5165#define H(x) ((unsigned long)&hfcm_map[x])
5166static struct pci_device_id hfmultipci_ids[] __devinitdata = {
5167
5168 /* Cards with HFC-4S Chip */
5169 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5170 PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */
5171 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5172 PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */
5173 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5174 PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */
5175 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5176 PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */
5177 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5178 PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */
5179 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5180 PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */
5181 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5182 PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */
5183 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5184 PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */
5185 { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S,
5186 PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)},
5187 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5188 PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */
5189 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5190 PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)},
5191 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5192 PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */
5193 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5194 PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */
5195 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD,
5196 PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */
5197
5198 /* Cards with HFC-8S Chip */
5199 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5200 PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */
5201 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5202 PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */
5203 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5204 PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */
5205 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
69e656cc 5206 PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, /* IOB8ST Recording */
af69fb3a
KK		 5207 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5208 PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */
5209 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5210 PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */
5211 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5212 PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */
5213 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD,
5214 PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */
5215
5216
5217 /* Cards with HFC-E1 Chip */
5218 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5219 PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */
5220 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5221 PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */
5222 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5223 PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */
5224 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5225 PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */
5226
5227 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5228 PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */
5229 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5230 PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */
5231 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD,
5232 PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */
5233
5234 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5235 PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */
5236 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD,
5237 PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */
5238 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID,
5239 0, 0, 0},
5240 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID,
5241 0, 0, 0},
5242 { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID,
5243 0, 0, 0},
5244 {0, }
5245};
5246#undef H
5247
5248MODULE_DEVICE_TABLE(pci, hfmultipci_ids);
5249
5250static int
5251hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
5252{
5253 struct hm_map *m = (struct hm_map *)ent->driver_data;
5254 int ret;
5255
69e656cc
KK		 5256 if (m == NULL && ent->vendor == PCI_VENDOR_ID_CCD && (
5257 ent->device == PCI_DEVICE_ID_CCD_HFC4S ||
5258 ent->device == PCI_DEVICE_ID_CCD_HFC8S ||
5259 ent->device == PCI_DEVICE_ID_CCD_HFCE1)) {
5260 printk(KERN_ERR
5261 "Unknown HFC multiport controller (vendor:%x device:%x "
5262 "subvendor:%x subdevice:%x)\n", ent->vendor, ent->device,
5263 ent->subvendor, ent->subdevice);
5264 printk(KERN_ERR
5265 "Please contact the driver maintainer for support.\n");
af69fb3a
KK		 5266 return -ENODEV;
5267 }
5268 ret = hfcmulti_init(pdev, ent);
5269 if (ret)
5270 return ret;
5271 HFC_cnt++;
5272 printk(KERN_INFO "%d devices registered\n", HFC_cnt);
5273 return 0;
5274}
5275
5276static struct pci_driver hfcmultipci_driver = {
5277 .name = "hfc_multi",
5278 .probe = hfcmulti_probe,
5279 .remove = __devexit_p(hfc_remove_pci),
5280 .id_table = hfmultipci_ids,
5281};
5282
5283static void __exit
5284HFCmulti_cleanup(void)
5285{
5286 struct hfc_multi *card, *next;
5287
69e656cc 5288 /* get rid of all devices of this driver */
af69fb3a
KK		 5289 list_for_each_entry_safe(card, next, &HFClist, list)
5290 release_card(card);
af69fb3a
KK		 5291 pci_unregister_driver(&hfcmultipci_driver);
5292}
5293
5294static int __init
5295HFCmulti_init(void)
5296{
5297 int err;
5298
69e656cc
KK		 5299 printk(KERN_INFO "mISDN: HFC-multi driver %s\n", HFC_MULTI_VERSION);
5300
af69fb3a 5301#ifdef IRQ_DEBUG
69e656cc 5302 printk(KERN_DEBUG "%s: IRQ_DEBUG IS ENABLED!\n", __func__);
af69fb3a
KK		 5303#endif
5304
5305 spin_lock_init(&HFClock);
5306 spin_lock_init(&plx_lock);
5307
5308 if (debug & DEBUG_HFCMULTI_INIT)
5309 printk(KERN_DEBUG "%s: init entered\n", __func__);
5310
af69fb3a
KK		 5311 switch (poll) {
5312 case 0:
5313 poll_timer = 6;
5314 poll = 128;
5315 break;
af69fb3a
KK		 5316 case 8:
5317 poll_timer = 2;
5318 break;
5319 case 16:
5320 poll_timer = 3;
5321 break;
5322 case 32:
5323 poll_timer = 4;
5324 break;
5325 case 64:
5326 poll_timer = 5;
5327 break;
5328 case 128:
5329 poll_timer = 6;
5330 break;
5331 case 256:
5332 poll_timer = 7;
5333 break;
5334 default:
5335 printk(KERN_ERR
5336 "%s: Wrong poll value (%d).\n", __func__, poll);
5337 err = -EINVAL;
5338 return err;
5339
5340 }
5341
3bd69ad1
AE		 5342 if (!clock)
5343 clock = 1;
5344
af69fb3a
KK		 5345 err = pci_register_driver(&hfcmultipci_driver);
5346 if (err < 0) {
5347 printk(KERN_ERR "error registering pci driver: %x\n", err);
af69fb3a
KK		 5348 return err;
5349 }
5350 return 0;
5351}
5352
5353
5354module_init(HFCmulti_init);
5355module_exit(HFCmulti_cleanup);
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