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af69fb3a KK |
1 | /* |
2 | * hfcmulti.c low level driver for hfc-4s/hfc-8s/hfc-e1 based cards | |
3 | * | |
4 | * Author Andreas Eversberg (jolly@eversberg.eu) | |
5 | * ported to mqueue mechanism: | |
6 | * Peter Sprenger (sprengermoving-bytes.de) | |
7 | * | |
8 | * inspired by existing hfc-pci driver: | |
9 | * Copyright 1999 by Werner Cornelius (werner@isdn-development.de) | |
10 | * Copyright 2008 by Karsten Keil (kkeil@suse.de) | |
11 | * Copyright 2008 by Andreas Eversberg (jolly@eversberg.eu) | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2, or (at your option) | |
16 | * any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | * | |
28 | * Thanks to Cologne Chip AG for this great controller! | |
29 | */ | |
30 | ||
31 | /* | |
32 | * module parameters: | |
33 | * type: | |
34 | * By default (0), the card is automatically detected. | |
35 | * Or use the following combinations: | |
36 | * Bit 0-7 = 0x00001 = HFC-E1 (1 port) | |
37 | * or Bit 0-7 = 0x00004 = HFC-4S (4 ports) | |
38 | * or Bit 0-7 = 0x00008 = HFC-8S (8 ports) | |
39 | * Bit 8 = 0x00100 = uLaw (instead of aLaw) | |
40 | * Bit 9 = 0x00200 = Disable DTMF detect on all B-channels via hardware | |
41 | * Bit 10 = spare | |
42 | * Bit 11 = 0x00800 = Force PCM bus into slave mode. (otherwhise auto) | |
43 | * or Bit 12 = 0x01000 = Force PCM bus into master mode. (otherwhise auto) | |
44 | * Bit 13 = spare | |
45 | * Bit 14 = 0x04000 = Use external ram (128K) | |
46 | * Bit 15 = 0x08000 = Use external ram (512K) | |
47 | * Bit 16 = 0x10000 = Use 64 timeslots instead of 32 | |
48 | * or Bit 17 = 0x20000 = Use 128 timeslots instead of anything else | |
49 | * Bit 18 = spare | |
50 | * Bit 19 = 0x80000 = Send the Watchdog a Signal (Dual E1 with Watchdog) | |
51 | * (all other bits are reserved and shall be 0) | |
52 | * example: 0x20204 one HFC-4S with dtmf detection and 128 timeslots on PCM | |
53 | * bus (PCM master) | |
54 | * | |
55 | * port: (optional or required for all ports on all installed cards) | |
56 | * HFC-4S/HFC-8S only bits: | |
57 | * Bit 0 = 0x001 = Use master clock for this S/T interface | |
58 | * (ony once per chip). | |
59 | * Bit 1 = 0x002 = transmitter line setup (non capacitive mode) | |
60 | * Don't use this unless you know what you are doing! | |
61 | * Bit 2 = 0x004 = Disable E-channel. (No E-channel processing) | |
62 | * example: 0x0001,0x0000,0x0000,0x0000 one HFC-4S with master clock | |
63 | * received from port 1 | |
64 | * | |
65 | * HFC-E1 only bits: | |
66 | * Bit 0 = 0x0001 = interface: 0=copper, 1=optical | |
67 | * Bit 1 = 0x0002 = reserved (later for 32 B-channels transparent mode) | |
68 | * Bit 2 = 0x0004 = Report LOS | |
69 | * Bit 3 = 0x0008 = Report AIS | |
70 | * Bit 4 = 0x0010 = Report SLIP | |
71 | * Bit 5 = 0x0020 = Report RDI | |
72 | * Bit 8 = 0x0100 = Turn off CRC-4 Multiframe Mode, use double frame | |
73 | * mode instead. | |
74 | * Bit 9 = 0x0200 = Force get clock from interface, even in NT mode. | |
75 | * or Bit 10 = 0x0400 = Force put clock to interface, even in TE mode. | |
76 | * Bit 11 = 0x0800 = Use direct RX clock for PCM sync rather than PLL. | |
77 | * (E1 only) | |
78 | * Bit 12-13 = 0xX000 = elastic jitter buffer (1-3), Set both bits to 0 | |
79 | * for default. | |
80 | * (all other bits are reserved and shall be 0) | |
81 | * | |
82 | * debug: | |
83 | * NOTE: only one debug value must be given for all cards | |
84 | * enable debugging (see hfc_multi.h for debug options) | |
85 | * | |
86 | * poll: | |
87 | * NOTE: only one poll value must be given for all cards | |
88 | * Give the number of samples for each fifo process. | |
89 | * By default 128 is used. Decrease to reduce delay, increase to | |
90 | * reduce cpu load. If unsure, don't mess with it! | |
91 | * Valid is 8, 16, 32, 64, 128, 256. | |
92 | * | |
93 | * pcm: | |
94 | * NOTE: only one pcm value must be given for every card. | |
95 | * The PCM bus id tells the mISDNdsp module about the connected PCM bus. | |
96 | * By default (0), the PCM bus id is 100 for the card that is PCM master. | |
97 | * If multiple cards are PCM master (because they are not interconnected), | |
98 | * each card with PCM master will have increasing PCM id. | |
99 | * All PCM busses with the same ID are expected to be connected and have | |
100 | * common time slots slots. | |
101 | * Only one chip of the PCM bus must be master, the others slave. | |
102 | * -1 means no support of PCM bus not even. | |
103 | * Omit this value, if all cards are interconnected or none is connected. | |
104 | * If unsure, don't give this parameter. | |
105 | * | |
106 | * dslot: | |
107 | * NOTE: only one poll value must be given for every card. | |
108 | * Also this value must be given for non-E1 cards. If omitted, the E1 | |
109 | * card has D-channel on time slot 16, which is default. | |
110 | * If 1..15 or 17..31, an alternate time slot is used for D-channel. | |
111 | * In this case, the application must be able to handle this. | |
112 | * If -1 is given, the D-channel is disabled and all 31 slots can be used | |
113 | * for B-channel. (only for specific applications) | |
114 | * If you don't know how to use it, you don't need it! | |
115 | * | |
116 | * iomode: | |
117 | * NOTE: only one mode value must be given for every card. | |
118 | * -> See hfc_multi.h for HFC_IO_MODE_* values | |
119 | * By default, the IO mode is pci memory IO (MEMIO). | |
120 | * Some cards requre specific IO mode, so it cannot be changed. | |
121 | * It may be usefull to set IO mode to register io (REGIO) to solve | |
122 | * PCI bridge problems. | |
123 | * If unsure, don't give this parameter. | |
124 | * | |
125 | * clockdelay_nt: | |
126 | * NOTE: only one clockdelay_nt value must be given once for all cards. | |
127 | * Give the value of the clock control register (A_ST_CLK_DLY) | |
128 | * of the S/T interfaces in NT mode. | |
129 | * This register is needed for the TBR3 certification, so don't change it. | |
130 | * | |
131 | * clockdelay_te: | |
132 | * NOTE: only one clockdelay_te value must be given once | |
133 | * Give the value of the clock control register (A_ST_CLK_DLY) | |
134 | * of the S/T interfaces in TE mode. | |
135 | * This register is needed for the TBR3 certification, so don't change it. | |
136 | */ | |
137 | ||
138 | /* | |
139 | * debug register access (never use this, it will flood your system log) | |
140 | * #define HFC_REGISTER_DEBUG | |
141 | */ | |
142 | ||
31981db0 | 143 | static const char *hfcmulti_revision = "2.02"; |
af69fb3a KK |
144 | |
145 | #include <linux/module.h> | |
146 | #include <linux/pci.h> | |
147 | #include <linux/delay.h> | |
148 | #include <linux/mISDNhw.h> | |
149 | #include <linux/mISDNdsp.h> | |
150 | ||
151 | /* | |
152 | #define IRQCOUNT_DEBUG | |
153 | #define IRQ_DEBUG | |
154 | */ | |
155 | ||
156 | #include "hfc_multi.h" | |
157 | #ifdef ECHOPREP | |
158 | #include "gaintab.h" | |
159 | #endif | |
160 | ||
161 | #define MAX_CARDS 8 | |
162 | #define MAX_PORTS (8 * MAX_CARDS) | |
163 | ||
164 | static LIST_HEAD(HFClist); | |
165 | static spinlock_t HFClock; /* global hfc list lock */ | |
166 | ||
167 | static void ph_state_change(struct dchannel *); | |
168 | static void (*hfc_interrupt)(void); | |
169 | static void (*register_interrupt)(void); | |
170 | static int (*unregister_interrupt)(void); | |
171 | static int interrupt_registered; | |
172 | ||
173 | static struct hfc_multi *syncmaster; | |
5b834354 | 174 | static int plxsd_master; /* if we have a master card (yet) */ |
af69fb3a | 175 | static spinlock_t plx_lock; /* may not acquire other lock inside */ |
af69fb3a KK |
176 | |
177 | #define TYP_E1 1 | |
178 | #define TYP_4S 4 | |
179 | #define TYP_8S 8 | |
180 | ||
181 | static int poll_timer = 6; /* default = 128 samples = 16ms */ | |
182 | /* number of POLL_TIMER interrupts for G2 timeout (ca 1s) */ | |
183 | static int nt_t1_count[] = { 3840, 1920, 960, 480, 240, 120, 60, 30 }; | |
184 | #define CLKDEL_TE 0x0f /* CLKDEL in TE mode */ | |
185 | #define CLKDEL_NT 0x6c /* CLKDEL in NT mode | |
186 | (0x60 MUST be included!) */ | |
187 | static u_char silence = 0xff; /* silence by LAW */ | |
188 | ||
189 | #define DIP_4S 0x1 /* DIP Switches for Beronet 1S/2S/4S cards */ | |
190 | #define DIP_8S 0x2 /* DIP Switches for Beronet 8S+ cards */ | |
191 | #define DIP_E1 0x3 /* DIP Switches for Beronet E1 cards */ | |
192 | ||
193 | /* | |
194 | * module stuff | |
195 | */ | |
196 | ||
197 | static uint type[MAX_CARDS]; | |
198 | static uint pcm[MAX_CARDS]; | |
199 | static uint dslot[MAX_CARDS]; | |
200 | static uint iomode[MAX_CARDS]; | |
201 | static uint port[MAX_PORTS]; | |
202 | static uint debug; | |
203 | static uint poll; | |
204 | static uint timer; | |
205 | static uint clockdelay_te = CLKDEL_TE; | |
206 | static uint clockdelay_nt = CLKDEL_NT; | |
207 | ||
208 | static int HFC_cnt, Port_cnt, PCM_cnt = 99; | |
209 | ||
210 | MODULE_AUTHOR("Andreas Eversberg"); | |
211 | MODULE_LICENSE("GPL"); | |
212 | module_param(debug, uint, S_IRUGO | S_IWUSR); | |
213 | module_param(poll, uint, S_IRUGO | S_IWUSR); | |
214 | module_param(timer, uint, S_IRUGO | S_IWUSR); | |
215 | module_param(clockdelay_te, uint, S_IRUGO | S_IWUSR); | |
216 | module_param(clockdelay_nt, uint, S_IRUGO | S_IWUSR); | |
217 | module_param_array(type, uint, NULL, S_IRUGO | S_IWUSR); | |
218 | module_param_array(pcm, uint, NULL, S_IRUGO | S_IWUSR); | |
219 | module_param_array(dslot, uint, NULL, S_IRUGO | S_IWUSR); | |
220 | module_param_array(iomode, uint, NULL, S_IRUGO | S_IWUSR); | |
221 | module_param_array(port, uint, NULL, S_IRUGO | S_IWUSR); | |
222 | ||
223 | #ifdef HFC_REGISTER_DEBUG | |
224 | #define HFC_outb(hc, reg, val) \ | |
225 | (hc->HFC_outb(hc, reg, val, __func__, __LINE__)) | |
226 | #define HFC_outb_nodebug(hc, reg, val) \ | |
227 | (hc->HFC_outb_nodebug(hc, reg, val, __func__, __LINE__)) | |
228 | #define HFC_inb(hc, reg) \ | |
229 | (hc->HFC_inb(hc, reg, __func__, __LINE__)) | |
230 | #define HFC_inb_nodebug(hc, reg) \ | |
231 | (hc->HFC_inb_nodebug(hc, reg, __func__, __LINE__)) | |
232 | #define HFC_inw(hc, reg) \ | |
233 | (hc->HFC_inw(hc, reg, __func__, __LINE__)) | |
234 | #define HFC_inw_nodebug(hc, reg) \ | |
235 | (hc->HFC_inw_nodebug(hc, reg, __func__, __LINE__)) | |
236 | #define HFC_wait(hc) \ | |
237 | (hc->HFC_wait(hc, __func__, __LINE__)) | |
238 | #define HFC_wait_nodebug(hc) \ | |
239 | (hc->HFC_wait_nodebug(hc, __func__, __LINE__)) | |
240 | #else | |
241 | #define HFC_outb(hc, reg, val) (hc->HFC_outb(hc, reg, val)) | |
242 | #define HFC_outb_nodebug(hc, reg, val) (hc->HFC_outb_nodebug(hc, reg, val)) | |
243 | #define HFC_inb(hc, reg) (hc->HFC_inb(hc, reg)) | |
244 | #define HFC_inb_nodebug(hc, reg) (hc->HFC_inb_nodebug(hc, reg)) | |
245 | #define HFC_inw(hc, reg) (hc->HFC_inw(hc, reg)) | |
246 | #define HFC_inw_nodebug(hc, reg) (hc->HFC_inw_nodebug(hc, reg)) | |
247 | #define HFC_wait(hc) (hc->HFC_wait(hc)) | |
248 | #define HFC_wait_nodebug(hc) (hc->HFC_wait_nodebug(hc)) | |
249 | #endif | |
250 | ||
251 | /* HFC_IO_MODE_PCIMEM */ | |
252 | static void | |
253 | #ifdef HFC_REGISTER_DEBUG | |
254 | HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val, | |
255 | const char *function, int line) | |
256 | #else | |
257 | HFC_outb_pcimem(struct hfc_multi *hc, u_char reg, u_char val) | |
258 | #endif | |
259 | { | |
260 | writeb(val, (hc->pci_membase)+reg); | |
261 | } | |
262 | static u_char | |
263 | #ifdef HFC_REGISTER_DEBUG | |
264 | HFC_inb_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
265 | #else | |
266 | HFC_inb_pcimem(struct hfc_multi *hc, u_char reg) | |
267 | #endif | |
268 | { | |
269 | return readb((hc->pci_membase)+reg); | |
270 | } | |
271 | static u_short | |
272 | #ifdef HFC_REGISTER_DEBUG | |
273 | HFC_inw_pcimem(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
274 | #else | |
275 | HFC_inw_pcimem(struct hfc_multi *hc, u_char reg) | |
276 | #endif | |
277 | { | |
278 | return readw((hc->pci_membase)+reg); | |
279 | } | |
280 | static void | |
281 | #ifdef HFC_REGISTER_DEBUG | |
282 | HFC_wait_pcimem(struct hfc_multi *hc, const char *function, int line) | |
283 | #else | |
284 | HFC_wait_pcimem(struct hfc_multi *hc) | |
285 | #endif | |
286 | { | |
287 | while (readb((hc->pci_membase)+R_STATUS) & V_BUSY); | |
288 | } | |
289 | ||
290 | /* HFC_IO_MODE_REGIO */ | |
291 | static void | |
292 | #ifdef HFC_REGISTER_DEBUG | |
293 | HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val, | |
294 | const char *function, int line) | |
295 | #else | |
296 | HFC_outb_regio(struct hfc_multi *hc, u_char reg, u_char val) | |
297 | #endif | |
298 | { | |
299 | outb(reg, (hc->pci_iobase)+4); | |
300 | outb(val, hc->pci_iobase); | |
301 | } | |
302 | static u_char | |
303 | #ifdef HFC_REGISTER_DEBUG | |
304 | HFC_inb_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
305 | #else | |
306 | HFC_inb_regio(struct hfc_multi *hc, u_char reg) | |
307 | #endif | |
308 | { | |
309 | outb(reg, (hc->pci_iobase)+4); | |
310 | return inb(hc->pci_iobase); | |
311 | } | |
312 | static u_short | |
313 | #ifdef HFC_REGISTER_DEBUG | |
314 | HFC_inw_regio(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
315 | #else | |
316 | HFC_inw_regio(struct hfc_multi *hc, u_char reg) | |
317 | #endif | |
318 | { | |
319 | outb(reg, (hc->pci_iobase)+4); | |
320 | return inw(hc->pci_iobase); | |
321 | } | |
322 | static void | |
323 | #ifdef HFC_REGISTER_DEBUG | |
324 | HFC_wait_regio(struct hfc_multi *hc, const char *function, int line) | |
325 | #else | |
326 | HFC_wait_regio(struct hfc_multi *hc) | |
327 | #endif | |
328 | { | |
329 | outb(R_STATUS, (hc->pci_iobase)+4); | |
330 | while (inb(hc->pci_iobase) & V_BUSY); | |
331 | } | |
332 | ||
333 | #ifdef HFC_REGISTER_DEBUG | |
334 | static void | |
335 | HFC_outb_debug(struct hfc_multi *hc, u_char reg, u_char val, | |
336 | const char *function, int line) | |
337 | { | |
338 | char regname[256] = "", bits[9] = "xxxxxxxx"; | |
339 | int i; | |
340 | ||
341 | i = -1; | |
342 | while (hfc_register_names[++i].name) { | |
343 | if (hfc_register_names[i].reg == reg) | |
344 | strcat(regname, hfc_register_names[i].name); | |
345 | } | |
346 | if (regname[0] == '\0') | |
347 | strcpy(regname, "register"); | |
348 | ||
349 | bits[7] = '0'+(!!(val&1)); | |
350 | bits[6] = '0'+(!!(val&2)); | |
351 | bits[5] = '0'+(!!(val&4)); | |
352 | bits[4] = '0'+(!!(val&8)); | |
353 | bits[3] = '0'+(!!(val&16)); | |
354 | bits[2] = '0'+(!!(val&32)); | |
355 | bits[1] = '0'+(!!(val&64)); | |
356 | bits[0] = '0'+(!!(val&128)); | |
357 | printk(KERN_DEBUG | |
358 | "HFC_outb(chip %d, %02x=%s, 0x%02x=%s); in %s() line %d\n", | |
359 | hc->id, reg, regname, val, bits, function, line); | |
360 | HFC_outb_nodebug(hc, reg, val); | |
361 | } | |
362 | static u_char | |
363 | HFC_inb_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
364 | { | |
365 | char regname[256] = "", bits[9] = "xxxxxxxx"; | |
366 | u_char val = HFC_inb_nodebug(hc, reg); | |
367 | int i; | |
368 | ||
369 | i = 0; | |
370 | while (hfc_register_names[i++].name) | |
371 | ; | |
372 | while (hfc_register_names[++i].name) { | |
373 | if (hfc_register_names[i].reg == reg) | |
374 | strcat(regname, hfc_register_names[i].name); | |
375 | } | |
376 | if (regname[0] == '\0') | |
377 | strcpy(regname, "register"); | |
378 | ||
379 | bits[7] = '0'+(!!(val&1)); | |
380 | bits[6] = '0'+(!!(val&2)); | |
381 | bits[5] = '0'+(!!(val&4)); | |
382 | bits[4] = '0'+(!!(val&8)); | |
383 | bits[3] = '0'+(!!(val&16)); | |
384 | bits[2] = '0'+(!!(val&32)); | |
385 | bits[1] = '0'+(!!(val&64)); | |
386 | bits[0] = '0'+(!!(val&128)); | |
387 | printk(KERN_DEBUG | |
388 | "HFC_inb(chip %d, %02x=%s) = 0x%02x=%s; in %s() line %d\n", | |
389 | hc->id, reg, regname, val, bits, function, line); | |
390 | return val; | |
391 | } | |
392 | static u_short | |
393 | HFC_inw_debug(struct hfc_multi *hc, u_char reg, const char *function, int line) | |
394 | { | |
395 | char regname[256] = ""; | |
396 | u_short val = HFC_inw_nodebug(hc, reg); | |
397 | int i; | |
398 | ||
399 | i = 0; | |
400 | while (hfc_register_names[i++].name) | |
401 | ; | |
402 | while (hfc_register_names[++i].name) { | |
403 | if (hfc_register_names[i].reg == reg) | |
404 | strcat(regname, hfc_register_names[i].name); | |
405 | } | |
406 | if (regname[0] == '\0') | |
407 | strcpy(regname, "register"); | |
408 | ||
409 | printk(KERN_DEBUG | |
410 | "HFC_inw(chip %d, %02x=%s) = 0x%04x; in %s() line %d\n", | |
411 | hc->id, reg, regname, val, function, line); | |
412 | return val; | |
413 | } | |
414 | static void | |
415 | HFC_wait_debug(struct hfc_multi *hc, const char *function, int line) | |
416 | { | |
417 | printk(KERN_DEBUG "HFC_wait(chip %d); in %s() line %d\n", | |
418 | hc->id, function, line); | |
419 | HFC_wait_nodebug(hc); | |
420 | } | |
421 | #endif | |
422 | ||
423 | /* write fifo data (REGIO) */ | |
5b834354 | 424 | static void |
af69fb3a KK |
425 | write_fifo_regio(struct hfc_multi *hc, u_char *data, int len) |
426 | { | |
427 | outb(A_FIFO_DATA0, (hc->pci_iobase)+4); | |
428 | while (len>>2) { | |
b3e0aeeb | 429 | outl(cpu_to_le32(*(u32 *)data), hc->pci_iobase); |
af69fb3a KK |
430 | data += 4; |
431 | len -= 4; | |
432 | } | |
433 | while (len>>1) { | |
b3e0aeeb | 434 | outw(cpu_to_le16(*(u16 *)data), hc->pci_iobase); |
af69fb3a KK |
435 | data += 2; |
436 | len -= 2; | |
437 | } | |
438 | while (len) { | |
439 | outb(*data, hc->pci_iobase); | |
440 | data++; | |
441 | len--; | |
442 | } | |
443 | } | |
444 | /* write fifo data (PCIMEM) */ | |
5b834354 | 445 | static void |
af69fb3a KK |
446 | write_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) |
447 | { | |
448 | while (len>>2) { | |
b3e0aeeb KK |
449 | writel(cpu_to_le32(*(u32 *)data), |
450 | hc->pci_membase + A_FIFO_DATA0); | |
af69fb3a KK |
451 | data += 4; |
452 | len -= 4; | |
453 | } | |
454 | while (len>>1) { | |
b3e0aeeb KK |
455 | writew(cpu_to_le16(*(u16 *)data), |
456 | hc->pci_membase + A_FIFO_DATA0); | |
af69fb3a KK |
457 | data += 2; |
458 | len -= 2; | |
459 | } | |
460 | while (len) { | |
b3e0aeeb | 461 | writeb(*data, hc->pci_membase + A_FIFO_DATA0); |
af69fb3a KK |
462 | data++; |
463 | len--; | |
464 | } | |
465 | } | |
466 | /* read fifo data (REGIO) */ | |
5b834354 | 467 | static void |
af69fb3a KK |
468 | read_fifo_regio(struct hfc_multi *hc, u_char *data, int len) |
469 | { | |
470 | outb(A_FIFO_DATA0, (hc->pci_iobase)+4); | |
471 | while (len>>2) { | |
b3e0aeeb | 472 | *(u32 *)data = le32_to_cpu(inl(hc->pci_iobase)); |
af69fb3a KK |
473 | data += 4; |
474 | len -= 4; | |
475 | } | |
476 | while (len>>1) { | |
b3e0aeeb | 477 | *(u16 *)data = le16_to_cpu(inw(hc->pci_iobase)); |
af69fb3a KK |
478 | data += 2; |
479 | len -= 2; | |
480 | } | |
481 | while (len) { | |
482 | *data = inb(hc->pci_iobase); | |
483 | data++; | |
484 | len--; | |
485 | } | |
486 | } | |
487 | ||
488 | /* read fifo data (PCIMEM) */ | |
5b834354 | 489 | static void |
af69fb3a KK |
490 | read_fifo_pcimem(struct hfc_multi *hc, u_char *data, int len) |
491 | { | |
492 | while (len>>2) { | |
493 | *(u32 *)data = | |
b3e0aeeb | 494 | le32_to_cpu(readl(hc->pci_membase + A_FIFO_DATA0)); |
af69fb3a KK |
495 | data += 4; |
496 | len -= 4; | |
497 | } | |
498 | while (len>>1) { | |
499 | *(u16 *)data = | |
b3e0aeeb | 500 | le16_to_cpu(readw(hc->pci_membase + A_FIFO_DATA0)); |
af69fb3a KK |
501 | data += 2; |
502 | len -= 2; | |
503 | } | |
504 | while (len) { | |
b3e0aeeb | 505 | *data = readb(hc->pci_membase + A_FIFO_DATA0); |
af69fb3a KK |
506 | data++; |
507 | len--; | |
508 | } | |
509 | } | |
510 | ||
511 | ||
512 | static void | |
513 | enable_hwirq(struct hfc_multi *hc) | |
514 | { | |
515 | hc->hw.r_irq_ctrl |= V_GLOB_IRQ_EN; | |
516 | HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); | |
517 | } | |
518 | ||
519 | static void | |
520 | disable_hwirq(struct hfc_multi *hc) | |
521 | { | |
522 | hc->hw.r_irq_ctrl &= ~((u_char)V_GLOB_IRQ_EN); | |
523 | HFC_outb(hc, R_IRQ_CTRL, hc->hw.r_irq_ctrl); | |
524 | } | |
525 | ||
526 | #define NUM_EC 2 | |
527 | #define MAX_TDM_CHAN 32 | |
528 | ||
529 | ||
530 | inline void | |
531 | enablepcibridge(struct hfc_multi *c) | |
532 | { | |
533 | HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); /* was _io before */ | |
534 | } | |
535 | ||
536 | inline void | |
537 | disablepcibridge(struct hfc_multi *c) | |
538 | { | |
539 | HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x2); /* was _io before */ | |
540 | } | |
541 | ||
542 | inline unsigned char | |
543 | readpcibridge(struct hfc_multi *hc, unsigned char address) | |
544 | { | |
545 | unsigned short cipv; | |
546 | unsigned char data; | |
547 | ||
548 | if (!hc->pci_iobase) | |
549 | return 0; | |
550 | ||
551 | /* slow down a PCI read access by 1 PCI clock cycle */ | |
552 | HFC_outb(hc, R_CTRL, 0x4); /*was _io before*/ | |
553 | ||
554 | if (address == 0) | |
555 | cipv = 0x4000; | |
556 | else | |
557 | cipv = 0x5800; | |
558 | ||
559 | /* select local bridge port address by writing to CIP port */ | |
560 | /* data = HFC_inb(c, cipv); * was _io before */ | |
561 | outw(cipv, hc->pci_iobase + 4); | |
562 | data = inb(hc->pci_iobase); | |
563 | ||
564 | /* restore R_CTRL for normal PCI read cycle speed */ | |
565 | HFC_outb(hc, R_CTRL, 0x0); /* was _io before */ | |
566 | ||
567 | return data; | |
568 | } | |
569 | ||
570 | inline void | |
571 | writepcibridge(struct hfc_multi *hc, unsigned char address, unsigned char data) | |
572 | { | |
573 | unsigned short cipv; | |
574 | unsigned int datav; | |
575 | ||
576 | if (!hc->pci_iobase) | |
577 | return; | |
578 | ||
579 | if (address == 0) | |
580 | cipv = 0x4000; | |
581 | else | |
582 | cipv = 0x5800; | |
583 | ||
584 | /* select local bridge port address by writing to CIP port */ | |
585 | outw(cipv, hc->pci_iobase + 4); | |
586 | /* define a 32 bit dword with 4 identical bytes for write sequence */ | |
587 | datav = data | ((__u32) data << 8) | ((__u32) data << 16) | | |
588 | ((__u32) data << 24); | |
589 | ||
590 | /* | |
591 | * write this 32 bit dword to the bridge data port | |
592 | * this will initiate a write sequence of up to 4 writes to the same | |
593 | * address on the local bus interface the number of write accesses | |
594 | * is undefined but >=1 and depends on the next PCI transaction | |
595 | * during write sequence on the local bus | |
596 | */ | |
597 | outl(datav, hc->pci_iobase); | |
598 | } | |
599 | ||
600 | inline void | |
601 | cpld_set_reg(struct hfc_multi *hc, unsigned char reg) | |
602 | { | |
603 | /* Do data pin read low byte */ | |
604 | HFC_outb(hc, R_GPIO_OUT1, reg); | |
605 | } | |
606 | ||
607 | inline void | |
608 | cpld_write_reg(struct hfc_multi *hc, unsigned char reg, unsigned char val) | |
609 | { | |
610 | cpld_set_reg(hc, reg); | |
611 | ||
612 | enablepcibridge(hc); | |
613 | writepcibridge(hc, 1, val); | |
614 | disablepcibridge(hc); | |
615 | ||
616 | return; | |
617 | } | |
618 | ||
619 | inline unsigned char | |
620 | cpld_read_reg(struct hfc_multi *hc, unsigned char reg) | |
621 | { | |
622 | unsigned char bytein; | |
623 | ||
624 | cpld_set_reg(hc, reg); | |
625 | ||
626 | /* Do data pin read low byte */ | |
627 | HFC_outb(hc, R_GPIO_OUT1, reg); | |
628 | ||
629 | enablepcibridge(hc); | |
630 | bytein = readpcibridge(hc, 1); | |
631 | disablepcibridge(hc); | |
632 | ||
633 | return bytein; | |
634 | } | |
635 | ||
636 | inline void | |
637 | vpm_write_address(struct hfc_multi *hc, unsigned short addr) | |
638 | { | |
639 | cpld_write_reg(hc, 0, 0xff & addr); | |
640 | cpld_write_reg(hc, 1, 0x01 & (addr >> 8)); | |
641 | } | |
642 | ||
643 | inline unsigned short | |
644 | vpm_read_address(struct hfc_multi *c) | |
645 | { | |
646 | unsigned short addr; | |
647 | unsigned short highbit; | |
648 | ||
649 | addr = cpld_read_reg(c, 0); | |
650 | highbit = cpld_read_reg(c, 1); | |
651 | ||
652 | addr = addr | (highbit << 8); | |
653 | ||
654 | return addr & 0x1ff; | |
655 | } | |
656 | ||
657 | inline unsigned char | |
658 | vpm_in(struct hfc_multi *c, int which, unsigned short addr) | |
659 | { | |
660 | unsigned char res; | |
661 | ||
662 | vpm_write_address(c, addr); | |
663 | ||
664 | if (!which) | |
665 | cpld_set_reg(c, 2); | |
666 | else | |
667 | cpld_set_reg(c, 3); | |
668 | ||
669 | enablepcibridge(c); | |
670 | res = readpcibridge(c, 1); | |
671 | disablepcibridge(c); | |
672 | ||
673 | cpld_set_reg(c, 0); | |
674 | ||
675 | return res; | |
676 | } | |
677 | ||
678 | inline void | |
679 | vpm_out(struct hfc_multi *c, int which, unsigned short addr, | |
680 | unsigned char data) | |
681 | { | |
682 | vpm_write_address(c, addr); | |
683 | ||
684 | enablepcibridge(c); | |
685 | ||
686 | if (!which) | |
687 | cpld_set_reg(c, 2); | |
688 | else | |
689 | cpld_set_reg(c, 3); | |
690 | ||
691 | writepcibridge(c, 1, data); | |
692 | ||
693 | cpld_set_reg(c, 0); | |
694 | ||
695 | disablepcibridge(c); | |
696 | ||
697 | { | |
698 | unsigned char regin; | |
699 | regin = vpm_in(c, which, addr); | |
700 | if (regin != data) | |
701 | printk(KERN_DEBUG "Wrote 0x%x to register 0x%x but got back " | |
702 | "0x%x\n", data, addr, regin); | |
703 | } | |
704 | ||
705 | } | |
706 | ||
707 | ||
5b834354 | 708 | static void |
af69fb3a KK |
709 | vpm_init(struct hfc_multi *wc) |
710 | { | |
711 | unsigned char reg; | |
712 | unsigned int mask; | |
713 | unsigned int i, x, y; | |
714 | unsigned int ver; | |
715 | ||
716 | for (x = 0; x < NUM_EC; x++) { | |
717 | /* Setup GPIO's */ | |
718 | if (!x) { | |
719 | ver = vpm_in(wc, x, 0x1a0); | |
720 | printk(KERN_DEBUG "VPM: Chip %d: ver %02x\n", x, ver); | |
721 | } | |
722 | ||
723 | for (y = 0; y < 4; y++) { | |
724 | vpm_out(wc, x, 0x1a8 + y, 0x00); /* GPIO out */ | |
725 | vpm_out(wc, x, 0x1ac + y, 0x00); /* GPIO dir */ | |
726 | vpm_out(wc, x, 0x1b0 + y, 0x00); /* GPIO sel */ | |
727 | } | |
728 | ||
729 | /* Setup TDM path - sets fsync and tdm_clk as inputs */ | |
730 | reg = vpm_in(wc, x, 0x1a3); /* misc_con */ | |
731 | vpm_out(wc, x, 0x1a3, reg & ~2); | |
732 | ||
733 | /* Setup Echo length (256 taps) */ | |
734 | vpm_out(wc, x, 0x022, 1); | |
735 | vpm_out(wc, x, 0x023, 0xff); | |
736 | ||
737 | /* Setup timeslots */ | |
738 | vpm_out(wc, x, 0x02f, 0x00); | |
739 | mask = 0x02020202 << (x * 4); | |
740 | ||
741 | /* Setup the tdm channel masks for all chips */ | |
742 | for (i = 0; i < 4; i++) | |
743 | vpm_out(wc, x, 0x33 - i, (mask >> (i << 3)) & 0xff); | |
744 | ||
745 | /* Setup convergence rate */ | |
746 | printk(KERN_DEBUG "VPM: A-law mode\n"); | |
747 | reg = 0x00 | 0x10 | 0x01; | |
748 | vpm_out(wc, x, 0x20, reg); | |
749 | printk(KERN_DEBUG "VPM reg 0x20 is %x\n", reg); | |
750 | /*vpm_out(wc, x, 0x20, (0x00 | 0x08 | 0x20 | 0x10)); */ | |
751 | ||
752 | vpm_out(wc, x, 0x24, 0x02); | |
753 | reg = vpm_in(wc, x, 0x24); | |
754 | printk(KERN_DEBUG "NLP Thresh is set to %d (0x%x)\n", reg, reg); | |
755 | ||
756 | /* Initialize echo cans */ | |
757 | for (i = 0; i < MAX_TDM_CHAN; i++) { | |
758 | if (mask & (0x00000001 << i)) | |
759 | vpm_out(wc, x, i, 0x00); | |
760 | } | |
761 | ||
762 | /* | |
763 | * ARM arch at least disallows a udelay of | |
764 | * more than 2ms... it gives a fake "__bad_udelay" | |
765 | * reference at link-time. | |
766 | * long delays in kernel code are pretty sucky anyway | |
767 | * for now work around it using 5 x 2ms instead of 1 x 10ms | |
768 | */ | |
769 | ||
770 | udelay(2000); | |
771 | udelay(2000); | |
772 | udelay(2000); | |
773 | udelay(2000); | |
774 | udelay(2000); | |
775 | ||
776 | /* Put in bypass mode */ | |
777 | for (i = 0; i < MAX_TDM_CHAN; i++) { | |
778 | if (mask & (0x00000001 << i)) | |
779 | vpm_out(wc, x, i, 0x01); | |
780 | } | |
781 | ||
782 | /* Enable bypass */ | |
783 | for (i = 0; i < MAX_TDM_CHAN; i++) { | |
784 | if (mask & (0x00000001 << i)) | |
785 | vpm_out(wc, x, 0x78 + i, 0x01); | |
786 | } | |
787 | ||
788 | } | |
789 | } | |
790 | ||
5b834354 | 791 | static void |
af69fb3a KK |
792 | vpm_check(struct hfc_multi *hctmp) |
793 | { | |
794 | unsigned char gpi2; | |
795 | ||
796 | gpi2 = HFC_inb(hctmp, R_GPI_IN2); | |
797 | ||
798 | if ((gpi2 & 0x3) != 0x3) | |
799 | printk(KERN_DEBUG "Got interrupt 0x%x from VPM!\n", gpi2); | |
800 | } | |
801 | ||
802 | ||
803 | /* | |
804 | * Interface to enable/disable the HW Echocan | |
805 | * | |
806 | * these functions are called within a spin_lock_irqsave on | |
807 | * the channel instance lock, so we are not disturbed by irqs | |
808 | * | |
809 | * we can later easily change the interface to make other | |
810 | * things configurable, for now we configure the taps | |
811 | * | |
812 | */ | |
813 | ||
5b834354 | 814 | static void |
af69fb3a KK |
815 | vpm_echocan_on(struct hfc_multi *hc, int ch, int taps) |
816 | { | |
817 | unsigned int timeslot; | |
818 | unsigned int unit; | |
819 | struct bchannel *bch = hc->chan[ch].bch; | |
820 | #ifdef TXADJ | |
821 | int txadj = -4; | |
822 | struct sk_buff *skb; | |
823 | #endif | |
824 | if (hc->chan[ch].protocol != ISDN_P_B_RAW) | |
825 | return; | |
826 | ||
827 | if (!bch) | |
828 | return; | |
829 | ||
830 | #ifdef TXADJ | |
831 | skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, | |
832 | sizeof(int), &txadj, GFP_ATOMIC); | |
833 | if (skb) | |
834 | recv_Bchannel_skb(bch, skb); | |
835 | #endif | |
836 | ||
837 | timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; | |
838 | unit = ch % 4; | |
839 | ||
840 | printk(KERN_NOTICE "vpm_echocan_on called taps [%d] on timeslot %d\n", | |
841 | taps, timeslot); | |
842 | ||
843 | vpm_out(hc, unit, timeslot, 0x7e); | |
844 | } | |
845 | ||
5b834354 | 846 | static void |
af69fb3a KK |
847 | vpm_echocan_off(struct hfc_multi *hc, int ch) |
848 | { | |
849 | unsigned int timeslot; | |
850 | unsigned int unit; | |
851 | struct bchannel *bch = hc->chan[ch].bch; | |
852 | #ifdef TXADJ | |
853 | int txadj = 0; | |
854 | struct sk_buff *skb; | |
855 | #endif | |
856 | ||
857 | if (hc->chan[ch].protocol != ISDN_P_B_RAW) | |
858 | return; | |
859 | ||
860 | if (!bch) | |
861 | return; | |
862 | ||
863 | #ifdef TXADJ | |
864 | skb = _alloc_mISDN_skb(PH_CONTROL_IND, HFC_VOL_CHANGE_TX, | |
865 | sizeof(int), &txadj, GFP_ATOMIC); | |
866 | if (skb) | |
867 | recv_Bchannel_skb(bch, skb); | |
868 | #endif | |
869 | ||
870 | timeslot = ((ch/4)*8) + ((ch%4)*4) + 1; | |
871 | unit = ch % 4; | |
872 | ||
873 | printk(KERN_NOTICE "vpm_echocan_off called on timeslot %d\n", | |
874 | timeslot); | |
875 | /* FILLME */ | |
876 | vpm_out(hc, unit, timeslot, 0x01); | |
877 | } | |
878 | ||
879 | ||
880 | /* | |
881 | * Speech Design resync feature | |
882 | * NOTE: This is called sometimes outside interrupt handler. | |
883 | * We must lock irqsave, so no other interrupt (other card) will occurr! | |
884 | * Also multiple interrupts may nest, so must lock each access (lists, card)! | |
885 | */ | |
886 | static inline void | |
887 | hfcmulti_resync(struct hfc_multi *locked, struct hfc_multi *newmaster, int rm) | |
888 | { | |
bcf91745 | 889 | struct hfc_multi *hc, *next, *pcmmaster = NULL; |
af69fb3a KK |
890 | u_int *plx_acc_32, pv; |
891 | u_long flags; | |
892 | ||
893 | spin_lock_irqsave(&HFClock, flags); | |
894 | spin_lock(&plx_lock); /* must be locked inside other locks */ | |
895 | ||
896 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
897 | printk(KERN_DEBUG "%s: RESYNC(syncmaster=0x%p)\n", | |
898 | __func__, syncmaster); | |
899 | ||
900 | /* select new master */ | |
901 | if (newmaster) { | |
902 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
903 | printk(KERN_DEBUG "using provided controller\n"); | |
904 | } else { | |
905 | list_for_each_entry_safe(hc, next, &HFClist, list) { | |
906 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
907 | if (hc->syncronized) { | |
908 | newmaster = hc; | |
909 | break; | |
910 | } | |
911 | } | |
912 | } | |
913 | } | |
914 | ||
915 | /* Disable sync of all cards */ | |
916 | list_for_each_entry_safe(hc, next, &HFClist, list) { | |
917 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
918 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | |
919 | pv = readl(plx_acc_32); | |
920 | pv &= ~PLX_SYNC_O_EN; | |
921 | writel(pv, plx_acc_32); | |
922 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { | |
923 | pcmmaster = hc; | |
924 | if (hc->type == 1) { | |
925 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
926 | printk(KERN_DEBUG | |
927 | "Schedule SYNC_I\n"); | |
928 | hc->e1_resync |= 1; /* get SYNC_I */ | |
929 | } | |
930 | } | |
931 | } | |
932 | } | |
933 | ||
934 | if (newmaster) { | |
935 | hc = newmaster; | |
936 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
937 | printk(KERN_DEBUG "id=%d (0x%p) = syncronized with " | |
938 | "interface.\n", hc->id, hc); | |
939 | /* Enable new sync master */ | |
940 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | |
941 | pv = readl(plx_acc_32); | |
942 | pv |= PLX_SYNC_O_EN; | |
943 | writel(pv, plx_acc_32); | |
944 | /* switch to jatt PLL, if not disabled by RX_SYNC */ | |
945 | if (hc->type == 1 && !test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) { | |
946 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
947 | printk(KERN_DEBUG "Schedule jatt PLL\n"); | |
948 | hc->e1_resync |= 2; /* switch to jatt */ | |
949 | } | |
950 | } else { | |
951 | if (pcmmaster) { | |
952 | hc = pcmmaster; | |
953 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
954 | printk(KERN_DEBUG | |
955 | "id=%d (0x%p) = PCM master syncronized " | |
956 | "with QUARTZ\n", hc->id, hc); | |
957 | if (hc->type == 1) { | |
958 | /* Use the crystal clock for the PCM | |
959 | master card */ | |
960 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
961 | printk(KERN_DEBUG | |
962 | "Schedule QUARTZ for HFC-E1\n"); | |
963 | hc->e1_resync |= 4; /* switch quartz */ | |
964 | } else { | |
965 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
966 | printk(KERN_DEBUG | |
967 | "QUARTZ is automatically " | |
968 | "enabled by HFC-%dS\n", hc->type); | |
969 | } | |
970 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | |
971 | pv = readl(plx_acc_32); | |
972 | pv |= PLX_SYNC_O_EN; | |
973 | writel(pv, plx_acc_32); | |
974 | } else | |
975 | if (!rm) | |
976 | printk(KERN_ERR "%s no pcm master, this MUST " | |
977 | "not happen!\n", __func__); | |
978 | } | |
979 | syncmaster = newmaster; | |
980 | ||
981 | spin_unlock(&plx_lock); | |
982 | spin_unlock_irqrestore(&HFClock, flags); | |
983 | } | |
984 | ||
985 | /* This must be called AND hc must be locked irqsave!!! */ | |
986 | inline void | |
987 | plxsd_checksync(struct hfc_multi *hc, int rm) | |
988 | { | |
989 | if (hc->syncronized) { | |
990 | if (syncmaster == NULL) { | |
991 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
992 | printk(KERN_WARNING "%s: GOT sync on card %d" | |
993 | " (id=%d)\n", __func__, hc->id + 1, | |
994 | hc->id); | |
995 | hfcmulti_resync(hc, hc, rm); | |
996 | } | |
997 | } else { | |
998 | if (syncmaster == hc) { | |
999 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1000 | printk(KERN_WARNING "%s: LOST sync on card %d" | |
1001 | " (id=%d)\n", __func__, hc->id + 1, | |
1002 | hc->id); | |
1003 | hfcmulti_resync(hc, NULL, rm); | |
1004 | } | |
1005 | } | |
1006 | } | |
1007 | ||
1008 | ||
1009 | /* | |
1010 | * free hardware resources used by driver | |
1011 | */ | |
1012 | static void | |
1013 | release_io_hfcmulti(struct hfc_multi *hc) | |
1014 | { | |
1015 | u_int *plx_acc_32, pv; | |
1016 | u_long plx_flags; | |
1017 | ||
1018 | if (debug & DEBUG_HFCMULTI_INIT) | |
1019 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
1020 | ||
1021 | /* soft reset also masks all interrupts */ | |
1022 | hc->hw.r_cirm |= V_SRES; | |
1023 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1024 | udelay(1000); | |
1025 | hc->hw.r_cirm &= ~V_SRES; | |
1026 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1027 | udelay(1000); /* instead of 'wait' that may cause locking */ | |
1028 | ||
1029 | /* release Speech Design card, if PLX was initialized */ | |
1030 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && hc->plx_membase) { | |
1031 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1032 | printk(KERN_DEBUG "%s: release PLXSD card %d\n", | |
1033 | __func__, hc->id + 1); | |
1034 | spin_lock_irqsave(&plx_lock, plx_flags); | |
1035 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | |
1036 | writel(PLX_GPIOC_INIT, plx_acc_32); | |
1037 | pv = readl(plx_acc_32); | |
1038 | /* Termination off */ | |
1039 | pv &= ~PLX_TERM_ON; | |
1040 | /* Disconnect the PCM */ | |
1041 | pv |= PLX_SLAVE_EN_N; | |
1042 | pv &= ~PLX_MASTER_EN; | |
1043 | pv &= ~PLX_SYNC_O_EN; | |
1044 | /* Put the DSP in Reset */ | |
1045 | pv &= ~PLX_DSP_RES_N; | |
1046 | writel(pv, plx_acc_32); | |
1047 | if (debug & DEBUG_HFCMULTI_INIT) | |
1048 | printk(KERN_WARNING "%s: PCM off: PLX_GPIO=%x\n", | |
1049 | __func__, pv); | |
1050 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1051 | } | |
1052 | ||
1053 | /* disable memory mapped ports / io ports */ | |
1054 | test_and_clear_bit(HFC_CHIP_PLXSD, &hc->chip); /* prevent resync */ | |
1055 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, 0); | |
1056 | if (hc->pci_membase) | |
1057 | iounmap((void *)hc->pci_membase); | |
1058 | if (hc->plx_membase) | |
1059 | iounmap((void *)hc->plx_membase); | |
1060 | if (hc->pci_iobase) | |
1061 | release_region(hc->pci_iobase, 8); | |
1062 | ||
1063 | if (hc->pci_dev) { | |
1064 | pci_disable_device(hc->pci_dev); | |
1065 | pci_set_drvdata(hc->pci_dev, NULL); | |
1066 | } | |
1067 | if (debug & DEBUG_HFCMULTI_INIT) | |
1068 | printk(KERN_DEBUG "%s: done\n", __func__); | |
1069 | } | |
1070 | ||
1071 | /* | |
1072 | * function called to reset the HFC chip. A complete software reset of chip | |
1073 | * and fifos is done. All configuration of the chip is done. | |
1074 | */ | |
1075 | ||
1076 | static int | |
1077 | init_chip(struct hfc_multi *hc) | |
1078 | { | |
1079 | u_long flags, val, val2 = 0, rev; | |
1080 | int i, err = 0; | |
1081 | u_char r_conf_en, rval; | |
1082 | u_int *plx_acc_32, pv; | |
1083 | u_long plx_flags, hfc_flags; | |
1084 | int plx_count; | |
1085 | struct hfc_multi *pos, *next, *plx_last_hc; | |
1086 | ||
1087 | spin_lock_irqsave(&hc->lock, flags); | |
1088 | /* reset all registers */ | |
1089 | memset(&hc->hw, 0, sizeof(struct hfcm_hw)); | |
1090 | ||
1091 | /* revision check */ | |
1092 | if (debug & DEBUG_HFCMULTI_INIT) | |
1093 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
1094 | val = HFC_inb(hc, R_CHIP_ID)>>4; | |
1095 | if (val != 0x8 && val != 0xc && val != 0xe) { | |
1096 | printk(KERN_INFO "HFC_multi: unknown CHIP_ID:%x\n", (u_int)val); | |
1097 | err = -EIO; | |
1098 | goto out; | |
1099 | } | |
1100 | rev = HFC_inb(hc, R_CHIP_RV); | |
1101 | printk(KERN_INFO | |
1102 | "HFC_multi: detected HFC with chip ID=0x%lx revision=%ld%s\n", | |
1103 | val, rev, (rev == 0) ? " (old FIFO handling)" : ""); | |
1104 | if (rev == 0) { | |
1105 | test_and_set_bit(HFC_CHIP_REVISION0, &hc->chip); | |
1106 | printk(KERN_WARNING | |
1107 | "HFC_multi: NOTE: Your chip is revision 0, " | |
1108 | "ask Cologne Chip for update. Newer chips " | |
1109 | "have a better FIFO handling. Old chips " | |
1110 | "still work but may have slightly lower " | |
1111 | "HDLC transmit performance.\n"); | |
1112 | } | |
1113 | if (rev > 1) { | |
1114 | printk(KERN_WARNING "HFC_multi: WARNING: This driver doesn't " | |
1115 | "consider chip revision = %ld. The chip / " | |
1116 | "bridge may not work.\n", rev); | |
1117 | } | |
1118 | ||
1119 | /* set s-ram size */ | |
1120 | hc->Flen = 0x10; | |
1121 | hc->Zmin = 0x80; | |
1122 | hc->Zlen = 384; | |
1123 | hc->DTMFbase = 0x1000; | |
1124 | if (test_bit(HFC_CHIP_EXRAM_128, &hc->chip)) { | |
1125 | if (debug & DEBUG_HFCMULTI_INIT) | |
1126 | printk(KERN_DEBUG "%s: changing to 128K extenal RAM\n", | |
1127 | __func__); | |
1128 | hc->hw.r_ctrl |= V_EXT_RAM; | |
1129 | hc->hw.r_ram_sz = 1; | |
1130 | hc->Flen = 0x20; | |
1131 | hc->Zmin = 0xc0; | |
1132 | hc->Zlen = 1856; | |
1133 | hc->DTMFbase = 0x2000; | |
1134 | } | |
1135 | if (test_bit(HFC_CHIP_EXRAM_512, &hc->chip)) { | |
1136 | if (debug & DEBUG_HFCMULTI_INIT) | |
1137 | printk(KERN_DEBUG "%s: changing to 512K extenal RAM\n", | |
1138 | __func__); | |
1139 | hc->hw.r_ctrl |= V_EXT_RAM; | |
1140 | hc->hw.r_ram_sz = 2; | |
1141 | hc->Flen = 0x20; | |
1142 | hc->Zmin = 0xc0; | |
1143 | hc->Zlen = 8000; | |
1144 | hc->DTMFbase = 0x2000; | |
1145 | } | |
1146 | hc->max_trans = poll << 1; | |
1147 | if (hc->max_trans > hc->Zlen) | |
1148 | hc->max_trans = hc->Zlen; | |
1149 | ||
1150 | /* Speech Design PLX bridge */ | |
1151 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1152 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1153 | printk(KERN_DEBUG "%s: initializing PLXSD card %d\n", | |
1154 | __func__, hc->id + 1); | |
1155 | spin_lock_irqsave(&plx_lock, plx_flags); | |
1156 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | |
1157 | writel(PLX_GPIOC_INIT, plx_acc_32); | |
1158 | pv = readl(plx_acc_32); | |
1159 | /* The first and the last cards are terminating the PCM bus */ | |
1160 | pv |= PLX_TERM_ON; /* hc is currently the last */ | |
1161 | /* Disconnect the PCM */ | |
1162 | pv |= PLX_SLAVE_EN_N; | |
1163 | pv &= ~PLX_MASTER_EN; | |
1164 | pv &= ~PLX_SYNC_O_EN; | |
1165 | /* Put the DSP in Reset */ | |
1166 | pv &= ~PLX_DSP_RES_N; | |
1167 | writel(pv, plx_acc_32); | |
1168 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1169 | if (debug & DEBUG_HFCMULTI_INIT) | |
1170 | printk(KERN_WARNING "%s: slave/term: PLX_GPIO=%x\n", | |
1171 | __func__, pv); | |
1172 | /* | |
1173 | * If we are the 3rd PLXSD card or higher, we must turn | |
1174 | * termination of last PLXSD card off. | |
1175 | */ | |
1176 | spin_lock_irqsave(&HFClock, hfc_flags); | |
1177 | plx_count = 0; | |
1178 | plx_last_hc = NULL; | |
1179 | list_for_each_entry_safe(pos, next, &HFClist, list) { | |
1180 | if (test_bit(HFC_CHIP_PLXSD, &pos->chip)) { | |
1181 | plx_count++; | |
1182 | if (pos != hc) | |
1183 | plx_last_hc = pos; | |
1184 | } | |
1185 | } | |
1186 | if (plx_count >= 3) { | |
1187 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
1188 | printk(KERN_DEBUG "%s: card %d is between, so " | |
1189 | "we disable termination\n", | |
1190 | __func__, plx_last_hc->id + 1); | |
1191 | spin_lock_irqsave(&plx_lock, plx_flags); | |
1192 | plx_acc_32 = (u_int *)(plx_last_hc->plx_membase | |
1193 | + PLX_GPIOC); | |
1194 | pv = readl(plx_acc_32); | |
1195 | pv &= ~PLX_TERM_ON; | |
1196 | writel(pv, plx_acc_32); | |
1197 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1198 | if (debug & DEBUG_HFCMULTI_INIT) | |
1199 | printk(KERN_WARNING "%s: term off: PLX_GPIO=%x\n", | |
1200 | __func__, pv); | |
1201 | } | |
1202 | spin_unlock_irqrestore(&HFClock, hfc_flags); | |
1203 | hc->hw.r_pcm_md0 = V_F0_LEN; /* shift clock for DSP */ | |
1204 | } | |
1205 | ||
1206 | /* we only want the real Z2 read-pointer for revision > 0 */ | |
1207 | if (!test_bit(HFC_CHIP_REVISION0, &hc->chip)) | |
1208 | hc->hw.r_ram_sz |= V_FZ_MD; | |
1209 | ||
1210 | /* select pcm mode */ | |
1211 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
1212 | if (debug & DEBUG_HFCMULTI_INIT) | |
1213 | printk(KERN_DEBUG "%s: setting PCM into slave mode\n", | |
1214 | __func__); | |
1215 | } else | |
1216 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) && !plxsd_master) { | |
1217 | if (debug & DEBUG_HFCMULTI_INIT) | |
1218 | printk(KERN_DEBUG "%s: setting PCM into master mode\n", | |
1219 | __func__); | |
1220 | hc->hw.r_pcm_md0 |= V_PCM_MD; | |
1221 | } else { | |
1222 | if (debug & DEBUG_HFCMULTI_INIT) | |
1223 | printk(KERN_DEBUG "%s: performing PCM auto detect\n", | |
1224 | __func__); | |
1225 | } | |
1226 | ||
1227 | /* soft reset */ | |
1228 | HFC_outb(hc, R_CTRL, hc->hw.r_ctrl); | |
1229 | HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); | |
1230 | HFC_outb(hc, R_FIFO_MD, 0); | |
1231 | hc->hw.r_cirm = V_SRES | V_HFCRES | V_PCMRES | V_STRES | V_RLD_EPR; | |
1232 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1233 | udelay(100); | |
1234 | hc->hw.r_cirm = 0; | |
1235 | HFC_outb(hc, R_CIRM, hc->hw.r_cirm); | |
1236 | udelay(100); | |
1237 | HFC_outb(hc, R_RAM_SZ, hc->hw.r_ram_sz); | |
1238 | ||
1239 | /* Speech Design PLX bridge pcm and sync mode */ | |
1240 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1241 | spin_lock_irqsave(&plx_lock, plx_flags); | |
1242 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | |
1243 | pv = readl(plx_acc_32); | |
1244 | /* Connect PCM */ | |
1245 | if (hc->hw.r_pcm_md0 & V_PCM_MD) { | |
1246 | pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; | |
1247 | pv |= PLX_SYNC_O_EN; | |
1248 | if (debug & DEBUG_HFCMULTI_INIT) | |
1249 | printk(KERN_WARNING "%s: master: PLX_GPIO=%x\n", | |
1250 | __func__, pv); | |
1251 | } else { | |
1252 | pv &= ~(PLX_MASTER_EN | PLX_SLAVE_EN_N); | |
1253 | pv &= ~PLX_SYNC_O_EN; | |
1254 | if (debug & DEBUG_HFCMULTI_INIT) | |
1255 | printk(KERN_WARNING "%s: slave: PLX_GPIO=%x\n", | |
1256 | __func__, pv); | |
1257 | } | |
1258 | writel(pv, plx_acc_32); | |
1259 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1260 | } | |
1261 | ||
1262 | /* PCM setup */ | |
1263 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x90); | |
1264 | if (hc->slots == 32) | |
1265 | HFC_outb(hc, R_PCM_MD1, 0x00); | |
1266 | if (hc->slots == 64) | |
1267 | HFC_outb(hc, R_PCM_MD1, 0x10); | |
1268 | if (hc->slots == 128) | |
1269 | HFC_outb(hc, R_PCM_MD1, 0x20); | |
1270 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0xa0); | |
1271 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) | |
1272 | HFC_outb(hc, R_PCM_MD2, V_SYNC_SRC); /* sync via SYNC_I / O */ | |
1273 | else | |
1274 | HFC_outb(hc, R_PCM_MD2, 0x00); /* sync from interface */ | |
1275 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); | |
1276 | for (i = 0; i < 256; i++) { | |
1277 | HFC_outb_nodebug(hc, R_SLOT, i); | |
1278 | HFC_outb_nodebug(hc, A_SL_CFG, 0); | |
1279 | HFC_outb_nodebug(hc, A_CONF, 0); | |
1280 | hc->slot_owner[i] = -1; | |
1281 | } | |
1282 | ||
1283 | /* set clock speed */ | |
1284 | if (test_bit(HFC_CHIP_CLOCK2, &hc->chip)) { | |
1285 | if (debug & DEBUG_HFCMULTI_INIT) | |
1286 | printk(KERN_DEBUG | |
1287 | "%s: setting double clock\n", __func__); | |
1288 | HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); | |
1289 | } | |
1290 | ||
1291 | /* B410P GPIO */ | |
1292 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) { | |
1293 | printk(KERN_NOTICE "Setting GPIOs\n"); | |
1294 | HFC_outb(hc, R_GPIO_SEL, 0x30); | |
1295 | HFC_outb(hc, R_GPIO_EN1, 0x3); | |
1296 | udelay(1000); | |
1297 | printk(KERN_NOTICE "calling vpm_init\n"); | |
1298 | vpm_init(hc); | |
1299 | } | |
1300 | ||
1301 | /* check if R_F0_CNT counts (8 kHz frame count) */ | |
1302 | val = HFC_inb(hc, R_F0_CNTL); | |
1303 | val += HFC_inb(hc, R_F0_CNTH) << 8; | |
1304 | if (debug & DEBUG_HFCMULTI_INIT) | |
1305 | printk(KERN_DEBUG | |
1306 | "HFC_multi F0_CNT %ld after reset\n", val); | |
1307 | spin_unlock_irqrestore(&hc->lock, flags); | |
1308 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1309 | schedule_timeout((HZ/100)?:1); /* Timeout minimum 10ms */ | |
1310 | spin_lock_irqsave(&hc->lock, flags); | |
1311 | val2 = HFC_inb(hc, R_F0_CNTL); | |
1312 | val2 += HFC_inb(hc, R_F0_CNTH) << 8; | |
1313 | if (debug & DEBUG_HFCMULTI_INIT) | |
1314 | printk(KERN_DEBUG | |
1315 | "HFC_multi F0_CNT %ld after 10 ms (1st try)\n", | |
1316 | val2); | |
1317 | if (val2 >= val+8) { /* 1 ms */ | |
1318 | /* it counts, so we keep the pcm mode */ | |
1319 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) | |
1320 | printk(KERN_INFO "controller is PCM bus MASTER\n"); | |
1321 | else | |
1322 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) | |
1323 | printk(KERN_INFO "controller is PCM bus SLAVE\n"); | |
1324 | else { | |
1325 | test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
1326 | printk(KERN_INFO "controller is PCM bus SLAVE " | |
1327 | "(auto detected)\n"); | |
1328 | } | |
1329 | } else { | |
1330 | /* does not count */ | |
1331 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) { | |
1332 | controller_fail: | |
1333 | printk(KERN_ERR "HFC_multi ERROR, getting no 125us " | |
1334 | "pulse. Seems that controller fails.\n"); | |
1335 | err = -EIO; | |
1336 | goto out; | |
1337 | } | |
1338 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
1339 | printk(KERN_INFO "controller is PCM bus SLAVE " | |
1340 | "(ignoring missing PCM clock)\n"); | |
1341 | } else { | |
1342 | /* only one pcm master */ | |
1343 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) | |
1344 | && plxsd_master) { | |
1345 | printk(KERN_ERR "HFC_multi ERROR, no clock " | |
1346 | "on another Speech Design card found. " | |
1347 | "Please be sure to connect PCM cable.\n"); | |
1348 | err = -EIO; | |
1349 | goto out; | |
1350 | } | |
1351 | /* retry with master clock */ | |
1352 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1353 | spin_lock_irqsave(&plx_lock, plx_flags); | |
1354 | plx_acc_32 = (u_int *)(hc->plx_membase + | |
1355 | PLX_GPIOC); | |
1356 | pv = readl(plx_acc_32); | |
1357 | pv |= PLX_MASTER_EN | PLX_SLAVE_EN_N; | |
1358 | pv |= PLX_SYNC_O_EN; | |
1359 | writel(pv, plx_acc_32); | |
1360 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1361 | if (debug & DEBUG_HFCMULTI_INIT) | |
1362 | printk(KERN_WARNING "%s: master: PLX_GPIO" | |
1363 | "=%x\n", __func__, pv); | |
1364 | } | |
1365 | hc->hw.r_pcm_md0 |= V_PCM_MD; | |
1366 | HFC_outb(hc, R_PCM_MD0, hc->hw.r_pcm_md0 | 0x00); | |
1367 | spin_unlock_irqrestore(&hc->lock, flags); | |
1368 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1369 | schedule_timeout((HZ/100)?:1); /* Timeout min. 10ms */ | |
1370 | spin_lock_irqsave(&hc->lock, flags); | |
1371 | val2 = HFC_inb(hc, R_F0_CNTL); | |
1372 | val2 += HFC_inb(hc, R_F0_CNTH) << 8; | |
1373 | if (debug & DEBUG_HFCMULTI_INIT) | |
1374 | printk(KERN_DEBUG "HFC_multi F0_CNT %ld after " | |
1375 | "10 ms (2nd try)\n", val2); | |
1376 | if (val2 >= val+8) { /* 1 ms */ | |
1377 | test_and_set_bit(HFC_CHIP_PCM_MASTER, | |
1378 | &hc->chip); | |
1379 | printk(KERN_INFO "controller is PCM bus MASTER " | |
1380 | "(auto detected)\n"); | |
1381 | } else | |
1382 | goto controller_fail; | |
1383 | } | |
1384 | } | |
1385 | ||
1386 | /* Release the DSP Reset */ | |
1387 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1388 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip)) | |
1389 | plxsd_master = 1; | |
1390 | spin_lock_irqsave(&plx_lock, plx_flags); | |
1391 | plx_acc_32 = (u_int *)(hc->plx_membase+PLX_GPIOC); | |
1392 | pv = readl(plx_acc_32); | |
1393 | pv |= PLX_DSP_RES_N; | |
1394 | writel(pv, plx_acc_32); | |
1395 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
1396 | if (debug & DEBUG_HFCMULTI_INIT) | |
1397 | printk(KERN_WARNING "%s: reset off: PLX_GPIO=%x\n", | |
1398 | __func__, pv); | |
1399 | } | |
1400 | ||
1401 | /* pcm id */ | |
1402 | if (hc->pcm) | |
1403 | printk(KERN_INFO "controller has given PCM BUS ID %d\n", | |
1404 | hc->pcm); | |
1405 | else { | |
1406 | if (test_bit(HFC_CHIP_PCM_MASTER, &hc->chip) | |
1407 | || test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
1408 | PCM_cnt++; /* SD has proprietary bridging */ | |
1409 | } | |
1410 | hc->pcm = PCM_cnt; | |
1411 | printk(KERN_INFO "controller has PCM BUS ID %d " | |
1412 | "(auto selected)\n", hc->pcm); | |
1413 | } | |
1414 | ||
1415 | /* set up timer */ | |
1416 | HFC_outb(hc, R_TI_WD, poll_timer); | |
1417 | hc->hw.r_irqmsk_misc |= V_TI_IRQMSK; | |
1418 | ||
1419 | /* | |
1420 | * set up 125us interrupt, only if function pointer is available | |
1421 | * and module parameter timer is set | |
1422 | */ | |
1423 | if (timer && hfc_interrupt && register_interrupt) { | |
1424 | /* only one chip should use this interrupt */ | |
1425 | timer = 0; | |
1426 | interrupt_registered = 1; | |
1427 | hc->hw.r_irqmsk_misc |= V_PROC_IRQMSK; | |
1428 | /* deactivate other interrupts in ztdummy */ | |
1429 | register_interrupt(); | |
1430 | } | |
1431 | ||
1432 | /* set E1 state machine IRQ */ | |
1433 | if (hc->type == 1) | |
1434 | hc->hw.r_irqmsk_misc |= V_STA_IRQMSK; | |
1435 | ||
1436 | /* set DTMF detection */ | |
1437 | if (test_bit(HFC_CHIP_DTMF, &hc->chip)) { | |
1438 | if (debug & DEBUG_HFCMULTI_INIT) | |
1439 | printk(KERN_DEBUG "%s: enabling DTMF detection " | |
1440 | "for all B-channel\n", __func__); | |
1441 | hc->hw.r_dtmf = V_DTMF_EN | V_DTMF_STOP; | |
1442 | if (test_bit(HFC_CHIP_ULAW, &hc->chip)) | |
1443 | hc->hw.r_dtmf |= V_ULAW_SEL; | |
1444 | HFC_outb(hc, R_DTMF_N, 102 - 1); | |
1445 | hc->hw.r_irqmsk_misc |= V_DTMF_IRQMSK; | |
1446 | } | |
1447 | ||
1448 | /* conference engine */ | |
1449 | if (test_bit(HFC_CHIP_ULAW, &hc->chip)) | |
1450 | r_conf_en = V_CONF_EN | V_ULAW; | |
1451 | else | |
1452 | r_conf_en = V_CONF_EN; | |
1453 | HFC_outb(hc, R_CONF_EN, r_conf_en); | |
1454 | ||
1455 | /* setting leds */ | |
1456 | switch (hc->leds) { | |
1457 | case 1: /* HFC-E1 OEM */ | |
1458 | if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) | |
1459 | HFC_outb(hc, R_GPIO_SEL, 0x32); | |
1460 | else | |
1461 | HFC_outb(hc, R_GPIO_SEL, 0x30); | |
1462 | ||
1463 | HFC_outb(hc, R_GPIO_EN1, 0x0f); | |
1464 | HFC_outb(hc, R_GPIO_OUT1, 0x00); | |
1465 | ||
1466 | HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); | |
1467 | break; | |
1468 | ||
1469 | case 2: /* HFC-4S OEM */ | |
1470 | case 3: | |
1471 | HFC_outb(hc, R_GPIO_SEL, 0xf0); | |
1472 | HFC_outb(hc, R_GPIO_EN1, 0xff); | |
1473 | HFC_outb(hc, R_GPIO_OUT1, 0x00); | |
1474 | break; | |
1475 | } | |
1476 | ||
1477 | /* set master clock */ | |
1478 | if (hc->masterclk >= 0) { | |
1479 | if (debug & DEBUG_HFCMULTI_INIT) | |
1480 | printk(KERN_DEBUG "%s: setting ST master clock " | |
1481 | "to port %d (0..%d)\n", | |
1482 | __func__, hc->masterclk, hc->ports-1); | |
1483 | hc->hw.r_st_sync = hc->masterclk | V_AUTO_SYNC; | |
1484 | HFC_outb(hc, R_ST_SYNC, hc->hw.r_st_sync); | |
1485 | } | |
1486 | ||
1487 | /* setting misc irq */ | |
1488 | HFC_outb(hc, R_IRQMSK_MISC, hc->hw.r_irqmsk_misc); | |
1489 | if (debug & DEBUG_HFCMULTI_INIT) | |
1490 | printk(KERN_DEBUG "r_irqmsk_misc.2: 0x%x\n", | |
1491 | hc->hw.r_irqmsk_misc); | |
1492 | ||
1493 | /* RAM access test */ | |
1494 | HFC_outb(hc, R_RAM_ADDR0, 0); | |
1495 | HFC_outb(hc, R_RAM_ADDR1, 0); | |
1496 | HFC_outb(hc, R_RAM_ADDR2, 0); | |
1497 | for (i = 0; i < 256; i++) { | |
1498 | HFC_outb_nodebug(hc, R_RAM_ADDR0, i); | |
1499 | HFC_outb_nodebug(hc, R_RAM_DATA, ((i*3)&0xff)); | |
1500 | } | |
1501 | for (i = 0; i < 256; i++) { | |
1502 | HFC_outb_nodebug(hc, R_RAM_ADDR0, i); | |
1503 | HFC_inb_nodebug(hc, R_RAM_DATA); | |
1504 | rval = HFC_inb_nodebug(hc, R_INT_DATA); | |
1505 | if (rval != ((i * 3) & 0xff)) { | |
1506 | printk(KERN_DEBUG | |
1507 | "addr:%x val:%x should:%x\n", i, rval, | |
1508 | (i * 3) & 0xff); | |
1509 | err++; | |
1510 | } | |
1511 | } | |
1512 | if (err) { | |
1513 | printk(KERN_DEBUG "aborting - %d RAM access errors\n", err); | |
1514 | err = -EIO; | |
1515 | goto out; | |
1516 | } | |
1517 | ||
1518 | if (debug & DEBUG_HFCMULTI_INIT) | |
1519 | printk(KERN_DEBUG "%s: done\n", __func__); | |
1520 | out: | |
1521 | spin_unlock_irqrestore(&hc->lock, flags); | |
1522 | return err; | |
1523 | } | |
1524 | ||
1525 | ||
1526 | /* | |
1527 | * control the watchdog | |
1528 | */ | |
1529 | static void | |
1530 | hfcmulti_watchdog(struct hfc_multi *hc) | |
1531 | { | |
1532 | hc->wdcount++; | |
1533 | ||
1534 | if (hc->wdcount > 10) { | |
1535 | hc->wdcount = 0; | |
1536 | hc->wdbyte = hc->wdbyte == V_GPIO_OUT2 ? | |
1537 | V_GPIO_OUT3 : V_GPIO_OUT2; | |
1538 | ||
1539 | /* printk("Sending Watchdog Kill %x\n",hc->wdbyte); */ | |
1540 | HFC_outb(hc, R_GPIO_EN0, V_GPIO_EN2 | V_GPIO_EN3); | |
1541 | HFC_outb(hc, R_GPIO_OUT0, hc->wdbyte); | |
1542 | } | |
1543 | } | |
1544 | ||
1545 | ||
1546 | ||
1547 | /* | |
1548 | * output leds | |
1549 | */ | |
1550 | static void | |
1551 | hfcmulti_leds(struct hfc_multi *hc) | |
1552 | { | |
1553 | unsigned long lled; | |
1554 | unsigned long leddw; | |
1555 | int i, state, active, leds; | |
1556 | struct dchannel *dch; | |
1557 | int led[4]; | |
1558 | ||
1559 | hc->ledcount += poll; | |
1560 | if (hc->ledcount > 4096) { | |
1561 | hc->ledcount -= 4096; | |
1562 | hc->ledstate = 0xAFFEAFFE; | |
1563 | } | |
1564 | ||
1565 | switch (hc->leds) { | |
1566 | case 1: /* HFC-E1 OEM */ | |
1567 | /* 2 red blinking: NT mode deactivate | |
1568 | * 2 red steady: TE mode deactivate | |
1569 | * left green: L1 active | |
1570 | * left red: frame sync, but no L1 | |
1571 | * right green: L2 active | |
1572 | */ | |
1573 | if (hc->chan[hc->dslot].sync != 2) { /* no frame sync */ | |
1574 | if (hc->chan[hc->dslot].dch->dev.D.protocol | |
1575 | != ISDN_P_NT_E1) { | |
1576 | led[0] = 1; | |
1577 | led[1] = 1; | |
1578 | } else if (hc->ledcount>>11) { | |
1579 | led[0] = 1; | |
1580 | led[1] = 1; | |
1581 | } else { | |
1582 | led[0] = 0; | |
1583 | led[1] = 0; | |
1584 | } | |
1585 | led[2] = 0; | |
1586 | led[3] = 0; | |
1587 | } else { /* with frame sync */ | |
1588 | /* TODO make it work */ | |
1589 | led[0] = 0; | |
1590 | led[1] = 0; | |
1591 | led[2] = 0; | |
1592 | led[3] = 1; | |
1593 | } | |
1594 | leds = (led[0] | (led[1]<<2) | (led[2]<<1) | (led[3]<<3))^0xF; | |
1595 | /* leds are inverted */ | |
1596 | if (leds != (int)hc->ledstate) { | |
1597 | HFC_outb_nodebug(hc, R_GPIO_OUT1, leds); | |
1598 | hc->ledstate = leds; | |
1599 | } | |
1600 | break; | |
1601 | ||
1602 | case 2: /* HFC-4S OEM */ | |
1603 | /* red blinking = PH_DEACTIVATE NT Mode | |
1604 | * red steady = PH_DEACTIVATE TE Mode | |
1605 | * green steady = PH_ACTIVATE | |
1606 | */ | |
1607 | for (i = 0; i < 4; i++) { | |
1608 | state = 0; | |
1609 | active = -1; | |
1610 | dch = hc->chan[(i << 2) | 2].dch; | |
1611 | if (dch) { | |
1612 | state = dch->state; | |
1613 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
1614 | active = 3; | |
1615 | else | |
1616 | active = 7; | |
1617 | } | |
1618 | if (state) { | |
1619 | if (state == active) { | |
1620 | led[i] = 1; /* led green */ | |
1621 | } else | |
1622 | if (dch->dev.D.protocol == ISDN_P_TE_S0) | |
1623 | /* TE mode: led red */ | |
1624 | led[i] = 2; | |
1625 | else | |
1626 | if (hc->ledcount>>11) | |
1627 | /* led red */ | |
1628 | led[i] = 2; | |
1629 | else | |
1630 | /* led off */ | |
1631 | led[i] = 0; | |
1632 | } else | |
1633 | led[i] = 0; /* led off */ | |
1634 | } | |
1635 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) { | |
1636 | leds = 0; | |
1637 | for (i = 0; i < 4; i++) { | |
1638 | if (led[i] == 1) { | |
1639 | /*green*/ | |
1640 | leds |= (0x2 << (i * 2)); | |
1641 | } else if (led[i] == 2) { | |
1642 | /*red*/ | |
1643 | leds |= (0x1 << (i * 2)); | |
1644 | } | |
1645 | } | |
1646 | if (leds != (int)hc->ledstate) { | |
1647 | vpm_out(hc, 0, 0x1a8 + 3, leds); | |
1648 | hc->ledstate = leds; | |
1649 | } | |
1650 | } else { | |
1651 | leds = ((led[3] > 0) << 0) | ((led[1] > 0) << 1) | | |
1652 | ((led[0] > 0) << 2) | ((led[2] > 0) << 3) | | |
1653 | ((led[3] & 1) << 4) | ((led[1] & 1) << 5) | | |
1654 | ((led[0] & 1) << 6) | ((led[2] & 1) << 7); | |
1655 | if (leds != (int)hc->ledstate) { | |
1656 | HFC_outb_nodebug(hc, R_GPIO_EN1, leds & 0x0F); | |
1657 | HFC_outb_nodebug(hc, R_GPIO_OUT1, leds >> 4); | |
1658 | hc->ledstate = leds; | |
1659 | } | |
1660 | } | |
1661 | break; | |
1662 | ||
1663 | case 3: /* HFC 1S/2S Beronet */ | |
1664 | /* red blinking = PH_DEACTIVATE NT Mode | |
1665 | * red steady = PH_DEACTIVATE TE Mode | |
1666 | * green steady = PH_ACTIVATE | |
1667 | */ | |
1668 | for (i = 0; i < 2; i++) { | |
1669 | state = 0; | |
1670 | active = -1; | |
1671 | dch = hc->chan[(i << 2) | 2].dch; | |
1672 | if (dch) { | |
1673 | state = dch->state; | |
1674 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
1675 | active = 3; | |
1676 | else | |
1677 | active = 7; | |
1678 | } | |
1679 | if (state) { | |
1680 | if (state == active) { | |
1681 | led[i] = 1; /* led green */ | |
1682 | } else | |
1683 | if (dch->dev.D.protocol == ISDN_P_TE_S0) | |
1684 | /* TE mode: led red */ | |
1685 | led[i] = 2; | |
1686 | else | |
1687 | if (hc->ledcount >> 11) | |
1688 | /* led red */ | |
1689 | led[i] = 2; | |
1690 | else | |
1691 | /* led off */ | |
1692 | led[i] = 0; | |
1693 | } else | |
1694 | led[i] = 0; /* led off */ | |
1695 | } | |
1696 | ||
1697 | ||
1698 | leds = (led[0] > 0) | ((led[1] > 0)<<1) | ((led[0]&1)<<2) | |
1699 | | ((led[1]&1)<<3); | |
1700 | if (leds != (int)hc->ledstate) { | |
1701 | HFC_outb_nodebug(hc, R_GPIO_EN1, | |
1702 | ((led[0] > 0) << 2) | ((led[1] > 0) << 3)); | |
1703 | HFC_outb_nodebug(hc, R_GPIO_OUT1, | |
1704 | ((led[0] & 1) << 2) | ((led[1] & 1) << 3)); | |
1705 | hc->ledstate = leds; | |
1706 | } | |
1707 | break; | |
1708 | case 8: /* HFC 8S+ Beronet */ | |
1709 | lled = 0; | |
1710 | ||
1711 | for (i = 0; i < 8; i++) { | |
1712 | state = 0; | |
1713 | active = -1; | |
1714 | dch = hc->chan[(i << 2) | 2].dch; | |
1715 | if (dch) { | |
1716 | state = dch->state; | |
1717 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
1718 | active = 3; | |
1719 | else | |
1720 | active = 7; | |
1721 | } | |
1722 | if (state) { | |
1723 | if (state == active) { | |
1724 | lled |= 0 << i; | |
1725 | } else | |
1726 | if (hc->ledcount >> 11) | |
1727 | lled |= 0 << i; | |
1728 | else | |
1729 | lled |= 1 << i; | |
1730 | } else | |
1731 | lled |= 1 << i; | |
1732 | } | |
1733 | leddw = lled << 24 | lled << 16 | lled << 8 | lled; | |
1734 | if (leddw != hc->ledstate) { | |
1735 | /* HFC_outb(hc, R_BRG_PCM_CFG, 1); | |
1736 | HFC_outb(c, R_BRG_PCM_CFG, (0x0 << 6) | 0x3); */ | |
1737 | /* was _io before */ | |
1738 | HFC_outb_nodebug(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); | |
1739 | outw(0x4000, hc->pci_iobase + 4); | |
1740 | outl(leddw, hc->pci_iobase); | |
1741 | HFC_outb_nodebug(hc, R_BRG_PCM_CFG, V_PCM_CLK); | |
1742 | hc->ledstate = leddw; | |
1743 | } | |
1744 | break; | |
1745 | } | |
1746 | } | |
1747 | /* | |
1748 | * read dtmf coefficients | |
1749 | */ | |
1750 | ||
1751 | static void | |
1752 | hfcmulti_dtmf(struct hfc_multi *hc) | |
1753 | { | |
1754 | s32 *coeff; | |
1755 | u_int mantissa; | |
1756 | int co, ch; | |
1757 | struct bchannel *bch = NULL; | |
1758 | u8 exponent; | |
1759 | int dtmf = 0; | |
1760 | int addr; | |
1761 | u16 w_float; | |
1762 | struct sk_buff *skb; | |
1763 | struct mISDNhead *hh; | |
1764 | ||
1765 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1766 | printk(KERN_DEBUG "%s: dtmf detection irq\n", __func__); | |
1767 | for (ch = 0; ch <= 31; ch++) { | |
1768 | /* only process enabled B-channels */ | |
1769 | bch = hc->chan[ch].bch; | |
1770 | if (!bch) | |
1771 | continue; | |
1772 | if (!hc->created[hc->chan[ch].port]) | |
1773 | continue; | |
1774 | if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
1775 | continue; | |
1776 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1777 | printk(KERN_DEBUG "%s: dtmf channel %d:", | |
1778 | __func__, ch); | |
1779 | coeff = &(hc->chan[ch].coeff[hc->chan[ch].coeff_count * 16]); | |
1780 | dtmf = 1; | |
1781 | for (co = 0; co < 8; co++) { | |
1782 | /* read W(n-1) coefficient */ | |
1783 | addr = hc->DTMFbase + ((co<<7) | (ch<<2)); | |
1784 | HFC_outb_nodebug(hc, R_RAM_ADDR0, addr); | |
1785 | HFC_outb_nodebug(hc, R_RAM_ADDR1, addr>>8); | |
1786 | HFC_outb_nodebug(hc, R_RAM_ADDR2, (addr>>16) | |
1787 | | V_ADDR_INC); | |
1788 | w_float = HFC_inb_nodebug(hc, R_RAM_DATA); | |
1789 | w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); | |
1790 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1791 | printk(" %04x", w_float); | |
1792 | ||
1793 | /* decode float (see chip doc) */ | |
1794 | mantissa = w_float & 0x0fff; | |
1795 | if (w_float & 0x8000) | |
1796 | mantissa |= 0xfffff000; | |
1797 | exponent = (w_float>>12) & 0x7; | |
1798 | if (exponent) { | |
1799 | mantissa ^= 0x1000; | |
1800 | mantissa <<= (exponent-1); | |
1801 | } | |
1802 | ||
1803 | /* store coefficient */ | |
1804 | coeff[co<<1] = mantissa; | |
1805 | ||
1806 | /* read W(n) coefficient */ | |
1807 | w_float = HFC_inb_nodebug(hc, R_RAM_DATA); | |
1808 | w_float |= (HFC_inb_nodebug(hc, R_RAM_DATA) << 8); | |
1809 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1810 | printk(" %04x", w_float); | |
1811 | ||
1812 | /* decode float (see chip doc) */ | |
1813 | mantissa = w_float & 0x0fff; | |
1814 | if (w_float & 0x8000) | |
1815 | mantissa |= 0xfffff000; | |
1816 | exponent = (w_float>>12) & 0x7; | |
1817 | if (exponent) { | |
1818 | mantissa ^= 0x1000; | |
1819 | mantissa <<= (exponent-1); | |
1820 | } | |
1821 | ||
1822 | /* store coefficient */ | |
1823 | coeff[(co<<1)|1] = mantissa; | |
1824 | } | |
1825 | if (debug & DEBUG_HFCMULTI_DTMF) | |
1826 | printk("%s: DTMF ready %08x %08x %08x %08x " | |
1827 | "%08x %08x %08x %08x\n", __func__, | |
1828 | coeff[0], coeff[1], coeff[2], coeff[3], | |
1829 | coeff[4], coeff[5], coeff[6], coeff[7]); | |
1830 | hc->chan[ch].coeff_count++; | |
1831 | if (hc->chan[ch].coeff_count == 8) { | |
1832 | hc->chan[ch].coeff_count = 0; | |
1833 | skb = mI_alloc_skb(512, GFP_ATOMIC); | |
1834 | if (!skb) { | |
1835 | printk(KERN_WARNING "%s: No memory for skb\n", | |
1836 | __func__); | |
1837 | continue; | |
1838 | } | |
1839 | hh = mISDN_HEAD_P(skb); | |
1840 | hh->prim = PH_CONTROL_IND; | |
1841 | hh->id = DTMF_HFC_COEF; | |
1842 | memcpy(skb_put(skb, 512), hc->chan[ch].coeff, 512); | |
1843 | recv_Bchannel_skb(bch, skb); | |
1844 | } | |
1845 | } | |
1846 | ||
1847 | /* restart DTMF processing */ | |
1848 | hc->dtmf = dtmf; | |
1849 | if (dtmf) | |
1850 | HFC_outb_nodebug(hc, R_DTMF, hc->hw.r_dtmf | V_RST_DTMF); | |
1851 | } | |
1852 | ||
1853 | ||
1854 | /* | |
1855 | * fill fifo as much as possible | |
1856 | */ | |
1857 | ||
1858 | static void | |
1859 | hfcmulti_tx(struct hfc_multi *hc, int ch) | |
1860 | { | |
1861 | int i, ii, temp, len = 0; | |
1862 | int Zspace, z1, z2; /* must be int for calculation */ | |
1863 | int Fspace, f1, f2; | |
1864 | u_char *d; | |
1865 | int *txpending, slot_tx; | |
1866 | struct bchannel *bch; | |
1867 | struct dchannel *dch; | |
1868 | struct sk_buff **sp = NULL; | |
1869 | int *idxp; | |
1870 | ||
1871 | bch = hc->chan[ch].bch; | |
1872 | dch = hc->chan[ch].dch; | |
1873 | if ((!dch) && (!bch)) | |
1874 | return; | |
1875 | ||
1876 | txpending = &hc->chan[ch].txpending; | |
1877 | slot_tx = hc->chan[ch].slot_tx; | |
1878 | if (dch) { | |
1879 | if (!test_bit(FLG_ACTIVE, &dch->Flags)) | |
1880 | return; | |
1881 | sp = &dch->tx_skb; | |
1882 | idxp = &dch->tx_idx; | |
1883 | } else { | |
1884 | if (!test_bit(FLG_ACTIVE, &bch->Flags)) | |
1885 | return; | |
1886 | sp = &bch->tx_skb; | |
1887 | idxp = &bch->tx_idx; | |
1888 | } | |
1889 | if (*sp) | |
1890 | len = (*sp)->len; | |
1891 | ||
1892 | if ((!len) && *txpending != 1) | |
1893 | return; /* no data */ | |
1894 | ||
1895 | if (test_bit(HFC_CHIP_B410P, &hc->chip) && | |
1896 | (hc->chan[ch].protocol == ISDN_P_B_RAW) && | |
1897 | (hc->chan[ch].slot_rx < 0) && | |
1898 | (hc->chan[ch].slot_tx < 0)) | |
1899 | HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch << 1)); | |
1900 | else | |
1901 | HFC_outb_nodebug(hc, R_FIFO, ch << 1); | |
1902 | HFC_wait_nodebug(hc); | |
1903 | ||
1904 | if (*txpending == 2) { | |
1905 | /* reset fifo */ | |
1906 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); | |
1907 | HFC_wait_nodebug(hc); | |
1908 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
1909 | *txpending = 1; | |
1910 | } | |
1911 | next_frame: | |
1912 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
1913 | f1 = HFC_inb_nodebug(hc, A_F1); | |
1914 | f2 = HFC_inb_nodebug(hc, A_F2); | |
1915 | while (f2 != (temp = HFC_inb_nodebug(hc, A_F2))) { | |
1916 | if (debug & DEBUG_HFCMULTI_FIFO) | |
1917 | printk(KERN_DEBUG | |
1918 | "%s(card %d): reread f2 because %d!=%d\n", | |
1919 | __func__, hc->id + 1, temp, f2); | |
1920 | f2 = temp; /* repeat until F2 is equal */ | |
1921 | } | |
1922 | Fspace = f2 - f1 - 1; | |
1923 | if (Fspace < 0) | |
1924 | Fspace += hc->Flen; | |
1925 | /* | |
1926 | * Old FIFO handling doesn't give us the current Z2 read | |
1927 | * pointer, so we cannot send the next frame before the fifo | |
1928 | * is empty. It makes no difference except for a slightly | |
1929 | * lower performance. | |
1930 | */ | |
1931 | if (test_bit(HFC_CHIP_REVISION0, &hc->chip)) { | |
1932 | if (f1 != f2) | |
1933 | Fspace = 0; | |
1934 | else | |
1935 | Fspace = 1; | |
1936 | } | |
1937 | /* one frame only for ST D-channels, to allow resending */ | |
1938 | if (hc->type != 1 && dch) { | |
1939 | if (f1 != f2) | |
1940 | Fspace = 0; | |
1941 | } | |
1942 | /* F-counter full condition */ | |
1943 | if (Fspace == 0) | |
1944 | return; | |
1945 | } | |
1946 | z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; | |
1947 | z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; | |
1948 | while (z2 != (temp = (HFC_inw_nodebug(hc, A_Z2) - hc->Zmin))) { | |
1949 | if (debug & DEBUG_HFCMULTI_FIFO) | |
1950 | printk(KERN_DEBUG "%s(card %d): reread z2 because " | |
1951 | "%d!=%d\n", __func__, hc->id + 1, temp, z2); | |
1952 | z2 = temp; /* repeat unti Z2 is equal */ | |
1953 | } | |
1954 | Zspace = z2 - z1; | |
1955 | if (Zspace <= 0) | |
1956 | Zspace += hc->Zlen; | |
1957 | Zspace -= 4; /* keep not too full, so pointers will not overrun */ | |
1958 | /* fill transparent data only to maxinum transparent load (minus 4) */ | |
1959 | if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
1960 | Zspace = Zspace - hc->Zlen + hc->max_trans; | |
1961 | if (Zspace <= 0) /* no space of 4 bytes */ | |
1962 | return; | |
1963 | ||
1964 | /* if no data */ | |
1965 | if (!len) { | |
1966 | if (z1 == z2) { /* empty */ | |
1967 | /* if done with FIFO audio data during PCM connection */ | |
1968 | if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && | |
1969 | *txpending && slot_tx >= 0) { | |
1970 | if (debug & DEBUG_HFCMULTI_MODE) | |
1971 | printk(KERN_DEBUG | |
1972 | "%s: reconnecting PCM due to no " | |
1973 | "more FIFO data: channel %d " | |
1974 | "slot_tx %d\n", | |
1975 | __func__, ch, slot_tx); | |
1976 | /* connect slot */ | |
1977 | HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | | |
1978 | V_HDLC_TRP | V_IFF); | |
1979 | HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); | |
1980 | HFC_wait_nodebug(hc); | |
1981 | HFC_outb(hc, A_CON_HDLC, 0xc0 | 0x00 | | |
1982 | V_HDLC_TRP | V_IFF); | |
1983 | HFC_outb_nodebug(hc, R_FIFO, ch<<1); | |
1984 | HFC_wait_nodebug(hc); | |
1985 | } | |
1986 | *txpending = 0; | |
1987 | } | |
1988 | return; /* no data */ | |
1989 | } | |
1990 | ||
1991 | /* if audio data and connected slot */ | |
1992 | if (bch && (!test_bit(FLG_HDLC, &bch->Flags)) && (!*txpending) | |
1993 | && slot_tx >= 0) { | |
1994 | if (debug & DEBUG_HFCMULTI_MODE) | |
1995 | printk(KERN_DEBUG "%s: disconnecting PCM due to " | |
1996 | "FIFO data: channel %d slot_tx %d\n", | |
1997 | __func__, ch, slot_tx); | |
1998 | /* disconnect slot */ | |
1999 | HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF); | |
2000 | HFC_outb_nodebug(hc, R_FIFO, ch<<1 | 1); | |
2001 | HFC_wait_nodebug(hc); | |
2002 | HFC_outb(hc, A_CON_HDLC, 0x80 | 0x00 | V_HDLC_TRP | V_IFF); | |
2003 | HFC_outb_nodebug(hc, R_FIFO, ch<<1); | |
2004 | HFC_wait_nodebug(hc); | |
2005 | } | |
2006 | *txpending = 1; | |
2007 | ||
2008 | /* show activity */ | |
2009 | hc->activity[hc->chan[ch].port] = 1; | |
2010 | ||
2011 | /* fill fifo to what we have left */ | |
2012 | ii = len; | |
2013 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) | |
2014 | temp = 1; | |
2015 | else | |
2016 | temp = 0; | |
2017 | i = *idxp; | |
2018 | d = (*sp)->data + i; | |
2019 | if (ii - i > Zspace) | |
2020 | ii = Zspace + i; | |
2021 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2022 | printk(KERN_DEBUG "%s(card %d): fifo(%d) has %d bytes space " | |
2023 | "left (z1=%04x, z2=%04x) sending %d of %d bytes %s\n", | |
2024 | __func__, hc->id + 1, ch, Zspace, z1, z2, ii-i, len-i, | |
2025 | temp ? "HDLC":"TRANS"); | |
2026 | ||
2027 | ||
2028 | /* Have to prep the audio data */ | |
2029 | hc->write_fifo(hc, d, ii - i); | |
2030 | *idxp = ii; | |
2031 | ||
2032 | /* if not all data has been written */ | |
2033 | if (ii != len) { | |
2034 | /* NOTE: fifo is started by the calling function */ | |
2035 | return; | |
2036 | } | |
2037 | ||
2038 | /* if all data has been written, terminate frame */ | |
2039 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
2040 | /* increment f-counter */ | |
2041 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); | |
2042 | HFC_wait_nodebug(hc); | |
2043 | } | |
2044 | ||
2045 | /* send confirm, since get_net_bframe will not do it with trans */ | |
2046 | if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
2047 | confirm_Bsend(bch); | |
2048 | ||
2049 | /* check for next frame */ | |
2050 | dev_kfree_skb(*sp); | |
2051 | if (bch && get_next_bframe(bch)) { /* hdlc is confirmed here */ | |
2052 | len = (*sp)->len; | |
2053 | goto next_frame; | |
2054 | } | |
2055 | if (dch && get_next_dframe(dch)) { | |
2056 | len = (*sp)->len; | |
2057 | goto next_frame; | |
2058 | } | |
2059 | ||
2060 | /* | |
2061 | * now we have no more data, so in case of transparent, | |
2062 | * we set the last byte in fifo to 'silence' in case we will get | |
2063 | * no more data at all. this prevents sending an undefined value. | |
2064 | */ | |
2065 | if (bch && test_bit(FLG_TRANSPARENT, &bch->Flags)) | |
2066 | HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence); | |
2067 | } | |
2068 | ||
2069 | ||
2070 | /* NOTE: only called if E1 card is in active state */ | |
2071 | static void | |
2072 | hfcmulti_rx(struct hfc_multi *hc, int ch) | |
2073 | { | |
2074 | int temp; | |
2075 | int Zsize, z1, z2 = 0; /* = 0, to make GCC happy */ | |
2076 | int f1 = 0, f2 = 0; /* = 0, to make GCC happy */ | |
2077 | int again = 0; | |
2078 | struct bchannel *bch; | |
2079 | struct dchannel *dch; | |
2080 | struct sk_buff *skb, **sp = NULL; | |
2081 | int maxlen; | |
2082 | ||
2083 | bch = hc->chan[ch].bch; | |
2084 | dch = hc->chan[ch].dch; | |
2085 | if ((!dch) && (!bch)) | |
2086 | return; | |
2087 | if (dch) { | |
2088 | if (!test_bit(FLG_ACTIVE, &dch->Flags)) | |
2089 | return; | |
2090 | sp = &dch->rx_skb; | |
2091 | maxlen = dch->maxlen; | |
2092 | } else { | |
2093 | if (!test_bit(FLG_ACTIVE, &bch->Flags)) | |
2094 | return; | |
2095 | sp = &bch->rx_skb; | |
2096 | maxlen = bch->maxlen; | |
2097 | } | |
2098 | next_frame: | |
2099 | /* on first AND before getting next valid frame, R_FIFO must be written | |
2100 | to. */ | |
2101 | if (test_bit(HFC_CHIP_B410P, &hc->chip) && | |
2102 | (hc->chan[ch].protocol == ISDN_P_B_RAW) && | |
2103 | (hc->chan[ch].slot_rx < 0) && | |
2104 | (hc->chan[ch].slot_tx < 0)) | |
2105 | HFC_outb_nodebug(hc, R_FIFO, 0x20 | (ch<<1) | 1); | |
2106 | else | |
2107 | HFC_outb_nodebug(hc, R_FIFO, (ch<<1)|1); | |
2108 | HFC_wait_nodebug(hc); | |
2109 | ||
2110 | /* ignore if rx is off BUT change fifo (above) to start pending TX */ | |
2111 | if (hc->chan[ch].rx_off) | |
2112 | return; | |
2113 | ||
2114 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
2115 | f1 = HFC_inb_nodebug(hc, A_F1); | |
2116 | while (f1 != (temp = HFC_inb_nodebug(hc, A_F1))) { | |
2117 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2118 | printk(KERN_DEBUG | |
2119 | "%s(card %d): reread f1 because %d!=%d\n", | |
2120 | __func__, hc->id + 1, temp, f1); | |
2121 | f1 = temp; /* repeat until F1 is equal */ | |
2122 | } | |
2123 | f2 = HFC_inb_nodebug(hc, A_F2); | |
2124 | } | |
2125 | z1 = HFC_inw_nodebug(hc, A_Z1) - hc->Zmin; | |
2126 | while (z1 != (temp = (HFC_inw_nodebug(hc, A_Z1) - hc->Zmin))) { | |
2127 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2128 | printk(KERN_DEBUG "%s(card %d): reread z2 because " | |
2129 | "%d!=%d\n", __func__, hc->id + 1, temp, z2); | |
2130 | z1 = temp; /* repeat until Z1 is equal */ | |
2131 | } | |
2132 | z2 = HFC_inw_nodebug(hc, A_Z2) - hc->Zmin; | |
2133 | Zsize = z1 - z2; | |
2134 | if ((dch || test_bit(FLG_HDLC, &bch->Flags)) && f1 != f2) | |
2135 | /* complete hdlc frame */ | |
2136 | Zsize++; | |
2137 | if (Zsize < 0) | |
2138 | Zsize += hc->Zlen; | |
2139 | /* if buffer is empty */ | |
2140 | if (Zsize <= 0) | |
2141 | return; | |
2142 | ||
2143 | if (*sp == NULL) { | |
2144 | *sp = mI_alloc_skb(maxlen + 3, GFP_ATOMIC); | |
2145 | if (*sp == NULL) { | |
2146 | printk(KERN_DEBUG "%s: No mem for rx_skb\n", | |
2147 | __func__); | |
2148 | return; | |
2149 | } | |
2150 | } | |
2151 | /* show activity */ | |
2152 | hc->activity[hc->chan[ch].port] = 1; | |
2153 | ||
2154 | /* empty fifo with what we have */ | |
2155 | if (dch || test_bit(FLG_HDLC, &bch->Flags)) { | |
2156 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2157 | printk(KERN_DEBUG "%s(card %d): fifo(%d) reading %d " | |
2158 | "bytes (z1=%04x, z2=%04x) HDLC %s (f1=%d, f2=%d) " | |
2159 | "got=%d (again %d)\n", __func__, hc->id + 1, ch, | |
2160 | Zsize, z1, z2, (f1 == f2) ? "fragment" : "COMPLETE", | |
2161 | f1, f2, Zsize + (*sp)->len, again); | |
2162 | /* HDLC */ | |
2163 | if ((Zsize + (*sp)->len) > (maxlen + 3)) { | |
2164 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2165 | printk(KERN_DEBUG | |
2166 | "%s(card %d): hdlc-frame too large.\n", | |
2167 | __func__, hc->id + 1); | |
2168 | skb_trim(*sp, 0); | |
2169 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); | |
2170 | HFC_wait_nodebug(hc); | |
2171 | return; | |
2172 | } | |
2173 | ||
2174 | hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); | |
2175 | ||
2176 | if (f1 != f2) { | |
2177 | /* increment Z2,F2-counter */ | |
2178 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_INC_F); | |
2179 | HFC_wait_nodebug(hc); | |
2180 | /* check size */ | |
2181 | if ((*sp)->len < 4) { | |
2182 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2183 | printk(KERN_DEBUG | |
2184 | "%s(card %d): Frame below minimum " | |
2185 | "size\n", __func__, hc->id + 1); | |
2186 | skb_trim(*sp, 0); | |
2187 | goto next_frame; | |
2188 | } | |
2189 | /* there is at least one complete frame, check crc */ | |
2190 | if ((*sp)->data[(*sp)->len - 1]) { | |
2191 | if (debug & DEBUG_HFCMULTI_CRC) | |
2192 | printk(KERN_DEBUG | |
2193 | "%s: CRC-error\n", __func__); | |
2194 | skb_trim(*sp, 0); | |
2195 | goto next_frame; | |
2196 | } | |
2197 | skb_trim(*sp, (*sp)->len - 3); | |
2198 | if ((*sp)->len < MISDN_COPY_SIZE) { | |
2199 | skb = *sp; | |
2200 | *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); | |
2201 | if (*sp) { | |
2202 | memcpy(skb_put(*sp, skb->len), | |
2203 | skb->data, skb->len); | |
2204 | skb_trim(skb, 0); | |
2205 | } else { | |
2206 | printk(KERN_DEBUG "%s: No mem\n", | |
2207 | __func__); | |
2208 | *sp = skb; | |
2209 | skb = NULL; | |
2210 | } | |
2211 | } else { | |
2212 | skb = NULL; | |
2213 | } | |
2214 | if (debug & DEBUG_HFCMULTI_FIFO) { | |
2215 | printk(KERN_DEBUG "%s(card %d):", | |
2216 | __func__, hc->id + 1); | |
2217 | temp = 0; | |
2218 | while (temp < (*sp)->len) | |
2219 | printk(" %02x", (*sp)->data[temp++]); | |
2220 | printk("\n"); | |
2221 | } | |
2222 | if (dch) | |
2223 | recv_Dchannel(dch); | |
2224 | else | |
2225 | recv_Bchannel(bch); | |
2226 | *sp = skb; | |
2227 | again++; | |
2228 | goto next_frame; | |
2229 | } | |
2230 | /* there is an incomplete frame */ | |
2231 | } else { | |
2232 | /* transparent */ | |
2233 | if (Zsize > skb_tailroom(*sp)) | |
2234 | Zsize = skb_tailroom(*sp); | |
2235 | hc->read_fifo(hc, skb_put(*sp, Zsize), Zsize); | |
2236 | if (((*sp)->len) < MISDN_COPY_SIZE) { | |
2237 | skb = *sp; | |
2238 | *sp = mI_alloc_skb(skb->len, GFP_ATOMIC); | |
2239 | if (*sp) { | |
2240 | memcpy(skb_put(*sp, skb->len), | |
2241 | skb->data, skb->len); | |
2242 | skb_trim(skb, 0); | |
2243 | } else { | |
2244 | printk(KERN_DEBUG "%s: No mem\n", __func__); | |
2245 | *sp = skb; | |
2246 | skb = NULL; | |
2247 | } | |
2248 | } else { | |
2249 | skb = NULL; | |
2250 | } | |
2251 | if (debug & DEBUG_HFCMULTI_FIFO) | |
2252 | printk(KERN_DEBUG | |
2253 | "%s(card %d): fifo(%d) reading %d bytes " | |
2254 | "(z1=%04x, z2=%04x) TRANS\n", | |
2255 | __func__, hc->id + 1, ch, Zsize, z1, z2); | |
2256 | /* only bch is transparent */ | |
2257 | recv_Bchannel(bch); | |
2258 | *sp = skb; | |
2259 | } | |
2260 | } | |
2261 | ||
2262 | ||
2263 | /* | |
2264 | * Interrupt handler | |
2265 | */ | |
2266 | static void | |
2267 | signal_state_up(struct dchannel *dch, int info, char *msg) | |
2268 | { | |
2269 | struct sk_buff *skb; | |
2270 | int id, data = info; | |
2271 | ||
2272 | if (debug & DEBUG_HFCMULTI_STATE) | |
2273 | printk(KERN_DEBUG "%s: %s\n", __func__, msg); | |
2274 | ||
2275 | id = TEI_SAPI | (GROUP_TEI << 8); /* manager address */ | |
2276 | ||
2277 | skb = _alloc_mISDN_skb(MPH_INFORMATION_IND, id, sizeof(data), &data, | |
2278 | GFP_ATOMIC); | |
2279 | if (!skb) | |
2280 | return; | |
2281 | recv_Dchannel_skb(dch, skb); | |
2282 | } | |
2283 | ||
2284 | static inline void | |
2285 | handle_timer_irq(struct hfc_multi *hc) | |
2286 | { | |
2287 | int ch, temp; | |
2288 | struct dchannel *dch; | |
2289 | u_long flags; | |
2290 | ||
2291 | /* process queued resync jobs */ | |
2292 | if (hc->e1_resync) { | |
2293 | /* lock, so e1_resync gets not changed */ | |
2294 | spin_lock_irqsave(&HFClock, flags); | |
2295 | if (hc->e1_resync & 1) { | |
2296 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
2297 | printk(KERN_DEBUG "Enable SYNC_I\n"); | |
2298 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC); | |
2299 | /* disable JATT, if RX_SYNC is set */ | |
2300 | if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) | |
2301 | HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); | |
2302 | } | |
2303 | if (hc->e1_resync & 2) { | |
2304 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
2305 | printk(KERN_DEBUG "Enable jatt PLL\n"); | |
2306 | HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); | |
2307 | } | |
2308 | if (hc->e1_resync & 4) { | |
2309 | if (debug & DEBUG_HFCMULTI_PLXSD) | |
2310 | printk(KERN_DEBUG | |
2311 | "Enable QUARTZ for HFC-E1\n"); | |
2312 | /* set jatt to quartz */ | |
2313 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | |
2314 | | V_JATT_OFF); | |
2315 | /* switch to JATT, in case it is not already */ | |
2316 | HFC_outb(hc, R_SYNC_OUT, 0); | |
2317 | } | |
2318 | hc->e1_resync = 0; | |
2319 | spin_unlock_irqrestore(&HFClock, flags); | |
2320 | } | |
2321 | ||
2322 | if (hc->type != 1 || hc->e1_state == 1) | |
2323 | for (ch = 0; ch <= 31; ch++) { | |
2324 | if (hc->created[hc->chan[ch].port]) { | |
2325 | hfcmulti_tx(hc, ch); | |
2326 | /* fifo is started when switching to rx-fifo */ | |
2327 | hfcmulti_rx(hc, ch); | |
2328 | if (hc->chan[ch].dch && | |
2329 | hc->chan[ch].nt_timer > -1) { | |
2330 | dch = hc->chan[ch].dch; | |
2331 | if (!(--hc->chan[ch].nt_timer)) { | |
2332 | schedule_event(dch, | |
2333 | FLG_PHCHANGE); | |
2334 | if (debug & | |
2335 | DEBUG_HFCMULTI_STATE) | |
2336 | printk(KERN_DEBUG | |
2337 | "%s: nt_timer at " | |
2338 | "state %x\n", | |
2339 | __func__, | |
2340 | dch->state); | |
2341 | } | |
2342 | } | |
2343 | } | |
2344 | } | |
2345 | if (hc->type == 1 && hc->created[0]) { | |
2346 | dch = hc->chan[hc->dslot].dch; | |
2347 | if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { | |
2348 | /* LOS */ | |
2349 | temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_SIG_LOS; | |
2350 | if (!temp && hc->chan[hc->dslot].los) | |
2351 | signal_state_up(dch, L1_SIGNAL_LOS_ON, | |
2352 | "LOS detected"); | |
2353 | if (temp && !hc->chan[hc->dslot].los) | |
2354 | signal_state_up(dch, L1_SIGNAL_LOS_OFF, | |
2355 | "LOS gone"); | |
2356 | hc->chan[hc->dslot].los = temp; | |
2357 | } | |
2358 | if (test_bit(HFC_CFG_REPORT_AIS, &hc->chan[hc->dslot].cfg)) { | |
2359 | /* AIS */ | |
2360 | temp = HFC_inb_nodebug(hc, R_SYNC_STA) & V_AIS; | |
2361 | if (!temp && hc->chan[hc->dslot].ais) | |
2362 | signal_state_up(dch, L1_SIGNAL_AIS_ON, | |
2363 | "AIS detected"); | |
2364 | if (temp && !hc->chan[hc->dslot].ais) | |
2365 | signal_state_up(dch, L1_SIGNAL_AIS_OFF, | |
2366 | "AIS gone"); | |
2367 | hc->chan[hc->dslot].ais = temp; | |
2368 | } | |
2369 | if (test_bit(HFC_CFG_REPORT_SLIP, &hc->chan[hc->dslot].cfg)) { | |
2370 | /* SLIP */ | |
2371 | temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_RX; | |
2372 | if (!temp && hc->chan[hc->dslot].slip_rx) | |
2373 | signal_state_up(dch, L1_SIGNAL_SLIP_RX, | |
2374 | " bit SLIP detected RX"); | |
2375 | hc->chan[hc->dslot].slip_rx = temp; | |
2376 | temp = HFC_inb_nodebug(hc, R_SLIP) & V_FOSLIP_TX; | |
2377 | if (!temp && hc->chan[hc->dslot].slip_tx) | |
2378 | signal_state_up(dch, L1_SIGNAL_SLIP_TX, | |
2379 | " bit SLIP detected TX"); | |
2380 | hc->chan[hc->dslot].slip_tx = temp; | |
2381 | } | |
2382 | if (test_bit(HFC_CFG_REPORT_RDI, &hc->chan[hc->dslot].cfg)) { | |
2383 | /* RDI */ | |
2384 | temp = HFC_inb_nodebug(hc, R_RX_SL0_0) & V_A; | |
2385 | if (!temp && hc->chan[hc->dslot].rdi) | |
2386 | signal_state_up(dch, L1_SIGNAL_RDI_ON, | |
2387 | "RDI detected"); | |
2388 | if (temp && !hc->chan[hc->dslot].rdi) | |
2389 | signal_state_up(dch, L1_SIGNAL_RDI_OFF, | |
2390 | "RDI gone"); | |
2391 | hc->chan[hc->dslot].rdi = temp; | |
2392 | } | |
2393 | temp = HFC_inb_nodebug(hc, R_JATT_DIR); | |
2394 | switch (hc->chan[hc->dslot].sync) { | |
2395 | case 0: | |
2396 | if ((temp & 0x60) == 0x60) { | |
2397 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2398 | printk(KERN_DEBUG | |
2399 | "%s: (id=%d) E1 now " | |
2400 | "in clock sync\n", | |
2401 | __func__, hc->id); | |
2402 | HFC_outb(hc, R_RX_OFF, | |
2403 | hc->chan[hc->dslot].jitter | V_RX_INIT); | |
2404 | HFC_outb(hc, R_TX_OFF, | |
2405 | hc->chan[hc->dslot].jitter | V_RX_INIT); | |
2406 | hc->chan[hc->dslot].sync = 1; | |
2407 | goto check_framesync; | |
2408 | } | |
2409 | break; | |
2410 | case 1: | |
2411 | if ((temp & 0x60) != 0x60) { | |
2412 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2413 | printk(KERN_DEBUG | |
2414 | "%s: (id=%d) E1 " | |
2415 | "lost clock sync\n", | |
2416 | __func__, hc->id); | |
2417 | hc->chan[hc->dslot].sync = 0; | |
2418 | break; | |
2419 | } | |
2420 | check_framesync: | |
2421 | temp = HFC_inb_nodebug(hc, R_SYNC_STA); | |
2422 | if (temp == 0x27) { | |
2423 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2424 | printk(KERN_DEBUG | |
2425 | "%s: (id=%d) E1 " | |
2426 | "now in frame sync\n", | |
2427 | __func__, hc->id); | |
2428 | hc->chan[hc->dslot].sync = 2; | |
2429 | } | |
2430 | break; | |
2431 | case 2: | |
2432 | if ((temp & 0x60) != 0x60) { | |
2433 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2434 | printk(KERN_DEBUG | |
2435 | "%s: (id=%d) E1 lost " | |
2436 | "clock & frame sync\n", | |
2437 | __func__, hc->id); | |
2438 | hc->chan[hc->dslot].sync = 0; | |
2439 | break; | |
2440 | } | |
2441 | temp = HFC_inb_nodebug(hc, R_SYNC_STA); | |
2442 | if (temp != 0x27) { | |
2443 | if (debug & DEBUG_HFCMULTI_SYNC) | |
2444 | printk(KERN_DEBUG | |
2445 | "%s: (id=%d) E1 " | |
2446 | "lost frame sync\n", | |
2447 | __func__, hc->id); | |
2448 | hc->chan[hc->dslot].sync = 1; | |
2449 | } | |
2450 | break; | |
2451 | } | |
2452 | } | |
2453 | ||
2454 | if (test_bit(HFC_CHIP_WATCHDOG, &hc->chip)) | |
2455 | hfcmulti_watchdog(hc); | |
2456 | ||
2457 | if (hc->leds) | |
2458 | hfcmulti_leds(hc); | |
2459 | } | |
2460 | ||
2461 | static void | |
2462 | ph_state_irq(struct hfc_multi *hc, u_char r_irq_statech) | |
2463 | { | |
2464 | struct dchannel *dch; | |
2465 | int ch; | |
2466 | int active; | |
2467 | u_char st_status, temp; | |
2468 | ||
2469 | /* state machine */ | |
2470 | for (ch = 0; ch <= 31; ch++) { | |
2471 | if (hc->chan[ch].dch) { | |
2472 | dch = hc->chan[ch].dch; | |
2473 | if (r_irq_statech & 1) { | |
2474 | HFC_outb_nodebug(hc, R_ST_SEL, | |
2475 | hc->chan[ch].port); | |
2476 | /* undocumented: delay after R_ST_SEL */ | |
2477 | udelay(1); | |
2478 | /* undocumented: status changes during read */ | |
2479 | st_status = HFC_inb_nodebug(hc, A_ST_RD_STATE); | |
2480 | while (st_status != (temp = | |
2481 | HFC_inb_nodebug(hc, A_ST_RD_STATE))) { | |
2482 | if (debug & DEBUG_HFCMULTI_STATE) | |
2483 | printk(KERN_DEBUG "%s: reread " | |
2484 | "STATE because %d!=%d\n", | |
2485 | __func__, temp, | |
2486 | st_status); | |
2487 | st_status = temp; /* repeat */ | |
2488 | } | |
2489 | ||
2490 | /* Speech Design TE-sync indication */ | |
2491 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) && | |
2492 | dch->dev.D.protocol == ISDN_P_TE_S0) { | |
2493 | if (st_status & V_FR_SYNC_ST) | |
2494 | hc->syncronized |= | |
2495 | (1 << hc->chan[ch].port); | |
2496 | else | |
2497 | hc->syncronized &= | |
2498 | ~(1 << hc->chan[ch].port); | |
2499 | } | |
2500 | dch->state = st_status & 0x0f; | |
2501 | if (dch->dev.D.protocol == ISDN_P_NT_S0) | |
2502 | active = 3; | |
2503 | else | |
2504 | active = 7; | |
2505 | if (dch->state == active) { | |
2506 | HFC_outb_nodebug(hc, R_FIFO, | |
2507 | (ch << 1) | 1); | |
2508 | HFC_wait_nodebug(hc); | |
2509 | HFC_outb_nodebug(hc, | |
2510 | R_INC_RES_FIFO, V_RES_F); | |
2511 | HFC_wait_nodebug(hc); | |
2512 | dch->tx_idx = 0; | |
2513 | } | |
2514 | schedule_event(dch, FLG_PHCHANGE); | |
2515 | if (debug & DEBUG_HFCMULTI_STATE) | |
2516 | printk(KERN_DEBUG | |
2517 | "%s: S/T newstate %x port %d\n", | |
2518 | __func__, dch->state, | |
2519 | hc->chan[ch].port); | |
2520 | } | |
2521 | r_irq_statech >>= 1; | |
2522 | } | |
2523 | } | |
2524 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) | |
2525 | plxsd_checksync(hc, 0); | |
2526 | } | |
2527 | ||
2528 | static void | |
2529 | fifo_irq(struct hfc_multi *hc, int block) | |
2530 | { | |
2531 | int ch, j; | |
2532 | struct dchannel *dch; | |
2533 | struct bchannel *bch; | |
2534 | u_char r_irq_fifo_bl; | |
2535 | ||
2536 | r_irq_fifo_bl = HFC_inb_nodebug(hc, R_IRQ_FIFO_BL0 + block); | |
2537 | j = 0; | |
2538 | while (j < 8) { | |
2539 | ch = (block << 2) + (j >> 1); | |
2540 | dch = hc->chan[ch].dch; | |
2541 | bch = hc->chan[ch].bch; | |
2542 | if (((!dch) && (!bch)) || (!hc->created[hc->chan[ch].port])) { | |
2543 | j += 2; | |
2544 | continue; | |
2545 | } | |
2546 | if (dch && (r_irq_fifo_bl & (1 << j)) && | |
2547 | test_bit(FLG_ACTIVE, &dch->Flags)) { | |
2548 | hfcmulti_tx(hc, ch); | |
2549 | /* start fifo */ | |
2550 | HFC_outb_nodebug(hc, R_FIFO, 0); | |
2551 | HFC_wait_nodebug(hc); | |
2552 | } | |
2553 | if (bch && (r_irq_fifo_bl & (1 << j)) && | |
2554 | test_bit(FLG_ACTIVE, &bch->Flags)) { | |
2555 | hfcmulti_tx(hc, ch); | |
2556 | /* start fifo */ | |
2557 | HFC_outb_nodebug(hc, R_FIFO, 0); | |
2558 | HFC_wait_nodebug(hc); | |
2559 | } | |
2560 | j++; | |
2561 | if (dch && (r_irq_fifo_bl & (1 << j)) && | |
2562 | test_bit(FLG_ACTIVE, &dch->Flags)) { | |
2563 | hfcmulti_rx(hc, ch); | |
2564 | } | |
2565 | if (bch && (r_irq_fifo_bl & (1 << j)) && | |
2566 | test_bit(FLG_ACTIVE, &bch->Flags)) { | |
2567 | hfcmulti_rx(hc, ch); | |
2568 | } | |
2569 | j++; | |
2570 | } | |
2571 | } | |
2572 | ||
2573 | #ifdef IRQ_DEBUG | |
2574 | int irqsem; | |
2575 | #endif | |
2576 | static irqreturn_t | |
2577 | hfcmulti_interrupt(int intno, void *dev_id) | |
2578 | { | |
2579 | #ifdef IRQCOUNT_DEBUG | |
2580 | static int iq1 = 0, iq2 = 0, iq3 = 0, iq4 = 0, | |
2581 | iq5 = 0, iq6 = 0, iqcnt = 0; | |
2582 | #endif | |
2583 | static int count; | |
2584 | struct hfc_multi *hc = dev_id; | |
2585 | struct dchannel *dch; | |
2586 | u_char r_irq_statech, status, r_irq_misc, r_irq_oview; | |
2587 | int i; | |
2588 | u_short *plx_acc, wval; | |
2589 | u_char e1_syncsta, temp; | |
2590 | u_long flags; | |
2591 | ||
2592 | if (!hc) { | |
2593 | printk(KERN_ERR "HFC-multi: Spurious interrupt!\n"); | |
2594 | return IRQ_NONE; | |
2595 | } | |
2596 | ||
2597 | spin_lock(&hc->lock); | |
2598 | ||
2599 | #ifdef IRQ_DEBUG | |
2600 | if (irqsem) | |
2601 | printk(KERN_ERR "irq for card %d during irq from " | |
2602 | "card %d, this is no bug.\n", hc->id + 1, irqsem); | |
2603 | irqsem = hc->id + 1; | |
2604 | #endif | |
2605 | ||
2606 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
2607 | spin_lock_irqsave(&plx_lock, flags); | |
2608 | plx_acc = (u_short *)(hc->plx_membase + PLX_INTCSR); | |
2609 | wval = readw(plx_acc); | |
2610 | spin_unlock_irqrestore(&plx_lock, flags); | |
2611 | if (!(wval & PLX_INTCSR_LINTI1_STATUS)) | |
2612 | goto irq_notforus; | |
2613 | } | |
2614 | ||
2615 | status = HFC_inb_nodebug(hc, R_STATUS); | |
2616 | r_irq_statech = HFC_inb_nodebug(hc, R_IRQ_STATECH); | |
2617 | #ifdef IRQCOUNT_DEBUG | |
2618 | if (r_irq_statech) | |
2619 | iq1++; | |
2620 | if (status & V_DTMF_STA) | |
2621 | iq2++; | |
2622 | if (status & V_LOST_STA) | |
2623 | iq3++; | |
2624 | if (status & V_EXT_IRQSTA) | |
2625 | iq4++; | |
2626 | if (status & V_MISC_IRQSTA) | |
2627 | iq5++; | |
2628 | if (status & V_FR_IRQSTA) | |
2629 | iq6++; | |
2630 | if (iqcnt++ > 5000) { | |
2631 | printk(KERN_ERR "iq1:%x iq2:%x iq3:%x iq4:%x iq5:%x iq6:%x\n", | |
2632 | iq1, iq2, iq3, iq4, iq5, iq6); | |
2633 | iqcnt = 0; | |
2634 | } | |
2635 | #endif | |
2636 | if (!r_irq_statech && | |
2637 | !(status & (V_DTMF_STA | V_LOST_STA | V_EXT_IRQSTA | | |
2638 | V_MISC_IRQSTA | V_FR_IRQSTA))) { | |
2639 | /* irq is not for us */ | |
2640 | goto irq_notforus; | |
2641 | } | |
2642 | hc->irqcnt++; | |
2643 | if (r_irq_statech) { | |
2644 | if (hc->type != 1) | |
2645 | ph_state_irq(hc, r_irq_statech); | |
2646 | } | |
2647 | if (status & V_EXT_IRQSTA) | |
2648 | ; /* external IRQ */ | |
2649 | if (status & V_LOST_STA) { | |
2650 | /* LOST IRQ */ | |
2651 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_LOST); /* clear irq! */ | |
2652 | } | |
2653 | if (status & V_MISC_IRQSTA) { | |
2654 | /* misc IRQ */ | |
2655 | r_irq_misc = HFC_inb_nodebug(hc, R_IRQ_MISC); | |
2656 | if (r_irq_misc & V_STA_IRQ) { | |
2657 | if (hc->type == 1) { | |
2658 | /* state machine */ | |
2659 | dch = hc->chan[hc->dslot].dch; | |
2660 | e1_syncsta = HFC_inb_nodebug(hc, R_SYNC_STA); | |
2661 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip) | |
2662 | && hc->e1_getclock) { | |
2663 | if (e1_syncsta & V_FR_SYNC_E1) | |
2664 | hc->syncronized = 1; | |
2665 | else | |
2666 | hc->syncronized = 0; | |
2667 | } | |
2668 | /* undocumented: status changes during read */ | |
2669 | dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA); | |
2670 | while (dch->state != (temp = | |
2671 | HFC_inb_nodebug(hc, R_E1_RD_STA))) { | |
2672 | if (debug & DEBUG_HFCMULTI_STATE) | |
2673 | printk(KERN_DEBUG "%s: reread " | |
2674 | "STATE because %d!=%d\n", | |
2675 | __func__, temp, | |
2676 | dch->state); | |
2677 | dch->state = temp; /* repeat */ | |
2678 | } | |
2679 | dch->state = HFC_inb_nodebug(hc, R_E1_RD_STA) | |
2680 | & 0x7; | |
2681 | schedule_event(dch, FLG_PHCHANGE); | |
2682 | if (debug & DEBUG_HFCMULTI_STATE) | |
2683 | printk(KERN_DEBUG | |
2684 | "%s: E1 (id=%d) newstate %x\n", | |
2685 | __func__, hc->id, dch->state); | |
2686 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) | |
2687 | plxsd_checksync(hc, 0); | |
2688 | } | |
2689 | } | |
2690 | if (r_irq_misc & V_TI_IRQ) | |
2691 | handle_timer_irq(hc); | |
2692 | ||
2693 | if (r_irq_misc & V_DTMF_IRQ) { | |
2694 | /* -> DTMF IRQ */ | |
2695 | hfcmulti_dtmf(hc); | |
2696 | } | |
2697 | /* TODO: REPLACE !!!! 125 us Interrupts are not acceptable */ | |
2698 | if (r_irq_misc & V_IRQ_PROC) { | |
2699 | /* IRQ every 125us */ | |
2700 | count++; | |
2701 | /* generate 1kHz signal */ | |
2702 | if (count == 8) { | |
2703 | if (hfc_interrupt) | |
2704 | hfc_interrupt(); | |
2705 | count = 0; | |
2706 | } | |
2707 | } | |
2708 | ||
2709 | } | |
2710 | if (status & V_FR_IRQSTA) { | |
2711 | /* FIFO IRQ */ | |
2712 | r_irq_oview = HFC_inb_nodebug(hc, R_IRQ_OVIEW); | |
2713 | for (i = 0; i < 8; i++) { | |
2714 | if (r_irq_oview & (1 << i)) | |
2715 | fifo_irq(hc, i); | |
2716 | } | |
2717 | } | |
2718 | ||
2719 | #ifdef IRQ_DEBUG | |
2720 | irqsem = 0; | |
2721 | #endif | |
2722 | spin_unlock(&hc->lock); | |
2723 | return IRQ_HANDLED; | |
2724 | ||
2725 | irq_notforus: | |
2726 | #ifdef IRQ_DEBUG | |
2727 | irqsem = 0; | |
2728 | #endif | |
2729 | spin_unlock(&hc->lock); | |
2730 | return IRQ_NONE; | |
2731 | } | |
2732 | ||
2733 | ||
2734 | /* | |
2735 | * timer callback for D-chan busy resolution. Currently no function | |
2736 | */ | |
2737 | ||
2738 | static void | |
2739 | hfcmulti_dbusy_timer(struct hfc_multi *hc) | |
2740 | { | |
2741 | } | |
2742 | ||
2743 | ||
2744 | /* | |
2745 | * activate/deactivate hardware for selected channels and mode | |
2746 | * | |
2747 | * configure B-channel with the given protocol | |
2748 | * ch eqals to the HFC-channel (0-31) | |
2749 | * ch is the number of channel (0-4,4-7,8-11,12-15,16-19,20-23,24-27,28-31 | |
2750 | * for S/T, 1-31 for E1) | |
2751 | * the hdlc interrupts will be set/unset | |
2752 | */ | |
2753 | static int | |
2754 | mode_hfcmulti(struct hfc_multi *hc, int ch, int protocol, int slot_tx, | |
2755 | int bank_tx, int slot_rx, int bank_rx) | |
2756 | { | |
2757 | int flow_tx = 0, flow_rx = 0, routing = 0; | |
2758 | int oslot_tx, oslot_rx; | |
2759 | int conf; | |
2760 | ||
2761 | if (ch < 0 || ch > 31) | |
2762 | return EINVAL; | |
2763 | oslot_tx = hc->chan[ch].slot_tx; | |
2764 | oslot_rx = hc->chan[ch].slot_rx; | |
2765 | conf = hc->chan[ch].conf; | |
2766 | ||
2767 | if (debug & DEBUG_HFCMULTI_MODE) | |
2768 | printk(KERN_DEBUG | |
2769 | "%s: card %d channel %d protocol %x slot old=%d new=%d " | |
2770 | "bank new=%d (TX) slot old=%d new=%d bank new=%d (RX)\n", | |
2771 | __func__, hc->id, ch, protocol, oslot_tx, slot_tx, | |
2772 | bank_tx, oslot_rx, slot_rx, bank_rx); | |
2773 | ||
2774 | if (oslot_tx >= 0 && slot_tx != oslot_tx) { | |
2775 | /* remove from slot */ | |
2776 | if (debug & DEBUG_HFCMULTI_MODE) | |
2777 | printk(KERN_DEBUG "%s: remove from slot %d (TX)\n", | |
2778 | __func__, oslot_tx); | |
2779 | if (hc->slot_owner[oslot_tx<<1] == ch) { | |
2780 | HFC_outb(hc, R_SLOT, oslot_tx << 1); | |
2781 | HFC_outb(hc, A_SL_CFG, 0); | |
2782 | HFC_outb(hc, A_CONF, 0); | |
2783 | hc->slot_owner[oslot_tx<<1] = -1; | |
2784 | } else { | |
2785 | if (debug & DEBUG_HFCMULTI_MODE) | |
2786 | printk(KERN_DEBUG | |
2787 | "%s: we are not owner of this tx slot " | |
2788 | "anymore, channel %d is.\n", | |
2789 | __func__, hc->slot_owner[oslot_tx<<1]); | |
2790 | } | |
2791 | } | |
2792 | ||
2793 | if (oslot_rx >= 0 && slot_rx != oslot_rx) { | |
2794 | /* remove from slot */ | |
2795 | if (debug & DEBUG_HFCMULTI_MODE) | |
2796 | printk(KERN_DEBUG | |
2797 | "%s: remove from slot %d (RX)\n", | |
2798 | __func__, oslot_rx); | |
2799 | if (hc->slot_owner[(oslot_rx << 1) | 1] == ch) { | |
2800 | HFC_outb(hc, R_SLOT, (oslot_rx << 1) | V_SL_DIR); | |
2801 | HFC_outb(hc, A_SL_CFG, 0); | |
2802 | hc->slot_owner[(oslot_rx << 1) | 1] = -1; | |
2803 | } else { | |
2804 | if (debug & DEBUG_HFCMULTI_MODE) | |
2805 | printk(KERN_DEBUG | |
2806 | "%s: we are not owner of this rx slot " | |
2807 | "anymore, channel %d is.\n", | |
2808 | __func__, | |
2809 | hc->slot_owner[(oslot_rx << 1) | 1]); | |
2810 | } | |
2811 | } | |
2812 | ||
2813 | if (slot_tx < 0) { | |
2814 | flow_tx = 0x80; /* FIFO->ST */ | |
2815 | /* disable pcm slot */ | |
2816 | hc->chan[ch].slot_tx = -1; | |
2817 | hc->chan[ch].bank_tx = 0; | |
2818 | } else { | |
2819 | /* set pcm slot */ | |
2820 | if (hc->chan[ch].txpending) | |
2821 | flow_tx = 0x80; /* FIFO->ST */ | |
2822 | else | |
2823 | flow_tx = 0xc0; /* PCM->ST */ | |
2824 | /* put on slot */ | |
2825 | routing = bank_tx ? 0xc0 : 0x80; | |
2826 | if (conf >= 0 || bank_tx > 1) | |
2827 | routing = 0x40; /* loop */ | |
2828 | if (debug & DEBUG_HFCMULTI_MODE) | |
2829 | printk(KERN_DEBUG "%s: put channel %d to slot %d bank" | |
2830 | " %d flow %02x routing %02x conf %d (TX)\n", | |
2831 | __func__, ch, slot_tx, bank_tx, | |
2832 | flow_tx, routing, conf); | |
2833 | HFC_outb(hc, R_SLOT, slot_tx << 1); | |
2834 | HFC_outb(hc, A_SL_CFG, (ch<<1) | routing); | |
2835 | HFC_outb(hc, A_CONF, (conf < 0) ? 0 : (conf | V_CONF_SL)); | |
2836 | hc->slot_owner[slot_tx << 1] = ch; | |
2837 | hc->chan[ch].slot_tx = slot_tx; | |
2838 | hc->chan[ch].bank_tx = bank_tx; | |
2839 | } | |
2840 | if (slot_rx < 0) { | |
2841 | /* disable pcm slot */ | |
2842 | flow_rx = 0x80; /* ST->FIFO */ | |
2843 | hc->chan[ch].slot_rx = -1; | |
2844 | hc->chan[ch].bank_rx = 0; | |
2845 | } else { | |
2846 | /* set pcm slot */ | |
2847 | if (hc->chan[ch].txpending) | |
2848 | flow_rx = 0x80; /* ST->FIFO */ | |
2849 | else | |
2850 | flow_rx = 0xc0; /* ST->(FIFO,PCM) */ | |
2851 | /* put on slot */ | |
2852 | routing = bank_rx?0x80:0xc0; /* reversed */ | |
2853 | if (conf >= 0 || bank_rx > 1) | |
2854 | routing = 0x40; /* loop */ | |
2855 | if (debug & DEBUG_HFCMULTI_MODE) | |
2856 | printk(KERN_DEBUG "%s: put channel %d to slot %d bank" | |
2857 | " %d flow %02x routing %02x conf %d (RX)\n", | |
2858 | __func__, ch, slot_rx, bank_rx, | |
2859 | flow_rx, routing, conf); | |
2860 | HFC_outb(hc, R_SLOT, (slot_rx<<1) | V_SL_DIR); | |
2861 | HFC_outb(hc, A_SL_CFG, (ch<<1) | V_CH_DIR | routing); | |
2862 | hc->slot_owner[(slot_rx<<1)|1] = ch; | |
2863 | hc->chan[ch].slot_rx = slot_rx; | |
2864 | hc->chan[ch].bank_rx = bank_rx; | |
2865 | } | |
2866 | ||
2867 | switch (protocol) { | |
2868 | case (ISDN_P_NONE): | |
2869 | /* disable TX fifo */ | |
2870 | HFC_outb(hc, R_FIFO, ch << 1); | |
2871 | HFC_wait(hc); | |
2872 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | V_IFF); | |
2873 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2874 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2875 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2876 | HFC_wait(hc); | |
2877 | /* disable RX fifo */ | |
2878 | HFC_outb(hc, R_FIFO, (ch<<1)|1); | |
2879 | HFC_wait(hc); | |
2880 | HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00); | |
2881 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2882 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2883 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2884 | HFC_wait(hc); | |
2885 | if (hc->chan[ch].bch && hc->type != 1) { | |
2886 | hc->hw.a_st_ctrl0[hc->chan[ch].port] &= | |
2887 | ((ch & 0x3) == 0)? ~V_B1_EN: ~V_B2_EN; | |
2888 | HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); | |
2889 | /* undocumented: delay after R_ST_SEL */ | |
2890 | udelay(1); | |
2891 | HFC_outb(hc, A_ST_CTRL0, | |
2892 | hc->hw.a_st_ctrl0[hc->chan[ch].port]); | |
2893 | } | |
2894 | if (hc->chan[ch].bch) { | |
2895 | test_and_clear_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); | |
2896 | test_and_clear_bit(FLG_TRANSPARENT, | |
2897 | &hc->chan[ch].bch->Flags); | |
2898 | } | |
2899 | break; | |
2900 | case (ISDN_P_B_RAW): /* B-channel */ | |
2901 | ||
2902 | if (test_bit(HFC_CHIP_B410P, &hc->chip) && | |
2903 | (hc->chan[ch].slot_rx < 0) && | |
2904 | (hc->chan[ch].slot_tx < 0)) { | |
2905 | ||
2906 | printk(KERN_DEBUG | |
2907 | "Setting B-channel %d to echo cancelable " | |
2908 | "state on PCM slot %d\n", ch, | |
2909 | ((ch / 4) * 8) + ((ch % 4) * 4) + 1); | |
2910 | printk(KERN_DEBUG | |
2911 | "Enabling pass through for channel\n"); | |
2912 | vpm_out(hc, ch, ((ch / 4) * 8) + | |
2913 | ((ch % 4) * 4) + 1, 0x01); | |
2914 | /* rx path */ | |
2915 | /* S/T -> PCM */ | |
2916 | HFC_outb(hc, R_FIFO, (ch << 1)); | |
2917 | HFC_wait(hc); | |
2918 | HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); | |
2919 | HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + | |
2920 | ((ch % 4) * 4) + 1) << 1); | |
2921 | HFC_outb(hc, A_SL_CFG, 0x80 | (ch << 1)); | |
2922 | ||
2923 | /* PCM -> FIFO */ | |
2924 | HFC_outb(hc, R_FIFO, 0x20 | (ch << 1) | 1); | |
2925 | HFC_wait(hc); | |
2926 | HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); | |
2927 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2928 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2929 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2930 | HFC_wait(hc); | |
2931 | HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + | |
2932 | ((ch % 4) * 4) + 1) << 1) | 1); | |
2933 | HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1) | 1); | |
2934 | ||
2935 | /* tx path */ | |
2936 | /* PCM -> S/T */ | |
2937 | HFC_outb(hc, R_FIFO, (ch << 1) | 1); | |
2938 | HFC_wait(hc); | |
2939 | HFC_outb(hc, A_CON_HDLC, 0xc0 | V_HDLC_TRP | V_IFF); | |
2940 | HFC_outb(hc, R_SLOT, ((((ch / 4) * 8) + | |
2941 | ((ch % 4) * 4)) << 1) | 1); | |
2942 | HFC_outb(hc, A_SL_CFG, 0x80 | 0x40 | (ch << 1) | 1); | |
2943 | ||
2944 | /* FIFO -> PCM */ | |
2945 | HFC_outb(hc, R_FIFO, 0x20 | (ch << 1)); | |
2946 | HFC_wait(hc); | |
2947 | HFC_outb(hc, A_CON_HDLC, 0x20 | V_HDLC_TRP | V_IFF); | |
2948 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2949 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2950 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2951 | HFC_wait(hc); | |
2952 | /* tx silence */ | |
2953 | HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence); | |
2954 | HFC_outb(hc, R_SLOT, (((ch / 4) * 8) + | |
2955 | ((ch % 4) * 4)) << 1); | |
2956 | HFC_outb(hc, A_SL_CFG, 0x80 | 0x20 | (ch << 1)); | |
2957 | } else { | |
2958 | /* enable TX fifo */ | |
2959 | HFC_outb(hc, R_FIFO, ch << 1); | |
2960 | HFC_wait(hc); | |
2961 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x00 | | |
2962 | V_HDLC_TRP | V_IFF); | |
2963 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2964 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2965 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2966 | HFC_wait(hc); | |
2967 | /* tx silence */ | |
2968 | HFC_outb_nodebug(hc, A_FIFO_DATA0_NOINC, silence); | |
2969 | /* enable RX fifo */ | |
2970 | HFC_outb(hc, R_FIFO, (ch<<1)|1); | |
2971 | HFC_wait(hc); | |
2972 | HFC_outb(hc, A_CON_HDLC, flow_rx | 0x00 | V_HDLC_TRP); | |
2973 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
2974 | HFC_outb(hc, A_IRQ_MSK, 0); | |
2975 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
2976 | HFC_wait(hc); | |
2977 | } | |
2978 | if (hc->type != 1) { | |
2979 | hc->hw.a_st_ctrl0[hc->chan[ch].port] |= | |
2980 | ((ch & 0x3) == 0) ? V_B1_EN : V_B2_EN; | |
2981 | HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); | |
2982 | /* undocumented: delay after R_ST_SEL */ | |
2983 | udelay(1); | |
2984 | HFC_outb(hc, A_ST_CTRL0, | |
2985 | hc->hw.a_st_ctrl0[hc->chan[ch].port]); | |
2986 | } | |
2987 | if (hc->chan[ch].bch) | |
2988 | test_and_set_bit(FLG_TRANSPARENT, | |
2989 | &hc->chan[ch].bch->Flags); | |
2990 | break; | |
2991 | case (ISDN_P_B_HDLC): /* B-channel */ | |
2992 | case (ISDN_P_TE_S0): /* D-channel */ | |
2993 | case (ISDN_P_NT_S0): | |
2994 | case (ISDN_P_TE_E1): | |
2995 | case (ISDN_P_NT_E1): | |
2996 | /* enable TX fifo */ | |
2997 | HFC_outb(hc, R_FIFO, ch<<1); | |
2998 | HFC_wait(hc); | |
2999 | if (hc->type == 1 || hc->chan[ch].bch) { | |
3000 | /* E1 or B-channel */ | |
3001 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04); | |
3002 | HFC_outb(hc, A_SUBCH_CFG, 0); | |
3003 | } else { | |
3004 | /* D-Channel without HDLC fill flags */ | |
3005 | HFC_outb(hc, A_CON_HDLC, flow_tx | 0x04 | V_IFF); | |
3006 | HFC_outb(hc, A_SUBCH_CFG, 2); | |
3007 | } | |
3008 | HFC_outb(hc, A_IRQ_MSK, V_IRQ); | |
3009 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
3010 | HFC_wait(hc); | |
3011 | /* enable RX fifo */ | |
3012 | HFC_outb(hc, R_FIFO, (ch<<1)|1); | |
3013 | HFC_wait(hc); | |
3014 | HFC_outb(hc, A_CON_HDLC, flow_rx | 0x04); | |
3015 | if (hc->type == 1 || hc->chan[ch].bch) | |
3016 | HFC_outb(hc, A_SUBCH_CFG, 0); /* full 8 bits */ | |
3017 | else | |
3018 | HFC_outb(hc, A_SUBCH_CFG, 2); /* 2 bits dchannel */ | |
3019 | HFC_outb(hc, A_IRQ_MSK, V_IRQ); | |
3020 | HFC_outb(hc, R_INC_RES_FIFO, V_RES_F); | |
3021 | HFC_wait(hc); | |
3022 | if (hc->chan[ch].bch) { | |
3023 | test_and_set_bit(FLG_HDLC, &hc->chan[ch].bch->Flags); | |
3024 | if (hc->type != 1) { | |
3025 | hc->hw.a_st_ctrl0[hc->chan[ch].port] |= | |
3026 | ((ch&0x3) == 0) ? V_B1_EN : V_B2_EN; | |
3027 | HFC_outb(hc, R_ST_SEL, hc->chan[ch].port); | |
3028 | /* undocumented: delay after R_ST_SEL */ | |
3029 | udelay(1); | |
3030 | HFC_outb(hc, A_ST_CTRL0, | |
3031 | hc->hw.a_st_ctrl0[hc->chan[ch].port]); | |
3032 | } | |
3033 | } | |
3034 | break; | |
3035 | default: | |
3036 | printk(KERN_DEBUG "%s: protocol not known %x\n", | |
3037 | __func__, protocol); | |
3038 | hc->chan[ch].protocol = ISDN_P_NONE; | |
3039 | return -ENOPROTOOPT; | |
3040 | } | |
3041 | hc->chan[ch].protocol = protocol; | |
3042 | return 0; | |
3043 | } | |
3044 | ||
3045 | ||
3046 | /* | |
3047 | * connect/disconnect PCM | |
3048 | */ | |
3049 | ||
3050 | static void | |
3051 | hfcmulti_pcm(struct hfc_multi *hc, int ch, int slot_tx, int bank_tx, | |
3052 | int slot_rx, int bank_rx) | |
3053 | { | |
3054 | if (slot_rx < 0 || slot_rx < 0 || bank_tx < 0 || bank_rx < 0) { | |
3055 | /* disable PCM */ | |
3056 | mode_hfcmulti(hc, ch, hc->chan[ch].protocol, -1, 0, -1, 0); | |
3057 | return; | |
3058 | } | |
3059 | ||
3060 | /* enable pcm */ | |
3061 | mode_hfcmulti(hc, ch, hc->chan[ch].protocol, slot_tx, bank_tx, | |
3062 | slot_rx, bank_rx); | |
3063 | } | |
3064 | ||
3065 | /* | |
3066 | * set/disable conference | |
3067 | */ | |
3068 | ||
3069 | static void | |
3070 | hfcmulti_conf(struct hfc_multi *hc, int ch, int num) | |
3071 | { | |
3072 | if (num >= 0 && num <= 7) | |
3073 | hc->chan[ch].conf = num; | |
3074 | else | |
3075 | hc->chan[ch].conf = -1; | |
3076 | mode_hfcmulti(hc, ch, hc->chan[ch].protocol, hc->chan[ch].slot_tx, | |
3077 | hc->chan[ch].bank_tx, hc->chan[ch].slot_rx, | |
3078 | hc->chan[ch].bank_rx); | |
3079 | } | |
3080 | ||
3081 | ||
3082 | /* | |
3083 | * set/disable sample loop | |
3084 | */ | |
3085 | ||
3086 | /* NOTE: this function is experimental and therefore disabled */ | |
3087 | ||
3088 | /* | |
3089 | * Layer 1 callback function | |
3090 | */ | |
3091 | static int | |
3092 | hfcm_l1callback(struct dchannel *dch, u_int cmd) | |
3093 | { | |
3094 | struct hfc_multi *hc = dch->hw; | |
3095 | u_long flags; | |
3096 | ||
3097 | switch (cmd) { | |
3098 | case INFO3_P8: | |
3099 | case INFO3_P10: | |
3100 | break; | |
3101 | case HW_RESET_REQ: | |
3102 | /* start activation */ | |
3103 | spin_lock_irqsave(&hc->lock, flags); | |
3104 | if (hc->type == 1) { | |
3105 | if (debug & DEBUG_HFCMULTI_MSG) | |
3106 | printk(KERN_DEBUG | |
3107 | "%s: HW_RESET_REQ no BRI\n", | |
3108 | __func__); | |
3109 | } else { | |
3110 | HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); | |
3111 | /* undocumented: delay after R_ST_SEL */ | |
3112 | udelay(1); | |
3113 | HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 3); /* F3 */ | |
3114 | udelay(6); /* wait at least 5,21us */ | |
3115 | HFC_outb(hc, A_ST_WR_STATE, 3); | |
3116 | HFC_outb(hc, A_ST_WR_STATE, 3 | (V_ST_ACT*3)); | |
3117 | /* activate */ | |
3118 | } | |
3119 | spin_unlock_irqrestore(&hc->lock, flags); | |
3120 | l1_event(dch->l1, HW_POWERUP_IND); | |
3121 | break; | |
3122 | case HW_DEACT_REQ: | |
3123 | /* start deactivation */ | |
3124 | spin_lock_irqsave(&hc->lock, flags); | |
3125 | if (hc->type == 1) { | |
3126 | if (debug & DEBUG_HFCMULTI_MSG) | |
3127 | printk(KERN_DEBUG | |
3128 | "%s: HW_DEACT_REQ no BRI\n", | |
3129 | __func__); | |
3130 | } else { | |
3131 | HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); | |
3132 | /* undocumented: delay after R_ST_SEL */ | |
3133 | udelay(1); | |
3134 | HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT*2); | |
3135 | /* deactivate */ | |
3136 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
3137 | hc->syncronized &= | |
3138 | ~(1 << hc->chan[dch->slot].port); | |
3139 | plxsd_checksync(hc, 0); | |
3140 | } | |
3141 | } | |
3142 | skb_queue_purge(&dch->squeue); | |
3143 | if (dch->tx_skb) { | |
3144 | dev_kfree_skb(dch->tx_skb); | |
3145 | dch->tx_skb = NULL; | |
3146 | } | |
3147 | dch->tx_idx = 0; | |
3148 | if (dch->rx_skb) { | |
3149 | dev_kfree_skb(dch->rx_skb); | |
3150 | dch->rx_skb = NULL; | |
3151 | } | |
3152 | test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); | |
3153 | if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) | |
3154 | del_timer(&dch->timer); | |
3155 | spin_unlock_irqrestore(&hc->lock, flags); | |
3156 | break; | |
3157 | case HW_POWERUP_REQ: | |
3158 | spin_lock_irqsave(&hc->lock, flags); | |
3159 | if (hc->type == 1) { | |
3160 | if (debug & DEBUG_HFCMULTI_MSG) | |
3161 | printk(KERN_DEBUG | |
3162 | "%s: HW_POWERUP_REQ no BRI\n", | |
3163 | __func__); | |
3164 | } else { | |
3165 | HFC_outb(hc, R_ST_SEL, hc->chan[dch->slot].port); | |
3166 | /* undocumented: delay after R_ST_SEL */ | |
3167 | udelay(1); | |
3168 | HFC_outb(hc, A_ST_WR_STATE, 3 | 0x10); /* activate */ | |
3169 | udelay(6); /* wait at least 5,21us */ | |
3170 | HFC_outb(hc, A_ST_WR_STATE, 3); /* activate */ | |
3171 | } | |
3172 | spin_unlock_irqrestore(&hc->lock, flags); | |
3173 | break; | |
3174 | case PH_ACTIVATE_IND: | |
3175 | test_and_set_bit(FLG_ACTIVE, &dch->Flags); | |
3176 | _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, | |
3177 | GFP_ATOMIC); | |
3178 | break; | |
3179 | case PH_DEACTIVATE_IND: | |
3180 | test_and_clear_bit(FLG_ACTIVE, &dch->Flags); | |
3181 | _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL, | |
3182 | GFP_ATOMIC); | |
3183 | break; | |
3184 | default: | |
3185 | if (dch->debug & DEBUG_HW) | |
3186 | printk(KERN_DEBUG "%s: unknown command %x\n", | |
3187 | __func__, cmd); | |
3188 | return -1; | |
3189 | } | |
3190 | return 0; | |
3191 | } | |
3192 | ||
3193 | /* | |
3194 | * Layer2 -> Layer 1 Transfer | |
3195 | */ | |
3196 | ||
3197 | static int | |
3198 | handle_dmsg(struct mISDNchannel *ch, struct sk_buff *skb) | |
3199 | { | |
3200 | struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); | |
3201 | struct dchannel *dch = container_of(dev, struct dchannel, dev); | |
3202 | struct hfc_multi *hc = dch->hw; | |
3203 | struct mISDNhead *hh = mISDN_HEAD_P(skb); | |
3204 | int ret = -EINVAL; | |
3205 | unsigned int id; | |
3206 | u_long flags; | |
3207 | ||
3208 | switch (hh->prim) { | |
3209 | case PH_DATA_REQ: | |
3210 | if (skb->len < 1) | |
3211 | break; | |
3212 | spin_lock_irqsave(&hc->lock, flags); | |
3213 | ret = dchannel_senddata(dch, skb); | |
3214 | if (ret > 0) { /* direct TX */ | |
3215 | id = hh->id; /* skb can be freed */ | |
3216 | hfcmulti_tx(hc, dch->slot); | |
3217 | ret = 0; | |
3218 | /* start fifo */ | |
3219 | HFC_outb(hc, R_FIFO, 0); | |
3220 | HFC_wait(hc); | |
3221 | spin_unlock_irqrestore(&hc->lock, flags); | |
3222 | queue_ch_frame(ch, PH_DATA_CNF, id, NULL); | |
3223 | } else | |
3224 | spin_unlock_irqrestore(&hc->lock, flags); | |
3225 | return ret; | |
3226 | case PH_ACTIVATE_REQ: | |
3227 | if (dch->dev.D.protocol != ISDN_P_TE_S0) { | |
3228 | spin_lock_irqsave(&hc->lock, flags); | |
3229 | ret = 0; | |
3230 | if (debug & DEBUG_HFCMULTI_MSG) | |
3231 | printk(KERN_DEBUG | |
3232 | "%s: PH_ACTIVATE port %d (0..%d)\n", | |
3233 | __func__, hc->chan[dch->slot].port, | |
3234 | hc->ports-1); | |
3235 | /* start activation */ | |
3236 | if (hc->type == 1) { | |
3237 | ph_state_change(dch); | |
3238 | if (debug & DEBUG_HFCMULTI_STATE) | |
3239 | printk(KERN_DEBUG | |
3240 | "%s: E1 report state %x \n", | |
3241 | __func__, dch->state); | |
3242 | } else { | |
3243 | HFC_outb(hc, R_ST_SEL, | |
3244 | hc->chan[dch->slot].port); | |
3245 | /* undocumented: delay after R_ST_SEL */ | |
3246 | udelay(1); | |
3247 | HFC_outb(hc, A_ST_WR_STATE, V_ST_LD_STA | 1); | |
3248 | /* G1 */ | |
3249 | udelay(6); /* wait at least 5,21us */ | |
3250 | HFC_outb(hc, A_ST_WR_STATE, 1); | |
3251 | HFC_outb(hc, A_ST_WR_STATE, 1 | | |
3252 | (V_ST_ACT*3)); /* activate */ | |
3253 | dch->state = 1; | |
3254 | } | |
3255 | spin_unlock_irqrestore(&hc->lock, flags); | |
3256 | } else | |
3257 | ret = l1_event(dch->l1, hh->prim); | |
3258 | break; | |
3259 | case PH_DEACTIVATE_REQ: | |
3260 | test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags); | |
3261 | if (dch->dev.D.protocol != ISDN_P_TE_S0) { | |
3262 | spin_lock_irqsave(&hc->lock, flags); | |
3263 | if (debug & DEBUG_HFCMULTI_MSG) | |
3264 | printk(KERN_DEBUG | |
3265 | "%s: PH_DEACTIVATE port %d (0..%d)\n", | |
3266 | __func__, hc->chan[dch->slot].port, | |
3267 | hc->ports-1); | |
3268 | /* start deactivation */ | |
3269 | if (hc->type == 1) { | |
3270 | if (debug & DEBUG_HFCMULTI_MSG) | |
3271 | printk(KERN_DEBUG | |
3272 | "%s: PH_DEACTIVATE no BRI\n", | |
3273 | __func__); | |
3274 | } else { | |
3275 | HFC_outb(hc, R_ST_SEL, | |
3276 | hc->chan[dch->slot].port); | |
3277 | /* undocumented: delay after R_ST_SEL */ | |
3278 | udelay(1); | |
3279 | HFC_outb(hc, A_ST_WR_STATE, V_ST_ACT * 2); | |
3280 | /* deactivate */ | |
3281 | dch->state = 1; | |
3282 | } | |
3283 | skb_queue_purge(&dch->squeue); | |
3284 | if (dch->tx_skb) { | |
3285 | dev_kfree_skb(dch->tx_skb); | |
3286 | dch->tx_skb = NULL; | |
3287 | } | |
3288 | dch->tx_idx = 0; | |
3289 | if (dch->rx_skb) { | |
3290 | dev_kfree_skb(dch->rx_skb); | |
3291 | dch->rx_skb = NULL; | |
3292 | } | |
3293 | test_and_clear_bit(FLG_TX_BUSY, &dch->Flags); | |
3294 | if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags)) | |
3295 | del_timer(&dch->timer); | |
3296 | #ifdef FIXME | |
3297 | if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags)) | |
3298 | dchannel_sched_event(&hc->dch, D_CLEARBUSY); | |
3299 | #endif | |
3300 | ret = 0; | |
3301 | spin_unlock_irqrestore(&hc->lock, flags); | |
3302 | } else | |
3303 | ret = l1_event(dch->l1, hh->prim); | |
3304 | break; | |
3305 | } | |
3306 | if (!ret) | |
3307 | dev_kfree_skb(skb); | |
3308 | return ret; | |
3309 | } | |
3310 | ||
3311 | static void | |
3312 | deactivate_bchannel(struct bchannel *bch) | |
3313 | { | |
3314 | struct hfc_multi *hc = bch->hw; | |
3315 | u_long flags; | |
3316 | ||
3317 | spin_lock_irqsave(&hc->lock, flags); | |
3318 | if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) { | |
3319 | dev_kfree_skb(bch->next_skb); | |
3320 | bch->next_skb = NULL; | |
3321 | } | |
3322 | if (bch->tx_skb) { | |
3323 | dev_kfree_skb(bch->tx_skb); | |
3324 | bch->tx_skb = NULL; | |
3325 | } | |
3326 | bch->tx_idx = 0; | |
3327 | if (bch->rx_skb) { | |
3328 | dev_kfree_skb(bch->rx_skb); | |
3329 | bch->rx_skb = NULL; | |
3330 | } | |
3331 | hc->chan[bch->slot].coeff_count = 0; | |
3332 | test_and_clear_bit(FLG_ACTIVE, &bch->Flags); | |
3333 | test_and_clear_bit(FLG_TX_BUSY, &bch->Flags); | |
3334 | hc->chan[bch->slot].rx_off = 0; | |
3335 | hc->chan[bch->slot].conf = -1; | |
3336 | mode_hfcmulti(hc, bch->slot, ISDN_P_NONE, -1, 0, -1, 0); | |
3337 | spin_unlock_irqrestore(&hc->lock, flags); | |
3338 | } | |
3339 | ||
3340 | static int | |
3341 | handle_bmsg(struct mISDNchannel *ch, struct sk_buff *skb) | |
3342 | { | |
3343 | struct bchannel *bch = container_of(ch, struct bchannel, ch); | |
3344 | struct hfc_multi *hc = bch->hw; | |
3345 | int ret = -EINVAL; | |
3346 | struct mISDNhead *hh = mISDN_HEAD_P(skb); | |
3347 | unsigned int id; | |
3348 | u_long flags; | |
3349 | ||
3350 | switch (hh->prim) { | |
3351 | case PH_DATA_REQ: | |
3352 | if (!skb->len) | |
3353 | break; | |
3354 | spin_lock_irqsave(&hc->lock, flags); | |
3355 | ret = bchannel_senddata(bch, skb); | |
3356 | if (ret > 0) { /* direct TX */ | |
3357 | id = hh->id; /* skb can be freed */ | |
3358 | hfcmulti_tx(hc, bch->slot); | |
3359 | ret = 0; | |
3360 | /* start fifo */ | |
3361 | HFC_outb_nodebug(hc, R_FIFO, 0); | |
3362 | HFC_wait_nodebug(hc); | |
3363 | if (!test_bit(FLG_TRANSPARENT, &bch->Flags)) { | |
3364 | spin_unlock_irqrestore(&hc->lock, flags); | |
3365 | queue_ch_frame(ch, PH_DATA_CNF, id, NULL); | |
3366 | } else | |
3367 | spin_unlock_irqrestore(&hc->lock, flags); | |
3368 | } else | |
3369 | spin_unlock_irqrestore(&hc->lock, flags); | |
3370 | return ret; | |
3371 | case PH_ACTIVATE_REQ: | |
3372 | if (debug & DEBUG_HFCMULTI_MSG) | |
3373 | printk(KERN_DEBUG "%s: PH_ACTIVATE ch %d (0..32)\n", | |
3374 | __func__, bch->slot); | |
3375 | spin_lock_irqsave(&hc->lock, flags); | |
3376 | /* activate B-channel if not already activated */ | |
3377 | if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags)) { | |
3378 | hc->chan[bch->slot].txpending = 0; | |
3379 | ret = mode_hfcmulti(hc, bch->slot, | |
3380 | ch->protocol, | |
3381 | hc->chan[bch->slot].slot_tx, | |
3382 | hc->chan[bch->slot].bank_tx, | |
3383 | hc->chan[bch->slot].slot_rx, | |
3384 | hc->chan[bch->slot].bank_rx); | |
3385 | if (!ret) { | |
3386 | if (ch->protocol == ISDN_P_B_RAW && !hc->dtmf | |
3387 | && test_bit(HFC_CHIP_DTMF, &hc->chip)) { | |
3388 | /* start decoder */ | |
3389 | hc->dtmf = 1; | |
3390 | if (debug & DEBUG_HFCMULTI_DTMF) | |
3391 | printk(KERN_DEBUG | |
3392 | "%s: start dtmf decoder\n", | |
3393 | __func__); | |
3394 | HFC_outb(hc, R_DTMF, hc->hw.r_dtmf | | |
3395 | V_RST_DTMF); | |
3396 | } | |
3397 | } | |
3398 | } else | |
3399 | ret = 0; | |
3400 | spin_unlock_irqrestore(&hc->lock, flags); | |
3401 | if (!ret) | |
3402 | _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0, NULL, | |
3403 | GFP_KERNEL); | |
3404 | break; | |
3405 | case PH_CONTROL_REQ: | |
3406 | spin_lock_irqsave(&hc->lock, flags); | |
3407 | switch (hh->id) { | |
3408 | case HFC_SPL_LOOP_ON: /* set sample loop */ | |
3409 | if (debug & DEBUG_HFCMULTI_MSG) | |
3410 | printk(KERN_DEBUG | |
3411 | "%s: HFC_SPL_LOOP_ON (len = %d)\n", | |
3412 | __func__, skb->len); | |
3413 | ret = 0; | |
3414 | break; | |
3415 | case HFC_SPL_LOOP_OFF: /* set silence */ | |
3416 | if (debug & DEBUG_HFCMULTI_MSG) | |
3417 | printk(KERN_DEBUG "%s: HFC_SPL_LOOP_OFF\n", | |
3418 | __func__); | |
3419 | ret = 0; | |
3420 | break; | |
3421 | default: | |
3422 | printk(KERN_ERR | |
3423 | "%s: unknown PH_CONTROL_REQ info %x\n", | |
3424 | __func__, hh->id); | |
3425 | ret = -EINVAL; | |
3426 | } | |
3427 | spin_unlock_irqrestore(&hc->lock, flags); | |
3428 | break; | |
3429 | case PH_DEACTIVATE_REQ: | |
3430 | deactivate_bchannel(bch); /* locked there */ | |
3431 | _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0, NULL, | |
3432 | GFP_KERNEL); | |
3433 | ret = 0; | |
3434 | break; | |
3435 | } | |
3436 | if (!ret) | |
3437 | dev_kfree_skb(skb); | |
3438 | return ret; | |
3439 | } | |
3440 | ||
3441 | /* | |
3442 | * bchannel control function | |
3443 | */ | |
3444 | static int | |
3445 | channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq) | |
3446 | { | |
3447 | int ret = 0; | |
3448 | struct dsp_features *features = | |
3449 | (struct dsp_features *)(*((u_long *)&cq->p1)); | |
3450 | struct hfc_multi *hc = bch->hw; | |
3451 | int slot_tx; | |
3452 | int bank_tx; | |
3453 | int slot_rx; | |
3454 | int bank_rx; | |
3455 | int num; | |
3456 | ||
3457 | switch (cq->op) { | |
3458 | case MISDN_CTRL_GETOP: | |
3459 | cq->op = MISDN_CTRL_HFC_OP | MISDN_CTRL_HW_FEATURES_OP | |
3460 | | MISDN_CTRL_RX_OFF; | |
3461 | break; | |
3462 | case MISDN_CTRL_RX_OFF: /* turn off / on rx stream */ | |
3463 | hc->chan[bch->slot].rx_off = !!cq->p1; | |
3464 | if (!hc->chan[bch->slot].rx_off) { | |
3465 | /* reset fifo on rx on */ | |
3466 | HFC_outb_nodebug(hc, R_FIFO, (bch->slot << 1) | 1); | |
3467 | HFC_wait_nodebug(hc); | |
3468 | HFC_outb_nodebug(hc, R_INC_RES_FIFO, V_RES_F); | |
3469 | HFC_wait_nodebug(hc); | |
3470 | } | |
3471 | if (debug & DEBUG_HFCMULTI_MSG) | |
3472 | printk(KERN_DEBUG "%s: RX_OFF request (nr=%d off=%d)\n", | |
3473 | __func__, bch->nr, hc->chan[bch->slot].rx_off); | |
3474 | break; | |
3475 | case MISDN_CTRL_HW_FEATURES: /* fill features structure */ | |
3476 | if (debug & DEBUG_HFCMULTI_MSG) | |
3477 | printk(KERN_DEBUG "%s: HW_FEATURE request\n", | |
3478 | __func__); | |
3479 | /* create confirm */ | |
3480 | features->hfc_id = hc->id; | |
3481 | if (test_bit(HFC_CHIP_DTMF, &hc->chip)) | |
3482 | features->hfc_dtmf = 1; | |
3483 | features->hfc_loops = 0; | |
3484 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) { | |
3485 | features->hfc_echocanhw = 1; | |
3486 | } else { | |
3487 | features->pcm_id = hc->pcm; | |
3488 | features->pcm_slots = hc->slots; | |
3489 | features->pcm_banks = 2; | |
3490 | } | |
3491 | break; | |
3492 | case MISDN_CTRL_HFC_PCM_CONN: /* connect to pcm timeslot (0..N) */ | |
3493 | slot_tx = cq->p1 & 0xff; | |
3494 | bank_tx = cq->p1 >> 8; | |
3495 | slot_rx = cq->p2 & 0xff; | |
3496 | bank_rx = cq->p2 >> 8; | |
3497 | if (debug & DEBUG_HFCMULTI_MSG) | |
3498 | printk(KERN_DEBUG | |
3499 | "%s: HFC_PCM_CONN slot %d bank %d (TX) " | |
3500 | "slot %d bank %d (RX)\n", | |
3501 | __func__, slot_tx, bank_tx, | |
3502 | slot_rx, bank_rx); | |
3503 | if (slot_tx < hc->slots && bank_tx <= 2 && | |
3504 | slot_rx < hc->slots && bank_rx <= 2) | |
3505 | hfcmulti_pcm(hc, bch->slot, | |
3506 | slot_tx, bank_tx, slot_rx, bank_rx); | |
3507 | else { | |
3508 | printk(KERN_WARNING | |
3509 | "%s: HFC_PCM_CONN slot %d bank %d (TX) " | |
3510 | "slot %d bank %d (RX) out of range\n", | |
3511 | __func__, slot_tx, bank_tx, | |
3512 | slot_rx, bank_rx); | |
3513 | ret = -EINVAL; | |
3514 | } | |
3515 | break; | |
3516 | case MISDN_CTRL_HFC_PCM_DISC: /* release interface from pcm timeslot */ | |
3517 | if (debug & DEBUG_HFCMULTI_MSG) | |
3518 | printk(KERN_DEBUG "%s: HFC_PCM_DISC\n", | |
3519 | __func__); | |
3520 | hfcmulti_pcm(hc, bch->slot, -1, 0, -1, 0); | |
3521 | break; | |
3522 | case MISDN_CTRL_HFC_CONF_JOIN: /* join conference (0..7) */ | |
3523 | num = cq->p1 & 0xff; | |
3524 | if (debug & DEBUG_HFCMULTI_MSG) | |
3525 | printk(KERN_DEBUG "%s: HFC_CONF_JOIN conf %d\n", | |
3526 | __func__, num); | |
3527 | if (num <= 7) | |
3528 | hfcmulti_conf(hc, bch->slot, num); | |
3529 | else { | |
3530 | printk(KERN_WARNING | |
3531 | "%s: HW_CONF_JOIN conf %d out of range\n", | |
3532 | __func__, num); | |
3533 | ret = -EINVAL; | |
3534 | } | |
3535 | break; | |
3536 | case MISDN_CTRL_HFC_CONF_SPLIT: /* split conference */ | |
3537 | if (debug & DEBUG_HFCMULTI_MSG) | |
3538 | printk(KERN_DEBUG "%s: HFC_CONF_SPLIT\n", __func__); | |
3539 | hfcmulti_conf(hc, bch->slot, -1); | |
3540 | break; | |
3541 | case MISDN_CTRL_HFC_ECHOCAN_ON: | |
3542 | if (debug & DEBUG_HFCMULTI_MSG) | |
3543 | printk(KERN_DEBUG "%s: HFC_ECHOCAN_ON\n", __func__); | |
3544 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) | |
3545 | vpm_echocan_on(hc, bch->slot, cq->p1); | |
3546 | else | |
3547 | ret = -EINVAL; | |
3548 | break; | |
3549 | ||
3550 | case MISDN_CTRL_HFC_ECHOCAN_OFF: | |
3551 | if (debug & DEBUG_HFCMULTI_MSG) | |
3552 | printk(KERN_DEBUG "%s: HFC_ECHOCAN_OFF\n", | |
3553 | __func__); | |
3554 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) | |
3555 | vpm_echocan_off(hc, bch->slot); | |
3556 | else | |
3557 | ret = -EINVAL; | |
3558 | break; | |
3559 | default: | |
3560 | printk(KERN_WARNING "%s: unknown Op %x\n", | |
3561 | __func__, cq->op); | |
3562 | ret = -EINVAL; | |
3563 | break; | |
3564 | } | |
3565 | return ret; | |
3566 | } | |
3567 | ||
3568 | static int | |
3569 | hfcm_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg) | |
3570 | { | |
3571 | struct bchannel *bch = container_of(ch, struct bchannel, ch); | |
3572 | struct hfc_multi *hc = bch->hw; | |
3573 | int err = -EINVAL; | |
3574 | u_long flags; | |
3575 | ||
3576 | if (bch->debug & DEBUG_HW) | |
3577 | printk(KERN_DEBUG "%s: cmd:%x %p\n", | |
3578 | __func__, cmd, arg); | |
3579 | switch (cmd) { | |
3580 | case CLOSE_CHANNEL: | |
3581 | test_and_clear_bit(FLG_OPEN, &bch->Flags); | |
3582 | if (test_bit(FLG_ACTIVE, &bch->Flags)) | |
3583 | deactivate_bchannel(bch); /* locked there */ | |
3584 | ch->protocol = ISDN_P_NONE; | |
3585 | ch->peer = NULL; | |
3586 | module_put(THIS_MODULE); | |
3587 | err = 0; | |
3588 | break; | |
3589 | case CONTROL_CHANNEL: | |
3590 | spin_lock_irqsave(&hc->lock, flags); | |
3591 | err = channel_bctrl(bch, arg); | |
3592 | spin_unlock_irqrestore(&hc->lock, flags); | |
3593 | break; | |
3594 | default: | |
3595 | printk(KERN_WARNING "%s: unknown prim(%x)\n", | |
3596 | __func__, cmd); | |
3597 | } | |
3598 | return err; | |
3599 | } | |
3600 | ||
3601 | /* | |
3602 | * handle D-channel events | |
3603 | * | |
3604 | * handle state change event | |
3605 | */ | |
3606 | static void | |
3607 | ph_state_change(struct dchannel *dch) | |
3608 | { | |
3609 | struct hfc_multi *hc = dch->hw; | |
3610 | int ch, i; | |
3611 | ||
3612 | if (!dch) { | |
3613 | printk(KERN_WARNING "%s: ERROR given dch is NULL\n", | |
3614 | __func__); | |
3615 | return; | |
3616 | } | |
3617 | ch = dch->slot; | |
3618 | ||
3619 | if (hc->type == 1) { | |
3620 | if (dch->dev.D.protocol == ISDN_P_TE_E1) { | |
3621 | if (debug & DEBUG_HFCMULTI_STATE) | |
3622 | printk(KERN_DEBUG | |
3623 | "%s: E1 TE (id=%d) newstate %x\n", | |
3624 | __func__, hc->id, dch->state); | |
3625 | } else { | |
3626 | if (debug & DEBUG_HFCMULTI_STATE) | |
3627 | printk(KERN_DEBUG | |
3628 | "%s: E1 NT (id=%d) newstate %x\n", | |
3629 | __func__, hc->id, dch->state); | |
3630 | } | |
3631 | switch (dch->state) { | |
3632 | case (1): | |
3633 | if (hc->e1_state != 1) { | |
3634 | for (i = 1; i <= 31; i++) { | |
3635 | /* reset fifos on e1 activation */ | |
3636 | HFC_outb_nodebug(hc, R_FIFO, (i << 1) | 1); | |
3637 | HFC_wait_nodebug(hc); | |
3638 | HFC_outb_nodebug(hc, | |
3639 | R_INC_RES_FIFO, V_RES_F); | |
3640 | HFC_wait_nodebug(hc); | |
3641 | } | |
3642 | } | |
3643 | test_and_set_bit(FLG_ACTIVE, &dch->Flags); | |
3644 | _queue_data(&dch->dev.D, PH_ACTIVATE_IND, | |
3645 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3646 | break; | |
3647 | ||
3648 | default: | |
3649 | if (hc->e1_state != 1) | |
3650 | return; | |
3651 | test_and_clear_bit(FLG_ACTIVE, &dch->Flags); | |
3652 | _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, | |
3653 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3654 | } | |
3655 | hc->e1_state = dch->state; | |
3656 | } else { | |
3657 | if (dch->dev.D.protocol == ISDN_P_TE_S0) { | |
3658 | if (debug & DEBUG_HFCMULTI_STATE) | |
3659 | printk(KERN_DEBUG | |
3660 | "%s: S/T TE newstate %x\n", | |
3661 | __func__, dch->state); | |
3662 | switch (dch->state) { | |
3663 | case (0): | |
3664 | l1_event(dch->l1, HW_RESET_IND); | |
3665 | break; | |
3666 | case (3): | |
3667 | l1_event(dch->l1, HW_DEACT_IND); | |
3668 | break; | |
3669 | case (5): | |
3670 | case (8): | |
3671 | l1_event(dch->l1, ANYSIGNAL); | |
3672 | break; | |
3673 | case (6): | |
3674 | l1_event(dch->l1, INFO2); | |
3675 | break; | |
3676 | case (7): | |
3677 | l1_event(dch->l1, INFO4_P8); | |
3678 | break; | |
3679 | } | |
3680 | } else { | |
3681 | if (debug & DEBUG_HFCMULTI_STATE) | |
3682 | printk(KERN_DEBUG "%s: S/T NT newstate %x\n", | |
3683 | __func__, dch->state); | |
3684 | switch (dch->state) { | |
3685 | case (2): | |
3686 | if (hc->chan[ch].nt_timer == 0) { | |
3687 | hc->chan[ch].nt_timer = -1; | |
3688 | HFC_outb(hc, R_ST_SEL, | |
3689 | hc->chan[ch].port); | |
3690 | /* undocumented: delay after R_ST_SEL */ | |
3691 | udelay(1); | |
3692 | HFC_outb(hc, A_ST_WR_STATE, 4 | | |
3693 | V_ST_LD_STA); /* G4 */ | |
3694 | udelay(6); /* wait at least 5,21us */ | |
3695 | HFC_outb(hc, A_ST_WR_STATE, 4); | |
3696 | dch->state = 4; | |
3697 | } else { | |
3698 | /* one extra count for the next event */ | |
3699 | hc->chan[ch].nt_timer = | |
3700 | nt_t1_count[poll_timer] + 1; | |
3701 | HFC_outb(hc, R_ST_SEL, | |
3702 | hc->chan[ch].port); | |
3703 | /* undocumented: delay after R_ST_SEL */ | |
3704 | udelay(1); | |
3705 | /* allow G2 -> G3 transition */ | |
3706 | HFC_outb(hc, A_ST_WR_STATE, 2 | | |
3707 | V_SET_G2_G3); | |
3708 | } | |
3709 | break; | |
3710 | case (1): | |
3711 | hc->chan[ch].nt_timer = -1; | |
3712 | test_and_clear_bit(FLG_ACTIVE, &dch->Flags); | |
3713 | _queue_data(&dch->dev.D, PH_DEACTIVATE_IND, | |
3714 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3715 | break; | |
3716 | case (4): | |
3717 | hc->chan[ch].nt_timer = -1; | |
3718 | break; | |
3719 | case (3): | |
3720 | hc->chan[ch].nt_timer = -1; | |
3721 | test_and_set_bit(FLG_ACTIVE, &dch->Flags); | |
3722 | _queue_data(&dch->dev.D, PH_ACTIVATE_IND, | |
3723 | MISDN_ID_ANY, 0, NULL, GFP_ATOMIC); | |
3724 | break; | |
3725 | } | |
3726 | } | |
3727 | } | |
3728 | } | |
3729 | ||
3730 | /* | |
3731 | * called for card mode init message | |
3732 | */ | |
3733 | ||
3734 | static void | |
3735 | hfcmulti_initmode(struct dchannel *dch) | |
3736 | { | |
3737 | struct hfc_multi *hc = dch->hw; | |
3738 | u_char a_st_wr_state, r_e1_wr_sta; | |
3739 | int i, pt; | |
3740 | ||
3741 | if (debug & DEBUG_HFCMULTI_INIT) | |
3742 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
3743 | ||
3744 | if (hc->type == 1) { | |
3745 | hc->chan[hc->dslot].slot_tx = -1; | |
3746 | hc->chan[hc->dslot].slot_rx = -1; | |
3747 | hc->chan[hc->dslot].conf = -1; | |
3748 | if (hc->dslot) { | |
3749 | mode_hfcmulti(hc, hc->dslot, dch->dev.D.protocol, | |
3750 | -1, 0, -1, 0); | |
3751 | dch->timer.function = (void *) hfcmulti_dbusy_timer; | |
3752 | dch->timer.data = (long) dch; | |
3753 | init_timer(&dch->timer); | |
3754 | } | |
3755 | for (i = 1; i <= 31; i++) { | |
3756 | if (i == hc->dslot) | |
3757 | continue; | |
3758 | hc->chan[i].slot_tx = -1; | |
3759 | hc->chan[i].slot_rx = -1; | |
3760 | hc->chan[i].conf = -1; | |
3761 | mode_hfcmulti(hc, i, ISDN_P_NONE, -1, 0, -1, 0); | |
3762 | } | |
3763 | /* E1 */ | |
3764 | if (test_bit(HFC_CFG_REPORT_LOS, &hc->chan[hc->dslot].cfg)) { | |
3765 | HFC_outb(hc, R_LOS0, 255); /* 2 ms */ | |
3766 | HFC_outb(hc, R_LOS1, 255); /* 512 ms */ | |
3767 | } | |
3768 | if (test_bit(HFC_CFG_OPTICAL, &hc->chan[hc->dslot].cfg)) { | |
3769 | HFC_outb(hc, R_RX0, 0); | |
3770 | hc->hw.r_tx0 = 0 | V_OUT_EN; | |
3771 | } else { | |
3772 | HFC_outb(hc, R_RX0, 1); | |
3773 | hc->hw.r_tx0 = 1 | V_OUT_EN; | |
3774 | } | |
3775 | hc->hw.r_tx1 = V_ATX | V_NTRI; | |
3776 | HFC_outb(hc, R_TX0, hc->hw.r_tx0); | |
3777 | HFC_outb(hc, R_TX1, hc->hw.r_tx1); | |
3778 | HFC_outb(hc, R_TX_FR0, 0x00); | |
3779 | HFC_outb(hc, R_TX_FR1, 0xf8); | |
3780 | ||
3781 | if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) | |
3782 | HFC_outb(hc, R_TX_FR2, V_TX_MF | V_TX_E | V_NEG_E); | |
3783 | ||
3784 | HFC_outb(hc, R_RX_FR0, V_AUTO_RESYNC | V_AUTO_RECO | 0); | |
3785 | ||
3786 | if (test_bit(HFC_CFG_CRC4, &hc->chan[hc->dslot].cfg)) | |
3787 | HFC_outb(hc, R_RX_FR1, V_RX_MF | V_RX_MF_SYNC); | |
3788 | ||
3789 | if (dch->dev.D.protocol == ISDN_P_NT_E1) { | |
3790 | if (debug & DEBUG_HFCMULTI_INIT) | |
3791 | printk(KERN_DEBUG "%s: E1 port is NT-mode\n", | |
3792 | __func__); | |
3793 | r_e1_wr_sta = 0; /* G0 */ | |
3794 | hc->e1_getclock = 0; | |
3795 | } else { | |
3796 | if (debug & DEBUG_HFCMULTI_INIT) | |
3797 | printk(KERN_DEBUG "%s: E1 port is TE-mode\n", | |
3798 | __func__); | |
3799 | r_e1_wr_sta = 0; /* F0 */ | |
3800 | hc->e1_getclock = 1; | |
3801 | } | |
3802 | if (test_bit(HFC_CHIP_RX_SYNC, &hc->chip)) | |
3803 | HFC_outb(hc, R_SYNC_OUT, V_SYNC_E1_RX); | |
3804 | else | |
3805 | HFC_outb(hc, R_SYNC_OUT, 0); | |
3806 | if (test_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip)) | |
3807 | hc->e1_getclock = 1; | |
3808 | if (test_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip)) | |
3809 | hc->e1_getclock = 0; | |
3810 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
3811 | /* SLAVE (clock master) */ | |
3812 | if (debug & DEBUG_HFCMULTI_INIT) | |
3813 | printk(KERN_DEBUG | |
3814 | "%s: E1 port is clock master " | |
3815 | "(clock from PCM)\n", __func__); | |
3816 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | V_PCM_SYNC); | |
3817 | } else { | |
3818 | if (hc->e1_getclock) { | |
3819 | /* MASTER (clock slave) */ | |
3820 | if (debug & DEBUG_HFCMULTI_INIT) | |
3821 | printk(KERN_DEBUG | |
3822 | "%s: E1 port is clock slave " | |
3823 | "(clock to PCM)\n", __func__); | |
3824 | HFC_outb(hc, R_SYNC_CTRL, V_SYNC_OFFS); | |
3825 | } else { | |
3826 | /* MASTER (clock master) */ | |
3827 | if (debug & DEBUG_HFCMULTI_INIT) | |
3828 | printk(KERN_DEBUG "%s: E1 port is " | |
3829 | "clock master " | |
3830 | "(clock from QUARTZ)\n", | |
3831 | __func__); | |
3832 | HFC_outb(hc, R_SYNC_CTRL, V_EXT_CLK_SYNC | | |
3833 | V_PCM_SYNC | V_JATT_OFF); | |
3834 | HFC_outb(hc, R_SYNC_OUT, 0); | |
3835 | } | |
3836 | } | |
3837 | HFC_outb(hc, R_JATT_ATT, 0x9c); /* undoc register */ | |
3838 | HFC_outb(hc, R_PWM_MD, V_PWM0_MD); | |
3839 | HFC_outb(hc, R_PWM0, 0x50); | |
3840 | HFC_outb(hc, R_PWM1, 0xff); | |
3841 | /* state machine setup */ | |
3842 | HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta | V_E1_LD_STA); | |
3843 | udelay(6); /* wait at least 5,21us */ | |
3844 | HFC_outb(hc, R_E1_WR_STA, r_e1_wr_sta); | |
3845 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
3846 | hc->syncronized = 0; | |
3847 | plxsd_checksync(hc, 0); | |
3848 | } | |
3849 | } else { | |
3850 | i = dch->slot; | |
3851 | hc->chan[i].slot_tx = -1; | |
3852 | hc->chan[i].slot_rx = -1; | |
3853 | hc->chan[i].conf = -1; | |
3854 | mode_hfcmulti(hc, i, dch->dev.D.protocol, -1, 0, -1, 0); | |
3855 | dch->timer.function = (void *)hfcmulti_dbusy_timer; | |
3856 | dch->timer.data = (long) dch; | |
3857 | init_timer(&dch->timer); | |
3858 | hc->chan[i - 2].slot_tx = -1; | |
3859 | hc->chan[i - 2].slot_rx = -1; | |
3860 | hc->chan[i - 2].conf = -1; | |
3861 | mode_hfcmulti(hc, i - 2, ISDN_P_NONE, -1, 0, -1, 0); | |
3862 | hc->chan[i - 1].slot_tx = -1; | |
3863 | hc->chan[i - 1].slot_rx = -1; | |
3864 | hc->chan[i - 1].conf = -1; | |
3865 | mode_hfcmulti(hc, i - 1, ISDN_P_NONE, -1, 0, -1, 0); | |
3866 | /* ST */ | |
3867 | pt = hc->chan[i].port; | |
3868 | /* select interface */ | |
3869 | HFC_outb(hc, R_ST_SEL, pt); | |
3870 | /* undocumented: delay after R_ST_SEL */ | |
3871 | udelay(1); | |
3872 | if (dch->dev.D.protocol == ISDN_P_NT_S0) { | |
3873 | if (debug & DEBUG_HFCMULTI_INIT) | |
3874 | printk(KERN_DEBUG | |
3875 | "%s: ST port %d is NT-mode\n", | |
3876 | __func__, pt); | |
3877 | /* clock delay */ | |
3878 | HFC_outb(hc, A_ST_CLK_DLY, clockdelay_nt); | |
3879 | a_st_wr_state = 1; /* G1 */ | |
3880 | hc->hw.a_st_ctrl0[pt] = V_ST_MD; | |
3881 | } else { | |
3882 | if (debug & DEBUG_HFCMULTI_INIT) | |
3883 | printk(KERN_DEBUG | |
3884 | "%s: ST port %d is TE-mode\n", | |
3885 | __func__, pt); | |
3886 | /* clock delay */ | |
3887 | HFC_outb(hc, A_ST_CLK_DLY, clockdelay_te); | |
3888 | a_st_wr_state = 2; /* F2 */ | |
3889 | hc->hw.a_st_ctrl0[pt] = 0; | |
3890 | } | |
3891 | if (!test_bit(HFC_CFG_NONCAP_TX, &hc->chan[i].cfg)) | |
3892 | hc->hw.a_st_ctrl0[pt] |= V_TX_LI; | |
3893 | /* line setup */ | |
3894 | HFC_outb(hc, A_ST_CTRL0, hc->hw.a_st_ctrl0[pt]); | |
3895 | /* disable E-channel */ | |
3896 | if ((dch->dev.D.protocol == ISDN_P_NT_S0) || | |
3897 | test_bit(HFC_CFG_DIS_ECHANNEL, &hc->chan[i].cfg)) | |
3898 | HFC_outb(hc, A_ST_CTRL1, V_E_IGNO); | |
3899 | else | |
3900 | HFC_outb(hc, A_ST_CTRL1, 0); | |
3901 | /* enable B-channel receive */ | |
3902 | HFC_outb(hc, A_ST_CTRL2, V_B1_RX_EN | V_B2_RX_EN); | |
3903 | /* state machine setup */ | |
3904 | HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state | V_ST_LD_STA); | |
3905 | udelay(6); /* wait at least 5,21us */ | |
3906 | HFC_outb(hc, A_ST_WR_STATE, a_st_wr_state); | |
3907 | hc->hw.r_sci_msk |= 1 << pt; | |
3908 | /* state machine interrupts */ | |
3909 | HFC_outb(hc, R_SCI_MSK, hc->hw.r_sci_msk); | |
3910 | /* unset sync on port */ | |
3911 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
3912 | hc->syncronized &= | |
3913 | ~(1 << hc->chan[dch->slot].port); | |
3914 | plxsd_checksync(hc, 0); | |
3915 | } | |
3916 | } | |
3917 | if (debug & DEBUG_HFCMULTI_INIT) | |
3918 | printk("%s: done\n", __func__); | |
3919 | } | |
3920 | ||
3921 | ||
3922 | static int | |
3923 | open_dchannel(struct hfc_multi *hc, struct dchannel *dch, | |
3924 | struct channel_req *rq) | |
3925 | { | |
3926 | int err = 0; | |
3927 | u_long flags; | |
3928 | ||
3929 | if (debug & DEBUG_HW_OPEN) | |
3930 | printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__, | |
3931 | dch->dev.id, __builtin_return_address(0)); | |
3932 | if (rq->protocol == ISDN_P_NONE) | |
3933 | return -EINVAL; | |
3934 | if ((dch->dev.D.protocol != ISDN_P_NONE) && | |
3935 | (dch->dev.D.protocol != rq->protocol)) { | |
3936 | if (debug & DEBUG_HFCMULTI_MODE) | |
3937 | printk(KERN_WARNING "%s: change protocol %x to %x\n", | |
3938 | __func__, dch->dev.D.protocol, rq->protocol); | |
3939 | } | |
3940 | if ((dch->dev.D.protocol == ISDN_P_TE_S0) | |
3941 | && (rq->protocol != ISDN_P_TE_S0)) | |
3942 | l1_event(dch->l1, CLOSE_CHANNEL); | |
3943 | if (dch->dev.D.protocol != rq->protocol) { | |
3944 | if (rq->protocol == ISDN_P_TE_S0) { | |
3945 | err = create_l1(dch, hfcm_l1callback); | |
3946 | if (err) | |
3947 | return err; | |
3948 | } | |
3949 | dch->dev.D.protocol = rq->protocol; | |
3950 | spin_lock_irqsave(&hc->lock, flags); | |
3951 | hfcmulti_initmode(dch); | |
3952 | spin_unlock_irqrestore(&hc->lock, flags); | |
3953 | } | |
3954 | ||
3955 | if (((rq->protocol == ISDN_P_NT_S0) && (dch->state == 3)) || | |
3956 | ((rq->protocol == ISDN_P_TE_S0) && (dch->state == 7)) || | |
3957 | ((rq->protocol == ISDN_P_NT_E1) && (dch->state == 1)) || | |
3958 | ((rq->protocol == ISDN_P_TE_E1) && (dch->state == 1))) { | |
3959 | _queue_data(&dch->dev.D, PH_ACTIVATE_IND, MISDN_ID_ANY, | |
3960 | 0, NULL, GFP_KERNEL); | |
3961 | } | |
3962 | rq->ch = &dch->dev.D; | |
3963 | if (!try_module_get(THIS_MODULE)) | |
3964 | printk(KERN_WARNING "%s:cannot get module\n", __func__); | |
3965 | return 0; | |
3966 | } | |
3967 | ||
3968 | static int | |
3969 | open_bchannel(struct hfc_multi *hc, struct dchannel *dch, | |
3970 | struct channel_req *rq) | |
3971 | { | |
3972 | struct bchannel *bch; | |
3973 | int ch; | |
3974 | ||
ff4cc1de | 3975 | if (!test_channelmap(rq->adr.channel, dch->dev.channelmap)) |
af69fb3a KK |
3976 | return -EINVAL; |
3977 | if (rq->protocol == ISDN_P_NONE) | |
3978 | return -EINVAL; | |
3979 | if (hc->type == 1) | |
3980 | ch = rq->adr.channel; | |
3981 | else | |
3982 | ch = (rq->adr.channel - 1) + (dch->slot - 2); | |
3983 | bch = hc->chan[ch].bch; | |
3984 | if (!bch) { | |
3985 | printk(KERN_ERR "%s:internal error ch %d has no bch\n", | |
3986 | __func__, ch); | |
3987 | return -EINVAL; | |
3988 | } | |
3989 | if (test_and_set_bit(FLG_OPEN, &bch->Flags)) | |
3990 | return -EBUSY; /* b-channel can be only open once */ | |
3991 | bch->ch.protocol = rq->protocol; | |
3992 | hc->chan[ch].rx_off = 0; | |
3993 | rq->ch = &bch->ch; | |
3994 | if (!try_module_get(THIS_MODULE)) | |
3995 | printk(KERN_WARNING "%s:cannot get module\n", __func__); | |
3996 | return 0; | |
3997 | } | |
3998 | ||
3999 | /* | |
4000 | * device control function | |
4001 | */ | |
4002 | static int | |
4003 | channel_dctrl(struct dchannel *dch, struct mISDN_ctrl_req *cq) | |
4004 | { | |
4005 | int ret = 0; | |
4006 | ||
4007 | switch (cq->op) { | |
4008 | case MISDN_CTRL_GETOP: | |
4009 | cq->op = 0; | |
4010 | break; | |
4011 | default: | |
4012 | printk(KERN_WARNING "%s: unknown Op %x\n", | |
4013 | __func__, cq->op); | |
4014 | ret = -EINVAL; | |
4015 | break; | |
4016 | } | |
4017 | return ret; | |
4018 | } | |
4019 | ||
4020 | static int | |
4021 | hfcm_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg) | |
4022 | { | |
4023 | struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D); | |
4024 | struct dchannel *dch = container_of(dev, struct dchannel, dev); | |
4025 | struct hfc_multi *hc = dch->hw; | |
4026 | struct channel_req *rq; | |
4027 | int err = 0; | |
4028 | u_long flags; | |
4029 | ||
4030 | if (dch->debug & DEBUG_HW) | |
4031 | printk(KERN_DEBUG "%s: cmd:%x %p\n", | |
4032 | __func__, cmd, arg); | |
4033 | switch (cmd) { | |
4034 | case OPEN_CHANNEL: | |
4035 | rq = arg; | |
4036 | switch (rq->protocol) { | |
4037 | case ISDN_P_TE_S0: | |
4038 | case ISDN_P_NT_S0: | |
4039 | if (hc->type == 1) { | |
4040 | err = -EINVAL; | |
4041 | break; | |
4042 | } | |
4043 | err = open_dchannel(hc, dch, rq); /* locked there */ | |
4044 | break; | |
4045 | case ISDN_P_TE_E1: | |
4046 | case ISDN_P_NT_E1: | |
4047 | if (hc->type != 1) { | |
4048 | err = -EINVAL; | |
4049 | break; | |
4050 | } | |
4051 | err = open_dchannel(hc, dch, rq); /* locked there */ | |
4052 | break; | |
4053 | default: | |
4054 | spin_lock_irqsave(&hc->lock, flags); | |
4055 | err = open_bchannel(hc, dch, rq); | |
4056 | spin_unlock_irqrestore(&hc->lock, flags); | |
4057 | } | |
4058 | break; | |
4059 | case CLOSE_CHANNEL: | |
4060 | if (debug & DEBUG_HW_OPEN) | |
4061 | printk(KERN_DEBUG "%s: dev(%d) close from %p\n", | |
4062 | __func__, dch->dev.id, | |
4063 | __builtin_return_address(0)); | |
4064 | module_put(THIS_MODULE); | |
4065 | break; | |
4066 | case CONTROL_CHANNEL: | |
4067 | spin_lock_irqsave(&hc->lock, flags); | |
4068 | err = channel_dctrl(dch, arg); | |
4069 | spin_unlock_irqrestore(&hc->lock, flags); | |
4070 | break; | |
4071 | default: | |
4072 | if (dch->debug & DEBUG_HW) | |
4073 | printk(KERN_DEBUG "%s: unknown command %x\n", | |
4074 | __func__, cmd); | |
4075 | err = -EINVAL; | |
4076 | } | |
4077 | return err; | |
4078 | } | |
4079 | ||
4080 | /* | |
4081 | * initialize the card | |
4082 | */ | |
4083 | ||
4084 | /* | |
4085 | * start timer irq, wait some time and check if we have interrupts. | |
4086 | * if not, reset chip and try again. | |
4087 | */ | |
4088 | static int | |
4089 | init_card(struct hfc_multi *hc) | |
4090 | { | |
4091 | int err = -EIO; | |
4092 | u_long flags; | |
4093 | u_short *plx_acc; | |
4094 | u_long plx_flags; | |
4095 | ||
4096 | if (debug & DEBUG_HFCMULTI_INIT) | |
4097 | printk(KERN_DEBUG "%s: entered\n", __func__); | |
4098 | ||
4099 | spin_lock_irqsave(&hc->lock, flags); | |
4100 | /* set interrupts but leave global interrupt disabled */ | |
4101 | hc->hw.r_irq_ctrl = V_FIFO_IRQ; | |
4102 | disable_hwirq(hc); | |
4103 | spin_unlock_irqrestore(&hc->lock, flags); | |
4104 | ||
4105 | if (request_irq(hc->pci_dev->irq, hfcmulti_interrupt, IRQF_SHARED, | |
4106 | "HFC-multi", hc)) { | |
4107 | printk(KERN_WARNING "mISDN: Could not get interrupt %d.\n", | |
4108 | hc->pci_dev->irq); | |
4109 | return -EIO; | |
4110 | } | |
4111 | hc->irq = hc->pci_dev->irq; | |
4112 | ||
4113 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4114 | spin_lock_irqsave(&plx_lock, plx_flags); | |
4115 | plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR); | |
4116 | writew((PLX_INTCSR_PCIINT_ENABLE | PLX_INTCSR_LINTI1_ENABLE), | |
4117 | plx_acc); /* enable PCI & LINT1 irq */ | |
4118 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
4119 | } | |
4120 | ||
4121 | if (debug & DEBUG_HFCMULTI_INIT) | |
4122 | printk(KERN_DEBUG "%s: IRQ %d count %d\n", | |
4123 | __func__, hc->irq, hc->irqcnt); | |
4124 | err = init_chip(hc); | |
4125 | if (err) | |
4126 | goto error; | |
4127 | /* | |
4128 | * Finally enable IRQ output | |
4129 | * this is only allowed, if an IRQ routine is allready | |
4130 | * established for this HFC, so don't do that earlier | |
4131 | */ | |
4132 | spin_lock_irqsave(&hc->lock, flags); | |
4133 | enable_hwirq(hc); | |
4134 | spin_unlock_irqrestore(&hc->lock, flags); | |
4135 | /* printk(KERN_DEBUG "no master irq set!!!\n"); */ | |
4136 | set_current_state(TASK_UNINTERRUPTIBLE); | |
4137 | schedule_timeout((100*HZ)/1000); /* Timeout 100ms */ | |
4138 | /* turn IRQ off until chip is completely initialized */ | |
4139 | spin_lock_irqsave(&hc->lock, flags); | |
4140 | disable_hwirq(hc); | |
4141 | spin_unlock_irqrestore(&hc->lock, flags); | |
4142 | if (debug & DEBUG_HFCMULTI_INIT) | |
4143 | printk(KERN_DEBUG "%s: IRQ %d count %d\n", | |
4144 | __func__, hc->irq, hc->irqcnt); | |
4145 | if (hc->irqcnt) { | |
4146 | if (debug & DEBUG_HFCMULTI_INIT) | |
4147 | printk(KERN_DEBUG "%s: done\n", __func__); | |
4148 | ||
4149 | return 0; | |
4150 | } | |
4151 | if (test_bit(HFC_CHIP_PCM_SLAVE, &hc->chip)) { | |
4152 | printk(KERN_INFO "ignoring missing interrupts\n"); | |
4153 | return 0; | |
4154 | } | |
4155 | ||
4156 | printk(KERN_ERR "HFC PCI: IRQ(%d) getting no interrupts during init.\n", | |
4157 | hc->irq); | |
4158 | ||
4159 | err = -EIO; | |
4160 | ||
4161 | error: | |
4162 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4163 | spin_lock_irqsave(&plx_lock, plx_flags); | |
4164 | plx_acc = (u_short *)(hc->plx_membase+PLX_INTCSR); | |
4165 | writew(0x00, plx_acc); /*disable IRQs*/ | |
4166 | spin_unlock_irqrestore(&plx_lock, plx_flags); | |
4167 | } | |
4168 | ||
4169 | if (debug & DEBUG_HFCMULTI_INIT) | |
4170 | printk(KERN_WARNING "%s: free irq %d\n", __func__, hc->irq); | |
4171 | if (hc->irq) { | |
4172 | free_irq(hc->irq, hc); | |
4173 | hc->irq = 0; | |
4174 | } | |
4175 | ||
4176 | if (debug & DEBUG_HFCMULTI_INIT) | |
4177 | printk(KERN_DEBUG "%s: done (err=%d)\n", __func__, err); | |
4178 | return err; | |
4179 | } | |
4180 | ||
4181 | /* | |
4182 | * find pci device and set it up | |
4183 | */ | |
4184 | ||
4185 | static int | |
4186 | setup_pci(struct hfc_multi *hc, struct pci_dev *pdev, | |
4187 | const struct pci_device_id *ent) | |
4188 | { | |
4189 | struct hm_map *m = (struct hm_map *)ent->driver_data; | |
4190 | ||
4191 | printk(KERN_INFO | |
4192 | "HFC-multi: card manufacturer: '%s' card name: '%s' clock: %s\n", | |
4193 | m->vendor_name, m->card_name, m->clock2 ? "double" : "normal"); | |
4194 | ||
4195 | hc->pci_dev = pdev; | |
4196 | if (m->clock2) | |
4197 | test_and_set_bit(HFC_CHIP_CLOCK2, &hc->chip); | |
4198 | ||
4199 | if (ent->device == 0xB410) { | |
4200 | test_and_set_bit(HFC_CHIP_B410P, &hc->chip); | |
4201 | test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); | |
4202 | test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
4203 | hc->slots = 32; | |
4204 | } | |
4205 | ||
4206 | if (hc->pci_dev->irq <= 0) { | |
4207 | printk(KERN_WARNING "HFC-multi: No IRQ for PCI card found.\n"); | |
4208 | return -EIO; | |
4209 | } | |
4210 | if (pci_enable_device(hc->pci_dev)) { | |
4211 | printk(KERN_WARNING "HFC-multi: Error enabling PCI card.\n"); | |
4212 | return -EIO; | |
4213 | } | |
4214 | hc->leds = m->leds; | |
4215 | hc->ledstate = 0xAFFEAFFE; | |
4216 | hc->opticalsupport = m->opticalsupport; | |
4217 | ||
4218 | /* set memory access methods */ | |
4219 | if (m->io_mode) /* use mode from card config */ | |
4220 | hc->io_mode = m->io_mode; | |
4221 | switch (hc->io_mode) { | |
4222 | case HFC_IO_MODE_PLXSD: | |
4223 | test_and_set_bit(HFC_CHIP_PLXSD, &hc->chip); | |
4224 | hc->slots = 128; /* required */ | |
4225 | /* fall through */ | |
4226 | case HFC_IO_MODE_PCIMEM: | |
4227 | hc->HFC_outb = HFC_outb_pcimem; | |
4228 | hc->HFC_inb = HFC_inb_pcimem; | |
4229 | hc->HFC_inw = HFC_inw_pcimem; | |
4230 | hc->HFC_wait = HFC_wait_pcimem; | |
4231 | hc->read_fifo = read_fifo_pcimem; | |
4232 | hc->write_fifo = write_fifo_pcimem; | |
4233 | break; | |
4234 | case HFC_IO_MODE_REGIO: | |
4235 | hc->HFC_outb = HFC_outb_regio; | |
4236 | hc->HFC_inb = HFC_inb_regio; | |
4237 | hc->HFC_inw = HFC_inw_regio; | |
4238 | hc->HFC_wait = HFC_wait_regio; | |
4239 | hc->read_fifo = read_fifo_regio; | |
4240 | hc->write_fifo = write_fifo_regio; | |
4241 | break; | |
4242 | default: | |
4243 | printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); | |
4244 | pci_disable_device(hc->pci_dev); | |
4245 | return -EIO; | |
4246 | } | |
4247 | hc->HFC_outb_nodebug = hc->HFC_outb; | |
4248 | hc->HFC_inb_nodebug = hc->HFC_inb; | |
4249 | hc->HFC_inw_nodebug = hc->HFC_inw; | |
4250 | hc->HFC_wait_nodebug = hc->HFC_wait; | |
4251 | #ifdef HFC_REGISTER_DEBUG | |
4252 | hc->HFC_outb = HFC_outb_debug; | |
4253 | hc->HFC_inb = HFC_inb_debug; | |
4254 | hc->HFC_inw = HFC_inw_debug; | |
4255 | hc->HFC_wait = HFC_wait_debug; | |
4256 | #endif | |
4257 | hc->pci_iobase = 0; | |
4258 | hc->pci_membase = NULL; | |
4259 | hc->plx_membase = NULL; | |
4260 | ||
4261 | switch (hc->io_mode) { | |
4262 | case HFC_IO_MODE_PLXSD: | |
4263 | hc->plx_origmembase = hc->pci_dev->resource[0].start; | |
4264 | /* MEMBASE 1 is PLX PCI Bridge */ | |
4265 | ||
4266 | if (!hc->plx_origmembase) { | |
4267 | printk(KERN_WARNING | |
4268 | "HFC-multi: No IO-Memory for PCI PLX bridge found\n"); | |
4269 | pci_disable_device(hc->pci_dev); | |
4270 | return -EIO; | |
4271 | } | |
4272 | ||
4273 | hc->plx_membase = ioremap(hc->plx_origmembase, 0x80); | |
4274 | if (!hc->plx_membase) { | |
4275 | printk(KERN_WARNING | |
4276 | "HFC-multi: failed to remap plx address space. " | |
4277 | "(internal error)\n"); | |
4278 | pci_disable_device(hc->pci_dev); | |
4279 | return -EIO; | |
4280 | } | |
4281 | printk(KERN_INFO | |
4282 | "HFC-multi: plx_membase:%#lx plx_origmembase:%#lx\n", | |
4283 | (u_long)hc->plx_membase, hc->plx_origmembase); | |
4284 | ||
4285 | hc->pci_origmembase = hc->pci_dev->resource[2].start; | |
4286 | /* MEMBASE 1 is PLX PCI Bridge */ | |
4287 | if (!hc->pci_origmembase) { | |
4288 | printk(KERN_WARNING | |
4289 | "HFC-multi: No IO-Memory for PCI card found\n"); | |
4290 | pci_disable_device(hc->pci_dev); | |
4291 | return -EIO; | |
4292 | } | |
4293 | ||
4294 | hc->pci_membase = ioremap(hc->pci_origmembase, 0x400); | |
4295 | if (!hc->pci_membase) { | |
4296 | printk(KERN_WARNING "HFC-multi: failed to remap io " | |
4297 | "address space. (internal error)\n"); | |
4298 | pci_disable_device(hc->pci_dev); | |
4299 | return -EIO; | |
4300 | } | |
4301 | ||
4302 | printk(KERN_INFO | |
4303 | "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d HZ %d " | |
4304 | "leds-type %d\n", | |
4305 | hc->id, (u_long)hc->pci_membase, hc->pci_origmembase, | |
4306 | hc->pci_dev->irq, HZ, hc->leds); | |
4307 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); | |
4308 | break; | |
4309 | case HFC_IO_MODE_PCIMEM: | |
4310 | hc->pci_origmembase = hc->pci_dev->resource[1].start; | |
4311 | if (!hc->pci_origmembase) { | |
4312 | printk(KERN_WARNING | |
4313 | "HFC-multi: No IO-Memory for PCI card found\n"); | |
4314 | pci_disable_device(hc->pci_dev); | |
4315 | return -EIO; | |
4316 | } | |
4317 | ||
4318 | hc->pci_membase = ioremap(hc->pci_origmembase, 256); | |
4319 | if (!hc->pci_membase) { | |
4320 | printk(KERN_WARNING | |
4321 | "HFC-multi: failed to remap io address space. " | |
4322 | "(internal error)\n"); | |
4323 | pci_disable_device(hc->pci_dev); | |
4324 | return -EIO; | |
4325 | } | |
4326 | printk(KERN_INFO "card %d: defined at MEMBASE %#lx (%#lx) IRQ %d " | |
4327 | "HZ %d leds-type %d\n", hc->id, (u_long)hc->pci_membase, | |
4328 | hc->pci_origmembase, hc->pci_dev->irq, HZ, hc->leds); | |
4329 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_MEMIO); | |
4330 | break; | |
4331 | case HFC_IO_MODE_REGIO: | |
4332 | hc->pci_iobase = (u_int) hc->pci_dev->resource[0].start; | |
4333 | if (!hc->pci_iobase) { | |
4334 | printk(KERN_WARNING | |
4335 | "HFC-multi: No IO for PCI card found\n"); | |
4336 | pci_disable_device(hc->pci_dev); | |
4337 | return -EIO; | |
4338 | } | |
4339 | ||
4340 | if (!request_region(hc->pci_iobase, 8, "hfcmulti")) { | |
4341 | printk(KERN_WARNING "HFC-multi: failed to request " | |
4342 | "address space at 0x%08lx (internal error)\n", | |
4343 | hc->pci_iobase); | |
4344 | pci_disable_device(hc->pci_dev); | |
4345 | return -EIO; | |
4346 | } | |
4347 | ||
4348 | printk(KERN_INFO | |
4349 | "%s %s: defined at IOBASE %#x IRQ %d HZ %d leds-type %d\n", | |
4350 | m->vendor_name, m->card_name, (u_int) hc->pci_iobase, | |
4351 | hc->pci_dev->irq, HZ, hc->leds); | |
4352 | pci_write_config_word(hc->pci_dev, PCI_COMMAND, PCI_ENA_REGIO); | |
4353 | break; | |
4354 | default: | |
4355 | printk(KERN_WARNING "HFC-multi: Invalid IO mode.\n"); | |
4356 | pci_disable_device(hc->pci_dev); | |
4357 | return -EIO; | |
4358 | } | |
4359 | ||
4360 | pci_set_drvdata(hc->pci_dev, hc); | |
4361 | ||
4362 | /* At this point the needed PCI config is done */ | |
4363 | /* fifos are still not enabled */ | |
4364 | return 0; | |
4365 | } | |
4366 | ||
4367 | ||
4368 | /* | |
4369 | * remove port | |
4370 | */ | |
4371 | ||
4372 | static void | |
4373 | release_port(struct hfc_multi *hc, struct dchannel *dch) | |
4374 | { | |
4375 | int pt, ci, i = 0; | |
4376 | u_long flags; | |
4377 | struct bchannel *pb; | |
4378 | ||
4379 | ci = dch->slot; | |
4380 | pt = hc->chan[ci].port; | |
4381 | ||
4382 | if (debug & DEBUG_HFCMULTI_INIT) | |
4383 | printk(KERN_DEBUG "%s: entered for port %d\n", | |
4384 | __func__, pt + 1); | |
4385 | ||
4386 | if (pt >= hc->ports) { | |
4387 | printk(KERN_WARNING "%s: ERROR port out of range (%d).\n", | |
4388 | __func__, pt + 1); | |
4389 | return; | |
4390 | } | |
4391 | ||
4392 | if (debug & DEBUG_HFCMULTI_INIT) | |
4393 | printk(KERN_DEBUG "%s: releasing port=%d\n", | |
4394 | __func__, pt + 1); | |
4395 | ||
4396 | if (dch->dev.D.protocol == ISDN_P_TE_S0) | |
4397 | l1_event(dch->l1, CLOSE_CHANNEL); | |
4398 | ||
4399 | hc->chan[ci].dch = NULL; | |
4400 | ||
4401 | if (hc->created[pt]) { | |
4402 | hc->created[pt] = 0; | |
4403 | mISDN_unregister_device(&dch->dev); | |
4404 | } | |
4405 | ||
4406 | spin_lock_irqsave(&hc->lock, flags); | |
4407 | ||
4408 | if (dch->timer.function) { | |
4409 | del_timer(&dch->timer); | |
4410 | dch->timer.function = NULL; | |
4411 | } | |
4412 | ||
4413 | if (hc->type == 1) { /* E1 */ | |
4414 | /* remove sync */ | |
4415 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4416 | hc->syncronized = 0; | |
4417 | plxsd_checksync(hc, 1); | |
4418 | } | |
4419 | /* free channels */ | |
4420 | for (i = 0; i <= 31; i++) { | |
4421 | if (hc->chan[i].bch) { | |
4422 | if (debug & DEBUG_HFCMULTI_INIT) | |
4423 | printk(KERN_DEBUG | |
4424 | "%s: free port %d channel %d\n", | |
4425 | __func__, hc->chan[i].port+1, i); | |
4426 | pb = hc->chan[i].bch; | |
4427 | hc->chan[i].bch = NULL; | |
4428 | spin_unlock_irqrestore(&hc->lock, flags); | |
4429 | mISDN_freebchannel(pb); | |
4430 | kfree(pb); | |
4431 | kfree(hc->chan[i].coeff); | |
4432 | spin_lock_irqsave(&hc->lock, flags); | |
4433 | } | |
4434 | } | |
4435 | } else { | |
4436 | /* remove sync */ | |
4437 | if (test_bit(HFC_CHIP_PLXSD, &hc->chip)) { | |
4438 | hc->syncronized &= | |
4439 | ~(1 << hc->chan[ci].port); | |
4440 | plxsd_checksync(hc, 1); | |
4441 | } | |
4442 | /* free channels */ | |
4443 | if (hc->chan[ci - 2].bch) { | |
4444 | if (debug & DEBUG_HFCMULTI_INIT) | |
4445 | printk(KERN_DEBUG | |
4446 | "%s: free port %d channel %d\n", | |
4447 | __func__, hc->chan[ci - 2].port+1, | |
4448 | ci - 2); | |
4449 | pb = hc->chan[ci - 2].bch; | |
4450 | hc->chan[ci - 2].bch = NULL; | |
4451 | spin_unlock_irqrestore(&hc->lock, flags); | |
4452 | mISDN_freebchannel(pb); | |
4453 | kfree(pb); | |
4454 | kfree(hc->chan[ci - 2].coeff); | |
4455 | spin_lock_irqsave(&hc->lock, flags); | |
4456 | } | |
4457 | if (hc->chan[ci - 1].bch) { | |
4458 | if (debug & DEBUG_HFCMULTI_INIT) | |
4459 | printk(KERN_DEBUG | |
4460 | "%s: free port %d channel %d\n", | |
4461 | __func__, hc->chan[ci - 1].port+1, | |
4462 | ci - 1); | |
4463 | pb = hc->chan[ci - 1].bch; | |
4464 | hc->chan[ci - 1].bch = NULL; | |
4465 | spin_unlock_irqrestore(&hc->lock, flags); | |
4466 | mISDN_freebchannel(pb); | |
4467 | kfree(pb); | |
4468 | kfree(hc->chan[ci - 1].coeff); | |
4469 | spin_lock_irqsave(&hc->lock, flags); | |
4470 | } | |
4471 | } | |
4472 | ||
4473 | spin_unlock_irqrestore(&hc->lock, flags); | |
4474 | ||
4475 | if (debug & DEBUG_HFCMULTI_INIT) | |
4476 | printk(KERN_DEBUG "%s: free port %d channel D\n", __func__, pt); | |
4477 | mISDN_freedchannel(dch); | |
4478 | kfree(dch); | |
4479 | ||
4480 | if (debug & DEBUG_HFCMULTI_INIT) | |
4481 | printk(KERN_DEBUG "%s: done!\n", __func__); | |
4482 | } | |
4483 | ||
4484 | static void | |
4485 | release_card(struct hfc_multi *hc) | |
4486 | { | |
4487 | u_long flags; | |
4488 | int ch; | |
4489 | ||
4490 | if (debug & DEBUG_HFCMULTI_INIT) | |
4491 | printk(KERN_WARNING "%s: release card (%d) entered\n", | |
4492 | __func__, hc->id); | |
4493 | ||
4494 | spin_lock_irqsave(&hc->lock, flags); | |
4495 | disable_hwirq(hc); | |
4496 | spin_unlock_irqrestore(&hc->lock, flags); | |
4497 | ||
4498 | udelay(1000); | |
4499 | ||
4500 | /* dimm leds */ | |
4501 | if (hc->leds) | |
4502 | hfcmulti_leds(hc); | |
4503 | ||
4504 | /* disable D-channels & B-channels */ | |
4505 | if (debug & DEBUG_HFCMULTI_INIT) | |
4506 | printk(KERN_DEBUG "%s: disable all channels (d and b)\n", | |
4507 | __func__); | |
4508 | for (ch = 0; ch <= 31; ch++) { | |
4509 | if (hc->chan[ch].dch) | |
4510 | release_port(hc, hc->chan[ch].dch); | |
4511 | } | |
4512 | ||
4513 | /* release hardware & irq */ | |
4514 | if (hc->irq) { | |
4515 | if (debug & DEBUG_HFCMULTI_INIT) | |
4516 | printk(KERN_WARNING "%s: free irq %d\n", | |
4517 | __func__, hc->irq); | |
4518 | free_irq(hc->irq, hc); | |
4519 | hc->irq = 0; | |
4520 | ||
4521 | } | |
4522 | release_io_hfcmulti(hc); | |
4523 | ||
4524 | if (debug & DEBUG_HFCMULTI_INIT) | |
4525 | printk(KERN_WARNING "%s: remove instance from list\n", | |
4526 | __func__); | |
4527 | list_del(&hc->list); | |
4528 | ||
4529 | if (debug & DEBUG_HFCMULTI_INIT) | |
4530 | printk(KERN_WARNING "%s: delete instance\n", __func__); | |
4531 | if (hc == syncmaster) | |
4532 | syncmaster = NULL; | |
4533 | kfree(hc); | |
4534 | if (debug & DEBUG_HFCMULTI_INIT) | |
4535 | printk(KERN_WARNING "%s: card successfully removed\n", | |
4536 | __func__); | |
4537 | } | |
4538 | ||
4539 | static int | |
4540 | init_e1_port(struct hfc_multi *hc, struct hm_map *m) | |
4541 | { | |
4542 | struct dchannel *dch; | |
4543 | struct bchannel *bch; | |
4544 | int ch, ret = 0; | |
4545 | char name[MISDN_MAX_IDLEN]; | |
4546 | ||
4547 | dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); | |
4548 | if (!dch) | |
4549 | return -ENOMEM; | |
4550 | dch->debug = debug; | |
4551 | mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); | |
4552 | dch->hw = hc; | |
4553 | dch->dev.Dprotocols = (1 << ISDN_P_TE_E1) | (1 << ISDN_P_NT_E1); | |
4554 | dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | | |
4555 | (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); | |
4556 | dch->dev.D.send = handle_dmsg; | |
4557 | dch->dev.D.ctrl = hfcm_dctrl; | |
4558 | dch->dev.nrbchan = (hc->dslot)?30:31; | |
4559 | dch->slot = hc->dslot; | |
4560 | hc->chan[hc->dslot].dch = dch; | |
4561 | hc->chan[hc->dslot].port = 0; | |
4562 | hc->chan[hc->dslot].nt_timer = -1; | |
4563 | for (ch = 1; ch <= 31; ch++) { | |
4564 | if (ch == hc->dslot) /* skip dchannel */ | |
4565 | continue; | |
4566 | bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); | |
4567 | if (!bch) { | |
4568 | printk(KERN_ERR "%s: no memory for bchannel\n", | |
4569 | __func__); | |
4570 | ret = -ENOMEM; | |
4571 | goto free_chan; | |
4572 | } | |
4573 | hc->chan[ch].coeff = kzalloc(512, GFP_KERNEL); | |
4574 | if (!hc->chan[ch].coeff) { | |
4575 | printk(KERN_ERR "%s: no memory for coeffs\n", | |
4576 | __func__); | |
4577 | ret = -ENOMEM; | |
4578 | goto free_chan; | |
4579 | } | |
4580 | bch->nr = ch; | |
4581 | bch->slot = ch; | |
4582 | bch->debug = debug; | |
4583 | mISDN_initbchannel(bch, MAX_DATA_MEM); | |
4584 | bch->hw = hc; | |
4585 | bch->ch.send = handle_bmsg; | |
4586 | bch->ch.ctrl = hfcm_bctrl; | |
4587 | bch->ch.nr = ch; | |
4588 | list_add(&bch->ch.list, &dch->dev.bchannels); | |
4589 | hc->chan[ch].bch = bch; | |
4590 | hc->chan[ch].port = 0; | |
ff4cc1de | 4591 | set_channelmap(bch->nr, dch->dev.channelmap); |
af69fb3a KK |
4592 | } |
4593 | /* set optical line type */ | |
4594 | if (port[Port_cnt] & 0x001) { | |
4595 | if (!m->opticalsupport) { | |
4596 | printk(KERN_INFO | |
4597 | "This board has no optical " | |
4598 | "support\n"); | |
4599 | } else { | |
4600 | if (debug & DEBUG_HFCMULTI_INIT) | |
4601 | printk(KERN_DEBUG | |
4602 | "%s: PORT set optical " | |
4603 | "interfacs: card(%d) " | |
4604 | "port(%d)\n", | |
4605 | __func__, | |
4606 | HFC_cnt + 1, 1); | |
4607 | test_and_set_bit(HFC_CFG_OPTICAL, | |
4608 | &hc->chan[hc->dslot].cfg); | |
4609 | } | |
4610 | } | |
4611 | /* set LOS report */ | |
4612 | if (port[Port_cnt] & 0x004) { | |
4613 | if (debug & DEBUG_HFCMULTI_INIT) | |
4614 | printk(KERN_DEBUG "%s: PORT set " | |
4615 | "LOS report: card(%d) port(%d)\n", | |
4616 | __func__, HFC_cnt + 1, 1); | |
4617 | test_and_set_bit(HFC_CFG_REPORT_LOS, | |
4618 | &hc->chan[hc->dslot].cfg); | |
4619 | } | |
4620 | /* set AIS report */ | |
4621 | if (port[Port_cnt] & 0x008) { | |
4622 | if (debug & DEBUG_HFCMULTI_INIT) | |
4623 | printk(KERN_DEBUG "%s: PORT set " | |
4624 | "AIS report: card(%d) port(%d)\n", | |
4625 | __func__, HFC_cnt + 1, 1); | |
4626 | test_and_set_bit(HFC_CFG_REPORT_AIS, | |
4627 | &hc->chan[hc->dslot].cfg); | |
4628 | } | |
4629 | /* set SLIP report */ | |
4630 | if (port[Port_cnt] & 0x010) { | |
4631 | if (debug & DEBUG_HFCMULTI_INIT) | |
4632 | printk(KERN_DEBUG | |
4633 | "%s: PORT set SLIP report: " | |
4634 | "card(%d) port(%d)\n", | |
4635 | __func__, HFC_cnt + 1, 1); | |
4636 | test_and_set_bit(HFC_CFG_REPORT_SLIP, | |
4637 | &hc->chan[hc->dslot].cfg); | |
4638 | } | |
4639 | /* set RDI report */ | |
4640 | if (port[Port_cnt] & 0x020) { | |
4641 | if (debug & DEBUG_HFCMULTI_INIT) | |
4642 | printk(KERN_DEBUG | |
4643 | "%s: PORT set RDI report: " | |
4644 | "card(%d) port(%d)\n", | |
4645 | __func__, HFC_cnt + 1, 1); | |
4646 | test_and_set_bit(HFC_CFG_REPORT_RDI, | |
4647 | &hc->chan[hc->dslot].cfg); | |
4648 | } | |
4649 | /* set CRC-4 Mode */ | |
4650 | if (!(port[Port_cnt] & 0x100)) { | |
4651 | if (debug & DEBUG_HFCMULTI_INIT) | |
4652 | printk(KERN_DEBUG "%s: PORT turn on CRC4 report:" | |
4653 | " card(%d) port(%d)\n", | |
4654 | __func__, HFC_cnt + 1, 1); | |
4655 | test_and_set_bit(HFC_CFG_CRC4, | |
4656 | &hc->chan[hc->dslot].cfg); | |
4657 | } else { | |
4658 | if (debug & DEBUG_HFCMULTI_INIT) | |
4659 | printk(KERN_DEBUG "%s: PORT turn off CRC4" | |
4660 | " report: card(%d) port(%d)\n", | |
4661 | __func__, HFC_cnt + 1, 1); | |
4662 | } | |
4663 | /* set forced clock */ | |
4664 | if (port[Port_cnt] & 0x0200) { | |
4665 | if (debug & DEBUG_HFCMULTI_INIT) | |
4666 | printk(KERN_DEBUG "%s: PORT force getting clock from " | |
4667 | "E1: card(%d) port(%d)\n", | |
4668 | __func__, HFC_cnt + 1, 1); | |
4669 | test_and_set_bit(HFC_CHIP_E1CLOCK_GET, &hc->chip); | |
4670 | } else | |
4671 | if (port[Port_cnt] & 0x0400) { | |
4672 | if (debug & DEBUG_HFCMULTI_INIT) | |
4673 | printk(KERN_DEBUG "%s: PORT force putting clock to " | |
4674 | "E1: card(%d) port(%d)\n", | |
4675 | __func__, HFC_cnt + 1, 1); | |
4676 | test_and_set_bit(HFC_CHIP_E1CLOCK_PUT, &hc->chip); | |
4677 | } | |
4678 | /* set JATT PLL */ | |
4679 | if (port[Port_cnt] & 0x0800) { | |
4680 | if (debug & DEBUG_HFCMULTI_INIT) | |
4681 | printk(KERN_DEBUG "%s: PORT disable JATT PLL on " | |
4682 | "E1: card(%d) port(%d)\n", | |
4683 | __func__, HFC_cnt + 1, 1); | |
4684 | test_and_set_bit(HFC_CHIP_RX_SYNC, &hc->chip); | |
4685 | } | |
4686 | /* set elastic jitter buffer */ | |
4687 | if (port[Port_cnt] & 0x3000) { | |
4688 | hc->chan[hc->dslot].jitter = (port[Port_cnt]>>12) & 0x3; | |
4689 | if (debug & DEBUG_HFCMULTI_INIT) | |
4690 | printk(KERN_DEBUG | |
4691 | "%s: PORT set elastic " | |
4692 | "buffer to %d: card(%d) port(%d)\n", | |
4693 | __func__, hc->chan[hc->dslot].jitter, | |
4694 | HFC_cnt + 1, 1); | |
4695 | } else | |
4696 | hc->chan[hc->dslot].jitter = 2; /* default */ | |
4697 | snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-e1.%d", HFC_cnt + 1); | |
4698 | ret = mISDN_register_device(&dch->dev, name); | |
4699 | if (ret) | |
4700 | goto free_chan; | |
4701 | hc->created[0] = 1; | |
4702 | return ret; | |
4703 | free_chan: | |
4704 | release_port(hc, dch); | |
4705 | return ret; | |
4706 | } | |
4707 | ||
4708 | static int | |
4709 | init_multi_port(struct hfc_multi *hc, int pt) | |
4710 | { | |
4711 | struct dchannel *dch; | |
4712 | struct bchannel *bch; | |
4713 | int ch, i, ret = 0; | |
4714 | char name[MISDN_MAX_IDLEN]; | |
4715 | ||
4716 | dch = kzalloc(sizeof(struct dchannel), GFP_KERNEL); | |
4717 | if (!dch) | |
4718 | return -ENOMEM; | |
4719 | dch->debug = debug; | |
4720 | mISDN_initdchannel(dch, MAX_DFRAME_LEN_L1, ph_state_change); | |
4721 | dch->hw = hc; | |
4722 | dch->dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0); | |
4723 | dch->dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) | | |
4724 | (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK)); | |
4725 | dch->dev.D.send = handle_dmsg; | |
4726 | dch->dev.D.ctrl = hfcm_dctrl; | |
4727 | dch->dev.nrbchan = 2; | |
4728 | i = pt << 2; | |
4729 | dch->slot = i + 2; | |
4730 | hc->chan[i + 2].dch = dch; | |
4731 | hc->chan[i + 2].port = pt; | |
4732 | hc->chan[i + 2].nt_timer = -1; | |
4733 | for (ch = 0; ch < dch->dev.nrbchan; ch++) { | |
4734 | bch = kzalloc(sizeof(struct bchannel), GFP_KERNEL); | |
4735 | if (!bch) { | |
4736 | printk(KERN_ERR "%s: no memory for bchannel\n", | |
4737 | __func__); | |
4738 | ret = -ENOMEM; | |
4739 | goto free_chan; | |
4740 | } | |
4741 | hc->chan[i + ch].coeff = kzalloc(512, GFP_KERNEL); | |
4742 | if (!hc->chan[i + ch].coeff) { | |
4743 | printk(KERN_ERR "%s: no memory for coeffs\n", | |
4744 | __func__); | |
4745 | ret = -ENOMEM; | |
4746 | goto free_chan; | |
4747 | } | |
4748 | bch->nr = ch + 1; | |
4749 | bch->slot = i + ch; | |
4750 | bch->debug = debug; | |
4751 | mISDN_initbchannel(bch, MAX_DATA_MEM); | |
4752 | bch->hw = hc; | |
4753 | bch->ch.send = handle_bmsg; | |
4754 | bch->ch.ctrl = hfcm_bctrl; | |
4755 | bch->ch.nr = ch + 1; | |
4756 | list_add(&bch->ch.list, &dch->dev.bchannels); | |
4757 | hc->chan[i + ch].bch = bch; | |
4758 | hc->chan[i + ch].port = pt; | |
ff4cc1de | 4759 | set_channelmap(bch->nr, dch->dev.channelmap); |
af69fb3a KK |
4760 | } |
4761 | /* set master clock */ | |
4762 | if (port[Port_cnt] & 0x001) { | |
4763 | if (debug & DEBUG_HFCMULTI_INIT) | |
4764 | printk(KERN_DEBUG | |
4765 | "%s: PROTOCOL set master clock: " | |
4766 | "card(%d) port(%d)\n", | |
4767 | __func__, HFC_cnt + 1, pt + 1); | |
4768 | if (dch->dev.D.protocol != ISDN_P_TE_S0) { | |
4769 | printk(KERN_ERR "Error: Master clock " | |
4770 | "for port(%d) of card(%d) is only" | |
4771 | " possible with TE-mode\n", | |
4772 | pt + 1, HFC_cnt + 1); | |
4773 | ret = -EINVAL; | |
4774 | goto free_chan; | |
4775 | } | |
4776 | if (hc->masterclk >= 0) { | |
4777 | printk(KERN_ERR "Error: Master clock " | |
4778 | "for port(%d) of card(%d) already " | |
4779 | "defined for port(%d)\n", | |
4780 | pt + 1, HFC_cnt + 1, hc->masterclk+1); | |
4781 | ret = -EINVAL; | |
4782 | goto free_chan; | |
4783 | } | |
4784 | hc->masterclk = pt; | |
4785 | } | |
4786 | /* set transmitter line to non capacitive */ | |
4787 | if (port[Port_cnt] & 0x002) { | |
4788 | if (debug & DEBUG_HFCMULTI_INIT) | |
4789 | printk(KERN_DEBUG | |
4790 | "%s: PROTOCOL set non capacitive " | |
4791 | "transmitter: card(%d) port(%d)\n", | |
4792 | __func__, HFC_cnt + 1, pt + 1); | |
4793 | test_and_set_bit(HFC_CFG_NONCAP_TX, | |
4794 | &hc->chan[i + 2].cfg); | |
4795 | } | |
4796 | /* disable E-channel */ | |
4797 | if (port[Port_cnt] & 0x004) { | |
4798 | if (debug & DEBUG_HFCMULTI_INIT) | |
4799 | printk(KERN_DEBUG | |
4800 | "%s: PROTOCOL disable E-channel: " | |
4801 | "card(%d) port(%d)\n", | |
4802 | __func__, HFC_cnt + 1, pt + 1); | |
4803 | test_and_set_bit(HFC_CFG_DIS_ECHANNEL, | |
4804 | &hc->chan[i + 2].cfg); | |
4805 | } | |
4806 | snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-%ds.%d/%d", | |
4807 | hc->type, HFC_cnt + 1, pt + 1); | |
4808 | ret = mISDN_register_device(&dch->dev, name); | |
4809 | if (ret) | |
4810 | goto free_chan; | |
4811 | hc->created[pt] = 1; | |
4812 | return ret; | |
4813 | free_chan: | |
4814 | release_port(hc, dch); | |
4815 | return ret; | |
4816 | } | |
4817 | ||
4818 | static int | |
4819 | hfcmulti_init(struct pci_dev *pdev, const struct pci_device_id *ent) | |
4820 | { | |
4821 | struct hm_map *m = (struct hm_map *)ent->driver_data; | |
4822 | int ret_err = 0; | |
4823 | int pt; | |
4824 | struct hfc_multi *hc; | |
4825 | u_long flags; | |
4826 | u_char dips = 0, pmj = 0; /* dip settings, port mode Jumpers */ | |
4827 | ||
4828 | if (HFC_cnt >= MAX_CARDS) { | |
4829 | printk(KERN_ERR "too many cards (max=%d).\n", | |
4830 | MAX_CARDS); | |
4831 | return -EINVAL; | |
4832 | } | |
4833 | if ((type[HFC_cnt] & 0xff) && (type[HFC_cnt] & 0xff) != m->type) { | |
4834 | printk(KERN_WARNING "HFC-MULTI: Card '%s:%s' type %d found but " | |
4835 | "type[%d] %d was supplied as module parameter\n", | |
4836 | m->vendor_name, m->card_name, m->type, HFC_cnt, | |
4837 | type[HFC_cnt] & 0xff); | |
4838 | printk(KERN_WARNING "HFC-MULTI: Load module without parameters " | |
4839 | "first, to see cards and their types."); | |
4840 | return -EINVAL; | |
4841 | } | |
4842 | if (debug & DEBUG_HFCMULTI_INIT) | |
4843 | printk(KERN_DEBUG "%s: Registering %s:%s chip type %d (0x%x)\n", | |
4844 | __func__, m->vendor_name, m->card_name, m->type, | |
4845 | type[HFC_cnt]); | |
4846 | ||
4847 | /* allocate card+fifo structure */ | |
4848 | hc = kzalloc(sizeof(struct hfc_multi), GFP_KERNEL); | |
4849 | if (!hc) { | |
4850 | printk(KERN_ERR "No kmem for HFC-Multi card\n"); | |
4851 | return -ENOMEM; | |
4852 | } | |
4853 | spin_lock_init(&hc->lock); | |
4854 | hc->mtyp = m; | |
4855 | hc->type = m->type; | |
4856 | hc->ports = m->ports; | |
4857 | hc->id = HFC_cnt; | |
4858 | hc->pcm = pcm[HFC_cnt]; | |
4859 | hc->io_mode = iomode[HFC_cnt]; | |
4860 | if (dslot[HFC_cnt] < 0) { | |
4861 | hc->dslot = 0; | |
4862 | printk(KERN_INFO "HFC-E1 card has disabled D-channel, but " | |
4863 | "31 B-channels\n"); | |
4864 | } if (dslot[HFC_cnt] > 0 && dslot[HFC_cnt] < 32) { | |
4865 | hc->dslot = dslot[HFC_cnt]; | |
4866 | printk(KERN_INFO "HFC-E1 card has alternating D-channel on " | |
4867 | "time slot %d\n", dslot[HFC_cnt]); | |
4868 | } else | |
4869 | hc->dslot = 16; | |
4870 | ||
4871 | /* set chip specific features */ | |
4872 | hc->masterclk = -1; | |
4873 | if (type[HFC_cnt] & 0x100) { | |
4874 | test_and_set_bit(HFC_CHIP_ULAW, &hc->chip); | |
4875 | silence = 0xff; /* ulaw silence */ | |
4876 | } else | |
4877 | silence = 0x2a; /* alaw silence */ | |
4878 | if (!(type[HFC_cnt] & 0x200)) | |
4879 | test_and_set_bit(HFC_CHIP_DTMF, &hc->chip); | |
4880 | ||
4881 | if (type[HFC_cnt] & 0x800) | |
4882 | test_and_set_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
4883 | if (type[HFC_cnt] & 0x1000) { | |
4884 | test_and_set_bit(HFC_CHIP_PCM_MASTER, &hc->chip); | |
4885 | test_and_clear_bit(HFC_CHIP_PCM_SLAVE, &hc->chip); | |
4886 | } | |
4887 | if (type[HFC_cnt] & 0x4000) | |
4888 | test_and_set_bit(HFC_CHIP_EXRAM_128, &hc->chip); | |
4889 | if (type[HFC_cnt] & 0x8000) | |
4890 | test_and_set_bit(HFC_CHIP_EXRAM_512, &hc->chip); | |
4891 | hc->slots = 32; | |
4892 | if (type[HFC_cnt] & 0x10000) | |
4893 | hc->slots = 64; | |
4894 | if (type[HFC_cnt] & 0x20000) | |
4895 | hc->slots = 128; | |
4896 | if (type[HFC_cnt] & 0x80000) { | |
4897 | test_and_set_bit(HFC_CHIP_WATCHDOG, &hc->chip); | |
4898 | hc->wdcount = 0; | |
4899 | hc->wdbyte = V_GPIO_OUT2; | |
4900 | printk(KERN_NOTICE "Watchdog enabled\n"); | |
4901 | } | |
4902 | ||
4903 | /* setup pci, hc->slots may change due to PLXSD */ | |
4904 | ret_err = setup_pci(hc, pdev, ent); | |
4905 | if (ret_err) { | |
4906 | if (hc == syncmaster) | |
4907 | syncmaster = NULL; | |
4908 | kfree(hc); | |
4909 | return ret_err; | |
4910 | } | |
4911 | ||
4912 | /* crate channels */ | |
4913 | for (pt = 0; pt < hc->ports; pt++) { | |
4914 | if (Port_cnt >= MAX_PORTS) { | |
4915 | printk(KERN_ERR "too many ports (max=%d).\n", | |
4916 | MAX_PORTS); | |
4917 | ret_err = -EINVAL; | |
4918 | goto free_card; | |
4919 | } | |
4920 | if (hc->type == 1) | |
4921 | ret_err = init_e1_port(hc, m); | |
4922 | else | |
4923 | ret_err = init_multi_port(hc, pt); | |
4924 | if (debug & DEBUG_HFCMULTI_INIT) | |
4925 | printk(KERN_DEBUG | |
4926 | "%s: Registering D-channel, card(%d) port(%d)" | |
4927 | "result %d\n", | |
4928 | __func__, HFC_cnt + 1, pt, ret_err); | |
4929 | ||
4930 | if (ret_err) { | |
4931 | while (pt) { /* release already registered ports */ | |
4932 | pt--; | |
4933 | release_port(hc, hc->chan[(pt << 2) + 2].dch); | |
4934 | } | |
4935 | goto free_card; | |
4936 | } | |
4937 | Port_cnt++; | |
4938 | } | |
4939 | ||
4940 | /* disp switches */ | |
4941 | switch (m->dip_type) { | |
4942 | case DIP_4S: | |
4943 | /* | |
4944 | * get DIP Setting for beroNet 1S/2S/4S cards | |
4945 | * check if Port Jumper config matches | |
4946 | * module param 'protocol' | |
4947 | * DIP Setting: (collect GPIO 13/14/15 (R_GPIO_IN1) + | |
4948 | * GPI 19/23 (R_GPI_IN2)) | |
4949 | */ | |
4950 | dips = ((~HFC_inb(hc, R_GPIO_IN1) & 0xE0) >> 5) | | |
4951 | ((~HFC_inb(hc, R_GPI_IN2) & 0x80) >> 3) | | |
4952 | (~HFC_inb(hc, R_GPI_IN2) & 0x08); | |
4953 | ||
4954 | /* Port mode (TE/NT) jumpers */ | |
4955 | pmj = ((HFC_inb(hc, R_GPI_IN3) >> 4) & 0xf); | |
4956 | ||
4957 | if (test_bit(HFC_CHIP_B410P, &hc->chip)) | |
4958 | pmj = ~pmj & 0xf; | |
4959 | ||
4960 | printk(KERN_INFO "%s: %s DIPs(0x%x) jumpers(0x%x)\n", | |
4961 | m->vendor_name, m->card_name, dips, pmj); | |
4962 | break; | |
4963 | case DIP_8S: | |
4964 | /* | |
4965 | * get DIP Setting for beroNet 8S0+ cards | |
4966 | * | |
4967 | * enable PCI auxbridge function | |
4968 | */ | |
4969 | HFC_outb(hc, R_BRG_PCM_CFG, 1 | V_PCM_CLK); | |
4970 | /* prepare access to auxport */ | |
4971 | outw(0x4000, hc->pci_iobase + 4); | |
4972 | /* | |
4973 | * some dummy reads are required to | |
4974 | * read valid DIP switch data | |
4975 | */ | |
4976 | dips = inb(hc->pci_iobase); | |
4977 | dips = inb(hc->pci_iobase); | |
4978 | dips = inb(hc->pci_iobase); | |
4979 | dips = ~inb(hc->pci_iobase) & 0x3F; | |
4980 | outw(0x0, hc->pci_iobase + 4); | |
4981 | /* disable PCI auxbridge function */ | |
4982 | HFC_outb(hc, R_BRG_PCM_CFG, V_PCM_CLK); | |
4983 | printk(KERN_INFO "%s: %s DIPs(0x%x)\n", | |
4984 | m->vendor_name, m->card_name, dips); | |
4985 | break; | |
4986 | case DIP_E1: | |
4987 | /* | |
4988 | * get DIP Setting for beroNet E1 cards | |
4989 | * DIP Setting: collect GPI 4/5/6/7 (R_GPI_IN0) | |
4990 | */ | |
4991 | dips = (~HFC_inb(hc, R_GPI_IN0) & 0xF0)>>4; | |
4992 | printk(KERN_INFO "%s: %s DIPs(0x%x)\n", | |
4993 | m->vendor_name, m->card_name, dips); | |
4994 | break; | |
4995 | } | |
4996 | ||
4997 | /* add to list */ | |
4998 | spin_lock_irqsave(&HFClock, flags); | |
4999 | list_add_tail(&hc->list, &HFClist); | |
5000 | spin_unlock_irqrestore(&HFClock, flags); | |
5001 | ||
5002 | /* initialize hardware */ | |
5003 | ret_err = init_card(hc); | |
5004 | if (ret_err) { | |
5005 | printk(KERN_ERR "init card returns %d\n", ret_err); | |
5006 | release_card(hc); | |
5007 | return ret_err; | |
5008 | } | |
5009 | ||
5010 | /* start IRQ and return */ | |
5011 | spin_lock_irqsave(&hc->lock, flags); | |
5012 | enable_hwirq(hc); | |
5013 | spin_unlock_irqrestore(&hc->lock, flags); | |
5014 | return 0; | |
5015 | ||
5016 | free_card: | |
5017 | release_io_hfcmulti(hc); | |
5018 | if (hc == syncmaster) | |
5019 | syncmaster = NULL; | |
5020 | kfree(hc); | |
5021 | return ret_err; | |
5022 | } | |
5023 | ||
5024 | static void __devexit hfc_remove_pci(struct pci_dev *pdev) | |
5025 | { | |
5026 | struct hfc_multi *card = pci_get_drvdata(pdev); | |
5027 | u_long flags; | |
5028 | ||
5029 | if (debug) | |
5030 | printk(KERN_INFO "removing hfc_multi card vendor:%x " | |
5031 | "device:%x subvendor:%x subdevice:%x\n", | |
5032 | pdev->vendor, pdev->device, | |
5033 | pdev->subsystem_vendor, pdev->subsystem_device); | |
5034 | ||
5035 | if (card) { | |
5036 | spin_lock_irqsave(&HFClock, flags); | |
5037 | release_card(card); | |
5038 | spin_unlock_irqrestore(&HFClock, flags); | |
5039 | } else { | |
5040 | if (debug) | |
5041 | printk(KERN_WARNING "%s: drvdata allready removed\n", | |
5042 | __func__); | |
5043 | } | |
5044 | } | |
5045 | ||
5046 | #define VENDOR_CCD "Cologne Chip AG" | |
5047 | #define VENDOR_BN "beroNet GmbH" | |
5048 | #define VENDOR_DIG "Digium Inc." | |
5049 | #define VENDOR_JH "Junghanns.NET GmbH" | |
5050 | #define VENDOR_PRIM "PrimuX" | |
5051 | ||
5052 | static const struct hm_map hfcm_map[] = { | |
5053 | /*0*/ {VENDOR_BN, "HFC-1S Card (mini PCI)", 4, 1, 1, 3, 0, DIP_4S, 0}, | |
31981db0 | 5054 | /*1*/ {VENDOR_BN, "HFC-2S Card", 4, 2, 1, 3, 0, DIP_4S, 0}, |
af69fb3a KK |
5055 | /*2*/ {VENDOR_BN, "HFC-2S Card (mini PCI)", 4, 2, 1, 3, 0, DIP_4S, 0}, |
5056 | /*3*/ {VENDOR_BN, "HFC-4S Card", 4, 4, 1, 2, 0, DIP_4S, 0}, | |
5057 | /*4*/ {VENDOR_BN, "HFC-4S Card (mini PCI)", 4, 4, 1, 2, 0, 0, 0}, | |
5058 | /*5*/ {VENDOR_CCD, "HFC-4S Eval (old)", 4, 4, 0, 0, 0, 0, 0}, | |
31981db0 | 5059 | /*6*/ {VENDOR_CCD, "HFC-4S IOB4ST", 4, 4, 1, 2, 0, DIP_4S, 0}, |
af69fb3a KK |
5060 | /*7*/ {VENDOR_CCD, "HFC-4S", 4, 4, 1, 2, 0, 0, 0}, |
5061 | /*8*/ {VENDOR_DIG, "HFC-4S Card", 4, 4, 0, 2, 0, 0, HFC_IO_MODE_REGIO}, | |
5062 | /*9*/ {VENDOR_CCD, "HFC-4S Swyx 4xS0 SX2 QuadBri", 4, 4, 1, 2, 0, 0, 0}, | |
5063 | /*10*/ {VENDOR_JH, "HFC-4S (junghanns 2.0)", 4, 4, 1, 2, 0, 0, 0}, | |
5064 | /*11*/ {VENDOR_PRIM, "HFC-2S Primux Card", 4, 2, 0, 0, 0, 0, 0}, | |
5065 | ||
5066 | /*12*/ {VENDOR_BN, "HFC-8S Card", 8, 8, 1, 0, 0, 0, 0}, | |
5067 | /*13*/ {VENDOR_BN, "HFC-8S Card (+)", 8, 8, 1, 8, 0, DIP_8S, | |
5068 | HFC_IO_MODE_REGIO}, | |
5069 | /*14*/ {VENDOR_CCD, "HFC-8S Eval (old)", 8, 8, 0, 0, 0, 0, 0}, | |
5070 | /*15*/ {VENDOR_CCD, "HFC-8S IOB4ST Recording", 8, 8, 1, 0, 0, 0, 0}, | |
5071 | ||
5072 | /*16*/ {VENDOR_CCD, "HFC-8S IOB8ST", 8, 8, 1, 0, 0, 0, 0}, | |
5073 | /*17*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0}, | |
5074 | /*18*/ {VENDOR_CCD, "HFC-8S", 8, 8, 1, 0, 0, 0, 0}, | |
5075 | ||
5076 | /*19*/ {VENDOR_BN, "HFC-E1 Card", 1, 1, 0, 1, 0, DIP_E1, 0}, | |
5077 | /*20*/ {VENDOR_BN, "HFC-E1 Card (mini PCI)", 1, 1, 0, 1, 0, 0, 0}, | |
5078 | /*21*/ {VENDOR_BN, "HFC-E1+ Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0}, | |
5079 | /*22*/ {VENDOR_BN, "HFC-E1 Card (Dual)", 1, 1, 0, 1, 0, DIP_E1, 0}, | |
5080 | ||
5081 | /*23*/ {VENDOR_CCD, "HFC-E1 Eval (old)", 1, 1, 0, 0, 0, 0, 0}, | |
5082 | /*24*/ {VENDOR_CCD, "HFC-E1 IOB1E1", 1, 1, 0, 1, 0, 0, 0}, | |
5083 | /*25*/ {VENDOR_CCD, "HFC-E1", 1, 1, 0, 1, 0, 0, 0}, | |
5084 | ||
5085 | /*26*/ {VENDOR_CCD, "HFC-4S Speech Design", 4, 4, 0, 0, 0, 0, | |
5086 | HFC_IO_MODE_PLXSD}, | |
5087 | /*27*/ {VENDOR_CCD, "HFC-E1 Speech Design", 1, 1, 0, 0, 0, 0, | |
5088 | HFC_IO_MODE_PLXSD}, | |
5089 | /*28*/ {VENDOR_CCD, "HFC-4S OpenVox", 4, 4, 1, 0, 0, 0, 0}, | |
5090 | /*29*/ {VENDOR_CCD, "HFC-2S OpenVox", 4, 2, 1, 0, 0, 0, 0}, | |
5091 | /*30*/ {VENDOR_CCD, "HFC-8S OpenVox", 8, 8, 1, 0, 0, 0, 0}, | |
5092 | }; | |
5093 | ||
5094 | #undef H | |
5095 | #define H(x) ((unsigned long)&hfcm_map[x]) | |
5096 | static struct pci_device_id hfmultipci_ids[] __devinitdata = { | |
5097 | ||
5098 | /* Cards with HFC-4S Chip */ | |
5099 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5100 | PCI_SUBDEVICE_ID_CCD_BN1SM, 0, 0, H(0)}, /* BN1S mini PCI */ | |
5101 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5102 | PCI_SUBDEVICE_ID_CCD_BN2S, 0, 0, H(1)}, /* BN2S */ | |
5103 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5104 | PCI_SUBDEVICE_ID_CCD_BN2SM, 0, 0, H(2)}, /* BN2S mini PCI */ | |
5105 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5106 | PCI_SUBDEVICE_ID_CCD_BN4S, 0, 0, H(3)}, /* BN4S */ | |
5107 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5108 | PCI_SUBDEVICE_ID_CCD_BN4SM, 0, 0, H(4)}, /* BN4S mini PCI */ | |
5109 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5110 | PCI_DEVICE_ID_CCD_HFC4S, 0, 0, H(5)}, /* Old Eval */ | |
5111 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5112 | PCI_SUBDEVICE_ID_CCD_IOB4ST, 0, 0, H(6)}, /* IOB4ST */ | |
5113 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5114 | PCI_SUBDEVICE_ID_CCD_HFC4S, 0, 0, H(7)}, /* 4S */ | |
5115 | { PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, | |
5116 | PCI_VENDOR_ID_DIGIUM, PCI_DEVICE_ID_DIGIUM_HFC4S, 0, 0, H(8)}, | |
5117 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5118 | PCI_SUBDEVICE_ID_CCD_SWYX4S, 0, 0, H(9)}, /* 4S Swyx */ | |
5119 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5120 | PCI_SUBDEVICE_ID_CCD_JH4S20, 0, 0, H(10)}, | |
5121 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5122 | PCI_SUBDEVICE_ID_CCD_PMX2S, 0, 0, H(11)}, /* Primux */ | |
5123 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5124 | PCI_SUBDEVICE_ID_CCD_OV4S, 0, 0, H(28)}, /* OpenVox 4 */ | |
5125 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_VENDOR_ID_CCD, | |
5126 | PCI_SUBDEVICE_ID_CCD_OV2S, 0, 0, H(29)}, /* OpenVox 2 */ | |
5127 | ||
5128 | /* Cards with HFC-8S Chip */ | |
5129 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5130 | PCI_SUBDEVICE_ID_CCD_BN8S, 0, 0, H(12)}, /* BN8S */ | |
5131 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5132 | PCI_SUBDEVICE_ID_CCD_BN8SP, 0, 0, H(13)}, /* BN8S+ */ | |
5133 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5134 | PCI_DEVICE_ID_CCD_HFC8S, 0, 0, H(14)}, /* old Eval */ | |
5135 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5136 | PCI_SUBDEVICE_ID_CCD_IOB8STR, 0, 0, H(15)}, | |
5137 | /* IOB8ST Recording */ | |
5138 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5139 | PCI_SUBDEVICE_ID_CCD_IOB8ST, 0, 0, H(16)}, /* IOB8ST */ | |
5140 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5141 | PCI_SUBDEVICE_ID_CCD_IOB8ST_1, 0, 0, H(17)}, /* IOB8ST */ | |
5142 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5143 | PCI_SUBDEVICE_ID_CCD_HFC8S, 0, 0, H(18)}, /* 8S */ | |
5144 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_VENDOR_ID_CCD, | |
5145 | PCI_SUBDEVICE_ID_CCD_OV8S, 0, 0, H(30)}, /* OpenVox 8 */ | |
5146 | ||
5147 | ||
5148 | /* Cards with HFC-E1 Chip */ | |
5149 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5150 | PCI_SUBDEVICE_ID_CCD_BNE1, 0, 0, H(19)}, /* BNE1 */ | |
5151 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5152 | PCI_SUBDEVICE_ID_CCD_BNE1M, 0, 0, H(20)}, /* BNE1 mini PCI */ | |
5153 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5154 | PCI_SUBDEVICE_ID_CCD_BNE1DP, 0, 0, H(21)}, /* BNE1 + (Dual) */ | |
5155 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5156 | PCI_SUBDEVICE_ID_CCD_BNE1D, 0, 0, H(22)}, /* BNE1 (Dual) */ | |
5157 | ||
5158 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5159 | PCI_DEVICE_ID_CCD_HFCE1, 0, 0, H(23)}, /* Old Eval */ | |
5160 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5161 | PCI_SUBDEVICE_ID_CCD_IOB1E1, 0, 0, H(24)}, /* IOB1E1 */ | |
5162 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_VENDOR_ID_CCD, | |
5163 | PCI_SUBDEVICE_ID_CCD_HFCE1, 0, 0, H(25)}, /* E1 */ | |
5164 | ||
5165 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, | |
5166 | PCI_SUBDEVICE_ID_CCD_SPD4S, 0, 0, H(26)}, /* PLX PCI Bridge */ | |
5167 | { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030, PCI_VENDOR_ID_CCD, | |
5168 | PCI_SUBDEVICE_ID_CCD_SPDE1, 0, 0, H(27)}, /* PLX PCI Bridge */ | |
5169 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC4S, PCI_ANY_ID, PCI_ANY_ID, | |
5170 | 0, 0, 0}, | |
5171 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFC8S, PCI_ANY_ID, PCI_ANY_ID, | |
5172 | 0, 0, 0}, | |
5173 | { PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_HFCE1, PCI_ANY_ID, PCI_ANY_ID, | |
5174 | 0, 0, 0}, | |
5175 | {0, } | |
5176 | }; | |
5177 | #undef H | |
5178 | ||
5179 | MODULE_DEVICE_TABLE(pci, hfmultipci_ids); | |
5180 | ||
5181 | static int | |
5182 | hfcmulti_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
5183 | { | |
5184 | struct hm_map *m = (struct hm_map *)ent->driver_data; | |
5185 | int ret; | |
5186 | ||
5187 | if (m == NULL) { | |
5188 | if (ent->vendor == PCI_VENDOR_ID_CCD) | |
5189 | if (ent->device == PCI_DEVICE_ID_CCD_HFC4S || | |
5190 | ent->device == PCI_DEVICE_ID_CCD_HFC8S || | |
5191 | ent->device == PCI_DEVICE_ID_CCD_HFCE1) | |
5192 | printk(KERN_ERR | |
5193 | "unknown HFC multiport controller " | |
5194 | "(vendor:%x device:%x subvendor:%x " | |
5195 | "subdevice:%x) Please contact the " | |
5196 | "driver maintainer for support.\n", | |
5197 | ent->vendor, ent->device, | |
5198 | ent->subvendor, ent->subdevice); | |
5199 | return -ENODEV; | |
5200 | } | |
5201 | ret = hfcmulti_init(pdev, ent); | |
5202 | if (ret) | |
5203 | return ret; | |
5204 | HFC_cnt++; | |
5205 | printk(KERN_INFO "%d devices registered\n", HFC_cnt); | |
5206 | return 0; | |
5207 | } | |
5208 | ||
5209 | static struct pci_driver hfcmultipci_driver = { | |
5210 | .name = "hfc_multi", | |
5211 | .probe = hfcmulti_probe, | |
5212 | .remove = __devexit_p(hfc_remove_pci), | |
5213 | .id_table = hfmultipci_ids, | |
5214 | }; | |
5215 | ||
5216 | static void __exit | |
5217 | HFCmulti_cleanup(void) | |
5218 | { | |
5219 | struct hfc_multi *card, *next; | |
5220 | ||
5221 | /* unload interrupt function symbol */ | |
5222 | if (hfc_interrupt) | |
5223 | symbol_put(ztdummy_extern_interrupt); | |
5224 | if (register_interrupt) | |
5225 | symbol_put(ztdummy_register_interrupt); | |
5226 | if (unregister_interrupt) { | |
5227 | if (interrupt_registered) { | |
5228 | interrupt_registered = 0; | |
5229 | unregister_interrupt(); | |
5230 | } | |
5231 | symbol_put(ztdummy_unregister_interrupt); | |
5232 | } | |
5233 | ||
5234 | list_for_each_entry_safe(card, next, &HFClist, list) | |
5235 | release_card(card); | |
5236 | /* get rid of all devices of this driver */ | |
5237 | pci_unregister_driver(&hfcmultipci_driver); | |
5238 | } | |
5239 | ||
5240 | static int __init | |
5241 | HFCmulti_init(void) | |
5242 | { | |
5243 | int err; | |
5244 | ||
5245 | #ifdef IRQ_DEBUG | |
5246 | printk(KERN_ERR "%s: IRQ_DEBUG IS ENABLED!\n", __func__); | |
5247 | #endif | |
5248 | ||
5249 | spin_lock_init(&HFClock); | |
5250 | spin_lock_init(&plx_lock); | |
5251 | ||
5252 | if (debug & DEBUG_HFCMULTI_INIT) | |
5253 | printk(KERN_DEBUG "%s: init entered\n", __func__); | |
5254 | ||
af69fb3a KK |
5255 | hfc_interrupt = symbol_get(ztdummy_extern_interrupt); |
5256 | register_interrupt = symbol_get(ztdummy_register_interrupt); | |
5257 | unregister_interrupt = symbol_get(ztdummy_unregister_interrupt); | |
5258 | printk(KERN_INFO "mISDN: HFC-multi driver %s\n", | |
5259 | hfcmulti_revision); | |
5260 | ||
5261 | switch (poll) { | |
5262 | case 0: | |
5263 | poll_timer = 6; | |
5264 | poll = 128; | |
5265 | break; | |
5266 | /* | |
5267 | * wenn dieses break nochmal verschwindet, | |
5268 | * gibt es heisse ohren :-) | |
5269 | * "without the break you will get hot ears ???" | |
5270 | */ | |
5271 | case 8: | |
5272 | poll_timer = 2; | |
5273 | break; | |
5274 | case 16: | |
5275 | poll_timer = 3; | |
5276 | break; | |
5277 | case 32: | |
5278 | poll_timer = 4; | |
5279 | break; | |
5280 | case 64: | |
5281 | poll_timer = 5; | |
5282 | break; | |
5283 | case 128: | |
5284 | poll_timer = 6; | |
5285 | break; | |
5286 | case 256: | |
5287 | poll_timer = 7; | |
5288 | break; | |
5289 | default: | |
5290 | printk(KERN_ERR | |
5291 | "%s: Wrong poll value (%d).\n", __func__, poll); | |
5292 | err = -EINVAL; | |
5293 | return err; | |
5294 | ||
5295 | } | |
5296 | ||
5297 | err = pci_register_driver(&hfcmultipci_driver); | |
5298 | if (err < 0) { | |
5299 | printk(KERN_ERR "error registering pci driver: %x\n", err); | |
5300 | if (hfc_interrupt) | |
5301 | symbol_put(ztdummy_extern_interrupt); | |
5302 | if (register_interrupt) | |
5303 | symbol_put(ztdummy_register_interrupt); | |
5304 | if (unregister_interrupt) { | |
5305 | if (interrupt_registered) { | |
5306 | interrupt_registered = 0; | |
5307 | unregister_interrupt(); | |
5308 | } | |
5309 | symbol_put(ztdummy_unregister_interrupt); | |
5310 | } | |
5311 | return err; | |
5312 | } | |
5313 | return 0; | |
5314 | } | |
5315 | ||
5316 | ||
5317 | module_init(HFCmulti_init); | |
5318 | module_exit(HFCmulti_cleanup); |