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mISDN: Add E-Channel logging features
[mirror_ubuntu-artful-kernel.git] / drivers / isdn / hardware / mISDN / hfcpci.c
CommitLineData
1700fe1a
KK		 1/*
2 *
3 * hfcpci.c low level driver for CCD's hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
8 *
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 */
27
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/mISDNhw.h>
32
33#include "hfc_pci.h"
34
35static const char *hfcpci_revision = "2.0";
36
1700fe1a
KK		 37static int HFC_cnt;
38static uint debug;
39
40MODULE_AUTHOR("Karsten Keil");
41MODULE_LICENSE("GPL");
42module_param(debug, uint, 0);
43
44static LIST_HEAD(HFClist);
1532dcb7 45static DEFINE_RWLOCK(HFClock);
1700fe1a
KK		 46
47enum {
48 HFC_CCD_2BD0,
49 HFC_CCD_B000,
50 HFC_CCD_B006,
51 HFC_CCD_B007,
52 HFC_CCD_B008,
53 HFC_CCD_B009,
54 HFC_CCD_B00A,
55 HFC_CCD_B00B,
56 HFC_CCD_B00C,
57 HFC_CCD_B100,
58 HFC_CCD_B700,
59 HFC_CCD_B701,
60 HFC_ASUS_0675,
61 HFC_BERKOM_A1T,
62 HFC_BERKOM_TCONCEPT,
63 HFC_ANIGMA_MC145575,
64 HFC_ZOLTRIX_2BD0,
65 HFC_DIGI_DF_M_IOM2_E,
66 HFC_DIGI_DF_M_E,
67 HFC_DIGI_DF_M_IOM2_A,
68 HFC_DIGI_DF_M_A,
69 HFC_ABOCOM_2BD1,
70 HFC_SITECOM_DC105V2,
71};
72
73struct hfcPCI_hw {
74 unsigned char cirm;
75 unsigned char ctmt;
76 unsigned char clkdel;
77 unsigned char states;
78 unsigned char conn;
79 unsigned char mst_m;
80 unsigned char int_m1;
81 unsigned char int_m2;
82 unsigned char sctrl;
83 unsigned char sctrl_r;
84 unsigned char sctrl_e;
85 unsigned char trm;
86 unsigned char fifo_en;
87 unsigned char bswapped;
88 unsigned char protocol;
89 int nt_timer;
1532dcb7 90 unsigned char __iomem *pci_io; /* start of PCI IO memory */
1700fe1a
KK		 91 dma_addr_t dmahandle;
92 void *fifos; /* FIFO memory */
93 int last_bfifo_cnt[2];
94 /* marker saving last b-fifo frame count */
95 struct timer_list timer;
96};
97
98#define HFC_CFG_MASTER 1
99#define HFC_CFG_SLAVE 2
100#define HFC_CFG_PCM 3
101#define HFC_CFG_2HFC 4
102#define HFC_CFG_SLAVEHFC 5
103#define HFC_CFG_NEG_F0 6
104#define HFC_CFG_SW_DD_DU 7
105
106#define FLG_HFC_TIMER_T1 16
107#define FLG_HFC_TIMER_T3 17
108
109#define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
110#define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
111#define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
112#define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
113
114
115struct hfc_pci {
116 struct list_head list;
117 u_char subtype;
118 u_char chanlimit;
119 u_char initdone;
120 u_long cfg;
121 u_int irq;
122 u_int irqcnt;
123 struct pci_dev *pdev;
124 struct hfcPCI_hw hw;
125 spinlock_t lock; /* card lock */
126 struct dchannel dch;
127 struct bchannel bch[2];
128};
129
130/* Interface functions */
131static void
132enable_hwirq(struct hfc_pci *hc)
133{
134 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
135 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
136}
137
138static void
139disable_hwirq(struct hfc_pci *hc)
140{
141 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
142 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
143}
144
145/*
146 * free hardware resources used by driver
147 */
148static void
149release_io_hfcpci(struct hfc_pci *hc)
150{
151 /* disable memory mapped ports + busmaster */
152 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
153 del_timer(&hc->hw.timer);
154 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
1532dcb7 155 iounmap(hc->hw.pci_io);
1700fe1a
KK		 156}
157
158/*
159 * set mode (NT or TE)
160 */
161static void
162hfcpci_setmode(struct hfc_pci *hc)
163{
164 if (hc->hw.protocol == ISDN_P_NT_S0) {
165 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
166 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
167 hc->hw.states = 1; /* G1 */
168 } else {
169 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
170 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
171 hc->hw.states = 2; /* F2 */
172 }
173 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
174 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
175 udelay(10);
176 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
177 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
178}
179
180/*
181 * function called to reset the HFC PCI chip. A complete software reset of chip
182 * and fifos is done.
183 */
184static void
185reset_hfcpci(struct hfc_pci *hc)
186{
187 u_char val;
188 int cnt = 0;
189
190 printk(KERN_DEBUG "reset_hfcpci: entered\n");
191 val = Read_hfc(hc, HFCPCI_CHIP_ID);
192 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
193 /* enable memory mapped ports, disable busmaster */
194 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
195 disable_hwirq(hc);
196 /* enable memory ports + busmaster */
197 pci_write_config_word(hc->pdev, PCI_COMMAND,
198 PCI_ENA_MEMIO + PCI_ENA_MASTER);
199 val = Read_hfc(hc, HFCPCI_STATUS);
200 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
201 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
202 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
203 set_current_state(TASK_UNINTERRUPTIBLE);
204 mdelay(10); /* Timeout 10ms */
205 hc->hw.cirm = 0; /* Reset Off */
206 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
207 val = Read_hfc(hc, HFCPCI_STATUS);
208 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
209 while (cnt < 50000) { /* max 50000 us */
210 udelay(5);
211 cnt += 5;
212 val = Read_hfc(hc, HFCPCI_STATUS);
213 if (!(val & 2))
214 break;
215 }
216 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
217
218 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
219
220 hc->hw.bswapped = 0; /* no exchange */
221 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
222 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
223 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
224 hc->hw.sctrl_r = 0;
225 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
226 hc->hw.mst_m = 0;
227 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
228 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
229 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
230 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
231 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
232 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
233 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
234 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
235
236 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
237 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
238 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
239
240 /* Clear already pending ints */
241 if (Read_hfc(hc, HFCPCI_INT_S1));
242
243 /* set NT/TE mode */
244 hfcpci_setmode(hc);
245
246 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
247 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
248
249 /*
250 * Init GCI/IOM2 in master mode
251 * Slots 0 and 1 are set for B-chan 1 and 2
252 * D- and monitor/CI channel are not enabled
253 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
254 * STIO2 is used as data input, B1+B2 from IOM->ST
255 * ST B-channel send disabled -> continous 1s
256 * The IOM slots are always enabled
257 */
258 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
259 /* set data flow directions: connect B1,B2: HFC to/from PCM */
260 hc->hw.conn = 0x09;
261 } else {
262 hc->hw.conn = 0x36; /* set data flow directions */
263 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
264 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
265 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
266 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
267 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
268 } else {
269 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
270 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
271 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
272 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
273 }
274 }
275 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
276 val = Read_hfc(hc, HFCPCI_INT_S2);
277}
278
279/*
280 * Timer function called when kernel timer expires
281 */
282static void
283hfcpci_Timer(struct hfc_pci *hc)
284{
285 hc->hw.timer.expires = jiffies + 75;
286 /* WD RESET */
287/*
288 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
289 * add_timer(&hc->hw.timer);
290 */
291}
292
293
294/*
295 * select a b-channel entry matching and active
296 */
297static struct bchannel *
298Sel_BCS(struct hfc_pci *hc, int channel)
299{
300 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
301 (hc->bch[0].nr & channel))
302 return &hc->bch[0];
303 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
304 (hc->bch[1].nr & channel))
305 return &hc->bch[1];
306 else
307 return NULL;
308}
309
310/*
311 * clear the desired B-channel rx fifo
312 */
313static void
314hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
315{
316 u_char fifo_state;
317 struct bzfifo *bzr;
318
319 if (fifo) {
320 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
321 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
322 } else {
323 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
324 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
325 }
326 if (fifo_state)
327 hc->hw.fifo_en ^= fifo_state;
328 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
329 hc->hw.last_bfifo_cnt[fifo] = 0;
330 bzr->f1 = MAX_B_FRAMES;
331 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
332 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
333 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
334 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
335 if (fifo_state)
336 hc->hw.fifo_en |= fifo_state;
337 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
338}
339
340/*
341 * clear the desired B-channel tx fifo
342 */
343static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
344{
345 u_char fifo_state;
346 struct bzfifo *bzt;
347
348 if (fifo) {
349 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
350 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
351 } else {
352 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
353 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
354 }
355 if (fifo_state)
356 hc->hw.fifo_en ^= fifo_state;
357 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
358 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
359 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
360 "z1(%x) z2(%x) state(%x)\n",
361 fifo, bzt->f1, bzt->f2,
362 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
363 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
364 fifo_state);
365 bzt->f2 = MAX_B_FRAMES;
366 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
367 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
f11d32df 368 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
1700fe1a
KK		 369 if (fifo_state)
370 hc->hw.fifo_en |= fifo_state;
371 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
372 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
373 printk(KERN_DEBUG
374 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
375 fifo, bzt->f1, bzt->f2,
376 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
377 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
378}
379
380/*
381 * read a complete B-frame out of the buffer
382 */
383static void
384hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
385 u_char *bdata, int count)
386{
387 u_char *ptr, *ptr1, new_f2;
388 int total, maxlen, new_z2;
389 struct zt *zp;
390
391 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
392 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
393 zp = &bz->za[bz->f2]; /* point to Z-Regs */
394 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
395 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
396 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
397 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
398 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
399 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
400 if (bch->debug & DEBUG_HW)
401 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
402 "invalid length %d or crc\n", count);
403#ifdef ERROR_STATISTIC
404 bch->err_inv++;
405#endif
406 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
407 bz->f2 = new_f2; /* next buffer */
408 } else {
409 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
410 if (!bch->rx_skb) {
411 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
412 return;
413 }
414 total = count;
415 count -= 3;
416 ptr = skb_put(bch->rx_skb, count);
417
418 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
419 maxlen = count; /* complete transfer */
420 else
421 maxlen = B_FIFO_SIZE + B_SUB_VAL -
422 le16_to_cpu(zp->z2); /* maximum */
423
424 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
425 /* start of data */
426 memcpy(ptr, ptr1, maxlen); /* copy data */
427 count -= maxlen;
428
429 if (count) { /* rest remaining */
430 ptr += maxlen;
431 ptr1 = bdata; /* start of buffer */
432 memcpy(ptr, ptr1, count); /* rest */
433 }
434 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
435 bz->f2 = new_f2; /* next buffer */
436 recv_Bchannel(bch);
437 }
438}
439
440/*
441 * D-channel receive procedure
442 */
443static int
444receive_dmsg(struct hfc_pci *hc)
445{
446 struct dchannel *dch = &hc->dch;
447 int maxlen;
448 int rcnt, total;
449 int count = 5;
450 u_char *ptr, *ptr1;
451 struct dfifo *df;
452 struct zt *zp;
453
454 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
455 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
456 zp = &df->za[df->f2 & D_FREG_MASK];
457 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
458 if (rcnt < 0)
459 rcnt += D_FIFO_SIZE;
460 rcnt++;
461 if (dch->debug & DEBUG_HW_DCHANNEL)
462 printk(KERN_DEBUG
463 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
464 df->f1, df->f2,
465 le16_to_cpu(zp->z1),
466 le16_to_cpu(zp->z2),
467 rcnt);
468
469 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
470 (df->data[le16_to_cpu(zp->z1)])) {
471 if (dch->debug & DEBUG_HW)
472 printk(KERN_DEBUG
473 "empty_fifo hfcpci paket inv. len "
474 "%d or crc %d\n",
475 rcnt,
476 df->data[le16_to_cpu(zp->z1)]);
477#ifdef ERROR_STATISTIC
478 cs->err_rx++;
479#endif
480 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
481 (MAX_D_FRAMES + 1); /* next buffer */
482 df->za[df->f2 & D_FREG_MASK].z2 =
f11d32df 483 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) & (D_FIFO_SIZE - 1));
1700fe1a
KK		 484 } else {
485 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
486 if (!dch->rx_skb) {
487 printk(KERN_WARNING
488 "HFC-PCI: D receive out of memory\n");
489 break;
490 }
491 total = rcnt;
492 rcnt -= 3;
493 ptr = skb_put(dch->rx_skb, rcnt);
494
495 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
496 maxlen = rcnt; /* complete transfer */
497 else
498 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
499 /* maximum */
500
501 ptr1 = df->data + le16_to_cpu(zp->z2);
502 /* start of data */
503 memcpy(ptr, ptr1, maxlen); /* copy data */
504 rcnt -= maxlen;
505
506 if (rcnt) { /* rest remaining */
507 ptr += maxlen;
508 ptr1 = df->data; /* start of buffer */
509 memcpy(ptr, ptr1, rcnt); /* rest */
510 }
511 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
512 (MAX_D_FRAMES + 1); /* next buffer */
513 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
514 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
515 recv_Dchannel(dch);
516 }
517 }
518 return 1;
519}
520
521/*
522 * check for transparent receive data and read max one threshold size if avail
523 */
1532dcb7 524static int
1700fe1a
KK		 525hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *bz, u_char *bdata)
526{
f11d32df 527 __le16 *z1r, *z2r;
1700fe1a
KK		 528 int new_z2, fcnt, maxlen;
529 u_char *ptr, *ptr1;
530
531 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
532 z2r = z1r + 1;
533
534 fcnt = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
535 if (!fcnt)
536 return 0; /* no data avail */
537
538 if (fcnt <= 0)
539 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
540 if (fcnt > HFCPCI_BTRANS_THRESHOLD)
541 fcnt = HFCPCI_BTRANS_THRESHOLD; /* limit size */
542
543 new_z2 = le16_to_cpu(*z2r) + fcnt; /* new position in fifo */
544 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
545 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
546
547 bch->rx_skb = mI_alloc_skb(fcnt, GFP_ATOMIC);
548 if (bch->rx_skb) {
549 ptr = skb_put(bch->rx_skb, fcnt);
550 if (le16_to_cpu(*z2r) + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
551 maxlen = fcnt; /* complete transfer */
552 else
553 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
554 /* maximum */
555
556 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
557 /* start of data */
558 memcpy(ptr, ptr1, maxlen); /* copy data */
559 fcnt -= maxlen;
560
561 if (fcnt) { /* rest remaining */
562 ptr += maxlen;
563 ptr1 = bdata; /* start of buffer */
564 memcpy(ptr, ptr1, fcnt); /* rest */
565 }
566 recv_Bchannel(bch);
567 } else
568 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
569
570 *z2r = cpu_to_le16(new_z2); /* new position */
571 return 1;
572}
573
574/*
575 * B-channel main receive routine
576 */
1532dcb7 577static void
1700fe1a
KK		 578main_rec_hfcpci(struct bchannel *bch)
579{
580 struct hfc_pci *hc = bch->hw;
581 int rcnt, real_fifo;
582 int receive, count = 5;
583 struct bzfifo *bz;
584 u_char *bdata;
585 struct zt *zp;
586
587
588 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
589 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
590 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
591 real_fifo = 1;
592 } else {
593 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
594 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
595 real_fifo = 0;
596 }
597Begin:
598 count--;
599 if (bz->f1 != bz->f2) {
600 if (bch->debug & DEBUG_HW_BCHANNEL)
601 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
602 bch->nr, bz->f1, bz->f2);
603 zp = &bz->za[bz->f2];
604
605 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
606 if (rcnt < 0)
607 rcnt += B_FIFO_SIZE;
608 rcnt++;
609 if (bch->debug & DEBUG_HW_BCHANNEL)
610 printk(KERN_DEBUG
611 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
612 bch->nr, le16_to_cpu(zp->z1),
613 le16_to_cpu(zp->z2), rcnt);
614 hfcpci_empty_bfifo(bch, bz, bdata, rcnt);
615 rcnt = bz->f1 - bz->f2;
616 if (rcnt < 0)
617 rcnt += MAX_B_FRAMES + 1;
618 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
619 rcnt = 0;
620 hfcpci_clear_fifo_rx(hc, real_fifo);
621 }
622 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
623 if (rcnt > 1)
624 receive = 1;
625 else
626 receive = 0;
627 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags))
628 receive = hfcpci_empty_fifo_trans(bch, bz, bdata);
629 else
630 receive = 0;
631 if (count && receive)
632 goto Begin;
633
634}
635
636/*
637 * D-channel send routine
638 */
639static void
640hfcpci_fill_dfifo(struct hfc_pci *hc)
641{
642 struct dchannel *dch = &hc->dch;
643 int fcnt;
644 int count, new_z1, maxlen;
645 struct dfifo *df;
646 u_char *src, *dst, new_f1;
647
648 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
649 printk(KERN_DEBUG "%s\n", __func__);
650
651 if (!dch->tx_skb)
652 return;
653 count = dch->tx_skb->len - dch->tx_idx;
654 if (count <= 0)
655 return;
656 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
657
658 if (dch->debug & DEBUG_HW_DFIFO)
659 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
660 df->f1, df->f2,
661 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
662 fcnt = df->f1 - df->f2; /* frame count actually buffered */
663 if (fcnt < 0)
664 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
665 if (fcnt > (MAX_D_FRAMES - 1)) {
666 if (dch->debug & DEBUG_HW_DCHANNEL)
667 printk(KERN_DEBUG
668 "hfcpci_fill_Dfifo more as 14 frames\n");
669#ifdef ERROR_STATISTIC
670 cs->err_tx++;
671#endif
672 return;
673 }
674 /* now determine free bytes in FIFO buffer */
675 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
676 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
677 if (maxlen <= 0)
678 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
679
680 if (dch->debug & DEBUG_HW_DCHANNEL)
681 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
682 count, maxlen);
683 if (count > maxlen) {
684 if (dch->debug & DEBUG_HW_DCHANNEL)
685 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
686 return;
687 }
688 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
689 (D_FIFO_SIZE - 1);
690 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
691 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
692 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
693 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
694 /* end fifo */
695 if (maxlen > count)
696 maxlen = count; /* limit size */
697 memcpy(dst, src, maxlen); /* first copy */
698
699 count -= maxlen; /* remaining bytes */
700 if (count) {
701 dst = df->data; /* start of buffer */
702 src += maxlen; /* new position */
703 memcpy(dst, src, count);
704 }
705 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
706 /* for next buffer */
707 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
708 /* new pos actual buffer */
709 df->f1 = new_f1; /* next frame */
710 dch->tx_idx = dch->tx_skb->len;
711}
712
713/*
714 * B-channel send routine
715 */
716static void
717hfcpci_fill_fifo(struct bchannel *bch)
718{
719 struct hfc_pci *hc = bch->hw;
720 int maxlen, fcnt;
721 int count, new_z1;
722 struct bzfifo *bz;
723 u_char *bdata;
724 u_char new_f1, *src, *dst;
f11d32df 725 __le16 *z1t, *z2t;
1700fe1a
KK		 726
727 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
728 printk(KERN_DEBUG "%s\n", __func__);
729 if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
730 return;
731 count = bch->tx_skb->len - bch->tx_idx;
732 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
733 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
734 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
735 } else {
736 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
737 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
738 }
739
740 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
741 z1t = &bz->za[MAX_B_FRAMES].z1;
742 z2t = z1t + 1;
743 if (bch->debug & DEBUG_HW_BCHANNEL)
744 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
745 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
746 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
747 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
748 if (fcnt <= 0)
749 fcnt += B_FIFO_SIZE;
750 /* fcnt contains available bytes in fifo */
751 fcnt = B_FIFO_SIZE - fcnt;
752 /* remaining bytes to send (bytes in fifo) */
8dd2f36f
AE		 753
754 /* "fill fifo if empty" feature */
755 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
756 /* printk(KERN_DEBUG "%s: buffer empty, so we have "
757 "underrun\n", __func__); */
758 /* fill buffer, to prevent future underrun */
759 count = HFCPCI_FILLEMPTY;
760 new_z1 = le16_to_cpu(*z1t) + count;
761 /* new buffer Position */
762 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
763 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
764 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
765 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
766 /* end of fifo */
767 if (bch->debug & DEBUG_HW_BFIFO)
768 printk(KERN_DEBUG "hfcpci_FFt fillempty "
769 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
770 fcnt, maxlen, new_z1, dst);
771 fcnt += count;
772 if (maxlen > count)
773 maxlen = count; /* limit size */
774 memset(dst, 0x2a, maxlen); /* first copy */
775 count -= maxlen; /* remaining bytes */
776 if (count) {
777 dst = bdata; /* start of buffer */
778 memset(dst, 0x2a, count);
779 }
780 *z1t = cpu_to_le16(new_z1); /* now send data */
781 }
782
1700fe1a
KK		 783next_t_frame:
784 count = bch->tx_skb->len - bch->tx_idx;
785 /* maximum fill shall be HFCPCI_BTRANS_MAX */
786 if (count > HFCPCI_BTRANS_MAX - fcnt)
787 count = HFCPCI_BTRANS_MAX - fcnt;
788 if (count <= 0)
789 return;
790 /* data is suitable for fifo */
791 new_z1 = le16_to_cpu(*z1t) + count;
792 /* new buffer Position */
793 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
794 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
795 src = bch->tx_skb->data + bch->tx_idx;
796 /* source pointer */
797 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
798 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
799 /* end of fifo */
800 if (bch->debug & DEBUG_HW_BFIFO)
801 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
802 "maxl(%d) nz1(%x) dst(%p)\n",
803 fcnt, maxlen, new_z1, dst);
804 fcnt += count;
805 bch->tx_idx += count;
806 if (maxlen > count)
807 maxlen = count; /* limit size */
808 memcpy(dst, src, maxlen); /* first copy */
809 count -= maxlen; /* remaining bytes */
810 if (count) {
811 dst = bdata; /* start of buffer */
812 src += maxlen; /* new position */
813 memcpy(dst, src, count);
814 }
815 *z1t = cpu_to_le16(new_z1); /* now send data */
816 if (bch->tx_idx < bch->tx_skb->len)
817 return;
818 /* send confirm, on trans, free on hdlc. */
819 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
820 confirm_Bsend(bch);
821 dev_kfree_skb(bch->tx_skb);
822 if (get_next_bframe(bch))
823 goto next_t_frame;
824 return;
825 }
826 if (bch->debug & DEBUG_HW_BCHANNEL)
827 printk(KERN_DEBUG
828 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
829 __func__, bch->nr, bz->f1, bz->f2,
830 bz->za[bz->f1].z1);
831 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
832 if (fcnt < 0)
833 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
834 if (fcnt > (MAX_B_FRAMES - 1)) {
835 if (bch->debug & DEBUG_HW_BCHANNEL)
836 printk(KERN_DEBUG
837 "hfcpci_fill_Bfifo more as 14 frames\n");
838 return;
839 }
840 /* now determine free bytes in FIFO buffer */
841 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
842 le16_to_cpu(bz->za[bz->f1].z1) - 1;
843 if (maxlen <= 0)
844 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
845
846 if (bch->debug & DEBUG_HW_BCHANNEL)
847 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
848 bch->nr, count, maxlen);
849
850 if (maxlen < count) {
851 if (bch->debug & DEBUG_HW_BCHANNEL)
852 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
853 return;
854 }
855 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
856 /* new buffer Position */
857 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
858 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
859
860 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
861 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
862 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
863 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
864 /* end fifo */
865 if (maxlen > count)
866 maxlen = count; /* limit size */
867 memcpy(dst, src, maxlen); /* first copy */
868
869 count -= maxlen; /* remaining bytes */
870 if (count) {
871 dst = bdata; /* start of buffer */
872 src += maxlen; /* new position */
873 memcpy(dst, src, count);
874 }
875 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
876 bz->f1 = new_f1; /* next frame */
877 dev_kfree_skb(bch->tx_skb);
878 get_next_bframe(bch);
879}
880
881
882
883/*
884 * handle L1 state changes TE
885 */
886
887static void
888ph_state_te(struct dchannel *dch)
889{
890 if (dch->debug)
891 printk(KERN_DEBUG "%s: TE newstate %x\n",
892 __func__, dch->state);
893 switch (dch->state) {
894 case 0:
895 l1_event(dch->l1, HW_RESET_IND);
896 break;
897 case 3:
898 l1_event(dch->l1, HW_DEACT_IND);
899 break;
900 case 5:
901 case 8:
902 l1_event(dch->l1, ANYSIGNAL);
903 break;
904 case 6:
905 l1_event(dch->l1, INFO2);
906 break;
907 case 7:
908 l1_event(dch->l1, INFO4_P8);
909 break;
910 }
911}
912
913/*
914 * handle L1 state changes NT
915 */
916
917static void
918handle_nt_timer3(struct dchannel *dch) {
919 struct hfc_pci *hc = dch->hw;
920
921 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
922 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
923 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
924 hc->hw.nt_timer = 0;
925 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
926 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
927 hc->hw.mst_m |= HFCPCI_MASTER;
928 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
929 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
930 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
931}
932
933static void
934ph_state_nt(struct dchannel *dch)
935{
936 struct hfc_pci *hc = dch->hw;
937
938 if (dch->debug)
939 printk(KERN_DEBUG "%s: NT newstate %x\n",
940 __func__, dch->state);
941 switch (dch->state) {
942 case 2:
943 if (hc->hw.nt_timer < 0) {
944 hc->hw.nt_timer = 0;
945 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
946 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
947 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
948 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
949 /* Clear already pending ints */
950 if (Read_hfc(hc, HFCPCI_INT_S1));
951 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
952 udelay(10);
953 Write_hfc(hc, HFCPCI_STATES, 4);
954 dch->state = 4;
955 } else if (hc->hw.nt_timer == 0) {
956 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
957 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
958 hc->hw.nt_timer = NT_T1_COUNT;
959 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
960 hc->hw.ctmt |= HFCPCI_TIM3_125;
961 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
962 HFCPCI_CLTIMER);
963 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
964 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
965 /* allow G2 -> G3 transition */
966 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
967 } else {
968 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
969 }
970 break;
971 case 1:
972 hc->hw.nt_timer = 0;
973 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
974 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
975 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
976 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
977 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
978 hc->hw.mst_m &= ~HFCPCI_MASTER;
979 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
980 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
981 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
982 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
983 break;
984 case 4:
985 hc->hw.nt_timer = 0;
986 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
987 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
988 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
989 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
990 break;
991 case 3:
992 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
993 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
994 &dch->Flags)) {
995 handle_nt_timer3(dch);
996 break;
997 }
998 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
999 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1000 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1001 hc->hw.nt_timer = NT_T3_COUNT;
1002 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1003 hc->hw.ctmt |= HFCPCI_TIM3_125;
1004 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1005 HFCPCI_CLTIMER);
1006 }
1007 break;
1008 }
1009}
1010
1011static void
1012ph_state(struct dchannel *dch)
1013{
1014 struct hfc_pci *hc = dch->hw;
1015
1016 if (hc->hw.protocol == ISDN_P_NT_S0) {
1017 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1018 hc->hw.nt_timer < 0)
1019 handle_nt_timer3(dch);
1020 else
1021 ph_state_nt(dch);
1022 } else
1023 ph_state_te(dch);
1024}
1025
1026/*
1027 * Layer 1 callback function
1028 */
1029static int
1030hfc_l1callback(struct dchannel *dch, u_int cmd)
1031{
1032 struct hfc_pci *hc = dch->hw;
1033
1034 switch (cmd) {
1035 case INFO3_P8:
1036 case INFO3_P10:
1037 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1038 hc->hw.mst_m |= HFCPCI_MASTER;
1039 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1040 break;
1041 case HW_RESET_REQ:
1042 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1043 /* HFC ST 3 */
1044 udelay(6);
1045 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1046 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1047 hc->hw.mst_m |= HFCPCI_MASTER;
1048 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1049 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1050 HFCPCI_DO_ACTION);
1051 l1_event(dch->l1, HW_POWERUP_IND);
1052 break;
1053 case HW_DEACT_REQ:
1054 hc->hw.mst_m &= ~HFCPCI_MASTER;
1055 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1056 skb_queue_purge(&dch->squeue);
1057 if (dch->tx_skb) {
1058 dev_kfree_skb(dch->tx_skb);
1059 dch->tx_skb = NULL;
1060 }
1061 dch->tx_idx = 0;
1062 if (dch->rx_skb) {
1063 dev_kfree_skb(dch->rx_skb);
1064 dch->rx_skb = NULL;
1065 }
1066 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1067 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1068 del_timer(&dch->timer);
1069 break;
1070 case HW_POWERUP_REQ:
1071 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1072 break;
1073 case PH_ACTIVATE_IND:
1074 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1075 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1076 GFP_ATOMIC);
1077 break;
1078 case PH_DEACTIVATE_IND:
1079 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1080 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1081 GFP_ATOMIC);
1082 break;
1083 default:
1084 if (dch->debug & DEBUG_HW)
1085 printk(KERN_DEBUG "%s: unknown command %x\n",
1086 __func__, cmd);
1087 return -1;
1088 }
1089 return 0;
1090}
1091
1092/*
1093 * Interrupt handler
1094 */
1095static inline void
1096tx_birq(struct bchannel *bch)
1097{
1098 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1099 hfcpci_fill_fifo(bch);
1100 else {
1101 if (bch->tx_skb)
1102 dev_kfree_skb(bch->tx_skb);
1103 if (get_next_bframe(bch))
1104 hfcpci_fill_fifo(bch);
1105 }
1106}
1107
1108static inline void
1109tx_dirq(struct dchannel *dch)
1110{
1111 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1112 hfcpci_fill_dfifo(dch->hw);
1113 else {
1114 if (dch->tx_skb)
1115 dev_kfree_skb(dch->tx_skb);
1116 if (get_next_dframe(dch))
1117 hfcpci_fill_dfifo(dch->hw);
1118 }
1119}
1120
1121static irqreturn_t
1122hfcpci_int(int intno, void *dev_id)
1123{
1124 struct hfc_pci *hc = dev_id;
1125 u_char exval;
1126 struct bchannel *bch;
1127 u_char val, stat;
1128
1129 spin_lock(&hc->lock);
1130 if (!(hc->hw.int_m2 & 0x08)) {
1131 spin_unlock(&hc->lock);
1132 return IRQ_NONE; /* not initialised */
1133 }
1134 stat = Read_hfc(hc, HFCPCI_STATUS);
1135 if (HFCPCI_ANYINT & stat) {
1136 val = Read_hfc(hc, HFCPCI_INT_S1);
1137 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1138 printk(KERN_DEBUG
1139 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1140 } else {
1141 /* shared */
1142 spin_unlock(&hc->lock);
1143 return IRQ_NONE;
1144 }
1145 hc->irqcnt++;
1146
1147 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1148 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1149 val &= hc->hw.int_m1;
1150 if (val & 0x40) { /* state machine irq */
1151 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1152 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1153 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1154 hc->dch.state, exval);
1155 hc->dch.state = exval;
1156 schedule_event(&hc->dch, FLG_PHCHANGE);
1157 val &= ~0x40;
1158 }
1159 if (val & 0x80) { /* timer irq */
1160 if (hc->hw.protocol == ISDN_P_NT_S0) {
1161 if ((--hc->hw.nt_timer) < 0)
1162 schedule_event(&hc->dch, FLG_PHCHANGE);
1163 }
1164 val &= ~0x80;
1165 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1166 }
1167 if (val & 0x08) {
1168 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1169 if (bch)
1170 main_rec_hfcpci(bch);
1171 else if (hc->dch.debug)
1172 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1173 }
1174 if (val & 0x10) {
1175 bch = Sel_BCS(hc, 2);
1176 if (bch)
1177 main_rec_hfcpci(bch);
1178 else if (hc->dch.debug)
1179 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1180 }
1181 if (val & 0x01) {
1182 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1183 if (bch)
1184 tx_birq(bch);
1185 else if (hc->dch.debug)
1186 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1187 }
1188 if (val & 0x02) {
1189 bch = Sel_BCS(hc, 2);
1190 if (bch)
1191 tx_birq(bch);
1192 else if (hc->dch.debug)
1193 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1194 }
1195 if (val & 0x20)
1196 receive_dmsg(hc);
1197 if (val & 0x04) { /* dframe transmitted */
1198 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1199 del_timer(&hc->dch.timer);
1200 tx_dirq(&hc->dch);
1201 }
1202 spin_unlock(&hc->lock);
1203 return IRQ_HANDLED;
1204}
1205
1206/*
1207 * timer callback for D-chan busy resolution. Currently no function
1208 */
1209static void
1210hfcpci_dbusy_timer(struct hfc_pci *hc)
1211{
1212}
1213
1214/*
1215 * activate/deactivate hardware for selected channels and mode
1216 */
1217static int
1218mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1219{
1220 struct hfc_pci *hc = bch->hw;
1221 int fifo2;
1222 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1223
1224 if (bch->debug & DEBUG_HW_BCHANNEL)
1225 printk(KERN_DEBUG
1226 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1227 bch->state, protocol, bch->nr, bc);
1228
1229 fifo2 = bc;
1230 pcm_mode = (bc>>24) & 0xff;
1231 if (pcm_mode) { /* PCM SLOT USE */
1232 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1233 printk(KERN_WARNING
1234 "%s: pcm channel id without HFC_CFG_PCM\n",
1235 __func__);
1236 rx_slot = (bc>>8) & 0xff;
1237 tx_slot = (bc>>16) & 0xff;
1238 bc = bc & 0xff;
1239 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) &&
1240 (protocol > ISDN_P_NONE))
1241 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1242 __func__);
1243 if (hc->chanlimit > 1) {
1244 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1245 hc->hw.sctrl_e &= ~0x80;
1246 } else {
1247 if (bc & 2) {
1248 if (protocol != ISDN_P_NONE) {
1249 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1250 hc->hw.sctrl_e |= 0x80;
1251 } else {
1252 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1253 hc->hw.sctrl_e &= ~0x80;
1254 }
1255 fifo2 = 1;
1256 } else {
1257 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1258 hc->hw.sctrl_e &= ~0x80;
1259 }
1260 }
1261 switch (protocol) {
1262 case (-1): /* used for init */
1263 bch->state = -1;
1264 bch->nr = bc;
1265 case (ISDN_P_NONE):
1266 if (bch->state == ISDN_P_NONE)
1267 return 0;
1268 if (bc & 2) {
1269 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1270 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1271 } else {
1272 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1273 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1274 }
1275 if (fifo2 & 2) {
1276 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1277 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1278 HFCPCI_INTS_B2REC);
1279 } else {
1280 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1281 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1282 HFCPCI_INTS_B1REC);
1283 }
1284#ifdef REVERSE_BITORDER
1285 if (bch->nr & 2)
1286 hc->hw.cirm &= 0x7f;
1287 else
1288 hc->hw.cirm &= 0xbf;
1289#endif
1290 bch->state = ISDN_P_NONE;
1291 bch->nr = bc;
1292 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1293 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1294 break;
1295 case (ISDN_P_B_RAW):
1296 bch->state = protocol;
1297 bch->nr = bc;
1298 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1299 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1300 if (bc & 2) {
1301 hc->hw.sctrl |= SCTRL_B2_ENA;
1302 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1303#ifdef REVERSE_BITORDER
1304 hc->hw.cirm |= 0x80;
1305#endif
1306 } else {
1307 hc->hw.sctrl |= SCTRL_B1_ENA;
1308 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1309#ifdef REVERSE_BITORDER
1310 hc->hw.cirm |= 0x40;
1311#endif
1312 }
1313 if (fifo2 & 2) {
1314 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1315 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1316 HFCPCI_INTS_B2REC);
1317 hc->hw.ctmt |= 2;
1318 hc->hw.conn &= ~0x18;
1319 } else {
1320 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1321 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1322 HFCPCI_INTS_B1REC);
1323 hc->hw.ctmt |= 1;
1324 hc->hw.conn &= ~0x03;
1325 }
1326 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1327 break;
1328 case (ISDN_P_B_HDLC):
1329 bch->state = protocol;
1330 bch->nr = bc;
1331 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1332 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1333 if (bc & 2) {
1334 hc->hw.sctrl |= SCTRL_B2_ENA;
1335 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1336 } else {
1337 hc->hw.sctrl |= SCTRL_B1_ENA;
1338 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1339 }
1340 if (fifo2 & 2) {
1341 hc->hw.last_bfifo_cnt[1] = 0;
1342 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1343 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1344 HFCPCI_INTS_B2REC);
1345 hc->hw.ctmt &= ~2;
1346 hc->hw.conn &= ~0x18;
1347 } else {
1348 hc->hw.last_bfifo_cnt[0] = 0;
1349 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1350 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1351 HFCPCI_INTS_B1REC);
1352 hc->hw.ctmt &= ~1;
1353 hc->hw.conn &= ~0x03;
1354 }
1355 test_and_set_bit(FLG_HDLC, &bch->Flags);
1356 break;
1357 default:
1358 printk(KERN_DEBUG "prot not known %x\n", protocol);
1359 return -ENOPROTOOPT;
1360 }
1361 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1362 if ((protocol == ISDN_P_NONE) ||
1363 (protocol == -1)) { /* init case */
1364 rx_slot = 0;
1365 tx_slot = 0;
1366 } else {
1367 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1368 rx_slot |= 0xC0;
1369 tx_slot |= 0xC0;
1370 } else {
1371 rx_slot |= 0x80;
1372 tx_slot |= 0x80;
1373 }
1374 }
1375 if (bc & 2) {
1376 hc->hw.conn &= 0xc7;
1377 hc->hw.conn |= 0x08;
1378 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1379 __func__, tx_slot);
1380 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1381 __func__, rx_slot);
1382 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1383 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1384 } else {
1385 hc->hw.conn &= 0xf8;
1386 hc->hw.conn |= 0x01;
1387 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1388 __func__, tx_slot);
1389 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1390 __func__, rx_slot);
1391 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1392 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1393 }
1394 }
1395 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1396 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1397 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1398 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1399 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1400 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1401 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1402#ifdef REVERSE_BITORDER
1403 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1404#endif
1405 return 0;
1406}
1407
1408static int
1409set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1410{
1411 struct hfc_pci *hc = bch->hw;
1412
1413 if (bch->debug & DEBUG_HW_BCHANNEL)
1414 printk(KERN_DEBUG
1415 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1416 bch->state, protocol, bch->nr, chan);
1417 if (bch->nr != chan) {
1418 printk(KERN_DEBUG
1419 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1420 bch->nr, chan);
1421 return -EINVAL;
1422 }
1423 switch (protocol) {
1424 case (ISDN_P_B_RAW):
1425 bch->state = protocol;
1426 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1427 if (chan & 2) {
1428 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1429 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1430 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1431 hc->hw.ctmt |= 2;
1432 hc->hw.conn &= ~0x18;
1433#ifdef REVERSE_BITORDER
1434 hc->hw.cirm |= 0x80;
1435#endif
1436 } else {
1437 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1438 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1439 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1440 hc->hw.ctmt |= 1;
1441 hc->hw.conn &= ~0x03;
1442#ifdef REVERSE_BITORDER
1443 hc->hw.cirm |= 0x40;
1444#endif
1445 }
1446 break;
1447 case (ISDN_P_B_HDLC):
1448 bch->state = protocol;
1449 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1450 if (chan & 2) {
1451 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1452 hc->hw.last_bfifo_cnt[1] = 0;
1453 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1454 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1455 hc->hw.ctmt &= ~2;
1456 hc->hw.conn &= ~0x18;
1457 } else {
1458 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1459 hc->hw.last_bfifo_cnt[0] = 0;
1460 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1461 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1462 hc->hw.ctmt &= ~1;
1463 hc->hw.conn &= ~0x03;
1464 }
1465 break;
1466 default:
1467 printk(KERN_DEBUG "prot not known %x\n", protocol);
1468 return -ENOPROTOOPT;
1469 }
1470 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1471 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1472 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1473 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1474 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1475#ifdef REVERSE_BITORDER
1476 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1477#endif
1478 return 0;
1479}
1480
1481static void
1482deactivate_bchannel(struct bchannel *bch)
1483{
1484 struct hfc_pci *hc = bch->hw;
1485 u_long flags;
1486
1487 spin_lock_irqsave(&hc->lock, flags);
1488 if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
1489 dev_kfree_skb(bch->next_skb);
1490 bch->next_skb = NULL;
1491 }
1492 if (bch->tx_skb) {
1493 dev_kfree_skb(bch->tx_skb);
1494 bch->tx_skb = NULL;
1495 }
1496 bch->tx_idx = 0;
1497 if (bch->rx_skb) {
1498 dev_kfree_skb(bch->rx_skb);
1499 bch->rx_skb = NULL;
1500 }
1501 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1502 test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
1503 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
1504 spin_unlock_irqrestore(&hc->lock, flags);
1505}
1506
1507/*
1508 * Layer 1 B-channel hardware access
1509 */
1510static int
1511channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1512{
8dd2f36f 1513 int ret = 0;
1700fe1a
KK		 1514
1515 switch (cq->op) {
1516 case MISDN_CTRL_GETOP:
8dd2f36f
AE		 1517 cq->op = MISDN_CTRL_FILL_EMPTY;
1518 break;
1519 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1520 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1521 if (debug & DEBUG_HW_OPEN)
1522 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1523 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1700fe1a
KK		 1524 break;
1525 default:
1526 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1527 ret = -EINVAL;
1528 break;
1529 }
1530 return ret;
1531}
1532static int
1533hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1534{
1535 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1536 struct hfc_pci *hc = bch->hw;
1537 int ret = -EINVAL;
1538 u_long flags;
1539
1540 if (bch->debug & DEBUG_HW)
1541 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1542 switch (cmd) {
1543 case HW_TESTRX_RAW:
1544 spin_lock_irqsave(&hc->lock, flags);
1545 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1546 spin_unlock_irqrestore(&hc->lock, flags);
1547 break;
1548 case HW_TESTRX_HDLC:
1549 spin_lock_irqsave(&hc->lock, flags);
1550 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1551 spin_unlock_irqrestore(&hc->lock, flags);
1552 break;
1553 case HW_TESTRX_OFF:
1554 spin_lock_irqsave(&hc->lock, flags);
1555 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1556 spin_unlock_irqrestore(&hc->lock, flags);
1557 ret = 0;
1558 break;
1559 case CLOSE_CHANNEL:
1560 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1561 if (test_bit(FLG_ACTIVE, &bch->Flags))
1562 deactivate_bchannel(bch);
1563 ch->protocol = ISDN_P_NONE;
1564 ch->peer = NULL;
1565 module_put(THIS_MODULE);
1566 ret = 0;
1567 break;
1568 case CONTROL_CHANNEL:
1569 ret = channel_bctrl(bch, arg);
1570 break;
1571 default:
1572 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1573 __func__, cmd);
1574 }
1575 return ret;
1576}
1577
1578/*
1579 * Layer2 -> Layer 1 Dchannel data
1580 */
1581static int
1582hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1583{
1584 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1585 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1586 struct hfc_pci *hc = dch->hw;
1587 int ret = -EINVAL;
1588 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1589 unsigned int id;
1590 u_long flags;
1591
1592 switch (hh->prim) {
1593 case PH_DATA_REQ:
1594 spin_lock_irqsave(&hc->lock, flags);
1595 ret = dchannel_senddata(dch, skb);
1596 if (ret > 0) { /* direct TX */
1597 id = hh->id; /* skb can be freed */
1598 hfcpci_fill_dfifo(dch->hw);
1599 ret = 0;
1600 spin_unlock_irqrestore(&hc->lock, flags);
1601 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1602 } else
1603 spin_unlock_irqrestore(&hc->lock, flags);
1604 return ret;
1605 case PH_ACTIVATE_REQ:
1606 spin_lock_irqsave(&hc->lock, flags);
1607 if (hc->hw.protocol == ISDN_P_NT_S0) {
1608 ret = 0;
1609 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1610 hc->hw.mst_m |= HFCPCI_MASTER;
1611 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1612 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1613 spin_unlock_irqrestore(&hc->lock, flags);
1614 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1615 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1616 break;
1617 }
1618 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1619 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1620 HFCPCI_DO_ACTION | 1);
1621 } else
1622 ret = l1_event(dch->l1, hh->prim);
1623 spin_unlock_irqrestore(&hc->lock, flags);
1624 break;
1625 case PH_DEACTIVATE_REQ:
1626 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1627 spin_lock_irqsave(&hc->lock, flags);
1628 if (hc->hw.protocol == ISDN_P_NT_S0) {
1629 /* prepare deactivation */
1630 Write_hfc(hc, HFCPCI_STATES, 0x40);
1631 skb_queue_purge(&dch->squeue);
1632 if (dch->tx_skb) {
1633 dev_kfree_skb(dch->tx_skb);
1634 dch->tx_skb = NULL;
1635 }
1636 dch->tx_idx = 0;
1637 if (dch->rx_skb) {
1638 dev_kfree_skb(dch->rx_skb);
1639 dch->rx_skb = NULL;
1640 }
1641 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1642 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1643 del_timer(&dch->timer);
1644#ifdef FIXME
1645 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1646 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1647#endif
1648 hc->hw.mst_m &= ~HFCPCI_MASTER;
1649 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1650 ret = 0;
1651 } else {
1652 ret = l1_event(dch->l1, hh->prim);
1653 }
1654 spin_unlock_irqrestore(&hc->lock, flags);
1655 break;
1656 }
1657 if (!ret)
1658 dev_kfree_skb(skb);
1659 return ret;
1660}
1661
1662/*
1663 * Layer2 -> Layer 1 Bchannel data
1664 */
1665static int
1666hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1667{
1668 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1669 struct hfc_pci *hc = bch->hw;
1670 int ret = -EINVAL;
1671 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1672 unsigned int id;
1673 u_long flags;
1674
1675 switch (hh->prim) {
1676 case PH_DATA_REQ:
1677 spin_lock_irqsave(&hc->lock, flags);
1678 ret = bchannel_senddata(bch, skb);
1679 if (ret > 0) { /* direct TX */
1680 id = hh->id; /* skb can be freed */
1681 hfcpci_fill_fifo(bch);
1682 ret = 0;
1683 spin_unlock_irqrestore(&hc->lock, flags);
1684 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1685 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1686 } else
1687 spin_unlock_irqrestore(&hc->lock, flags);
1688 return ret;
1689 case PH_ACTIVATE_REQ:
1690 spin_lock_irqsave(&hc->lock, flags);
1691 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1692 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1693 else
1694 ret = 0;
1695 spin_unlock_irqrestore(&hc->lock, flags);
1696 if (!ret)
1697 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1698 NULL, GFP_KERNEL);
1699 break;
1700 case PH_DEACTIVATE_REQ:
1701 deactivate_bchannel(bch);
1702 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1703 NULL, GFP_KERNEL);
1704 ret = 0;
1705 break;
1706 }
1707 if (!ret)
1708 dev_kfree_skb(skb);
1709 return ret;
1710}
1711
1712/*
1713 * called for card init message
1714 */
1715
1532dcb7 1716static void
1700fe1a
KK		 1717inithfcpci(struct hfc_pci *hc)
1718{
1719 printk(KERN_DEBUG "inithfcpci: entered\n");
1720 hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1721 hc->dch.timer.data = (long) &hc->dch;
1722 init_timer(&hc->dch.timer);
1723 hc->chanlimit = 2;
1724 mode_hfcpci(&hc->bch[0], 1, -1);
1725 mode_hfcpci(&hc->bch[1], 2, -1);
1726}
1727
1728
1729static int
1730init_card(struct hfc_pci *hc)
1731{
1732 int cnt = 3;
1733 u_long flags;
1734
1735 printk(KERN_DEBUG "init_card: entered\n");
1736
1737
1738 spin_lock_irqsave(&hc->lock, flags);
1739 disable_hwirq(hc);
1740 spin_unlock_irqrestore(&hc->lock, flags);
1741 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1742 printk(KERN_WARNING
1743 "mISDN: couldn't get interrupt %d\n", hc->irq);
1744 return -EIO;
1745 }
1746 spin_lock_irqsave(&hc->lock, flags);
1747 reset_hfcpci(hc);
1748 while (cnt) {
1749 inithfcpci(hc);
1750 /*
1751 * Finally enable IRQ output
1752 * this is only allowed, if an IRQ routine is allready
1753 * established for this HFC, so don't do that earlier
1754 */
1755 enable_hwirq(hc);
1756 spin_unlock_irqrestore(&hc->lock, flags);
1757 /* Timeout 80ms */
1758 current->state = TASK_UNINTERRUPTIBLE;
1759 schedule_timeout((80*HZ)/1000);
1760 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1761 hc->irq, hc->irqcnt);
1762 /* now switch timer interrupt off */
1763 spin_lock_irqsave(&hc->lock, flags);
1764 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1765 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1766 /* reinit mode reg */
1767 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1768 if (!hc->irqcnt) {
1769 printk(KERN_WARNING
1770 "HFC PCI: IRQ(%d) getting no interrupts "
1771 "during init %d\n", hc->irq, 4 - cnt);
1772 if (cnt == 1) {
1773 spin_unlock_irqrestore(&hc->lock, flags);
1774 return -EIO;
1775 } else {
1776 reset_hfcpci(hc);
1777 cnt--;
1778 }
1779 } else {
1780 spin_unlock_irqrestore(&hc->lock, flags);
1781 hc->initdone = 1;
1782 return 0;
1783 }
1784 }
1785 disable_hwirq(hc);
1786 spin_unlock_irqrestore(&hc->lock, flags);
1787 free_irq(hc->irq, hc);
1788 return -EIO;
1789}
1790
1791static int
1792channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1793{
1794 int ret = 0;
1795 u_char slot;
1796
1797 switch (cq->op) {
1798 case MISDN_CTRL_GETOP:
1799 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1800 MISDN_CTRL_DISCONNECT;
1801 break;
1802 case MISDN_CTRL_LOOP:
1803 /* channel 0 disabled loop */
1804 if (cq->channel < 0 || cq->channel > 2) {
1805 ret = -EINVAL;
1806 break;
1807 }
1808 if (cq->channel & 1) {
1809 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1810 slot = 0xC0;
1811 else
1812 slot = 0x80;
1813 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1814 __func__, slot);
1815 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1816 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1817 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1818 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1819 }
1820 if (cq->channel & 2) {
1821 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1822 slot = 0xC1;
1823 else
1824 slot = 0x81;
1825 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1826 __func__, slot);
1827 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1828 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1829 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1830 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1831 }
1832 if (cq->channel & 3)
1833 hc->hw.trm |= 0x80; /* enable IOM-loop */
1834 else {
1835 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1836 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1837 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1838 }
1839 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1840 break;
1841 case MISDN_CTRL_CONNECT:
1842 if (cq->channel == cq->p1) {
1843 ret = -EINVAL;
1844 break;
1845 }
1846 if (cq->channel < 1 || cq->channel > 2 ||
1847 cq->p1 < 1 || cq->p1 > 2) {
1848 ret = -EINVAL;
1849 break;
1850 }
1851 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1852 slot = 0xC0;
1853 else
1854 slot = 0x80;
1855 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1856 __func__, slot);
1857 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1858 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1859 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1860 slot = 0xC1;
1861 else
1862 slot = 0x81;
1863 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1864 __func__, slot);
1865 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1866 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1867 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1868 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1869 hc->hw.trm |= 0x80;
1870 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1871 break;
1872 case MISDN_CTRL_DISCONNECT:
1873 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1874 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1875 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1876 break;
1877 default:
1878 printk(KERN_WARNING "%s: unknown Op %x\n",
1879 __func__, cq->op);
1880 ret = -EINVAL;
1881 break;
1882 }
1883 return ret;
1884}
1885
1886static int
1887open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1888 struct channel_req *rq)
1889{
1890 int err = 0;
1891
1892 if (debug & DEBUG_HW_OPEN)
1893 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1894 hc->dch.dev.id, __builtin_return_address(0));
1895 if (rq->protocol == ISDN_P_NONE)
1896 return -EINVAL;
1897 if (!hc->initdone) {
1898 if (rq->protocol == ISDN_P_TE_S0) {
1899 err = create_l1(&hc->dch, hfc_l1callback);
1900 if (err)
1901 return err;
1902 }
1903 hc->hw.protocol = rq->protocol;
1904 ch->protocol = rq->protocol;
1905 err = init_card(hc);
1906 if (err)
1907 return err;
1908 } else {
1909 if (rq->protocol != ch->protocol) {
1910 if (hc->hw.protocol == ISDN_P_TE_S0)
1911 l1_event(hc->dch.l1, CLOSE_CHANNEL);
1912 hc->hw.protocol = rq->protocol;
1913 ch->protocol = rq->protocol;
1914 hfcpci_setmode(hc);
1915 }
1916 }
1917
1918 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1919 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1920 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1921 0, NULL, GFP_KERNEL);
1922 }
1923 rq->ch = ch;
1924 if (!try_module_get(THIS_MODULE))
1925 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1926 return 0;
1927}
1928
1929static int
1930open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1931{
1932 struct bchannel *bch;
1933
1934 if (rq->adr.channel > 2)
1935 return -EINVAL;
1936 if (rq->protocol == ISDN_P_NONE)
1937 return -EINVAL;
1938 bch = &hc->bch[rq->adr.channel - 1];
1939 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1940 return -EBUSY; /* b-channel can be only open once */
8dd2f36f 1941 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1700fe1a
KK		 1942 bch->ch.protocol = rq->protocol;
1943 rq->ch = &bch->ch; /* TODO: E-channel */
1944 if (!try_module_get(THIS_MODULE))
1945 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1946 return 0;
1947}
1948
1949/*
1950 * device control function
1951 */
1952static int
1953hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1954{
1955 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1956 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1957 struct hfc_pci *hc = dch->hw;
1958 struct channel_req *rq;
1959 int err = 0;
1960
1961 if (dch->debug & DEBUG_HW)
1962 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1963 __func__, cmd, arg);
1964 switch (cmd) {
1965 case OPEN_CHANNEL:
1966 rq = arg;
a9b61830
MB		 1967 if ((rq->protocol == ISDN_P_TE_S0) ||
1968 (rq->protocol == ISDN_P_NT_S0))
1700fe1a
KK		 1969 err = open_dchannel(hc, ch, rq);
1970 else
1971 err = open_bchannel(hc, rq);
1972 break;
1973 case CLOSE_CHANNEL:
1974 if (debug & DEBUG_HW_OPEN)
1975 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
1976 __func__, hc->dch.dev.id,
1977 __builtin_return_address(0));
1978 module_put(THIS_MODULE);
1979 break;
1980 case CONTROL_CHANNEL:
1981 err = channel_ctrl(hc, arg);
1982 break;
1983 default:
1984 if (dch->debug & DEBUG_HW)
1985 printk(KERN_DEBUG "%s: unknown command %x\n",
1986 __func__, cmd);
1987 return -EINVAL;
1988 }
1989 return err;
1990}
1991
1992static int
1993setup_hw(struct hfc_pci *hc)
1994{
1995 void *buffer;
1996
1997 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
1998 hc->hw.cirm = 0;
1999 hc->dch.state = 0;
2000 pci_set_master(hc->pdev);
2001 if (!hc->irq) {
2002 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2003 return 1;
2004 }
1532dcb7 2005 hc->hw.pci_io = (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
1700fe1a
KK		 2006
2007 if (!hc->hw.pci_io) {
2008 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2009 return 1;
2010 }
2011 /* Allocate memory for FIFOS */
2012 /* the memory needs to be on a 32k boundary within the first 4G */
2013 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2014 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2015 /* We silently assume the address is okay if nonzero */
2016 if (!buffer) {
2017 printk(KERN_WARNING
2018 "HFC-PCI: Error allocating memory for FIFO!\n");
2019 return 1;
2020 }
2021 hc->hw.fifos = buffer;
2022 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2023 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2024 printk(KERN_INFO
2025 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2026 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
7878ac81 2027 (u_long) hc->hw.dmahandle, hc->irq, HZ);
1700fe1a
KK		 2028 /* enable memory mapped ports, disable busmaster */
2029 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2030 hc->hw.int_m2 = 0;
2031 disable_hwirq(hc);
2032 hc->hw.int_m1 = 0;
2033 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2034 /* At this point the needed PCI config is done */
2035 /* fifos are still not enabled */
2036 hc->hw.timer.function = (void *) hfcpci_Timer;
2037 hc->hw.timer.data = (long) hc;
2038 init_timer(&hc->hw.timer);
2039 /* default PCM master */
2040 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2041 return 0;
2042}
2043
2044static void
2045release_card(struct hfc_pci *hc) {
2046 u_long flags;
2047
2048 spin_lock_irqsave(&hc->lock, flags);
2049 hc->hw.int_m2 = 0; /* interrupt output off ! */
2050 disable_hwirq(hc);
2051 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2052 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2053 if (hc->dch.timer.function != NULL) {
2054 del_timer(&hc->dch.timer);
2055 hc->dch.timer.function = NULL;
2056 }
2057 spin_unlock_irqrestore(&hc->lock, flags);
2058 if (hc->hw.protocol == ISDN_P_TE_S0)
2059 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2060 if (hc->initdone)
2061 free_irq(hc->irq, hc);
2062 release_io_hfcpci(hc); /* must release after free_irq! */
2063 mISDN_unregister_device(&hc->dch.dev);
2064 mISDN_freebchannel(&hc->bch[1]);
2065 mISDN_freebchannel(&hc->bch[0]);
2066 mISDN_freedchannel(&hc->dch);
2067 list_del(&hc->list);
2068 pci_set_drvdata(hc->pdev, NULL);
2069 kfree(hc);
2070}
2071
2072static int
2073setup_card(struct hfc_pci *card)
2074{
2075 int err = -EINVAL;
2076 u_int i;
2077 u_long flags;
2078 char name[MISDN_MAX_IDLEN];
2079
1700fe1a
KK		 2080 card->dch.debug = debug;
2081 spin_lock_init(&card->lock);
2082 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2083 card->dch.hw = card;
2084 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2085 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2086 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2087 card->dch.dev.D.send = hfcpci_l2l1D;
2088 card->dch.dev.D.ctrl = hfc_dctrl;
2089 card->dch.dev.nrbchan = 2;
2090 for (i = 0; i < 2; i++) {
2091 card->bch[i].nr = i + 1;
ff4cc1de 2092 set_channelmap(i + 1, card->dch.dev.channelmap);
1700fe1a
KK		 2093 card->bch[i].debug = debug;
2094 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2095 card->bch[i].hw = card;
2096 card->bch[i].ch.send = hfcpci_l2l1B;
2097 card->bch[i].ch.ctrl = hfc_bctrl;
2098 card->bch[i].ch.nr = i + 1;
2099 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2100 }
2101 err = setup_hw(card);
2102 if (err)
2103 goto error;
2104 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
2105 err = mISDN_register_device(&card->dch.dev, name);
2106 if (err)
2107 goto error;
2108 HFC_cnt++;
2109 write_lock_irqsave(&HFClock, flags);
2110 list_add_tail(&card->list, &HFClist);
2111 write_unlock_irqrestore(&HFClock, flags);
2112 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2113 return 0;
2114error:
2115 mISDN_freebchannel(&card->bch[1]);
2116 mISDN_freebchannel(&card->bch[0]);
2117 mISDN_freedchannel(&card->dch);
2118 kfree(card);
2119 return err;
2120}
2121
2122/* private data in the PCI devices list */
2123struct _hfc_map {
2124 u_int subtype;
2125 u_int flag;
2126 char *name;
2127};
2128
2129static const struct _hfc_map hfc_map[] =
2130{
2131 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2132 {HFC_CCD_B000, 0, "Billion B000"},
2133 {HFC_CCD_B006, 0, "Billion B006"},
2134 {HFC_CCD_B007, 0, "Billion B007"},
2135 {HFC_CCD_B008, 0, "Billion B008"},
2136 {HFC_CCD_B009, 0, "Billion B009"},
2137 {HFC_CCD_B00A, 0, "Billion B00A"},
2138 {HFC_CCD_B00B, 0, "Billion B00B"},
2139 {HFC_CCD_B00C, 0, "Billion B00C"},
2140 {HFC_CCD_B100, 0, "Seyeon B100"},
2141 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2142 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2143 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2144 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2145 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2146 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2147 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2148 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2149 {HFC_DIGI_DF_M_IOM2_E, 0,
2150 "Digi International DataFire Micro V IOM2 (Europe)"},
2151 {HFC_DIGI_DF_M_E, 0,
2152 "Digi International DataFire Micro V (Europe)"},
2153 {HFC_DIGI_DF_M_IOM2_A, 0,
2154 "Digi International DataFire Micro V IOM2 (North America)"},
2155 {HFC_DIGI_DF_M_A, 0,
2156 "Digi International DataFire Micro V (North America)"},
2157 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2158 {},
2159};
2160
2161static struct pci_device_id hfc_ids[] =
2162{
2163 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0,
2164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[0]},
2165 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000,
2166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[1]},
2167 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006,
2168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[2]},
2169 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[3]},
2171 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008,
2172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[4]},
2173 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009,
2174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[5]},
2175 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A,
2176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[6]},
2177 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B,
2178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[7]},
2179 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C,
2180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[8]},
2181 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100,
2182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[9]},
2183 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700,
2184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[10]},
2185 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701,
2186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[11]},
2187 {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1,
2188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[12]},
2189 {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675,
2190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[13]},
2191 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT,
2192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[14]},
2193 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T,
2194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[15]},
2195 {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575,
2196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[16]},
2197 {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0,
2198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[17]},
2199 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,
2200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[18]},
2201 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,
2202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[19]},
2203 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,
2204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[20]},
2205 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,
2206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[21]},
2207 {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2,
2208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[22]},
2209 {},
2210};
2211
2212static int __devinit
2213hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2214{
2215 int err = -ENOMEM;
2216 struct hfc_pci *card;
2217 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2218
2219 card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2220 if (!card) {
2221 printk(KERN_ERR "No kmem for HFC card\n");
2222 return err;
2223 }
2224 card->pdev = pdev;
2225 card->subtype = m->subtype;
2226 err = pci_enable_device(pdev);
2227 if (err) {
2228 kfree(card);
2229 return err;
2230 }
2231
2232 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2233 m->name, pci_name(pdev));
2234
2235 card->irq = pdev->irq;
2236 pci_set_drvdata(pdev, card);
2237 err = setup_card(card);
2238 if (err)
2239 pci_set_drvdata(pdev, NULL);
2240 return err;
2241}
2242
2243static void __devexit
2244hfc_remove_pci(struct pci_dev *pdev)
2245{
2246 struct hfc_pci *card = pci_get_drvdata(pdev);
2247 u_long flags;
2248
2249 if (card) {
2250 write_lock_irqsave(&HFClock, flags);
2251 release_card(card);
2252 write_unlock_irqrestore(&HFClock, flags);
2253 } else
2254 if (debug)
2255 printk(KERN_WARNING "%s: drvdata allready removed\n",
2256 __func__);
2257}
2258
2259
2260static struct pci_driver hfc_driver = {
2261 .name = "hfcpci",
2262 .probe = hfc_probe,
2263 .remove = __devexit_p(hfc_remove_pci),
2264 .id_table = hfc_ids,
2265};
2266
2267static int __init
2268HFC_init(void)
2269{
2270 int err;
2271
2272 err = pci_register_driver(&hfc_driver);
2273 return err;
2274}
2275
2276static void __exit
2277HFC_cleanup(void)
2278{
2279 struct hfc_pci *card, *next;
2280
2281 list_for_each_entry_safe(card, next, &HFClist, list) {
2282 release_card(card);
2283 }
2284 pci_unregister_driver(&hfc_driver);
2285}
2286
2287module_init(HFC_init);
2288module_exit(HFC_cleanup);
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