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1700fe1a
KK		 1/*
2 *
3 * hfcpci.c low level driver for CCD's hfc-pci based cards
4 *
5 * Author Werner Cornelius (werner@isdn4linux.de)
6 * based on existing driver for CCD hfc ISA cards
7 * type approval valid for HFC-S PCI A based card
8 *
9 * Copyright 1999 by Werner Cornelius (werner@isdn-development.de)
10 * Copyright 2008 by Karsten Keil <kkeil@novell.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
87c5fa1b
AE		 26 * Module options:
27 *
28 * debug:
29 * NOTE: only one poll value must be given for all cards
30 * See hfc_pci.h for debug flags.
31 *
32 * poll:
33 * NOTE: only one poll value must be given for all cards
34 * Give the number of samples for each fifo process.
35 * By default 128 is used. Decrease to reduce delay, increase to
36 * reduce cpu load. If unsure, don't mess with it!
37 * A value of 128 will use controller's interrupt. Other values will
38 * use kernel timer, because the controller will not allow lower values
39 * than 128.
40 * Also note that the value depends on the kernel timer frequency.
41 * If kernel uses a frequency of 1000 Hz, steps of 8 samples are possible.
42 * If the kernel uses 100 Hz, steps of 80 samples are possible.
43 * If the kernel uses 300 Hz, steps of about 26 samples are possible.
44 *
1700fe1a
KK		 45 */
46
47#include <linux/module.h>
48#include <linux/pci.h>
49#include <linux/delay.h>
50#include <linux/mISDNhw.h>
51
52#include "hfc_pci.h"
53
54static const char *hfcpci_revision = "2.0";
55
1700fe1a
KK		 56static int HFC_cnt;
57static uint debug;
87c5fa1b
AE		 58static uint poll, tics;
59struct timer_list hfc_tl;
60u32 hfc_jiffies;
1700fe1a
KK		 61
62MODULE_AUTHOR("Karsten Keil");
63MODULE_LICENSE("GPL");
9785a8f8 64module_param(debug, uint, S_IRUGO | S_IWUSR);
87c5fa1b 65module_param(poll, uint, S_IRUGO | S_IWUSR);
1700fe1a 66
1700fe1a
KK		 67enum {
68 HFC_CCD_2BD0,
69 HFC_CCD_B000,
70 HFC_CCD_B006,
71 HFC_CCD_B007,
72 HFC_CCD_B008,
73 HFC_CCD_B009,
74 HFC_CCD_B00A,
75 HFC_CCD_B00B,
76 HFC_CCD_B00C,
77 HFC_CCD_B100,
78 HFC_CCD_B700,
79 HFC_CCD_B701,
80 HFC_ASUS_0675,
81 HFC_BERKOM_A1T,
82 HFC_BERKOM_TCONCEPT,
83 HFC_ANIGMA_MC145575,
84 HFC_ZOLTRIX_2BD0,
85 HFC_DIGI_DF_M_IOM2_E,
86 HFC_DIGI_DF_M_E,
87 HFC_DIGI_DF_M_IOM2_A,
88 HFC_DIGI_DF_M_A,
89 HFC_ABOCOM_2BD1,
90 HFC_SITECOM_DC105V2,
91};
92
93struct hfcPCI_hw {
94 unsigned char cirm;
95 unsigned char ctmt;
96 unsigned char clkdel;
97 unsigned char states;
98 unsigned char conn;
99 unsigned char mst_m;
100 unsigned char int_m1;
101 unsigned char int_m2;
102 unsigned char sctrl;
103 unsigned char sctrl_r;
104 unsigned char sctrl_e;
105 unsigned char trm;
106 unsigned char fifo_en;
107 unsigned char bswapped;
108 unsigned char protocol;
109 int nt_timer;
1532dcb7 110 unsigned char __iomem *pci_io; /* start of PCI IO memory */
1700fe1a
KK		 111 dma_addr_t dmahandle;
112 void *fifos; /* FIFO memory */
113 int last_bfifo_cnt[2];
114 /* marker saving last b-fifo frame count */
115 struct timer_list timer;
116};
117
118#define HFC_CFG_MASTER 1
119#define HFC_CFG_SLAVE 2
120#define HFC_CFG_PCM 3
121#define HFC_CFG_2HFC 4
122#define HFC_CFG_SLAVEHFC 5
123#define HFC_CFG_NEG_F0 6
124#define HFC_CFG_SW_DD_DU 7
125
126#define FLG_HFC_TIMER_T1 16
127#define FLG_HFC_TIMER_T3 17
128
129#define NT_T1_COUNT 1120 /* number of 3.125ms interrupts (3.5s) */
130#define NT_T3_COUNT 31 /* number of 3.125ms interrupts (97 ms) */
131#define CLKDEL_TE 0x0e /* CLKDEL in TE mode */
132#define CLKDEL_NT 0x6c /* CLKDEL in NT mode */
133
134
135struct hfc_pci {
1700fe1a
KK		 136 u_char subtype;
137 u_char chanlimit;
138 u_char initdone;
139 u_long cfg;
140 u_int irq;
141 u_int irqcnt;
142 struct pci_dev *pdev;
143 struct hfcPCI_hw hw;
144 spinlock_t lock; /* card lock */
145 struct dchannel dch;
146 struct bchannel bch[2];
147};
148
149/* Interface functions */
150static void
151enable_hwirq(struct hfc_pci *hc)
152{
153 hc->hw.int_m2 |= HFCPCI_IRQ_ENABLE;
154 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
155}
156
157static void
158disable_hwirq(struct hfc_pci *hc)
159{
160 hc->hw.int_m2 &= ~((u_char)HFCPCI_IRQ_ENABLE);
161 Write_hfc(hc, HFCPCI_INT_M2, hc->hw.int_m2);
162}
163
164/*
165 * free hardware resources used by driver
166 */
167static void
168release_io_hfcpci(struct hfc_pci *hc)
169{
170 /* disable memory mapped ports + busmaster */
171 pci_write_config_word(hc->pdev, PCI_COMMAND, 0);
172 del_timer(&hc->hw.timer);
173 pci_free_consistent(hc->pdev, 0x8000, hc->hw.fifos, hc->hw.dmahandle);
1532dcb7 174 iounmap(hc->hw.pci_io);
1700fe1a
KK		 175}
176
177/*
178 * set mode (NT or TE)
179 */
180static void
181hfcpci_setmode(struct hfc_pci *hc)
182{
183 if (hc->hw.protocol == ISDN_P_NT_S0) {
184 hc->hw.clkdel = CLKDEL_NT; /* ST-Bit delay for NT-Mode */
185 hc->hw.sctrl |= SCTRL_MODE_NT; /* NT-MODE */
186 hc->hw.states = 1; /* G1 */
187 } else {
188 hc->hw.clkdel = CLKDEL_TE; /* ST-Bit delay for TE-Mode */
189 hc->hw.sctrl &= ~SCTRL_MODE_NT; /* TE-MODE */
190 hc->hw.states = 2; /* F2 */
191 }
192 Write_hfc(hc, HFCPCI_CLKDEL, hc->hw.clkdel);
193 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | hc->hw.states);
194 udelay(10);
195 Write_hfc(hc, HFCPCI_STATES, hc->hw.states | 0x40); /* Deactivate */
196 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
197}
198
199/*
200 * function called to reset the HFC PCI chip. A complete software reset of chip
201 * and fifos is done.
202 */
203static void
204reset_hfcpci(struct hfc_pci *hc)
205{
206 u_char val;
207 int cnt = 0;
208
209 printk(KERN_DEBUG "reset_hfcpci: entered\n");
210 val = Read_hfc(hc, HFCPCI_CHIP_ID);
211 printk(KERN_INFO "HFC_PCI: resetting HFC ChipId(%x)\n", val);
212 /* enable memory mapped ports, disable busmaster */
213 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
214 disable_hwirq(hc);
215 /* enable memory ports + busmaster */
216 pci_write_config_word(hc->pdev, PCI_COMMAND,
217 PCI_ENA_MEMIO + PCI_ENA_MASTER);
218 val = Read_hfc(hc, HFCPCI_STATUS);
219 printk(KERN_DEBUG "HFC-PCI status(%x) before reset\n", val);
220 hc->hw.cirm = HFCPCI_RESET; /* Reset On */
221 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
222 set_current_state(TASK_UNINTERRUPTIBLE);
223 mdelay(10); /* Timeout 10ms */
224 hc->hw.cirm = 0; /* Reset Off */
225 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
226 val = Read_hfc(hc, HFCPCI_STATUS);
227 printk(KERN_DEBUG "HFC-PCI status(%x) after reset\n", val);
228 while (cnt < 50000) { /* max 50000 us */
229 udelay(5);
230 cnt += 5;
231 val = Read_hfc(hc, HFCPCI_STATUS);
232 if (!(val & 2))
233 break;
234 }
235 printk(KERN_DEBUG "HFC-PCI status(%x) after %dus\n", val, cnt);
236
237 hc->hw.fifo_en = 0x30; /* only D fifos enabled */
238
239 hc->hw.bswapped = 0; /* no exchange */
240 hc->hw.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER;
241 hc->hw.trm = HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */
242 hc->hw.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */
243 hc->hw.sctrl_r = 0;
244 hc->hw.sctrl_e = HFCPCI_AUTO_AWAKE; /* S/T Auto awake */
245 hc->hw.mst_m = 0;
246 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
247 hc->hw.mst_m |= HFCPCI_MASTER; /* HFC Master Mode */
248 if (test_bit(HFC_CFG_NEG_F0, &hc->cfg))
249 hc->hw.mst_m |= HFCPCI_F0_NEGATIV;
250 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
251 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
252 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
253 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
254
255 hc->hw.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC |
256 HFCPCI_INTS_L1STATE | HFCPCI_INTS_TIMER;
257 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
258
259 /* Clear already pending ints */
260 if (Read_hfc(hc, HFCPCI_INT_S1));
261
262 /* set NT/TE mode */
263 hfcpci_setmode(hc);
264
265 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
266 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
267
268 /*
269 * Init GCI/IOM2 in master mode
270 * Slots 0 and 1 are set for B-chan 1 and 2
271 * D- and monitor/CI channel are not enabled
272 * STIO1 is used as output for data, B1+B2 from ST->IOM+HFC
273 * STIO2 is used as data input, B1+B2 from IOM->ST
274 * ST B-channel send disabled -> continous 1s
275 * The IOM slots are always enabled
276 */
277 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
278 /* set data flow directions: connect B1,B2: HFC to/from PCM */
279 hc->hw.conn = 0x09;
280 } else {
281 hc->hw.conn = 0x36; /* set data flow directions */
282 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
283 Write_hfc(hc, HFCPCI_B1_SSL, 0xC0);
284 Write_hfc(hc, HFCPCI_B2_SSL, 0xC1);
285 Write_hfc(hc, HFCPCI_B1_RSL, 0xC0);
286 Write_hfc(hc, HFCPCI_B2_RSL, 0xC1);
287 } else {
288 Write_hfc(hc, HFCPCI_B1_SSL, 0x80);
289 Write_hfc(hc, HFCPCI_B2_SSL, 0x81);
290 Write_hfc(hc, HFCPCI_B1_RSL, 0x80);
291 Write_hfc(hc, HFCPCI_B2_RSL, 0x81);
292 }
293 }
294 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
295 val = Read_hfc(hc, HFCPCI_INT_S2);
296}
297
298/*
299 * Timer function called when kernel timer expires
300 */
301static void
302hfcpci_Timer(struct hfc_pci *hc)
303{
304 hc->hw.timer.expires = jiffies + 75;
305 /* WD RESET */
306/*
307 * WriteReg(hc, HFCD_DATA, HFCD_CTMT, hc->hw.ctmt | 0x80);
308 * add_timer(&hc->hw.timer);
309 */
310}
311
312
313/*
314 * select a b-channel entry matching and active
315 */
316static struct bchannel *
317Sel_BCS(struct hfc_pci *hc, int channel)
318{
319 if (test_bit(FLG_ACTIVE, &hc->bch[0].Flags) &&
320 (hc->bch[0].nr & channel))
321 return &hc->bch[0];
322 else if (test_bit(FLG_ACTIVE, &hc->bch[1].Flags) &&
323 (hc->bch[1].nr & channel))
324 return &hc->bch[1];
325 else
326 return NULL;
327}
328
329/*
330 * clear the desired B-channel rx fifo
331 */
332static void
333hfcpci_clear_fifo_rx(struct hfc_pci *hc, int fifo)
334{
335 u_char fifo_state;
336 struct bzfifo *bzr;
337
338 if (fifo) {
339 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
340 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2RX;
341 } else {
342 bzr = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
343 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1RX;
344 }
345 if (fifo_state)
346 hc->hw.fifo_en ^= fifo_state;
347 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
348 hc->hw.last_bfifo_cnt[fifo] = 0;
349 bzr->f1 = MAX_B_FRAMES;
350 bzr->f2 = bzr->f1; /* init F pointers to remain constant */
351 bzr->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
352 bzr->za[MAX_B_FRAMES].z2 = cpu_to_le16(
353 le16_to_cpu(bzr->za[MAX_B_FRAMES].z1));
354 if (fifo_state)
355 hc->hw.fifo_en |= fifo_state;
356 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
357}
358
359/*
360 * clear the desired B-channel tx fifo
361 */
362static void hfcpci_clear_fifo_tx(struct hfc_pci *hc, int fifo)
363{
364 u_char fifo_state;
365 struct bzfifo *bzt;
366
367 if (fifo) {
368 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
369 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B2TX;
370 } else {
371 bzt = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
372 fifo_state = hc->hw.fifo_en & HFCPCI_FIFOEN_B1TX;
373 }
374 if (fifo_state)
375 hc->hw.fifo_en ^= fifo_state;
376 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
377 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
378 printk(KERN_DEBUG "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) "
379 "z1(%x) z2(%x) state(%x)\n",
380 fifo, bzt->f1, bzt->f2,
381 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
382 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2),
383 fifo_state);
384 bzt->f2 = MAX_B_FRAMES;
385 bzt->f1 = bzt->f2; /* init F pointers to remain constant */
386 bzt->za[MAX_B_FRAMES].z1 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 1);
f11d32df 387 bzt->za[MAX_B_FRAMES].z2 = cpu_to_le16(B_FIFO_SIZE + B_SUB_VAL - 2);
1700fe1a
KK		 388 if (fifo_state)
389 hc->hw.fifo_en |= fifo_state;
390 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
391 if (hc->bch[fifo].debug & DEBUG_HW_BCHANNEL)
392 printk(KERN_DEBUG
393 "hfcpci_clear_fifo_tx%d f1(%x) f2(%x) z1(%x) z2(%x)\n",
394 fifo, bzt->f1, bzt->f2,
395 le16_to_cpu(bzt->za[MAX_B_FRAMES].z1),
396 le16_to_cpu(bzt->za[MAX_B_FRAMES].z2));
397}
398
399/*
400 * read a complete B-frame out of the buffer
401 */
402static void
403hfcpci_empty_bfifo(struct bchannel *bch, struct bzfifo *bz,
404 u_char *bdata, int count)
405{
406 u_char *ptr, *ptr1, new_f2;
407 int total, maxlen, new_z2;
408 struct zt *zp;
409
410 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
411 printk(KERN_DEBUG "hfcpci_empty_fifo\n");
412 zp = &bz->za[bz->f2]; /* point to Z-Regs */
413 new_z2 = le16_to_cpu(zp->z2) + count; /* new position in fifo */
414 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
415 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
416 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES;
417 if ((count > MAX_DATA_SIZE + 3) || (count < 4) ||
418 (*(bdata + (le16_to_cpu(zp->z1) - B_SUB_VAL)))) {
419 if (bch->debug & DEBUG_HW)
420 printk(KERN_DEBUG "hfcpci_empty_fifo: incoming packet "
421 "invalid length %d or crc\n", count);
422#ifdef ERROR_STATISTIC
423 bch->err_inv++;
424#endif
425 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
426 bz->f2 = new_f2; /* next buffer */
427 } else {
428 bch->rx_skb = mI_alloc_skb(count - 3, GFP_ATOMIC);
429 if (!bch->rx_skb) {
430 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
431 return;
432 }
433 total = count;
434 count -= 3;
435 ptr = skb_put(bch->rx_skb, count);
436
437 if (le16_to_cpu(zp->z2) + count <= B_FIFO_SIZE + B_SUB_VAL)
438 maxlen = count; /* complete transfer */
439 else
440 maxlen = B_FIFO_SIZE + B_SUB_VAL -
441 le16_to_cpu(zp->z2); /* maximum */
442
443 ptr1 = bdata + (le16_to_cpu(zp->z2) - B_SUB_VAL);
444 /* start of data */
445 memcpy(ptr, ptr1, maxlen); /* copy data */
446 count -= maxlen;
447
448 if (count) { /* rest remaining */
449 ptr += maxlen;
450 ptr1 = bdata; /* start of buffer */
451 memcpy(ptr, ptr1, count); /* rest */
452 }
453 bz->za[new_f2].z2 = cpu_to_le16(new_z2);
454 bz->f2 = new_f2; /* next buffer */
455 recv_Bchannel(bch);
456 }
457}
458
459/*
460 * D-channel receive procedure
461 */
462static int
463receive_dmsg(struct hfc_pci *hc)
464{
465 struct dchannel *dch = &hc->dch;
466 int maxlen;
467 int rcnt, total;
468 int count = 5;
469 u_char *ptr, *ptr1;
470 struct dfifo *df;
471 struct zt *zp;
472
473 df = &((union fifo_area *)(hc->hw.fifos))->d_chan.d_rx;
474 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) {
475 zp = &df->za[df->f2 & D_FREG_MASK];
476 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
477 if (rcnt < 0)
478 rcnt += D_FIFO_SIZE;
479 rcnt++;
480 if (dch->debug & DEBUG_HW_DCHANNEL)
481 printk(KERN_DEBUG
482 "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)\n",
483 df->f1, df->f2,
484 le16_to_cpu(zp->z1),
485 le16_to_cpu(zp->z2),
486 rcnt);
487
488 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) ||
489 (df->data[le16_to_cpu(zp->z1)])) {
490 if (dch->debug & DEBUG_HW)
491 printk(KERN_DEBUG
492 "empty_fifo hfcpci paket inv. len "
493 "%d or crc %d\n",
494 rcnt,
495 df->data[le16_to_cpu(zp->z1)]);
496#ifdef ERROR_STATISTIC
497 cs->err_rx++;
498#endif
499 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
500 (MAX_D_FRAMES + 1); /* next buffer */
501 df->za[df->f2 & D_FREG_MASK].z2 =
f11d32df 502 cpu_to_le16((le16_to_cpu(zp->z2) + rcnt) & (D_FIFO_SIZE - 1));
1700fe1a
KK		 503 } else {
504 dch->rx_skb = mI_alloc_skb(rcnt - 3, GFP_ATOMIC);
505 if (!dch->rx_skb) {
506 printk(KERN_WARNING
507 "HFC-PCI: D receive out of memory\n");
508 break;
509 }
510 total = rcnt;
511 rcnt -= 3;
512 ptr = skb_put(dch->rx_skb, rcnt);
513
514 if (le16_to_cpu(zp->z2) + rcnt <= D_FIFO_SIZE)
515 maxlen = rcnt; /* complete transfer */
516 else
517 maxlen = D_FIFO_SIZE - le16_to_cpu(zp->z2);
518 /* maximum */
519
520 ptr1 = df->data + le16_to_cpu(zp->z2);
521 /* start of data */
522 memcpy(ptr, ptr1, maxlen); /* copy data */
523 rcnt -= maxlen;
524
525 if (rcnt) { /* rest remaining */
526 ptr += maxlen;
527 ptr1 = df->data; /* start of buffer */
528 memcpy(ptr, ptr1, rcnt); /* rest */
529 }
530 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) |
531 (MAX_D_FRAMES + 1); /* next buffer */
532 df->za[df->f2 & D_FREG_MASK].z2 = cpu_to_le16((
533 le16_to_cpu(zp->z2) + total) & (D_FIFO_SIZE - 1));
534 recv_Dchannel(dch);
535 }
536 }
537 return 1;
538}
539
540/*
87c5fa1b 541 * check for transparent receive data and read max one 'poll' size if avail
1700fe1a 542 */
87c5fa1b 543static void
1700fe1a
KK		 544hfcpci_empty_fifo_trans(struct bchannel *bch, struct bzfifo *bz, u_char *bdata)
545{
f11d32df 546 __le16 *z1r, *z2r;
1700fe1a
KK		 547 int new_z2, fcnt, maxlen;
548 u_char *ptr, *ptr1;
549
550 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */
551 z2r = z1r + 1;
552
553 fcnt = le16_to_cpu(*z1r) - le16_to_cpu(*z2r);
554 if (!fcnt)
87c5fa1b 555 return; /* no data avail */
1700fe1a
KK		 556
557 if (fcnt <= 0)
558 fcnt += B_FIFO_SIZE; /* bytes actually buffered */
1700fe1a
KK		 559 new_z2 = le16_to_cpu(*z2r) + fcnt; /* new position in fifo */
560 if (new_z2 >= (B_FIFO_SIZE + B_SUB_VAL))
561 new_z2 -= B_FIFO_SIZE; /* buffer wrap */
562
87c5fa1b
AE		 563 if (fcnt > MAX_DATA_SIZE) { /* flush, if oversized */
564 *z2r = cpu_to_le16(new_z2); /* new position */
565 return;
566 }
567
1700fe1a
KK		 568 bch->rx_skb = mI_alloc_skb(fcnt, GFP_ATOMIC);
569 if (bch->rx_skb) {
570 ptr = skb_put(bch->rx_skb, fcnt);
571 if (le16_to_cpu(*z2r) + fcnt <= B_FIFO_SIZE + B_SUB_VAL)
572 maxlen = fcnt; /* complete transfer */
573 else
574 maxlen = B_FIFO_SIZE + B_SUB_VAL - le16_to_cpu(*z2r);
575 /* maximum */
576
577 ptr1 = bdata + (le16_to_cpu(*z2r) - B_SUB_VAL);
578 /* start of data */
579 memcpy(ptr, ptr1, maxlen); /* copy data */
580 fcnt -= maxlen;
581
582 if (fcnt) { /* rest remaining */
583 ptr += maxlen;
584 ptr1 = bdata; /* start of buffer */
585 memcpy(ptr, ptr1, fcnt); /* rest */
586 }
587 recv_Bchannel(bch);
588 } else
589 printk(KERN_WARNING "HFCPCI: receive out of memory\n");
590
591 *z2r = cpu_to_le16(new_z2); /* new position */
1700fe1a
KK		 592}
593
594/*
595 * B-channel main receive routine
596 */
1532dcb7 597static void
1700fe1a
KK		 598main_rec_hfcpci(struct bchannel *bch)
599{
600 struct hfc_pci *hc = bch->hw;
601 int rcnt, real_fifo;
87c5fa1b 602 int receive = 0, count = 5;
1700fe1a
KK		 603 struct bzfifo *bz;
604 u_char *bdata;
605 struct zt *zp;
606
1700fe1a
KK		 607 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
608 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b2;
609 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b2;
610 real_fifo = 1;
611 } else {
612 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.rxbz_b1;
613 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.rxdat_b1;
614 real_fifo = 0;
615 }
616Begin:
617 count--;
618 if (bz->f1 != bz->f2) {
619 if (bch->debug & DEBUG_HW_BCHANNEL)
620 printk(KERN_DEBUG "hfcpci rec ch(%x) f1(%d) f2(%d)\n",
621 bch->nr, bz->f1, bz->f2);
622 zp = &bz->za[bz->f2];
623
624 rcnt = le16_to_cpu(zp->z1) - le16_to_cpu(zp->z2);
625 if (rcnt < 0)
626 rcnt += B_FIFO_SIZE;
627 rcnt++;
628 if (bch->debug & DEBUG_HW_BCHANNEL)
629 printk(KERN_DEBUG
630 "hfcpci rec ch(%x) z1(%x) z2(%x) cnt(%d)\n",
631 bch->nr, le16_to_cpu(zp->z1),
632 le16_to_cpu(zp->z2), rcnt);
633 hfcpci_empty_bfifo(bch, bz, bdata, rcnt);
634 rcnt = bz->f1 - bz->f2;
635 if (rcnt < 0)
636 rcnt += MAX_B_FRAMES + 1;
637 if (hc->hw.last_bfifo_cnt[real_fifo] > rcnt + 1) {
638 rcnt = 0;
639 hfcpci_clear_fifo_rx(hc, real_fifo);
640 }
641 hc->hw.last_bfifo_cnt[real_fifo] = rcnt;
642 if (rcnt > 1)
643 receive = 1;
644 else
645 receive = 0;
87c5fa1b
AE		 646 } else if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
647 hfcpci_empty_fifo_trans(bch, bz, bdata);
648 return;
649 } else
1700fe1a
KK		 650 receive = 0;
651 if (count && receive)
652 goto Begin;
653
654}
655
656/*
657 * D-channel send routine
658 */
659static void
660hfcpci_fill_dfifo(struct hfc_pci *hc)
661{
662 struct dchannel *dch = &hc->dch;
663 int fcnt;
664 int count, new_z1, maxlen;
665 struct dfifo *df;
666 u_char *src, *dst, new_f1;
667
668 if ((dch->debug & DEBUG_HW_DCHANNEL) && !(dch->debug & DEBUG_HW_DFIFO))
669 printk(KERN_DEBUG "%s\n", __func__);
670
671 if (!dch->tx_skb)
672 return;
673 count = dch->tx_skb->len - dch->tx_idx;
674 if (count <= 0)
675 return;
676 df = &((union fifo_area *) (hc->hw.fifos))->d_chan.d_tx;
677
678 if (dch->debug & DEBUG_HW_DFIFO)
679 printk(KERN_DEBUG "%s:f1(%d) f2(%d) z1(f1)(%x)\n", __func__,
680 df->f1, df->f2,
681 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1));
682 fcnt = df->f1 - df->f2; /* frame count actually buffered */
683 if (fcnt < 0)
684 fcnt += (MAX_D_FRAMES + 1); /* if wrap around */
685 if (fcnt > (MAX_D_FRAMES - 1)) {
686 if (dch->debug & DEBUG_HW_DCHANNEL)
687 printk(KERN_DEBUG
688 "hfcpci_fill_Dfifo more as 14 frames\n");
689#ifdef ERROR_STATISTIC
690 cs->err_tx++;
691#endif
692 return;
693 }
694 /* now determine free bytes in FIFO buffer */
695 maxlen = le16_to_cpu(df->za[df->f2 & D_FREG_MASK].z2) -
696 le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) - 1;
697 if (maxlen <= 0)
698 maxlen += D_FIFO_SIZE; /* count now contains available bytes */
699
700 if (dch->debug & DEBUG_HW_DCHANNEL)
701 printk(KERN_DEBUG "hfcpci_fill_Dfifo count(%d/%d)\n",
702 count, maxlen);
703 if (count > maxlen) {
704 if (dch->debug & DEBUG_HW_DCHANNEL)
705 printk(KERN_DEBUG "hfcpci_fill_Dfifo no fifo mem\n");
706 return;
707 }
708 new_z1 = (le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1) + count) &
709 (D_FIFO_SIZE - 1);
710 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1);
711 src = dch->tx_skb->data + dch->tx_idx; /* source pointer */
712 dst = df->data + le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
713 maxlen = D_FIFO_SIZE - le16_to_cpu(df->za[df->f1 & D_FREG_MASK].z1);
714 /* end fifo */
715 if (maxlen > count)
716 maxlen = count; /* limit size */
717 memcpy(dst, src, maxlen); /* first copy */
718
719 count -= maxlen; /* remaining bytes */
720 if (count) {
721 dst = df->data; /* start of buffer */
722 src += maxlen; /* new position */
723 memcpy(dst, src, count);
724 }
725 df->za[new_f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
726 /* for next buffer */
727 df->za[df->f1 & D_FREG_MASK].z1 = cpu_to_le16(new_z1);
728 /* new pos actual buffer */
729 df->f1 = new_f1; /* next frame */
730 dch->tx_idx = dch->tx_skb->len;
731}
732
733/*
734 * B-channel send routine
735 */
736static void
737hfcpci_fill_fifo(struct bchannel *bch)
738{
739 struct hfc_pci *hc = bch->hw;
740 int maxlen, fcnt;
741 int count, new_z1;
742 struct bzfifo *bz;
743 u_char *bdata;
744 u_char new_f1, *src, *dst;
f11d32df 745 __le16 *z1t, *z2t;
1700fe1a
KK		 746
747 if ((bch->debug & DEBUG_HW_BCHANNEL) && !(bch->debug & DEBUG_HW_BFIFO))
748 printk(KERN_DEBUG "%s\n", __func__);
749 if ((!bch->tx_skb) || bch->tx_skb->len <= 0)
750 return;
751 count = bch->tx_skb->len - bch->tx_idx;
752 if ((bch->nr & 2) && (!hc->hw.bswapped)) {
753 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b2;
754 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b2;
755 } else {
756 bz = &((union fifo_area *)(hc->hw.fifos))->b_chans.txbz_b1;
757 bdata = ((union fifo_area *)(hc->hw.fifos))->b_chans.txdat_b1;
758 }
759
760 if (test_bit(FLG_TRANSPARENT, &bch->Flags)) {
761 z1t = &bz->za[MAX_B_FRAMES].z1;
762 z2t = z1t + 1;
763 if (bch->debug & DEBUG_HW_BCHANNEL)
764 printk(KERN_DEBUG "hfcpci_fill_fifo_trans ch(%x) "
765 "cnt(%d) z1(%x) z2(%x)\n", bch->nr, count,
766 le16_to_cpu(*z1t), le16_to_cpu(*z2t));
767 fcnt = le16_to_cpu(*z2t) - le16_to_cpu(*z1t);
768 if (fcnt <= 0)
769 fcnt += B_FIFO_SIZE;
770 /* fcnt contains available bytes in fifo */
771 fcnt = B_FIFO_SIZE - fcnt;
772 /* remaining bytes to send (bytes in fifo) */
8dd2f36f
AE		 773
774 /* "fill fifo if empty" feature */
775 if (test_bit(FLG_FILLEMPTY, &bch->Flags) && !fcnt) {
776 /* printk(KERN_DEBUG "%s: buffer empty, so we have "
777 "underrun\n", __func__); */
778 /* fill buffer, to prevent future underrun */
779 count = HFCPCI_FILLEMPTY;
780 new_z1 = le16_to_cpu(*z1t) + count;
781 /* new buffer Position */
782 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
783 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
784 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
785 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
786 /* end of fifo */
787 if (bch->debug & DEBUG_HW_BFIFO)
788 printk(KERN_DEBUG "hfcpci_FFt fillempty "
789 "fcnt(%d) maxl(%d) nz1(%x) dst(%p)\n",
790 fcnt, maxlen, new_z1, dst);
791 fcnt += count;
792 if (maxlen > count)
793 maxlen = count; /* limit size */
794 memset(dst, 0x2a, maxlen); /* first copy */
795 count -= maxlen; /* remaining bytes */
796 if (count) {
797 dst = bdata; /* start of buffer */
798 memset(dst, 0x2a, count);
799 }
800 *z1t = cpu_to_le16(new_z1); /* now send data */
801 }
802
1700fe1a
KK		 803next_t_frame:
804 count = bch->tx_skb->len - bch->tx_idx;
87c5fa1b
AE		 805 /* maximum fill shall be poll*2 */
806 if (count > (poll << 1) - fcnt)
807 count = (poll << 1) - fcnt;
1700fe1a
KK		 808 if (count <= 0)
809 return;
810 /* data is suitable for fifo */
811 new_z1 = le16_to_cpu(*z1t) + count;
812 /* new buffer Position */
813 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
814 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
815 src = bch->tx_skb->data + bch->tx_idx;
816 /* source pointer */
817 dst = bdata + (le16_to_cpu(*z1t) - B_SUB_VAL);
818 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(*z1t);
819 /* end of fifo */
820 if (bch->debug & DEBUG_HW_BFIFO)
821 printk(KERN_DEBUG "hfcpci_FFt fcnt(%d) "
822 "maxl(%d) nz1(%x) dst(%p)\n",
823 fcnt, maxlen, new_z1, dst);
824 fcnt += count;
825 bch->tx_idx += count;
826 if (maxlen > count)
827 maxlen = count; /* limit size */
828 memcpy(dst, src, maxlen); /* first copy */
829 count -= maxlen; /* remaining bytes */
830 if (count) {
831 dst = bdata; /* start of buffer */
832 src += maxlen; /* new position */
833 memcpy(dst, src, count);
834 }
835 *z1t = cpu_to_le16(new_z1); /* now send data */
836 if (bch->tx_idx < bch->tx_skb->len)
837 return;
838 /* send confirm, on trans, free on hdlc. */
839 if (test_bit(FLG_TRANSPARENT, &bch->Flags))
840 confirm_Bsend(bch);
841 dev_kfree_skb(bch->tx_skb);
842 if (get_next_bframe(bch))
843 goto next_t_frame;
844 return;
845 }
846 if (bch->debug & DEBUG_HW_BCHANNEL)
847 printk(KERN_DEBUG
848 "%s: ch(%x) f1(%d) f2(%d) z1(f1)(%x)\n",
849 __func__, bch->nr, bz->f1, bz->f2,
850 bz->za[bz->f1].z1);
851 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */
852 if (fcnt < 0)
853 fcnt += (MAX_B_FRAMES + 1); /* if wrap around */
854 if (fcnt > (MAX_B_FRAMES - 1)) {
855 if (bch->debug & DEBUG_HW_BCHANNEL)
856 printk(KERN_DEBUG
857 "hfcpci_fill_Bfifo more as 14 frames\n");
858 return;
859 }
860 /* now determine free bytes in FIFO buffer */
861 maxlen = le16_to_cpu(bz->za[bz->f2].z2) -
862 le16_to_cpu(bz->za[bz->f1].z1) - 1;
863 if (maxlen <= 0)
864 maxlen += B_FIFO_SIZE; /* count now contains available bytes */
865
866 if (bch->debug & DEBUG_HW_BCHANNEL)
867 printk(KERN_DEBUG "hfcpci_fill_fifo ch(%x) count(%d/%d)\n",
868 bch->nr, count, maxlen);
869
870 if (maxlen < count) {
871 if (bch->debug & DEBUG_HW_BCHANNEL)
872 printk(KERN_DEBUG "hfcpci_fill_fifo no fifo mem\n");
873 return;
874 }
875 new_z1 = le16_to_cpu(bz->za[bz->f1].z1) + count;
876 /* new buffer Position */
877 if (new_z1 >= (B_FIFO_SIZE + B_SUB_VAL))
878 new_z1 -= B_FIFO_SIZE; /* buffer wrap */
879
880 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES);
881 src = bch->tx_skb->data + bch->tx_idx; /* source pointer */
882 dst = bdata + (le16_to_cpu(bz->za[bz->f1].z1) - B_SUB_VAL);
883 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - le16_to_cpu(bz->za[bz->f1].z1);
884 /* end fifo */
885 if (maxlen > count)
886 maxlen = count; /* limit size */
887 memcpy(dst, src, maxlen); /* first copy */
888
889 count -= maxlen; /* remaining bytes */
890 if (count) {
891 dst = bdata; /* start of buffer */
892 src += maxlen; /* new position */
893 memcpy(dst, src, count);
894 }
895 bz->za[new_f1].z1 = cpu_to_le16(new_z1); /* for next buffer */
896 bz->f1 = new_f1; /* next frame */
897 dev_kfree_skb(bch->tx_skb);
898 get_next_bframe(bch);
899}
900
901
902
903/*
904 * handle L1 state changes TE
905 */
906
907static void
908ph_state_te(struct dchannel *dch)
909{
910 if (dch->debug)
911 printk(KERN_DEBUG "%s: TE newstate %x\n",
912 __func__, dch->state);
913 switch (dch->state) {
914 case 0:
915 l1_event(dch->l1, HW_RESET_IND);
916 break;
917 case 3:
918 l1_event(dch->l1, HW_DEACT_IND);
919 break;
920 case 5:
921 case 8:
922 l1_event(dch->l1, ANYSIGNAL);
923 break;
924 case 6:
925 l1_event(dch->l1, INFO2);
926 break;
927 case 7:
928 l1_event(dch->l1, INFO4_P8);
929 break;
930 }
931}
932
933/*
934 * handle L1 state changes NT
935 */
936
937static void
938handle_nt_timer3(struct dchannel *dch) {
939 struct hfc_pci *hc = dch->hw;
940
941 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
942 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
943 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
944 hc->hw.nt_timer = 0;
945 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
946 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
947 hc->hw.mst_m |= HFCPCI_MASTER;
948 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
949 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
950 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
951}
952
953static void
954ph_state_nt(struct dchannel *dch)
955{
956 struct hfc_pci *hc = dch->hw;
957
958 if (dch->debug)
959 printk(KERN_DEBUG "%s: NT newstate %x\n",
960 __func__, dch->state);
961 switch (dch->state) {
962 case 2:
963 if (hc->hw.nt_timer < 0) {
964 hc->hw.nt_timer = 0;
965 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
966 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
967 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
968 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
969 /* Clear already pending ints */
970 if (Read_hfc(hc, HFCPCI_INT_S1));
971 Write_hfc(hc, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE);
972 udelay(10);
973 Write_hfc(hc, HFCPCI_STATES, 4);
974 dch->state = 4;
975 } else if (hc->hw.nt_timer == 0) {
976 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
977 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
978 hc->hw.nt_timer = NT_T1_COUNT;
979 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
980 hc->hw.ctmt |= HFCPCI_TIM3_125;
981 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
982 HFCPCI_CLTIMER);
983 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
984 test_and_set_bit(FLG_HFC_TIMER_T1, &dch->Flags);
985 /* allow G2 -> G3 transition */
986 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
987 } else {
988 Write_hfc(hc, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3);
989 }
990 break;
991 case 1:
992 hc->hw.nt_timer = 0;
993 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
994 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
995 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
996 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
997 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
998 hc->hw.mst_m &= ~HFCPCI_MASTER;
999 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1000 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1001 _queue_data(&dch->dev.D, PH_DEACTIVATE_IND,
1002 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1003 break;
1004 case 4:
1005 hc->hw.nt_timer = 0;
1006 test_and_clear_bit(FLG_HFC_TIMER_T3, &dch->Flags);
1007 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1008 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1009 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1010 break;
1011 case 3:
1012 if (!test_and_set_bit(FLG_HFC_TIMER_T3, &dch->Flags)) {
1013 if (!test_and_clear_bit(FLG_L2_ACTIVATED,
1014 &dch->Flags)) {
1015 handle_nt_timer3(dch);
1016 break;
1017 }
1018 test_and_clear_bit(FLG_HFC_TIMER_T1, &dch->Flags);
1019 hc->hw.int_m1 |= HFCPCI_INTS_TIMER;
1020 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1021 hc->hw.nt_timer = NT_T3_COUNT;
1022 hc->hw.ctmt &= ~HFCPCI_AUTO_TIMER;
1023 hc->hw.ctmt |= HFCPCI_TIM3_125;
1024 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt |
1025 HFCPCI_CLTIMER);
1026 }
1027 break;
1028 }
1029}
1030
1031static void
1032ph_state(struct dchannel *dch)
1033{
1034 struct hfc_pci *hc = dch->hw;
1035
1036 if (hc->hw.protocol == ISDN_P_NT_S0) {
1037 if (test_bit(FLG_HFC_TIMER_T3, &dch->Flags) &&
1038 hc->hw.nt_timer < 0)
1039 handle_nt_timer3(dch);
1040 else
1041 ph_state_nt(dch);
1042 } else
1043 ph_state_te(dch);
1044}
1045
1046/*
1047 * Layer 1 callback function
1048 */
1049static int
1050hfc_l1callback(struct dchannel *dch, u_int cmd)
1051{
1052 struct hfc_pci *hc = dch->hw;
1053
1054 switch (cmd) {
1055 case INFO3_P8:
1056 case INFO3_P10:
1057 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1058 hc->hw.mst_m |= HFCPCI_MASTER;
1059 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1060 break;
1061 case HW_RESET_REQ:
1062 Write_hfc(hc, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3);
1063 /* HFC ST 3 */
1064 udelay(6);
1065 Write_hfc(hc, HFCPCI_STATES, 3); /* HFC ST 2 */
1066 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1067 hc->hw.mst_m |= HFCPCI_MASTER;
1068 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1069 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1070 HFCPCI_DO_ACTION);
1071 l1_event(dch->l1, HW_POWERUP_IND);
1072 break;
1073 case HW_DEACT_REQ:
1074 hc->hw.mst_m &= ~HFCPCI_MASTER;
1075 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1076 skb_queue_purge(&dch->squeue);
1077 if (dch->tx_skb) {
1078 dev_kfree_skb(dch->tx_skb);
1079 dch->tx_skb = NULL;
1080 }
1081 dch->tx_idx = 0;
1082 if (dch->rx_skb) {
1083 dev_kfree_skb(dch->rx_skb);
1084 dch->rx_skb = NULL;
1085 }
1086 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1087 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1088 del_timer(&dch->timer);
1089 break;
1090 case HW_POWERUP_REQ:
1091 Write_hfc(hc, HFCPCI_STATES, HFCPCI_DO_ACTION);
1092 break;
1093 case PH_ACTIVATE_IND:
1094 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
1095 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1096 GFP_ATOMIC);
1097 break;
1098 case PH_DEACTIVATE_IND:
1099 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
1100 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
1101 GFP_ATOMIC);
1102 break;
1103 default:
1104 if (dch->debug & DEBUG_HW)
1105 printk(KERN_DEBUG "%s: unknown command %x\n",
1106 __func__, cmd);
1107 return -1;
1108 }
1109 return 0;
1110}
1111
1112/*
1113 * Interrupt handler
1114 */
1115static inline void
1116tx_birq(struct bchannel *bch)
1117{
1118 if (bch->tx_skb && bch->tx_idx < bch->tx_skb->len)
1119 hfcpci_fill_fifo(bch);
1120 else {
1121 if (bch->tx_skb)
1122 dev_kfree_skb(bch->tx_skb);
1123 if (get_next_bframe(bch))
1124 hfcpci_fill_fifo(bch);
1125 }
1126}
1127
1128static inline void
1129tx_dirq(struct dchannel *dch)
1130{
1131 if (dch->tx_skb && dch->tx_idx < dch->tx_skb->len)
1132 hfcpci_fill_dfifo(dch->hw);
1133 else {
1134 if (dch->tx_skb)
1135 dev_kfree_skb(dch->tx_skb);
1136 if (get_next_dframe(dch))
1137 hfcpci_fill_dfifo(dch->hw);
1138 }
1139}
1140
1141static irqreturn_t
1142hfcpci_int(int intno, void *dev_id)
1143{
1144 struct hfc_pci *hc = dev_id;
1145 u_char exval;
1146 struct bchannel *bch;
1147 u_char val, stat;
1148
1149 spin_lock(&hc->lock);
1150 if (!(hc->hw.int_m2 & 0x08)) {
1151 spin_unlock(&hc->lock);
1152 return IRQ_NONE; /* not initialised */
1153 }
1154 stat = Read_hfc(hc, HFCPCI_STATUS);
1155 if (HFCPCI_ANYINT & stat) {
1156 val = Read_hfc(hc, HFCPCI_INT_S1);
1157 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1158 printk(KERN_DEBUG
1159 "HFC-PCI: stat(%02x) s1(%02x)\n", stat, val);
1160 } else {
1161 /* shared */
1162 spin_unlock(&hc->lock);
1163 return IRQ_NONE;
1164 }
1165 hc->irqcnt++;
1166
1167 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1168 printk(KERN_DEBUG "HFC-PCI irq %x\n", val);
1169 val &= hc->hw.int_m1;
1170 if (val & 0x40) { /* state machine irq */
1171 exval = Read_hfc(hc, HFCPCI_STATES) & 0xf;
1172 if (hc->dch.debug & DEBUG_HW_DCHANNEL)
1173 printk(KERN_DEBUG "ph_state chg %d->%d\n",
1174 hc->dch.state, exval);
1175 hc->dch.state = exval;
1176 schedule_event(&hc->dch, FLG_PHCHANGE);
1177 val &= ~0x40;
1178 }
1179 if (val & 0x80) { /* timer irq */
1180 if (hc->hw.protocol == ISDN_P_NT_S0) {
1181 if ((--hc->hw.nt_timer) < 0)
1182 schedule_event(&hc->dch, FLG_PHCHANGE);
1183 }
1184 val &= ~0x80;
1185 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt | HFCPCI_CLTIMER);
1186 }
87c5fa1b 1187 if (val & 0x08) { /* B1 rx */
1700fe1a
KK		 1188 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1189 if (bch)
1190 main_rec_hfcpci(bch);
1191 else if (hc->dch.debug)
1192 printk(KERN_DEBUG "hfcpci spurious 0x08 IRQ\n");
1193 }
87c5fa1b 1194 if (val & 0x10) { /* B2 rx */
1700fe1a
KK		 1195 bch = Sel_BCS(hc, 2);
1196 if (bch)
1197 main_rec_hfcpci(bch);
1198 else if (hc->dch.debug)
1199 printk(KERN_DEBUG "hfcpci spurious 0x10 IRQ\n");
1200 }
87c5fa1b 1201 if (val & 0x01) { /* B1 tx */
1700fe1a
KK		 1202 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
1203 if (bch)
1204 tx_birq(bch);
1205 else if (hc->dch.debug)
1206 printk(KERN_DEBUG "hfcpci spurious 0x01 IRQ\n");
1207 }
87c5fa1b 1208 if (val & 0x02) { /* B2 tx */
1700fe1a
KK		 1209 bch = Sel_BCS(hc, 2);
1210 if (bch)
1211 tx_birq(bch);
1212 else if (hc->dch.debug)
1213 printk(KERN_DEBUG "hfcpci spurious 0x02 IRQ\n");
1214 }
87c5fa1b 1215 if (val & 0x20) /* D rx */
1700fe1a 1216 receive_dmsg(hc);
87c5fa1b 1217 if (val & 0x04) { /* D tx */
1700fe1a
KK		 1218 if (test_and_clear_bit(FLG_BUSY_TIMER, &hc->dch.Flags))
1219 del_timer(&hc->dch.timer);
1220 tx_dirq(&hc->dch);
1221 }
1222 spin_unlock(&hc->lock);
1223 return IRQ_HANDLED;
1224}
1225
1226/*
1227 * timer callback for D-chan busy resolution. Currently no function
1228 */
1229static void
1230hfcpci_dbusy_timer(struct hfc_pci *hc)
1231{
1232}
1233
1234/*
1235 * activate/deactivate hardware for selected channels and mode
1236 */
1237static int
1238mode_hfcpci(struct bchannel *bch, int bc, int protocol)
1239{
1240 struct hfc_pci *hc = bch->hw;
1241 int fifo2;
1242 u_char rx_slot = 0, tx_slot = 0, pcm_mode;
1243
1244 if (bch->debug & DEBUG_HW_BCHANNEL)
1245 printk(KERN_DEBUG
1246 "HFCPCI bchannel protocol %x-->%x ch %x-->%x\n",
1247 bch->state, protocol, bch->nr, bc);
1248
1249 fifo2 = bc;
1250 pcm_mode = (bc>>24) & 0xff;
1251 if (pcm_mode) { /* PCM SLOT USE */
1252 if (!test_bit(HFC_CFG_PCM, &hc->cfg))
1253 printk(KERN_WARNING
1254 "%s: pcm channel id without HFC_CFG_PCM\n",
1255 __func__);
1256 rx_slot = (bc>>8) & 0xff;
1257 tx_slot = (bc>>16) & 0xff;
1258 bc = bc & 0xff;
1259 } else if (test_bit(HFC_CFG_PCM, &hc->cfg) &&
1260 (protocol > ISDN_P_NONE))
1261 printk(KERN_WARNING "%s: no pcm channel id but HFC_CFG_PCM\n",
1262 __func__);
1263 if (hc->chanlimit > 1) {
1264 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1265 hc->hw.sctrl_e &= ~0x80;
1266 } else {
1267 if (bc & 2) {
1268 if (protocol != ISDN_P_NONE) {
1269 hc->hw.bswapped = 1; /* B1 and B2 exchanged */
1270 hc->hw.sctrl_e |= 0x80;
1271 } else {
1272 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1273 hc->hw.sctrl_e &= ~0x80;
1274 }
1275 fifo2 = 1;
1276 } else {
1277 hc->hw.bswapped = 0; /* B1 and B2 normal mode */
1278 hc->hw.sctrl_e &= ~0x80;
1279 }
1280 }
1281 switch (protocol) {
1282 case (-1): /* used for init */
1283 bch->state = -1;
1284 bch->nr = bc;
1285 case (ISDN_P_NONE):
1286 if (bch->state == ISDN_P_NONE)
1287 return 0;
1288 if (bc & 2) {
1289 hc->hw.sctrl &= ~SCTRL_B2_ENA;
1290 hc->hw.sctrl_r &= ~SCTRL_B2_ENA;
1291 } else {
1292 hc->hw.sctrl &= ~SCTRL_B1_ENA;
1293 hc->hw.sctrl_r &= ~SCTRL_B1_ENA;
1294 }
1295 if (fifo2 & 2) {
1296 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B2;
1297 hc->hw.int_m1 &= ~(HFCPCI_INTS_B2TRANS +
1298 HFCPCI_INTS_B2REC);
1299 } else {
1300 hc->hw.fifo_en &= ~HFCPCI_FIFOEN_B1;
1301 hc->hw.int_m1 &= ~(HFCPCI_INTS_B1TRANS +
1302 HFCPCI_INTS_B1REC);
1303 }
1304#ifdef REVERSE_BITORDER
1305 if (bch->nr & 2)
1306 hc->hw.cirm &= 0x7f;
1307 else
1308 hc->hw.cirm &= 0xbf;
1309#endif
1310 bch->state = ISDN_P_NONE;
1311 bch->nr = bc;
1312 test_and_clear_bit(FLG_HDLC, &bch->Flags);
1313 test_and_clear_bit(FLG_TRANSPARENT, &bch->Flags);
1314 break;
1315 case (ISDN_P_B_RAW):
1316 bch->state = protocol;
1317 bch->nr = bc;
1318 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1319 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1320 if (bc & 2) {
1321 hc->hw.sctrl |= SCTRL_B2_ENA;
1322 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1323#ifdef REVERSE_BITORDER
1324 hc->hw.cirm |= 0x80;
1325#endif
1326 } else {
1327 hc->hw.sctrl |= SCTRL_B1_ENA;
1328 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1329#ifdef REVERSE_BITORDER
1330 hc->hw.cirm |= 0x40;
1331#endif
1332 }
1333 if (fifo2 & 2) {
1334 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
87c5fa1b
AE		 1335 if (!tics)
1336 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1337 HFCPCI_INTS_B2REC);
1700fe1a
KK		 1338 hc->hw.ctmt |= 2;
1339 hc->hw.conn &= ~0x18;
1340 } else {
1341 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
87c5fa1b
AE		 1342 if (!tics)
1343 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1344 HFCPCI_INTS_B1REC);
1700fe1a
KK		 1345 hc->hw.ctmt |= 1;
1346 hc->hw.conn &= ~0x03;
1347 }
1348 test_and_set_bit(FLG_TRANSPARENT, &bch->Flags);
1349 break;
1350 case (ISDN_P_B_HDLC):
1351 bch->state = protocol;
1352 bch->nr = bc;
1353 hfcpci_clear_fifo_rx(hc, (fifo2 & 2)?1:0);
1354 hfcpci_clear_fifo_tx(hc, (fifo2 & 2)?1:0);
1355 if (bc & 2) {
1356 hc->hw.sctrl |= SCTRL_B2_ENA;
1357 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1358 } else {
1359 hc->hw.sctrl |= SCTRL_B1_ENA;
1360 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1361 }
1362 if (fifo2 & 2) {
1363 hc->hw.last_bfifo_cnt[1] = 0;
1364 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2;
1365 hc->hw.int_m1 |= (HFCPCI_INTS_B2TRANS +
1366 HFCPCI_INTS_B2REC);
1367 hc->hw.ctmt &= ~2;
1368 hc->hw.conn &= ~0x18;
1369 } else {
1370 hc->hw.last_bfifo_cnt[0] = 0;
1371 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1;
1372 hc->hw.int_m1 |= (HFCPCI_INTS_B1TRANS +
1373 HFCPCI_INTS_B1REC);
1374 hc->hw.ctmt &= ~1;
1375 hc->hw.conn &= ~0x03;
1376 }
1377 test_and_set_bit(FLG_HDLC, &bch->Flags);
1378 break;
1379 default:
1380 printk(KERN_DEBUG "prot not known %x\n", protocol);
1381 return -ENOPROTOOPT;
1382 }
1383 if (test_bit(HFC_CFG_PCM, &hc->cfg)) {
1384 if ((protocol == ISDN_P_NONE) ||
1385 (protocol == -1)) { /* init case */
1386 rx_slot = 0;
1387 tx_slot = 0;
1388 } else {
1389 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg)) {
1390 rx_slot |= 0xC0;
1391 tx_slot |= 0xC0;
1392 } else {
1393 rx_slot |= 0x80;
1394 tx_slot |= 0x80;
1395 }
1396 }
1397 if (bc & 2) {
1398 hc->hw.conn &= 0xc7;
1399 hc->hw.conn |= 0x08;
1400 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL 0x%x\n",
1401 __func__, tx_slot);
1402 printk(KERN_DEBUG "%s: Write_hfc: B2_RSL 0x%x\n",
1403 __func__, rx_slot);
1404 Write_hfc(hc, HFCPCI_B2_SSL, tx_slot);
1405 Write_hfc(hc, HFCPCI_B2_RSL, rx_slot);
1406 } else {
1407 hc->hw.conn &= 0xf8;
1408 hc->hw.conn |= 0x01;
1409 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL 0x%x\n",
1410 __func__, tx_slot);
1411 printk(KERN_DEBUG "%s: Write_hfc: B1_RSL 0x%x\n",
1412 __func__, rx_slot);
1413 Write_hfc(hc, HFCPCI_B1_SSL, tx_slot);
1414 Write_hfc(hc, HFCPCI_B1_RSL, rx_slot);
1415 }
1416 }
1417 Write_hfc(hc, HFCPCI_SCTRL_E, hc->hw.sctrl_e);
1418 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1419 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1420 Write_hfc(hc, HFCPCI_SCTRL, hc->hw.sctrl);
1421 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1422 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1423 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1424#ifdef REVERSE_BITORDER
1425 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1426#endif
1427 return 0;
1428}
1429
1430static int
1431set_hfcpci_rxtest(struct bchannel *bch, int protocol, int chan)
1432{
1433 struct hfc_pci *hc = bch->hw;
1434
1435 if (bch->debug & DEBUG_HW_BCHANNEL)
1436 printk(KERN_DEBUG
1437 "HFCPCI bchannel test rx protocol %x-->%x ch %x-->%x\n",
1438 bch->state, protocol, bch->nr, chan);
1439 if (bch->nr != chan) {
1440 printk(KERN_DEBUG
1441 "HFCPCI rxtest wrong channel parameter %x/%x\n",
1442 bch->nr, chan);
1443 return -EINVAL;
1444 }
1445 switch (protocol) {
1446 case (ISDN_P_B_RAW):
1447 bch->state = protocol;
1448 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1449 if (chan & 2) {
1450 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1451 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
87c5fa1b
AE		 1452 if (!tics)
1453 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1700fe1a
KK		 1454 hc->hw.ctmt |= 2;
1455 hc->hw.conn &= ~0x18;
1456#ifdef REVERSE_BITORDER
1457 hc->hw.cirm |= 0x80;
1458#endif
1459 } else {
1460 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1461 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
87c5fa1b
AE		 1462 if (!tics)
1463 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1700fe1a
KK		 1464 hc->hw.ctmt |= 1;
1465 hc->hw.conn &= ~0x03;
1466#ifdef REVERSE_BITORDER
1467 hc->hw.cirm |= 0x40;
1468#endif
1469 }
1470 break;
1471 case (ISDN_P_B_HDLC):
1472 bch->state = protocol;
1473 hfcpci_clear_fifo_rx(hc, (chan & 2)?1:0);
1474 if (chan & 2) {
1475 hc->hw.sctrl_r |= SCTRL_B2_ENA;
1476 hc->hw.last_bfifo_cnt[1] = 0;
1477 hc->hw.fifo_en |= HFCPCI_FIFOEN_B2RX;
1478 hc->hw.int_m1 |= HFCPCI_INTS_B2REC;
1479 hc->hw.ctmt &= ~2;
1480 hc->hw.conn &= ~0x18;
1481 } else {
1482 hc->hw.sctrl_r |= SCTRL_B1_ENA;
1483 hc->hw.last_bfifo_cnt[0] = 0;
1484 hc->hw.fifo_en |= HFCPCI_FIFOEN_B1RX;
1485 hc->hw.int_m1 |= HFCPCI_INTS_B1REC;
1486 hc->hw.ctmt &= ~1;
1487 hc->hw.conn &= ~0x03;
1488 }
1489 break;
1490 default:
1491 printk(KERN_DEBUG "prot not known %x\n", protocol);
1492 return -ENOPROTOOPT;
1493 }
1494 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1495 Write_hfc(hc, HFCPCI_FIFO_EN, hc->hw.fifo_en);
1496 Write_hfc(hc, HFCPCI_SCTRL_R, hc->hw.sctrl_r);
1497 Write_hfc(hc, HFCPCI_CTMT, hc->hw.ctmt);
1498 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1499#ifdef REVERSE_BITORDER
1500 Write_hfc(hc, HFCPCI_CIRM, hc->hw.cirm);
1501#endif
1502 return 0;
1503}
1504
1505static void
1506deactivate_bchannel(struct bchannel *bch)
1507{
1508 struct hfc_pci *hc = bch->hw;
1509 u_long flags;
1510
1511 spin_lock_irqsave(&hc->lock, flags);
1512 if (test_and_clear_bit(FLG_TX_NEXT, &bch->Flags)) {
1513 dev_kfree_skb(bch->next_skb);
1514 bch->next_skb = NULL;
1515 }
1516 if (bch->tx_skb) {
1517 dev_kfree_skb(bch->tx_skb);
1518 bch->tx_skb = NULL;
1519 }
1520 bch->tx_idx = 0;
1521 if (bch->rx_skb) {
1522 dev_kfree_skb(bch->rx_skb);
1523 bch->rx_skb = NULL;
1524 }
1525 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1526 test_and_clear_bit(FLG_ACTIVE, &bch->Flags);
1527 test_and_clear_bit(FLG_TX_BUSY, &bch->Flags);
1528 spin_unlock_irqrestore(&hc->lock, flags);
1529}
1530
1531/*
1532 * Layer 1 B-channel hardware access
1533 */
1534static int
1535channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1536{
8dd2f36f 1537 int ret = 0;
1700fe1a
KK		 1538
1539 switch (cq->op) {
1540 case MISDN_CTRL_GETOP:
8dd2f36f
AE		 1541 cq->op = MISDN_CTRL_FILL_EMPTY;
1542 break;
1543 case MISDN_CTRL_FILL_EMPTY: /* fill fifo, if empty */
1544 test_and_set_bit(FLG_FILLEMPTY, &bch->Flags);
1545 if (debug & DEBUG_HW_OPEN)
1546 printk(KERN_DEBUG "%s: FILL_EMPTY request (nr=%d "
1547 "off=%d)\n", __func__, bch->nr, !!cq->p1);
1700fe1a
KK		 1548 break;
1549 default:
1550 printk(KERN_WARNING "%s: unknown Op %x\n", __func__, cq->op);
1551 ret = -EINVAL;
1552 break;
1553 }
1554 return ret;
1555}
1556static int
1557hfc_bctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1558{
1559 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1560 struct hfc_pci *hc = bch->hw;
1561 int ret = -EINVAL;
1562 u_long flags;
1563
1564 if (bch->debug & DEBUG_HW)
1565 printk(KERN_DEBUG "%s: cmd:%x %p\n", __func__, cmd, arg);
1566 switch (cmd) {
1567 case HW_TESTRX_RAW:
1568 spin_lock_irqsave(&hc->lock, flags);
1569 ret = set_hfcpci_rxtest(bch, ISDN_P_B_RAW, (int)(long)arg);
1570 spin_unlock_irqrestore(&hc->lock, flags);
1571 break;
1572 case HW_TESTRX_HDLC:
1573 spin_lock_irqsave(&hc->lock, flags);
1574 ret = set_hfcpci_rxtest(bch, ISDN_P_B_HDLC, (int)(long)arg);
1575 spin_unlock_irqrestore(&hc->lock, flags);
1576 break;
1577 case HW_TESTRX_OFF:
1578 spin_lock_irqsave(&hc->lock, flags);
1579 mode_hfcpci(bch, bch->nr, ISDN_P_NONE);
1580 spin_unlock_irqrestore(&hc->lock, flags);
1581 ret = 0;
1582 break;
1583 case CLOSE_CHANNEL:
1584 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1585 if (test_bit(FLG_ACTIVE, &bch->Flags))
1586 deactivate_bchannel(bch);
1587 ch->protocol = ISDN_P_NONE;
1588 ch->peer = NULL;
1589 module_put(THIS_MODULE);
1590 ret = 0;
1591 break;
1592 case CONTROL_CHANNEL:
1593 ret = channel_bctrl(bch, arg);
1594 break;
1595 default:
1596 printk(KERN_WARNING "%s: unknown prim(%x)\n",
1597 __func__, cmd);
1598 }
1599 return ret;
1600}
1601
1602/*
1603 * Layer2 -> Layer 1 Dchannel data
1604 */
1605static int
1606hfcpci_l2l1D(struct mISDNchannel *ch, struct sk_buff *skb)
1607{
1608 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1609 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1610 struct hfc_pci *hc = dch->hw;
1611 int ret = -EINVAL;
1612 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1613 unsigned int id;
1614 u_long flags;
1615
1616 switch (hh->prim) {
1617 case PH_DATA_REQ:
1618 spin_lock_irqsave(&hc->lock, flags);
1619 ret = dchannel_senddata(dch, skb);
1620 if (ret > 0) { /* direct TX */
1621 id = hh->id; /* skb can be freed */
1622 hfcpci_fill_dfifo(dch->hw);
1623 ret = 0;
1624 spin_unlock_irqrestore(&hc->lock, flags);
1625 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1626 } else
1627 spin_unlock_irqrestore(&hc->lock, flags);
1628 return ret;
1629 case PH_ACTIVATE_REQ:
1630 spin_lock_irqsave(&hc->lock, flags);
1631 if (hc->hw.protocol == ISDN_P_NT_S0) {
1632 ret = 0;
1633 if (test_bit(HFC_CFG_MASTER, &hc->cfg))
1634 hc->hw.mst_m |= HFCPCI_MASTER;
1635 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1636 if (test_bit(FLG_ACTIVE, &dch->Flags)) {
1637 spin_unlock_irqrestore(&hc->lock, flags);
1638 _queue_data(&dch->dev.D, PH_ACTIVATE_IND,
1639 MISDN_ID_ANY, 0, NULL, GFP_ATOMIC);
1640 break;
1641 }
1642 test_and_set_bit(FLG_L2_ACTIVATED, &dch->Flags);
1643 Write_hfc(hc, HFCPCI_STATES, HFCPCI_ACTIVATE |
1644 HFCPCI_DO_ACTION | 1);
1645 } else
1646 ret = l1_event(dch->l1, hh->prim);
1647 spin_unlock_irqrestore(&hc->lock, flags);
1648 break;
1649 case PH_DEACTIVATE_REQ:
1650 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
1651 spin_lock_irqsave(&hc->lock, flags);
1652 if (hc->hw.protocol == ISDN_P_NT_S0) {
1653 /* prepare deactivation */
1654 Write_hfc(hc, HFCPCI_STATES, 0x40);
1655 skb_queue_purge(&dch->squeue);
1656 if (dch->tx_skb) {
1657 dev_kfree_skb(dch->tx_skb);
1658 dch->tx_skb = NULL;
1659 }
1660 dch->tx_idx = 0;
1661 if (dch->rx_skb) {
1662 dev_kfree_skb(dch->rx_skb);
1663 dch->rx_skb = NULL;
1664 }
1665 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
1666 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
1667 del_timer(&dch->timer);
1668#ifdef FIXME
1669 if (test_and_clear_bit(FLG_L1_BUSY, &dch->Flags))
1670 dchannel_sched_event(&hc->dch, D_CLEARBUSY);
1671#endif
1672 hc->hw.mst_m &= ~HFCPCI_MASTER;
1673 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1674 ret = 0;
1675 } else {
1676 ret = l1_event(dch->l1, hh->prim);
1677 }
1678 spin_unlock_irqrestore(&hc->lock, flags);
1679 break;
1680 }
1681 if (!ret)
1682 dev_kfree_skb(skb);
1683 return ret;
1684}
1685
1686/*
1687 * Layer2 -> Layer 1 Bchannel data
1688 */
1689static int
1690hfcpci_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
1691{
1692 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1693 struct hfc_pci *hc = bch->hw;
1694 int ret = -EINVAL;
1695 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1696 unsigned int id;
1697 u_long flags;
1698
1699 switch (hh->prim) {
1700 case PH_DATA_REQ:
1701 spin_lock_irqsave(&hc->lock, flags);
1702 ret = bchannel_senddata(bch, skb);
1703 if (ret > 0) { /* direct TX */
1704 id = hh->id; /* skb can be freed */
1705 hfcpci_fill_fifo(bch);
1706 ret = 0;
1707 spin_unlock_irqrestore(&hc->lock, flags);
1708 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1709 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1710 } else
1711 spin_unlock_irqrestore(&hc->lock, flags);
1712 return ret;
1713 case PH_ACTIVATE_REQ:
1714 spin_lock_irqsave(&hc->lock, flags);
1715 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1716 ret = mode_hfcpci(bch, bch->nr, ch->protocol);
1717 else
1718 ret = 0;
1719 spin_unlock_irqrestore(&hc->lock, flags);
1720 if (!ret)
1721 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1722 NULL, GFP_KERNEL);
1723 break;
1724 case PH_DEACTIVATE_REQ:
1725 deactivate_bchannel(bch);
1726 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1727 NULL, GFP_KERNEL);
1728 ret = 0;
1729 break;
1730 }
1731 if (!ret)
1732 dev_kfree_skb(skb);
1733 return ret;
1734}
1735
1736/*
1737 * called for card init message
1738 */
1739
1532dcb7 1740static void
1700fe1a
KK		 1741inithfcpci(struct hfc_pci *hc)
1742{
1743 printk(KERN_DEBUG "inithfcpci: entered\n");
1744 hc->dch.timer.function = (void *) hfcpci_dbusy_timer;
1745 hc->dch.timer.data = (long) &hc->dch;
1746 init_timer(&hc->dch.timer);
1747 hc->chanlimit = 2;
1748 mode_hfcpci(&hc->bch[0], 1, -1);
1749 mode_hfcpci(&hc->bch[1], 2, -1);
1750}
1751
1752
1753static int
1754init_card(struct hfc_pci *hc)
1755{
1756 int cnt = 3;
1757 u_long flags;
1758
1759 printk(KERN_DEBUG "init_card: entered\n");
1760
1761
1762 spin_lock_irqsave(&hc->lock, flags);
1763 disable_hwirq(hc);
1764 spin_unlock_irqrestore(&hc->lock, flags);
1765 if (request_irq(hc->irq, hfcpci_int, IRQF_SHARED, "HFC PCI", hc)) {
1766 printk(KERN_WARNING
1767 "mISDN: couldn't get interrupt %d\n", hc->irq);
1768 return -EIO;
1769 }
1770 spin_lock_irqsave(&hc->lock, flags);
1771 reset_hfcpci(hc);
1772 while (cnt) {
1773 inithfcpci(hc);
1774 /*
1775 * Finally enable IRQ output
1776 * this is only allowed, if an IRQ routine is allready
1777 * established for this HFC, so don't do that earlier
1778 */
1779 enable_hwirq(hc);
1780 spin_unlock_irqrestore(&hc->lock, flags);
1781 /* Timeout 80ms */
1782 current->state = TASK_UNINTERRUPTIBLE;
1783 schedule_timeout((80*HZ)/1000);
1784 printk(KERN_INFO "HFC PCI: IRQ %d count %d\n",
1785 hc->irq, hc->irqcnt);
1786 /* now switch timer interrupt off */
1787 spin_lock_irqsave(&hc->lock, flags);
1788 hc->hw.int_m1 &= ~HFCPCI_INTS_TIMER;
1789 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
1790 /* reinit mode reg */
1791 Write_hfc(hc, HFCPCI_MST_MODE, hc->hw.mst_m);
1792 if (!hc->irqcnt) {
1793 printk(KERN_WARNING
1794 "HFC PCI: IRQ(%d) getting no interrupts "
1795 "during init %d\n", hc->irq, 4 - cnt);
1796 if (cnt == 1) {
1797 spin_unlock_irqrestore(&hc->lock, flags);
1798 return -EIO;
1799 } else {
1800 reset_hfcpci(hc);
1801 cnt--;
1802 }
1803 } else {
1804 spin_unlock_irqrestore(&hc->lock, flags);
1805 hc->initdone = 1;
1806 return 0;
1807 }
1808 }
1809 disable_hwirq(hc);
1810 spin_unlock_irqrestore(&hc->lock, flags);
1811 free_irq(hc->irq, hc);
1812 return -EIO;
1813}
1814
1815static int
1816channel_ctrl(struct hfc_pci *hc, struct mISDN_ctrl_req *cq)
1817{
1818 int ret = 0;
1819 u_char slot;
1820
1821 switch (cq->op) {
1822 case MISDN_CTRL_GETOP:
1823 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_CONNECT |
1824 MISDN_CTRL_DISCONNECT;
1825 break;
1826 case MISDN_CTRL_LOOP:
1827 /* channel 0 disabled loop */
1828 if (cq->channel < 0 || cq->channel > 2) {
1829 ret = -EINVAL;
1830 break;
1831 }
1832 if (cq->channel & 1) {
1833 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1834 slot = 0xC0;
1835 else
1836 slot = 0x80;
1837 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1838 __func__, slot);
1839 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1840 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1841 hc->hw.conn = (hc->hw.conn & ~7) | 6;
1842 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1843 }
1844 if (cq->channel & 2) {
1845 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1846 slot = 0xC1;
1847 else
1848 slot = 0x81;
1849 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1850 __func__, slot);
1851 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1852 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1853 hc->hw.conn = (hc->hw.conn & ~0x38) | 0x30;
1854 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1855 }
1856 if (cq->channel & 3)
1857 hc->hw.trm |= 0x80; /* enable IOM-loop */
1858 else {
1859 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1860 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1861 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1862 }
1863 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1864 break;
1865 case MISDN_CTRL_CONNECT:
1866 if (cq->channel == cq->p1) {
1867 ret = -EINVAL;
1868 break;
1869 }
1870 if (cq->channel < 1 || cq->channel > 2 ||
1871 cq->p1 < 1 || cq->p1 > 2) {
1872 ret = -EINVAL;
1873 break;
1874 }
1875 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1876 slot = 0xC0;
1877 else
1878 slot = 0x80;
1879 printk(KERN_DEBUG "%s: Write_hfc: B1_SSL/RSL 0x%x\n",
1880 __func__, slot);
1881 Write_hfc(hc, HFCPCI_B1_SSL, slot);
1882 Write_hfc(hc, HFCPCI_B2_RSL, slot);
1883 if (test_bit(HFC_CFG_SW_DD_DU, &hc->cfg))
1884 slot = 0xC1;
1885 else
1886 slot = 0x81;
1887 printk(KERN_DEBUG "%s: Write_hfc: B2_SSL/RSL 0x%x\n",
1888 __func__, slot);
1889 Write_hfc(hc, HFCPCI_B2_SSL, slot);
1890 Write_hfc(hc, HFCPCI_B1_RSL, slot);
1891 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x36;
1892 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1893 hc->hw.trm |= 0x80;
1894 Write_hfc(hc, HFCPCI_TRM, hc->hw.trm);
1895 break;
1896 case MISDN_CTRL_DISCONNECT:
1897 hc->hw.conn = (hc->hw.conn & ~0x3f) | 0x09;
1898 Write_hfc(hc, HFCPCI_CONNECT, hc->hw.conn);
1899 hc->hw.trm &= 0x7f; /* disable IOM-loop */
1900 break;
1901 default:
1902 printk(KERN_WARNING "%s: unknown Op %x\n",
1903 __func__, cq->op);
1904 ret = -EINVAL;
1905 break;
1906 }
1907 return ret;
1908}
1909
1910static int
1911open_dchannel(struct hfc_pci *hc, struct mISDNchannel *ch,
1912 struct channel_req *rq)
1913{
1914 int err = 0;
1915
1916 if (debug & DEBUG_HW_OPEN)
1917 printk(KERN_DEBUG "%s: dev(%d) open from %p\n", __func__,
1918 hc->dch.dev.id, __builtin_return_address(0));
1919 if (rq->protocol == ISDN_P_NONE)
1920 return -EINVAL;
55a6af97
MB		 1921 if (rq->adr.channel == 1) {
1922 /* TODO: E-Channel */
1923 return -EINVAL;
1924 }
1700fe1a
KK		 1925 if (!hc->initdone) {
1926 if (rq->protocol == ISDN_P_TE_S0) {
1927 err = create_l1(&hc->dch, hfc_l1callback);
1928 if (err)
1929 return err;
1930 }
1931 hc->hw.protocol = rq->protocol;
1932 ch->protocol = rq->protocol;
1933 err = init_card(hc);
1934 if (err)
1935 return err;
1936 } else {
1937 if (rq->protocol != ch->protocol) {
1938 if (hc->hw.protocol == ISDN_P_TE_S0)
1939 l1_event(hc->dch.l1, CLOSE_CHANNEL);
c3b3cdeb
AE		 1940 if (rq->protocol == ISDN_P_TE_S0) {
1941 err = create_l1(&hc->dch, hfc_l1callback);
1942 if (err)
1943 return err;
1944 }
1700fe1a
KK		 1945 hc->hw.protocol = rq->protocol;
1946 ch->protocol = rq->protocol;
1947 hfcpci_setmode(hc);
1948 }
1949 }
1950
1951 if (((ch->protocol == ISDN_P_NT_S0) && (hc->dch.state == 3)) ||
1952 ((ch->protocol == ISDN_P_TE_S0) && (hc->dch.state == 7))) {
1953 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
1954 0, NULL, GFP_KERNEL);
1955 }
1956 rq->ch = ch;
1957 if (!try_module_get(THIS_MODULE))
1958 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1959 return 0;
1960}
1961
1962static int
1963open_bchannel(struct hfc_pci *hc, struct channel_req *rq)
1964{
1965 struct bchannel *bch;
1966
1967 if (rq->adr.channel > 2)
1968 return -EINVAL;
1969 if (rq->protocol == ISDN_P_NONE)
1970 return -EINVAL;
1971 bch = &hc->bch[rq->adr.channel - 1];
1972 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1973 return -EBUSY; /* b-channel can be only open once */
8dd2f36f 1974 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1700fe1a
KK		 1975 bch->ch.protocol = rq->protocol;
1976 rq->ch = &bch->ch; /* TODO: E-channel */
1977 if (!try_module_get(THIS_MODULE))
1978 printk(KERN_WARNING "%s:cannot get module\n", __func__);
1979 return 0;
1980}
1981
1982/*
1983 * device control function
1984 */
1985static int
1986hfc_dctrl(struct mISDNchannel *ch, u_int cmd, void *arg)
1987{
1988 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1989 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1990 struct hfc_pci *hc = dch->hw;
1991 struct channel_req *rq;
1992 int err = 0;
1993
1994 if (dch->debug & DEBUG_HW)
1995 printk(KERN_DEBUG "%s: cmd:%x %p\n",
1996 __func__, cmd, arg);
1997 switch (cmd) {
1998 case OPEN_CHANNEL:
1999 rq = arg;
a9b61830
MB		 2000 if ((rq->protocol == ISDN_P_TE_S0) ||
2001 (rq->protocol == ISDN_P_NT_S0))
1700fe1a
KK		 2002 err = open_dchannel(hc, ch, rq);
2003 else
2004 err = open_bchannel(hc, rq);
2005 break;
2006 case CLOSE_CHANNEL:
2007 if (debug & DEBUG_HW_OPEN)
2008 printk(KERN_DEBUG "%s: dev(%d) close from %p\n",
2009 __func__, hc->dch.dev.id,
2010 __builtin_return_address(0));
2011 module_put(THIS_MODULE);
2012 break;
2013 case CONTROL_CHANNEL:
2014 err = channel_ctrl(hc, arg);
2015 break;
2016 default:
2017 if (dch->debug & DEBUG_HW)
2018 printk(KERN_DEBUG "%s: unknown command %x\n",
2019 __func__, cmd);
2020 return -EINVAL;
2021 }
2022 return err;
2023}
2024
2025static int
2026setup_hw(struct hfc_pci *hc)
2027{
2028 void *buffer;
2029
2030 printk(KERN_INFO "mISDN: HFC-PCI driver %s\n", hfcpci_revision);
2031 hc->hw.cirm = 0;
2032 hc->dch.state = 0;
2033 pci_set_master(hc->pdev);
2034 if (!hc->irq) {
2035 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n");
2036 return 1;
2037 }
1532dcb7 2038 hc->hw.pci_io = (char __iomem *)(unsigned long)hc->pdev->resource[1].start;
1700fe1a
KK		 2039
2040 if (!hc->hw.pci_io) {
2041 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n");
2042 return 1;
2043 }
2044 /* Allocate memory for FIFOS */
2045 /* the memory needs to be on a 32k boundary within the first 4G */
2046 pci_set_dma_mask(hc->pdev, 0xFFFF8000);
2047 buffer = pci_alloc_consistent(hc->pdev, 0x8000, &hc->hw.dmahandle);
2048 /* We silently assume the address is okay if nonzero */
2049 if (!buffer) {
2050 printk(KERN_WARNING
2051 "HFC-PCI: Error allocating memory for FIFO!\n");
2052 return 1;
2053 }
2054 hc->hw.fifos = buffer;
2055 pci_write_config_dword(hc->pdev, 0x80, hc->hw.dmahandle);
2056 hc->hw.pci_io = ioremap((ulong) hc->hw.pci_io, 256);
2057 printk(KERN_INFO
2058 "HFC-PCI: defined at mem %#lx fifo %#lx(%#lx) IRQ %d HZ %d\n",
2059 (u_long) hc->hw.pci_io, (u_long) hc->hw.fifos,
7878ac81 2060 (u_long) hc->hw.dmahandle, hc->irq, HZ);
1700fe1a
KK		 2061 /* enable memory mapped ports, disable busmaster */
2062 pci_write_config_word(hc->pdev, PCI_COMMAND, PCI_ENA_MEMIO);
2063 hc->hw.int_m2 = 0;
2064 disable_hwirq(hc);
2065 hc->hw.int_m1 = 0;
2066 Write_hfc(hc, HFCPCI_INT_M1, hc->hw.int_m1);
2067 /* At this point the needed PCI config is done */
2068 /* fifos are still not enabled */
2069 hc->hw.timer.function = (void *) hfcpci_Timer;
2070 hc->hw.timer.data = (long) hc;
2071 init_timer(&hc->hw.timer);
2072 /* default PCM master */
2073 test_and_set_bit(HFC_CFG_MASTER, &hc->cfg);
2074 return 0;
2075}
2076
2077static void
2078release_card(struct hfc_pci *hc) {
2079 u_long flags;
2080
2081 spin_lock_irqsave(&hc->lock, flags);
2082 hc->hw.int_m2 = 0; /* interrupt output off ! */
2083 disable_hwirq(hc);
2084 mode_hfcpci(&hc->bch[0], 1, ISDN_P_NONE);
2085 mode_hfcpci(&hc->bch[1], 2, ISDN_P_NONE);
2086 if (hc->dch.timer.function != NULL) {
2087 del_timer(&hc->dch.timer);
2088 hc->dch.timer.function = NULL;
2089 }
2090 spin_unlock_irqrestore(&hc->lock, flags);
2091 if (hc->hw.protocol == ISDN_P_TE_S0)
2092 l1_event(hc->dch.l1, CLOSE_CHANNEL);
2093 if (hc->initdone)
2094 free_irq(hc->irq, hc);
2095 release_io_hfcpci(hc); /* must release after free_irq! */
2096 mISDN_unregister_device(&hc->dch.dev);
2097 mISDN_freebchannel(&hc->bch[1]);
2098 mISDN_freebchannel(&hc->bch[0]);
2099 mISDN_freedchannel(&hc->dch);
1700fe1a
KK		 2100 pci_set_drvdata(hc->pdev, NULL);
2101 kfree(hc);
2102}
2103
2104static int
2105setup_card(struct hfc_pci *card)
2106{
2107 int err = -EINVAL;
2108 u_int i;
1700fe1a
KK		 2109 char name[MISDN_MAX_IDLEN];
2110
1700fe1a
KK		 2111 card->dch.debug = debug;
2112 spin_lock_init(&card->lock);
2113 mISDN_initdchannel(&card->dch, MAX_DFRAME_LEN_L1, ph_state);
2114 card->dch.hw = card;
2115 card->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0) | (1 << ISDN_P_NT_S0);
2116 card->dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
2117 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
2118 card->dch.dev.D.send = hfcpci_l2l1D;
2119 card->dch.dev.D.ctrl = hfc_dctrl;
2120 card->dch.dev.nrbchan = 2;
2121 for (i = 0; i < 2; i++) {
2122 card->bch[i].nr = i + 1;
ff4cc1de 2123 set_channelmap(i + 1, card->dch.dev.channelmap);
1700fe1a
KK		 2124 card->bch[i].debug = debug;
2125 mISDN_initbchannel(&card->bch[i], MAX_DATA_MEM);
2126 card->bch[i].hw = card;
2127 card->bch[i].ch.send = hfcpci_l2l1B;
2128 card->bch[i].ch.ctrl = hfc_bctrl;
2129 card->bch[i].ch.nr = i + 1;
2130 list_add(&card->bch[i].ch.list, &card->dch.dev.bchannels);
2131 }
2132 err = setup_hw(card);
2133 if (err)
2134 goto error;
2135 snprintf(name, MISDN_MAX_IDLEN - 1, "hfc-pci.%d", HFC_cnt + 1);
b36b654a 2136 err = mISDN_register_device(&card->dch.dev, &card->pdev->dev, name);
1700fe1a
KK		 2137 if (err)
2138 goto error;
2139 HFC_cnt++;
1700fe1a
KK		 2140 printk(KERN_INFO "HFC %d cards installed\n", HFC_cnt);
2141 return 0;
2142error:
2143 mISDN_freebchannel(&card->bch[1]);
2144 mISDN_freebchannel(&card->bch[0]);
2145 mISDN_freedchannel(&card->dch);
2146 kfree(card);
2147 return err;
2148}
2149
2150/* private data in the PCI devices list */
2151struct _hfc_map {
2152 u_int subtype;
2153 u_int flag;
2154 char *name;
2155};
2156
2157static const struct _hfc_map hfc_map[] =
2158{
2159 {HFC_CCD_2BD0, 0, "CCD/Billion/Asuscom 2BD0"},
2160 {HFC_CCD_B000, 0, "Billion B000"},
2161 {HFC_CCD_B006, 0, "Billion B006"},
2162 {HFC_CCD_B007, 0, "Billion B007"},
2163 {HFC_CCD_B008, 0, "Billion B008"},
2164 {HFC_CCD_B009, 0, "Billion B009"},
2165 {HFC_CCD_B00A, 0, "Billion B00A"},
2166 {HFC_CCD_B00B, 0, "Billion B00B"},
2167 {HFC_CCD_B00C, 0, "Billion B00C"},
2168 {HFC_CCD_B100, 0, "Seyeon B100"},
2169 {HFC_CCD_B700, 0, "Primux II S0 B700"},
2170 {HFC_CCD_B701, 0, "Primux II S0 NT B701"},
2171 {HFC_ABOCOM_2BD1, 0, "Abocom/Magitek 2BD1"},
2172 {HFC_ASUS_0675, 0, "Asuscom/Askey 675"},
2173 {HFC_BERKOM_TCONCEPT, 0, "German telekom T-Concept"},
2174 {HFC_BERKOM_A1T, 0, "German telekom A1T"},
2175 {HFC_ANIGMA_MC145575, 0, "Motorola MC145575"},
2176 {HFC_ZOLTRIX_2BD0, 0, "Zoltrix 2BD0"},
2177 {HFC_DIGI_DF_M_IOM2_E, 0,
2178 "Digi International DataFire Micro V IOM2 (Europe)"},
2179 {HFC_DIGI_DF_M_E, 0,
2180 "Digi International DataFire Micro V (Europe)"},
2181 {HFC_DIGI_DF_M_IOM2_A, 0,
2182 "Digi International DataFire Micro V IOM2 (North America)"},
2183 {HFC_DIGI_DF_M_A, 0,
2184 "Digi International DataFire Micro V (North America)"},
2185 {HFC_SITECOM_DC105V2, 0, "Sitecom Connectivity DC-105 ISDN TA"},
2186 {},
2187};
2188
2189static struct pci_device_id hfc_ids[] =
2190{
2191 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_2BD0,
2192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[0]},
2193 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B000,
2194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[1]},
2195 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B006,
2196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[2]},
2197 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B007,
2198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[3]},
2199 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B008,
2200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[4]},
2201 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B009,
2202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[5]},
2203 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00A,
2204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[6]},
2205 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00B,
2206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[7]},
2207 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B00C,
2208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[8]},
2209 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B100,
2210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[9]},
2211 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B700,
2212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[10]},
2213 {PCI_VENDOR_ID_CCD, PCI_DEVICE_ID_CCD_B701,
2214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[11]},
2215 {PCI_VENDOR_ID_ABOCOM, PCI_DEVICE_ID_ABOCOM_2BD1,
2216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[12]},
2217 {PCI_VENDOR_ID_ASUSTEK, PCI_DEVICE_ID_ASUSTEK_0675,
2218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[13]},
2219 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT,
2220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[14]},
2221 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_A1T,
2222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[15]},
2223 {PCI_VENDOR_ID_ANIGMA, PCI_DEVICE_ID_ANIGMA_MC145575,
2224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[16]},
2225 {PCI_VENDOR_ID_ZOLTRIX, PCI_DEVICE_ID_ZOLTRIX_2BD0,
2226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[17]},
2227 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_E,
2228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[18]},
2229 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_E,
2230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[19]},
2231 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_IOM2_A,
2232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[20]},
2233 {PCI_VENDOR_ID_DIGI, PCI_DEVICE_ID_DIGI_DF_M_A,
2234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[21]},
2235 {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2,
2236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, (unsigned long) &hfc_map[22]},
2237 {},
2238};
2239
2240static int __devinit
2241hfc_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2242{
2243 int err = -ENOMEM;
2244 struct hfc_pci *card;
2245 struct _hfc_map *m = (struct _hfc_map *)ent->driver_data;
2246
2247 card = kzalloc(sizeof(struct hfc_pci), GFP_ATOMIC);
2248 if (!card) {
2249 printk(KERN_ERR "No kmem for HFC card\n");
2250 return err;
2251 }
2252 card->pdev = pdev;
2253 card->subtype = m->subtype;
2254 err = pci_enable_device(pdev);
2255 if (err) {
2256 kfree(card);
2257 return err;
2258 }
2259
2260 printk(KERN_INFO "mISDN_hfcpci: found adapter %s at %s\n",
2261 m->name, pci_name(pdev));
2262
2263 card->irq = pdev->irq;
2264 pci_set_drvdata(pdev, card);
2265 err = setup_card(card);
2266 if (err)
2267 pci_set_drvdata(pdev, NULL);
2268 return err;
2269}
2270
2271static void __devexit
2272hfc_remove_pci(struct pci_dev *pdev)
2273{
2274 struct hfc_pci *card = pci_get_drvdata(pdev);
1700fe1a 2275
b36b654a 2276 if (card)
1700fe1a 2277 release_card(card);
b36b654a 2278 else
1700fe1a 2279 if (debug)
b36b654a 2280 printk(KERN_WARNING "%s: drvdata already removed\n",
1700fe1a
KK		 2281 __func__);
2282}
2283
2284
2285static struct pci_driver hfc_driver = {
2286 .name = "hfcpci",
2287 .probe = hfc_probe,
2288 .remove = __devexit_p(hfc_remove_pci),
2289 .id_table = hfc_ids,
2290};
2291
b36b654a
MU		 2292static int
2293_hfcpci_softirq(struct device *dev, void *arg)
2294{
2295 struct hfc_pci *hc = dev_get_drvdata(dev);
2296 struct bchannel *bch;
2297 if (hc == NULL)
2298 return 0;
2299
2300 if (hc->hw.int_m2 & HFCPCI_IRQ_ENABLE) {
2301 spin_lock(&hc->lock);
2302 bch = Sel_BCS(hc, hc->hw.bswapped ? 2 : 1);
2303 if (bch && bch->state == ISDN_P_B_RAW) { /* B1 rx&tx */
2304 main_rec_hfcpci(bch);
2305 tx_birq(bch);
2306 }
2307 bch = Sel_BCS(hc, hc->hw.bswapped ? 1 : 2);
2308 if (bch && bch->state == ISDN_P_B_RAW) { /* B2 rx&tx */
2309 main_rec_hfcpci(bch);
2310 tx_birq(bch);
2311 }
2312 spin_unlock(&hc->lock);
2313 }
2314 return 0;
2315}
2316
2317static void
2318hfcpci_softirq(void *arg)
2319{
2320 (void) driver_for_each_device(&hfc_driver.driver, NULL, arg,
2321 _hfcpci_softirq);
2322
2323 /* if next event would be in the past ... */
2324 if ((s32)(hfc_jiffies + tics - jiffies) <= 0)
2325 hfc_jiffies = jiffies + 1;
2326 else
2327 hfc_jiffies += tics;
2328 hfc_tl.expires = hfc_jiffies;
2329 add_timer(&hfc_tl);
2330}
2331
1700fe1a
KK		 2332static int __init
2333HFC_init(void)
2334{
2335 int err;
2336
87c5fa1b
AE		 2337 if (!poll)
2338 poll = HFCPCI_BTRANS_THRESHOLD;
2339
2340 if (poll != HFCPCI_BTRANS_THRESHOLD) {
400fd978 2341 tics = (poll * HZ) / 8000;
87c5fa1b
AE		 2342 if (tics < 1)
2343 tics = 1;
400fd978 2344 poll = (tics * 8000) / HZ;
87c5fa1b
AE		 2345 if (poll > 256 || poll < 8) {
2346 printk(KERN_ERR "%s: Wrong poll value %d not in range "
2347 "of 8..256.\n", __func__, poll);
2348 err = -EINVAL;
2349 return err;
2350 }
2351 }
2352 if (poll != HFCPCI_BTRANS_THRESHOLD) {
2353 printk(KERN_INFO "%s: Using alternative poll value of %d\n",
2354 __func__, poll);
2355 hfc_tl.function = (void *)hfcpci_softirq;
2356 hfc_tl.data = 0;
2357 init_timer(&hfc_tl);
2358 hfc_tl.expires = jiffies + tics;
2359 hfc_jiffies = hfc_tl.expires;
2360 add_timer(&hfc_tl);
2361 } else
2362 tics = 0; /* indicate the use of controller's timer */
2363
1700fe1a 2364 err = pci_register_driver(&hfc_driver);
87c5fa1b
AE		 2365 if (err) {
2366 if (timer_pending(&hfc_tl))
2367 del_timer(&hfc_tl);
2368 }
2369
1700fe1a
KK		 2370 return err;
2371}
2372
2373static void __exit
2374HFC_cleanup(void)
2375{
87c5fa1b
AE		 2376 if (timer_pending(&hfc_tl))
2377 del_timer(&hfc_tl);
2378
1700fe1a
KK		 2379 pci_unregister_driver(&hfc_driver);
2380}
2381
2382module_init(HFC_init);
2383module_exit(HFC_cleanup);
e314f89a
MU		 2384
2385MODULE_DEVICE_TABLE(pci, hfc_ids);
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