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[mirror_ubuntu-zesty-kernel.git] / drivers / isdn / hardware / mISDN / mISDNipac.c
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cae86d4a
KK		 1/*
2 * isac.c ISAC specific routines
3 *
4 * Author Karsten Keil <keil@isdn4linux.de>
5 *
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
a6b7a407 23#include <linux/irqreturn.h>
5a0e3ad6 24#include <linux/slab.h>
cae86d4a
KK		 25#include <linux/module.h>
26#include <linux/mISDNhw.h>
27#include "ipac.h"
28
29
30#define DBUSY_TIMER_VALUE 80
31#define ARCOFI_USE 1
32
33#define ISAC_REV "2.0"
34
35MODULE_AUTHOR("Karsten Keil");
36MODULE_VERSION(ISAC_REV);
37MODULE_LICENSE("GPL v2");
38
39#define ReadISAC(is, o) (is->read_reg(is->dch.hw, o + is->off))
40#define WriteISAC(is, o, v) (is->write_reg(is->dch.hw, o + is->off, v))
41#define ReadHSCX(h, o) (h->ip->read_reg(h->ip->hw, h->off + o))
42#define WriteHSCX(h, o, v) (h->ip->write_reg(h->ip->hw, h->off + o, v))
43#define ReadIPAC(ip, o) (ip->read_reg(ip->hw, o))
44#define WriteIPAC(ip, o, v) (ip->write_reg(ip->hw, o, v))
45
46static inline void
47ph_command(struct isac_hw *isac, u8 command)
48{
49 pr_debug("%s: ph_command %x\n", isac->name, command);
50 if (isac->type & IPAC_TYPE_ISACX)
51 WriteISAC(isac, ISACX_CIX0, (command << 4) | 0xE);
52 else
53 WriteISAC(isac, ISAC_CIX0, (command << 2) | 3);
54}
55
56static void
57isac_ph_state_change(struct isac_hw *isac)
58{
59 switch (isac->state) {
60 case (ISAC_IND_RS):
61 case (ISAC_IND_EI):
62 ph_command(isac, ISAC_CMD_DUI);
63 }
64 schedule_event(&isac->dch, FLG_PHCHANGE);
65}
66
67static void
68isac_ph_state_bh(struct dchannel *dch)
69{
70 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
71
72 switch (isac->state) {
73 case ISAC_IND_RS:
74 case ISAC_IND_EI:
75 dch->state = 0;
76 l1_event(dch->l1, HW_RESET_IND);
77 break;
78 case ISAC_IND_DID:
79 dch->state = 3;
80 l1_event(dch->l1, HW_DEACT_CNF);
81 break;
82 case ISAC_IND_DR:
83 dch->state = 3;
84 l1_event(dch->l1, HW_DEACT_IND);
85 break;
86 case ISAC_IND_PU:
87 dch->state = 4;
88 l1_event(dch->l1, HW_POWERUP_IND);
89 break;
90 case ISAC_IND_RSY:
91 if (dch->state <= 5) {
92 dch->state = 5;
93 l1_event(dch->l1, ANYSIGNAL);
94 } else {
95 dch->state = 8;
96 l1_event(dch->l1, LOSTFRAMING);
97 }
98 break;
99 case ISAC_IND_ARD:
100 dch->state = 6;
101 l1_event(dch->l1, INFO2);
102 break;
103 case ISAC_IND_AI8:
104 dch->state = 7;
105 l1_event(dch->l1, INFO4_P8);
106 break;
107 case ISAC_IND_AI10:
108 dch->state = 7;
109 l1_event(dch->l1, INFO4_P10);
110 break;
111 }
112 pr_debug("%s: TE newstate %x\n", isac->name, dch->state);
113}
114
115void
116isac_empty_fifo(struct isac_hw *isac, int count)
117{
118 u8 *ptr;
119
120 pr_debug("%s: %s %d\n", isac->name, __func__, count);
121
122 if (!isac->dch.rx_skb) {
123 isac->dch.rx_skb = mI_alloc_skb(isac->dch.maxlen, GFP_ATOMIC);
124 if (!isac->dch.rx_skb) {
125 pr_info("%s: D receive out of memory\n", isac->name);
126 WriteISAC(isac, ISAC_CMDR, 0x80);
127 return;
128 }
129 }
130 if ((isac->dch.rx_skb->len + count) >= isac->dch.maxlen) {
131 pr_debug("%s: %s overrun %d\n", isac->name, __func__,
132 isac->dch.rx_skb->len + count);
133 WriteISAC(isac, ISAC_CMDR, 0x80);
134 return;
135 }
136 ptr = skb_put(isac->dch.rx_skb, count);
137 isac->read_fifo(isac->dch.hw, isac->off, ptr, count);
138 WriteISAC(isac, ISAC_CMDR, 0x80);
139 if (isac->dch.debug & DEBUG_HW_DFIFO) {
140 char pfx[MISDN_MAX_IDLEN + 16];
141
142 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-recv %s %d ",
143 isac->name, count);
144 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
145 }
146}
147
148static void
149isac_fill_fifo(struct isac_hw *isac)
150{
151 int count, more;
152 u8 *ptr;
153
154 if (!isac->dch.tx_skb)
155 return;
156 count = isac->dch.tx_skb->len - isac->dch.tx_idx;
157 if (count <= 0)
158 return;
159
160 more = 0;
161 if (count > 32) {
162 more = !0;
163 count = 32;
164 }
165 pr_debug("%s: %s %d\n", isac->name, __func__, count);
166 ptr = isac->dch.tx_skb->data + isac->dch.tx_idx;
167 isac->dch.tx_idx += count;
168 isac->write_fifo(isac->dch.hw, isac->off, ptr, count);
169 WriteISAC(isac, ISAC_CMDR, more ? 0x8 : 0xa);
170 if (test_and_set_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
171 pr_debug("%s: %s dbusytimer running\n", isac->name, __func__);
172 del_timer(&isac->dch.timer);
173 }
174 init_timer(&isac->dch.timer);
175 isac->dch.timer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000);
176 add_timer(&isac->dch.timer);
177 if (isac->dch.debug & DEBUG_HW_DFIFO) {
178 char pfx[MISDN_MAX_IDLEN + 16];
179
180 snprintf(pfx, MISDN_MAX_IDLEN + 15, "D-send %s %d ",
181 isac->name, count);
182 print_hex_dump_bytes(pfx, DUMP_PREFIX_OFFSET, ptr, count);
183 }
184}
185
186static void
187isac_rme_irq(struct isac_hw *isac)
188{
189 u8 val, count;
190
191 val = ReadISAC(isac, ISAC_RSTA);
192 if ((val & 0x70) != 0x20) {
193 if (val & 0x40) {
194 pr_debug("%s: ISAC RDO\n", isac->name);
195#ifdef ERROR_STATISTIC
196 isac->dch.err_rx++;
197#endif
198 }
199 if (!(val & 0x20)) {
200 pr_debug("%s: ISAC CRC error\n", isac->name);
201#ifdef ERROR_STATISTIC
202 isac->dch.err_crc++;
203#endif
204 }
205 WriteISAC(isac, ISAC_CMDR, 0x80);
206 if (isac->dch.rx_skb)
207 dev_kfree_skb(isac->dch.rx_skb);
208 isac->dch.rx_skb = NULL;
209 } else {
210 count = ReadISAC(isac, ISAC_RBCL) & 0x1f;
211 if (count == 0)
212 count = 32;
213 isac_empty_fifo(isac, count);
214 recv_Dchannel(&isac->dch);
215 }
216}
217
218static void
219isac_xpr_irq(struct isac_hw *isac)
220{
221 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
222 del_timer(&isac->dch.timer);
223 if (isac->dch.tx_skb && isac->dch.tx_idx < isac->dch.tx_skb->len) {
224 isac_fill_fifo(isac);
225 } else {
226 if (isac->dch.tx_skb)
227 dev_kfree_skb(isac->dch.tx_skb);
228 if (get_next_dframe(&isac->dch))
229 isac_fill_fifo(isac);
230 }
231}
232
233static void
234isac_retransmit(struct isac_hw *isac)
235{
236 if (test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags))
237 del_timer(&isac->dch.timer);
238 if (test_bit(FLG_TX_BUSY, &isac->dch.Flags)) {
239 /* Restart frame */
240 isac->dch.tx_idx = 0;
241 isac_fill_fifo(isac);
242 } else if (isac->dch.tx_skb) { /* should not happen */
243 pr_info("%s: tx_skb exist but not busy\n", isac->name);
244 test_and_set_bit(FLG_TX_BUSY, &isac->dch.Flags);
245 isac->dch.tx_idx = 0;
246 isac_fill_fifo(isac);
247 } else {
248 pr_info("%s: ISAC XDU no TX_BUSY\n", isac->name);
249 if (get_next_dframe(&isac->dch))
250 isac_fill_fifo(isac);
251 }
252}
253
254static void
255isac_mos_irq(struct isac_hw *isac)
256{
257 u8 val;
258 int ret;
259
260 val = ReadISAC(isac, ISAC_MOSR);
261 pr_debug("%s: ISAC MOSR %02x\n", isac->name, val);
262#if ARCOFI_USE
263 if (val & 0x08) {
264 if (!isac->mon_rx) {
265 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
266 if (!isac->mon_rx) {
267 pr_info("%s: ISAC MON RX out of memory!\n",
268 isac->name);
269 isac->mocr &= 0xf0;
270 isac->mocr |= 0x0a;
271 WriteISAC(isac, ISAC_MOCR, isac->mocr);
272 goto afterMONR0;
273 } else
274 isac->mon_rxp = 0;
275 }
276 if (isac->mon_rxp >= MAX_MON_FRAME) {
277 isac->mocr &= 0xf0;
278 isac->mocr |= 0x0a;
279 WriteISAC(isac, ISAC_MOCR, isac->mocr);
280 isac->mon_rxp = 0;
281 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
282 goto afterMONR0;
283 }
284 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR0);
285 pr_debug("%s: ISAC MOR0 %02x\n", isac->name,
286 isac->mon_rx[isac->mon_rxp - 1]);
287 if (isac->mon_rxp == 1) {
288 isac->mocr |= 0x04;
289 WriteISAC(isac, ISAC_MOCR, isac->mocr);
290 }
291 }
292afterMONR0:
293 if (val & 0x80) {
294 if (!isac->mon_rx) {
295 isac->mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC);
296 if (!isac->mon_rx) {
297 pr_info("%s: ISAC MON RX out of memory!\n",
298 isac->name);
299 isac->mocr &= 0x0f;
300 isac->mocr |= 0xa0;
301 WriteISAC(isac, ISAC_MOCR, isac->mocr);
302 goto afterMONR1;
303 } else
304 isac->mon_rxp = 0;
305 }
306 if (isac->mon_rxp >= MAX_MON_FRAME) {
307 isac->mocr &= 0x0f;
308 isac->mocr |= 0xa0;
309 WriteISAC(isac, ISAC_MOCR, isac->mocr);
310 isac->mon_rxp = 0;
311 pr_debug("%s: ISAC MON RX overflow!\n", isac->name);
312 goto afterMONR1;
313 }
314 isac->mon_rx[isac->mon_rxp++] = ReadISAC(isac, ISAC_MOR1);
315 pr_debug("%s: ISAC MOR1 %02x\n", isac->name,
316 isac->mon_rx[isac->mon_rxp - 1]);
317 isac->mocr |= 0x40;
318 WriteISAC(isac, ISAC_MOCR, isac->mocr);
319 }
320afterMONR1:
321 if (val & 0x04) {
322 isac->mocr &= 0xf0;
323 WriteISAC(isac, ISAC_MOCR, isac->mocr);
324 isac->mocr |= 0x0a;
325 WriteISAC(isac, ISAC_MOCR, isac->mocr);
326 if (isac->monitor) {
327 ret = isac->monitor(isac->dch.hw, MONITOR_RX_0,
328 isac->mon_rx, isac->mon_rxp);
329 if (ret)
330 kfree(isac->mon_rx);
331 } else {
332 pr_info("%s: MONITOR 0 received %d but no user\n",
333 isac->name, isac->mon_rxp);
334 kfree(isac->mon_rx);
335 }
336 isac->mon_rx = NULL;
337 isac->mon_rxp = 0;
338 }
339 if (val & 0x40) {
340 isac->mocr &= 0x0f;
341 WriteISAC(isac, ISAC_MOCR, isac->mocr);
342 isac->mocr |= 0xa0;
343 WriteISAC(isac, ISAC_MOCR, isac->mocr);
344 if (isac->monitor) {
345 ret = isac->monitor(isac->dch.hw, MONITOR_RX_1,
346 isac->mon_rx, isac->mon_rxp);
347 if (ret)
348 kfree(isac->mon_rx);
349 } else {
350 pr_info("%s: MONITOR 1 received %d but no user\n",
351 isac->name, isac->mon_rxp);
352 kfree(isac->mon_rx);
353 }
354 isac->mon_rx = NULL;
355 isac->mon_rxp = 0;
356 }
357 if (val & 0x02) {
358 if ((!isac->mon_tx) || (isac->mon_txc &&
359 (isac->mon_txp >= isac->mon_txc) && !(val & 0x08))) {
360 isac->mocr &= 0xf0;
361 WriteISAC(isac, ISAC_MOCR, isac->mocr);
362 isac->mocr |= 0x0a;
363 WriteISAC(isac, ISAC_MOCR, isac->mocr);
364 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
365 if (isac->monitor)
366 ret = isac->monitor(isac->dch.hw,
367 MONITOR_TX_0, NULL, 0);
368 }
369 kfree(isac->mon_tx);
370 isac->mon_tx = NULL;
371 isac->mon_txc = 0;
372 isac->mon_txp = 0;
373 goto AfterMOX0;
374 }
375 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
376 if (isac->monitor)
377 ret = isac->monitor(isac->dch.hw,
378 MONITOR_TX_0, NULL, 0);
379 kfree(isac->mon_tx);
380 isac->mon_tx = NULL;
381 isac->mon_txc = 0;
382 isac->mon_txp = 0;
383 goto AfterMOX0;
384 }
385 WriteISAC(isac, ISAC_MOX0, isac->mon_tx[isac->mon_txp++]);
386 pr_debug("%s: ISAC %02x -> MOX0\n", isac->name,
387 isac->mon_tx[isac->mon_txp - 1]);
388 }
389AfterMOX0:
390 if (val & 0x20) {
391 if ((!isac->mon_tx) || (isac->mon_txc &&
392 (isac->mon_txp >= isac->mon_txc) && !(val & 0x80))) {
393 isac->mocr &= 0x0f;
394 WriteISAC(isac, ISAC_MOCR, isac->mocr);
395 isac->mocr |= 0xa0;
396 WriteISAC(isac, ISAC_MOCR, isac->mocr);
397 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
398 if (isac->monitor)
399 ret = isac->monitor(isac->dch.hw,
400 MONITOR_TX_1, NULL, 0);
401 }
402 kfree(isac->mon_tx);
403 isac->mon_tx = NULL;
404 isac->mon_txc = 0;
405 isac->mon_txp = 0;
406 goto AfterMOX1;
407 }
408 if (isac->mon_txc && (isac->mon_txp >= isac->mon_txc)) {
409 if (isac->monitor)
410 ret = isac->monitor(isac->dch.hw,
411 MONITOR_TX_1, NULL, 0);
412 kfree(isac->mon_tx);
413 isac->mon_tx = NULL;
414 isac->mon_txc = 0;
415 isac->mon_txp = 0;
416 goto AfterMOX1;
417 }
418 WriteISAC(isac, ISAC_MOX1, isac->mon_tx[isac->mon_txp++]);
419 pr_debug("%s: ISAC %02x -> MOX1\n", isac->name,
420 isac->mon_tx[isac->mon_txp - 1]);
421 }
422AfterMOX1:
423 val = 0; /* dummy to avoid warning */
424#endif
425}
426
427static void
428isac_cisq_irq(struct isac_hw *isac) {
429 u8 val;
430
431 val = ReadISAC(isac, ISAC_CIR0);
432 pr_debug("%s: ISAC CIR0 %02X\n", isac->name, val);
433 if (val & 2) {
434 pr_debug("%s: ph_state change %x->%x\n", isac->name,
435 isac->state, (val >> 2) & 0xf);
436 isac->state = (val >> 2) & 0xf;
437 isac_ph_state_change(isac);
438 }
439 if (val & 1) {
440 val = ReadISAC(isac, ISAC_CIR1);
441 pr_debug("%s: ISAC CIR1 %02X\n", isac->name, val);
442 }
443}
444
445static void
446isacsx_cic_irq(struct isac_hw *isac)
447{
448 u8 val;
449
450 val = ReadISAC(isac, ISACX_CIR0);
451 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
452 if (val & ISACX_CIR0_CIC0) {
453 pr_debug("%s: ph_state change %x->%x\n", isac->name,
454 isac->state, val >> 4);
455 isac->state = val >> 4;
456 isac_ph_state_change(isac);
457 }
458}
459
460static void
461isacsx_rme_irq(struct isac_hw *isac)
462{
463 int count;
464 u8 val;
465
466 val = ReadISAC(isac, ISACX_RSTAD);
467 if ((val & (ISACX_RSTAD_VFR |
468 ISACX_RSTAD_RDO |
469 ISACX_RSTAD_CRC |
470 ISACX_RSTAD_RAB))
471 != (ISACX_RSTAD_VFR | ISACX_RSTAD_CRC)) {
472 pr_debug("%s: RSTAD %#x, dropped\n", isac->name, val);
473#ifdef ERROR_STATISTIC
474 if (val & ISACX_RSTAD_CRC)
475 isac->dch.err_rx++;
476 else
477 isac->dch.err_crc++;
478#endif
479 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
480 if (isac->dch.rx_skb)
481 dev_kfree_skb(isac->dch.rx_skb);
482 isac->dch.rx_skb = NULL;
483 } else {
484 count = ReadISAC(isac, ISACX_RBCLD) & 0x1f;
485 if (count == 0)
486 count = 32;
487 isac_empty_fifo(isac, count);
488 if (isac->dch.rx_skb) {
489 skb_trim(isac->dch.rx_skb, isac->dch.rx_skb->len - 1);
490 pr_debug("%s: dchannel received %d\n", isac->name,
491 isac->dch.rx_skb->len);
492 recv_Dchannel(&isac->dch);
493 }
494 }
495}
496
497irqreturn_t
498mISDNisac_irq(struct isac_hw *isac, u8 val)
499{
500 if (unlikely(!val))
501 return IRQ_NONE;
502 pr_debug("%s: ISAC interrupt %02x\n", isac->name, val);
503 if (isac->type & IPAC_TYPE_ISACX) {
504 if (val & ISACX__CIC)
505 isacsx_cic_irq(isac);
506 if (val & ISACX__ICD) {
507 val = ReadISAC(isac, ISACX_ISTAD);
508 pr_debug("%s: ISTAD %02x\n", isac->name, val);
509 if (val & ISACX_D_XDU) {
510 pr_debug("%s: ISAC XDU\n", isac->name);
511#ifdef ERROR_STATISTIC
512 isac->dch.err_tx++;
513#endif
514 isac_retransmit(isac);
515 }
516 if (val & ISACX_D_XMR) {
517 pr_debug("%s: ISAC XMR\n", isac->name);
518#ifdef ERROR_STATISTIC
519 isac->dch.err_tx++;
520#endif
521 isac_retransmit(isac);
522 }
523 if (val & ISACX_D_XPR)
524 isac_xpr_irq(isac);
525 if (val & ISACX_D_RFO) {
526 pr_debug("%s: ISAC RFO\n", isac->name);
527 WriteISAC(isac, ISACX_CMDRD, ISACX_CMDRD_RMC);
528 }
529 if (val & ISACX_D_RME)
530 isacsx_rme_irq(isac);
531 if (val & ISACX_D_RPF)
532 isac_empty_fifo(isac, 0x20);
533 }
534 } else {
535 if (val & 0x80) /* RME */
536 isac_rme_irq(isac);
537 if (val & 0x40) /* RPF */
538 isac_empty_fifo(isac, 32);
539 if (val & 0x10) /* XPR */
540 isac_xpr_irq(isac);
541 if (val & 0x04) /* CISQ */
542 isac_cisq_irq(isac);
543 if (val & 0x20) /* RSC - never */
544 pr_debug("%s: ISAC RSC interrupt\n", isac->name);
545 if (val & 0x02) /* SIN - never */
546 pr_debug("%s: ISAC SIN interrupt\n", isac->name);
547 if (val & 0x01) { /* EXI */
548 val = ReadISAC(isac, ISAC_EXIR);
549 pr_debug("%s: ISAC EXIR %02x\n", isac->name, val);
550 if (val & 0x80) /* XMR */
551 pr_debug("%s: ISAC XMR\n", isac->name);
552 if (val & 0x40) { /* XDU */
553 pr_debug("%s: ISAC XDU\n", isac->name);
554#ifdef ERROR_STATISTIC
555 isac->dch.err_tx++;
556#endif
557 isac_retransmit(isac);
558 }
559 if (val & 0x04) /* MOS */
560 isac_mos_irq(isac);
561 }
562 }
563 return IRQ_HANDLED;
564}
565EXPORT_SYMBOL(mISDNisac_irq);
566
567static int
568isac_l1hw(struct mISDNchannel *ch, struct sk_buff *skb)
569{
570 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
571 struct dchannel *dch = container_of(dev, struct dchannel, dev);
572 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
573 int ret = -EINVAL;
574 struct mISDNhead *hh = mISDN_HEAD_P(skb);
575 u32 id;
576 u_long flags;
577
578 switch (hh->prim) {
579 case PH_DATA_REQ:
580 spin_lock_irqsave(isac->hwlock, flags);
581 ret = dchannel_senddata(dch, skb);
582 if (ret > 0) { /* direct TX */
583 id = hh->id; /* skb can be freed */
584 isac_fill_fifo(isac);
585 ret = 0;
586 spin_unlock_irqrestore(isac->hwlock, flags);
587 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
588 } else
589 spin_unlock_irqrestore(isac->hwlock, flags);
590 return ret;
591 case PH_ACTIVATE_REQ:
592 ret = l1_event(dch->l1, hh->prim);
593 break;
594 case PH_DEACTIVATE_REQ:
595 test_and_clear_bit(FLG_L2_ACTIVATED, &dch->Flags);
596 ret = l1_event(dch->l1, hh->prim);
597 break;
598 }
599
600 if (!ret)
601 dev_kfree_skb(skb);
602 return ret;
603}
604
605static int
606isac_ctrl(struct isac_hw *isac, u32 cmd, u_long para)
607{
608 u8 tl = 0;
609 u_long flags;
610
611 switch (cmd) {
612 case HW_TESTLOOP:
613 spin_lock_irqsave(isac->hwlock, flags);
614 if (!(isac->type & IPAC_TYPE_ISACX)) {
615 /* TODO: implement for IPAC_TYPE_ISACX */
616 if (para & 1) /* B1 */
617 tl |= 0x0c;
618 else if (para & 2) /* B2 */
619 tl |= 0x3;
620 /* we only support IOM2 mode */
621 WriteISAC(isac, ISAC_SPCR, tl);
622 if (tl)
623 WriteISAC(isac, ISAC_ADF1, 0x8);
624 else
625 WriteISAC(isac, ISAC_ADF1, 0x0);
626 }
627 spin_unlock_irqrestore(isac->hwlock, flags);
628 break;
629 default:
630 pr_debug("%s: %s unknown command %x %lx\n", isac->name,
631 __func__, cmd, para);
632 return -1;
633 }
634 return 0;
635}
636
637static int
638isac_l1cmd(struct dchannel *dch, u32 cmd)
639{
640 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
641 u_long flags;
642
643 pr_debug("%s: cmd(%x) state(%02x)\n", isac->name, cmd, isac->state);
644 switch (cmd) {
645 case INFO3_P8:
646 spin_lock_irqsave(isac->hwlock, flags);
647 ph_command(isac, ISAC_CMD_AR8);
648 spin_unlock_irqrestore(isac->hwlock, flags);
649 break;
650 case INFO3_P10:
651 spin_lock_irqsave(isac->hwlock, flags);
652 ph_command(isac, ISAC_CMD_AR10);
653 spin_unlock_irqrestore(isac->hwlock, flags);
654 break;
655 case HW_RESET_REQ:
656 spin_lock_irqsave(isac->hwlock, flags);
657 if ((isac->state == ISAC_IND_EI) ||
658 (isac->state == ISAC_IND_DR) ||
659 (isac->state == ISAC_IND_RS))
660 ph_command(isac, ISAC_CMD_TIM);
661 else
662 ph_command(isac, ISAC_CMD_RS);
663 spin_unlock_irqrestore(isac->hwlock, flags);
664 break;
665 case HW_DEACT_REQ:
666 skb_queue_purge(&dch->squeue);
667 if (dch->tx_skb) {
668 dev_kfree_skb(dch->tx_skb);
669 dch->tx_skb = NULL;
670 }
671 dch->tx_idx = 0;
672 if (dch->rx_skb) {
673 dev_kfree_skb(dch->rx_skb);
674 dch->rx_skb = NULL;
675 }
676 test_and_clear_bit(FLG_TX_BUSY, &dch->Flags);
677 if (test_and_clear_bit(FLG_BUSY_TIMER, &dch->Flags))
678 del_timer(&dch->timer);
679 break;
680 case HW_POWERUP_REQ:
681 spin_lock_irqsave(isac->hwlock, flags);
682 ph_command(isac, ISAC_CMD_TIM);
683 spin_unlock_irqrestore(isac->hwlock, flags);
684 break;
685 case PH_ACTIVATE_IND:
686 test_and_set_bit(FLG_ACTIVE, &dch->Flags);
687 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
688 GFP_ATOMIC);
689 break;
690 case PH_DEACTIVATE_IND:
691 test_and_clear_bit(FLG_ACTIVE, &dch->Flags);
692 _queue_data(&dch->dev.D, cmd, MISDN_ID_ANY, 0, NULL,
693 GFP_ATOMIC);
694 break;
695 default:
696 pr_debug("%s: %s unknown command %x\n", isac->name,
697 __func__, cmd);
698 return -1;
699 }
700 return 0;
701}
702
703static void
704isac_release(struct isac_hw *isac)
705{
706 if (isac->type & IPAC_TYPE_ISACX)
707 WriteISAC(isac, ISACX_MASK, 0xff);
708 else
709 WriteISAC(isac, ISAC_MASK, 0xff);
710 if (isac->dch.timer.function != NULL) {
711 del_timer(&isac->dch.timer);
712 isac->dch.timer.function = NULL;
713 }
714 kfree(isac->mon_rx);
715 isac->mon_rx = NULL;
716 kfree(isac->mon_tx);
717 isac->mon_tx = NULL;
718 if (isac->dch.l1)
719 l1_event(isac->dch.l1, CLOSE_CHANNEL);
720 mISDN_freedchannel(&isac->dch);
721}
722
723static void
724dbusy_timer_handler(struct isac_hw *isac)
725{
726 int rbch, star;
727 u_long flags;
728
729 if (test_bit(FLG_BUSY_TIMER, &isac->dch.Flags)) {
730 spin_lock_irqsave(isac->hwlock, flags);
731 rbch = ReadISAC(isac, ISAC_RBCH);
732 star = ReadISAC(isac, ISAC_STAR);
733 pr_debug("%s: D-Channel Busy RBCH %02x STAR %02x\n",
734 isac->name, rbch, star);
735 if (rbch & ISAC_RBCH_XAC) /* D-Channel Busy */
736 test_and_set_bit(FLG_L1_BUSY, &isac->dch.Flags);
737 else {
738 /* discard frame; reset transceiver */
739 test_and_clear_bit(FLG_BUSY_TIMER, &isac->dch.Flags);
740 if (isac->dch.tx_idx)
741 isac->dch.tx_idx = 0;
742 else
743 pr_info("%s: ISAC D-Channel Busy no tx_idx\n",
744 isac->name);
745 /* Transmitter reset */
746 WriteISAC(isac, ISAC_CMDR, 0x01);
747 }
748 spin_unlock_irqrestore(isac->hwlock, flags);
749 }
750}
751
752static int
753open_dchannel(struct isac_hw *isac, struct channel_req *rq)
754{
755 pr_debug("%s: %s dev(%d) open from %p\n", isac->name, __func__,
756 isac->dch.dev.id, __builtin_return_address(1));
757 if (rq->protocol != ISDN_P_TE_S0)
758 return -EINVAL;
759 if (rq->adr.channel == 1)
760 /* E-Channel not supported */
761 return -EINVAL;
762 rq->ch = &isac->dch.dev.D;
763 rq->ch->protocol = rq->protocol;
764 if (isac->dch.state == 7)
765 _queue_data(rq->ch, PH_ACTIVATE_IND, MISDN_ID_ANY,
766 0, NULL, GFP_KERNEL);
767 return 0;
768}
769
770static const char *ISACVer[] =
771{"2086/2186 V1.1", "2085 B1", "2085 B2",
772 "2085 V2.3"};
773
774static int
775isac_init(struct isac_hw *isac)
776{
777 u8 val;
778 int err = 0;
779
780 if (!isac->dch.l1) {
781 err = create_l1(&isac->dch, isac_l1cmd);
782 if (err)
783 return err;
784 }
785 isac->mon_tx = NULL;
786 isac->mon_rx = NULL;
787 isac->dch.timer.function = (void *) dbusy_timer_handler;
788 isac->dch.timer.data = (long)isac;
789 init_timer(&isac->dch.timer);
790 isac->mocr = 0xaa;
791 if (isac->type & IPAC_TYPE_ISACX) {
792 /* Disable all IRQ */
793 WriteISAC(isac, ISACX_MASK, 0xff);
794 val = ReadISAC(isac, ISACX_STARD);
795 pr_debug("%s: ISACX STARD %x\n", isac->name, val);
796 val = ReadISAC(isac, ISACX_ISTAD);
797 pr_debug("%s: ISACX ISTAD %x\n", isac->name, val);
798 val = ReadISAC(isac, ISACX_ISTA);
799 pr_debug("%s: ISACX ISTA %x\n", isac->name, val);
800 /* clear LDD */
801 WriteISAC(isac, ISACX_TR_CONF0, 0x00);
802 /* enable transmitter */
803 WriteISAC(isac, ISACX_TR_CONF2, 0x00);
804 /* transparent mode 0, RAC, stop/go */
805 WriteISAC(isac, ISACX_MODED, 0xc9);
806 /* all HDLC IRQ unmasked */
807 val = ReadISAC(isac, ISACX_ID);
808 if (isac->dch.debug & DEBUG_HW)
809 pr_notice("%s: ISACX Design ID %x\n",
810 isac->name, val & 0x3f);
811 val = ReadISAC(isac, ISACX_CIR0);
812 pr_debug("%s: ISACX CIR0 %02X\n", isac->name, val);
813 isac->state = val >> 4;
814 isac_ph_state_change(isac);
815 ph_command(isac, ISAC_CMD_RS);
816 WriteISAC(isac, ISACX_MASK, IPACX__ON);
817 WriteISAC(isac, ISACX_MASKD, 0x00);
818 } else { /* old isac */
819 WriteISAC(isac, ISAC_MASK, 0xff);
820 val = ReadISAC(isac, ISAC_STAR);
821 pr_debug("%s: ISAC STAR %x\n", isac->name, val);
822 val = ReadISAC(isac, ISAC_MODE);
823 pr_debug("%s: ISAC MODE %x\n", isac->name, val);
824 val = ReadISAC(isac, ISAC_ADF2);
825 pr_debug("%s: ISAC ADF2 %x\n", isac->name, val);
826 val = ReadISAC(isac, ISAC_ISTA);
827 pr_debug("%s: ISAC ISTA %x\n", isac->name, val);
828 if (val & 0x01) {
829 val = ReadISAC(isac, ISAC_EXIR);
830 pr_debug("%s: ISAC EXIR %x\n", isac->name, val);
831 }
832 val = ReadISAC(isac, ISAC_RBCH);
833 if (isac->dch.debug & DEBUG_HW)
834 pr_notice("%s: ISAC version (%x): %s\n", isac->name,
835 val, ISACVer[(val >> 5) & 3]);
836 isac->type |= ((val >> 5) & 3);
837 if (!isac->adf2)
838 isac->adf2 = 0x80;
839 if (!(isac->adf2 & 0x80)) { /* only IOM 2 Mode */
840 pr_info("%s: only support IOM2 mode but adf2=%02x\n",
841 isac->name, isac->adf2);
842 isac_release(isac);
843 return -EINVAL;
844 }
845 WriteISAC(isac, ISAC_ADF2, isac->adf2);
846 WriteISAC(isac, ISAC_SQXR, 0x2f);
847 WriteISAC(isac, ISAC_SPCR, 0x00);
848 WriteISAC(isac, ISAC_STCR, 0x70);
849 WriteISAC(isac, ISAC_MODE, 0xc9);
850 WriteISAC(isac, ISAC_TIMR, 0x00);
851 WriteISAC(isac, ISAC_ADF1, 0x00);
852 val = ReadISAC(isac, ISAC_CIR0);
853 pr_debug("%s: ISAC CIR0 %x\n", isac->name, val);
854 isac->state = (val >> 2) & 0xf;
855 isac_ph_state_change(isac);
856 ph_command(isac, ISAC_CMD_RS);
857 WriteISAC(isac, ISAC_MASK, 0);
858 }
859 return err;
860}
861
862int
863mISDNisac_init(struct isac_hw *isac, void *hw)
864{
865 mISDN_initdchannel(&isac->dch, MAX_DFRAME_LEN_L1, isac_ph_state_bh);
866 isac->dch.hw = hw;
867 isac->dch.dev.D.send = isac_l1hw;
868 isac->init = isac_init;
869 isac->release = isac_release;
870 isac->ctrl = isac_ctrl;
871 isac->open = open_dchannel;
872 isac->dch.dev.Dprotocols = (1 << ISDN_P_TE_S0);
873 isac->dch.dev.nrbchan = 2;
874 return 0;
875}
876EXPORT_SYMBOL(mISDNisac_init);
877
878static void
879waitforCEC(struct hscx_hw *hx)
880{
881 u8 starb, to = 50;
882
883 while (to) {
884 starb = ReadHSCX(hx, IPAC_STARB);
885 if (!(starb & 0x04))
886 break;
887 udelay(1);
888 to--;
889 }
890 if (to < 50)
891 pr_debug("%s: B%1d CEC %d us\n", hx->ip->name, hx->bch.nr,
892 50 - to);
893 if (!to)
894 pr_info("%s: B%1d CEC timeout\n", hx->ip->name, hx->bch.nr);
895}
896
897
898static void
899waitforXFW(struct hscx_hw *hx)
900{
901 u8 starb, to = 50;
902
903 while (to) {
904 starb = ReadHSCX(hx, IPAC_STARB);
905 if ((starb & 0x44) == 0x40)
906 break;
907 udelay(1);
908 to--;
909 }
910 if (to < 50)
911 pr_debug("%s: B%1d XFW %d us\n", hx->ip->name, hx->bch.nr,
912 50 - to);
913 if (!to)
914 pr_info("%s: B%1d XFW timeout\n", hx->ip->name, hx->bch.nr);
915}
916
917static void
918hscx_cmdr(struct hscx_hw *hx, u8 cmd)
919{
920 if (hx->ip->type & IPAC_TYPE_IPACX)
921 WriteHSCX(hx, IPACX_CMDRB, cmd);
922 else {
923 waitforCEC(hx);
924 WriteHSCX(hx, IPAC_CMDRB, cmd);
925 }
926}
927
928static void
929hscx_empty_fifo(struct hscx_hw *hscx, u8 count)
930{
931 u8 *p;
932
933 pr_debug("%s: B%1d %d\n", hscx->ip->name, hscx->bch.nr, count);
934 if (!hscx->bch.rx_skb) {
935 hscx->bch.rx_skb = mI_alloc_skb(hscx->bch.maxlen, GFP_ATOMIC);
936 if (!hscx->bch.rx_skb) {
937 pr_info("%s: B receive out of memory\n",
938 hscx->ip->name);
939 hscx_cmdr(hscx, 0x80); /* RMC */
940 return;
941 }
942 }
943 if ((hscx->bch.rx_skb->len + count) > hscx->bch.maxlen) {
944 pr_debug("%s: overrun %d\n", hscx->ip->name,
945 hscx->bch.rx_skb->len + count);
946 skb_trim(hscx->bch.rx_skb, 0);
947 hscx_cmdr(hscx, 0x80); /* RMC */
948 return;
949 }
950 p = skb_put(hscx->bch.rx_skb, count);
951
952 if (hscx->ip->type & IPAC_TYPE_IPACX)
953 hscx->ip->read_fifo(hscx->ip->hw,
954 hscx->off + IPACX_RFIFOB, p, count);
955 else
956 hscx->ip->read_fifo(hscx->ip->hw,
957 hscx->off, p, count);
958
959 hscx_cmdr(hscx, 0x80); /* RMC */
960
961 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
962 snprintf(hscx->log, 64, "B%1d-recv %s %d ",
963 hscx->bch.nr, hscx->ip->name, count);
964 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
965 }
966}
967
968static void
969hscx_fill_fifo(struct hscx_hw *hscx)
970{
971 int count, more;
972 u8 *p;
973
974 if (!hscx->bch.tx_skb)
975 return;
976 count = hscx->bch.tx_skb->len - hscx->bch.tx_idx;
977 if (count <= 0)
978 return;
979 p = hscx->bch.tx_skb->data + hscx->bch.tx_idx;
980
981 more = test_bit(FLG_TRANSPARENT, &hscx->bch.Flags) ? 1 : 0;
982 if (count > hscx->fifo_size) {
983 count = hscx->fifo_size;
984 more = 1;
985 }
986 pr_debug("%s: B%1d %d/%d/%d\n", hscx->ip->name, hscx->bch.nr, count,
987 hscx->bch.tx_idx, hscx->bch.tx_skb->len);
988 hscx->bch.tx_idx += count;
989
990 if (hscx->ip->type & IPAC_TYPE_IPACX)
991 hscx->ip->write_fifo(hscx->ip->hw,
992 hscx->off + IPACX_XFIFOB, p, count);
993 else {
994 waitforXFW(hscx);
995 hscx->ip->write_fifo(hscx->ip->hw,
996 hscx->off, p, count);
997 }
998 hscx_cmdr(hscx, more ? 0x08 : 0x0a);
999
1000 if (hscx->bch.debug & DEBUG_HW_BFIFO) {
1001 snprintf(hscx->log, 64, "B%1d-send %s %d ",
1002 hscx->bch.nr, hscx->ip->name, count);
1003 print_hex_dump_bytes(hscx->log, DUMP_PREFIX_OFFSET, p, count);
1004 }
1005}
1006
1007static void
1008hscx_xpr(struct hscx_hw *hx)
1009{
1010 if (hx->bch.tx_skb && hx->bch.tx_idx < hx->bch.tx_skb->len)
1011 hscx_fill_fifo(hx);
1012 else {
1013 if (hx->bch.tx_skb) {
1014 /* send confirm, on trans, free on hdlc. */
1015 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags))
1016 confirm_Bsend(&hx->bch);
1017 dev_kfree_skb(hx->bch.tx_skb);
1018 }
1019 if (get_next_bframe(&hx->bch))
1020 hscx_fill_fifo(hx);
1021 }
1022}
1023
1024static void
1025ipac_rme(struct hscx_hw *hx)
1026{
1027 int count;
1028 u8 rstab;
1029
1030 if (hx->ip->type & IPAC_TYPE_IPACX)
1031 rstab = ReadHSCX(hx, IPACX_RSTAB);
1032 else
1033 rstab = ReadHSCX(hx, IPAC_RSTAB);
1034 pr_debug("%s: B%1d RSTAB %02x\n", hx->ip->name, hx->bch.nr, rstab);
1035 if ((rstab & 0xf0) != 0xa0) {
1036 /* !(VFR && !RDO && CRC && !RAB) */
1037 if (!(rstab & 0x80)) {
1038 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1039 pr_notice("%s: B%1d invalid frame\n",
1040 hx->ip->name, hx->bch.nr);
1041 }
1042 if (rstab & 0x40) {
1043 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1044 pr_notice("%s: B%1d RDO proto=%x\n",
1045 hx->ip->name, hx->bch.nr,
1046 hx->bch.state);
1047 }
1048 if (!(rstab & 0x20)) {
1049 if (hx->bch.debug & DEBUG_HW_BCHANNEL)
1050 pr_notice("%s: B%1d CRC error\n",
1051 hx->ip->name, hx->bch.nr);
1052 }
1053 hscx_cmdr(hx, 0x80); /* Do RMC */
1054 return;
1055 }
1056 if (hx->ip->type & IPAC_TYPE_IPACX)
1057 count = ReadHSCX(hx, IPACX_RBCLB);
1058 else
1059 count = ReadHSCX(hx, IPAC_RBCLB);
1060 count &= (hx->fifo_size - 1);
1061 if (count == 0)
1062 count = hx->fifo_size;
1063 hscx_empty_fifo(hx, count);
1064 if (!hx->bch.rx_skb)
1065 return;
1066 if (hx->bch.rx_skb->len < 2) {
1067 pr_debug("%s: B%1d frame to short %d\n",
1068 hx->ip->name, hx->bch.nr, hx->bch.rx_skb->len);
1069 skb_trim(hx->bch.rx_skb, 0);
1070 } else {
1071 skb_trim(hx->bch.rx_skb, hx->bch.rx_skb->len - 1);
1072 recv_Bchannel(&hx->bch, 0);
1073 }
1074}
1075
1076static void
1077ipac_irq(struct hscx_hw *hx, u8 ista)
1078{
1079 u8 istab, m, exirb = 0;
1080
1081 if (hx->ip->type & IPAC_TYPE_IPACX)
1082 istab = ReadHSCX(hx, IPACX_ISTAB);
1083 else if (hx->ip->type & IPAC_TYPE_IPAC) {
1084 istab = ReadHSCX(hx, IPAC_ISTAB);
1085 m = (hx->bch.nr & 1) ? IPAC__EXA : IPAC__EXB;
1086 if (m & ista) {
1087 exirb = ReadHSCX(hx, IPAC_EXIRB);
1088 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1089 hx->bch.nr, exirb);
1090 }
1091 } else if (hx->bch.nr & 2) { /* HSCX B */
1092 if (ista & (HSCX__EXA | HSCX__ICA))
1093 ipac_irq(&hx->ip->hscx[0], ista);
1094 if (ista & HSCX__EXB) {
1095 exirb = ReadHSCX(hx, IPAC_EXIRB);
1096 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1097 hx->bch.nr, exirb);
1098 }
1099 istab = ista & 0xF8;
1100 } else { /* HSCX A */
1101 istab = ReadHSCX(hx, IPAC_ISTAB);
1102 if (ista & HSCX__EXA) {
1103 exirb = ReadHSCX(hx, IPAC_EXIRB);
1104 pr_debug("%s: B%1d EXIRB %02x\n", hx->ip->name,
1105 hx->bch.nr, exirb);
1106 }
1107 istab = istab & 0xF8;
1108 }
1109 if (exirb & IPAC_B_XDU)
1110 istab |= IPACX_B_XDU;
1111 if (exirb & IPAC_B_RFO)
1112 istab |= IPACX_B_RFO;
1113 pr_debug("%s: B%1d ISTAB %02x\n", hx->ip->name, hx->bch.nr, istab);
1114
1115 if (!test_bit(FLG_ACTIVE, &hx->bch.Flags))
1116 return;
1117
1118 if (istab & IPACX_B_RME)
1119 ipac_rme(hx);
1120
1121 if (istab & IPACX_B_RPF) {
1122 hscx_empty_fifo(hx, hx->fifo_size);
1123 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
1124 /* receive transparent audio data */
1125 if (hx->bch.rx_skb)
1126 recv_Bchannel(&hx->bch, 0);
1127 }
1128 }
1129
1130 if (istab & IPACX_B_RFO) {
1131 pr_debug("%s: B%1d RFO error\n", hx->ip->name, hx->bch.nr);
1132 hscx_cmdr(hx, 0x40); /* RRES */
1133 }
1134
1135 if (istab & IPACX_B_XPR)
1136 hscx_xpr(hx);
1137
1138 if (istab & IPACX_B_XDU) {
1139 if (test_bit(FLG_TRANSPARENT, &hx->bch.Flags)) {
1140 hscx_fill_fifo(hx);
1141 return;
1142 }
1143 pr_debug("%s: B%1d XDU error at len %d\n", hx->ip->name,
1144 hx->bch.nr, hx->bch.tx_idx);
1145 hx->bch.tx_idx = 0;
1146 hscx_cmdr(hx, 0x01); /* XRES */
1147 }
1148}
1149
1150irqreturn_t
1151mISDNipac_irq(struct ipac_hw *ipac, int maxloop)
1152{
1153 int cnt = maxloop + 1;
1154 u8 ista, istad;
1155 struct isac_hw *isac = &ipac->isac;
1156
1157 if (ipac->type & IPAC_TYPE_IPACX) {
1158 ista = ReadIPAC(ipac, ISACX_ISTA);
1159 while (ista && cnt--) {
1160 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1161 if (ista & IPACX__ICA)
1162 ipac_irq(&ipac->hscx[0], ista);
1163 if (ista & IPACX__ICB)
1164 ipac_irq(&ipac->hscx[1], ista);
1165 if (ista & (ISACX__ICD | ISACX__CIC))
1166 mISDNisac_irq(&ipac->isac, ista);
1167 ista = ReadIPAC(ipac, ISACX_ISTA);
1168 }
1169 } else if (ipac->type & IPAC_TYPE_IPAC) {
1170 ista = ReadIPAC(ipac, IPAC_ISTA);
1171 while (ista && cnt--) {
1172 pr_debug("%s: ISTA %02x\n", ipac->name, ista);
1173 if (ista & (IPAC__ICD | IPAC__EXD)) {
1174 istad = ReadISAC(isac, ISAC_ISTA);
1175 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1176 if (istad & IPAC_D_TIN2)
1177 pr_debug("%s TIN2 irq\n", ipac->name);
1178 if (ista & IPAC__EXD)
1179 istad |= 1; /* ISAC EXI */
1180 mISDNisac_irq(isac, istad);
1181 }
1182 if (ista & (IPAC__ICA | IPAC__EXA))
1183 ipac_irq(&ipac->hscx[0], ista);
1184 if (ista & (IPAC__ICB | IPAC__EXB))
1185 ipac_irq(&ipac->hscx[1], ista);
1186 ista = ReadIPAC(ipac, IPAC_ISTA);
1187 }
1188 } else if (ipac->type & IPAC_TYPE_HSCX) {
1189 while (cnt) {
1190 ista = ReadIPAC(ipac, IPAC_ISTAB + ipac->hscx[1].off);
1191 pr_debug("%s: B2 ISTA %02x\n", ipac->name, ista);
1192 if (ista)
1193 ipac_irq(&ipac->hscx[1], ista);
1194 istad = ReadISAC(isac, ISAC_ISTA);
1195 pr_debug("%s: ISTAD %02x\n", ipac->name, istad);
1196 if (istad)
1197 mISDNisac_irq(isac, istad);
1198 if (0 == (ista | istad))
1199 break;
1200 cnt--;
1201 }
1202 }
1203 if (cnt > maxloop) /* only for ISAC/HSCX without PCI IRQ test */
1204 return IRQ_NONE;
1205 if (cnt < maxloop)
1206 pr_debug("%s: %d irqloops cpu%d\n", ipac->name,
1207 maxloop - cnt, smp_processor_id());
1208 if (maxloop && !cnt)
1209 pr_notice("%s: %d IRQ LOOP cpu%d\n", ipac->name,
1210 maxloop, smp_processor_id());
1211 return IRQ_HANDLED;
1212}
1213EXPORT_SYMBOL(mISDNipac_irq);
1214
1215static int
1216hscx_mode(struct hscx_hw *hscx, u32 bprotocol)
1217{
1218 pr_debug("%s: HSCX %c protocol %x-->%x ch %d\n", hscx->ip->name,
1219 '@' + hscx->bch.nr, hscx->bch.state, bprotocol, hscx->bch.nr);
1220 if (hscx->ip->type & IPAC_TYPE_IPACX) {
1221 if (hscx->bch.nr & 1) { /* B1 and ICA */
1222 WriteIPAC(hscx->ip, ISACX_BCHA_TSDP_BC1, 0x80);
1223 WriteIPAC(hscx->ip, ISACX_BCHA_CR, 0x88);
1224 } else { /* B2 and ICB */
1225 WriteIPAC(hscx->ip, ISACX_BCHB_TSDP_BC1, 0x81);
1226 WriteIPAC(hscx->ip, ISACX_BCHB_CR, 0x88);
1227 }
1228 switch (bprotocol) {
1229 case ISDN_P_NONE: /* init */
1230 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* rec off */
1231 WriteHSCX(hscx, IPACX_EXMB, 0x30); /* std adj. */
1232 WriteHSCX(hscx, IPACX_MASKB, 0xFF); /* ints off */
1233 hscx_cmdr(hscx, 0x41);
1234 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1235 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1236 break;
1237 case ISDN_P_B_RAW:
1238 WriteHSCX(hscx, IPACX_MODEB, 0x88); /* ex trans */
1239 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* trans */
1240 hscx_cmdr(hscx, 0x41);
1241 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1242 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1243 break;
1244 case ISDN_P_B_HDLC:
1245 WriteHSCX(hscx, IPACX_MODEB, 0xC0); /* trans */
1246 WriteHSCX(hscx, IPACX_EXMB, 0x00); /* hdlc,crc */
1247 hscx_cmdr(hscx, 0x41);
1248 WriteHSCX(hscx, IPACX_MASKB, IPACX_B_ON);
1249 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1250 break;
1251 default:
1252 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1253 bprotocol);
1254 return -ENOPROTOOPT;
1255 }
1256 } else if (hscx->ip->type & IPAC_TYPE_IPAC) { /* IPAC */
1257 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1258 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1259 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1260 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1261 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1262 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1263 switch (bprotocol) {
1264 case ISDN_P_NONE:
1265 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1266 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1267 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1268 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1269 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1270 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1271 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1272 break;
1273 case ISDN_P_B_RAW:
1274 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1275 WriteHSCX(hscx, IPAC_CCR1, 0x82);
1276 hscx_cmdr(hscx, 0x41);
1277 WriteHSCX(hscx, IPAC_MASKB, 0);
1278 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1279 break;
1280 case ISDN_P_B_HDLC:
1281 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1282 WriteHSCX(hscx, IPAC_CCR1, 0x8a);
1283 hscx_cmdr(hscx, 0x41);
1284 WriteHSCX(hscx, IPAC_MASKB, 0);
1285 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1286 break;
1287 default:
1288 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1289 bprotocol);
1290 return -ENOPROTOOPT;
1291 }
1292 } else if (hscx->ip->type & IPAC_TYPE_HSCX) { /* HSCX */
1293 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1294 WriteHSCX(hscx, IPAC_CCR2, 0x30);
1295 WriteHSCX(hscx, IPAC_XCCR, 0x07);
1296 WriteHSCX(hscx, IPAC_RCCR, 0x07);
1297 WriteHSCX(hscx, IPAC_TSAX, hscx->slot);
1298 WriteHSCX(hscx, IPAC_TSAR, hscx->slot);
1299 switch (bprotocol) {
1300 case ISDN_P_NONE:
1301 WriteHSCX(hscx, IPAC_TSAX, 0x1F);
1302 WriteHSCX(hscx, IPAC_TSAR, 0x1F);
1303 WriteHSCX(hscx, IPAC_MODEB, 0x84);
1304 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1305 WriteHSCX(hscx, IPAC_MASKB, 0xFF); /* ints off */
1306 test_and_clear_bit(FLG_HDLC, &hscx->bch.Flags);
1307 test_and_clear_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1308 break;
1309 case ISDN_P_B_RAW:
1310 WriteHSCX(hscx, IPAC_MODEB, 0xe4); /* ex trans */
1311 WriteHSCX(hscx, IPAC_CCR1, 0x85);
1312 hscx_cmdr(hscx, 0x41);
1313 WriteHSCX(hscx, IPAC_MASKB, 0);
1314 test_and_set_bit(FLG_TRANSPARENT, &hscx->bch.Flags);
1315 break;
1316 case ISDN_P_B_HDLC:
1317 WriteHSCX(hscx, IPAC_MODEB, 0x8c);
1318 WriteHSCX(hscx, IPAC_CCR1, 0x8d);
1319 hscx_cmdr(hscx, 0x41);
1320 WriteHSCX(hscx, IPAC_MASKB, 0);
1321 test_and_set_bit(FLG_HDLC, &hscx->bch.Flags);
1322 break;
1323 default:
1324 pr_info("%s: protocol not known %x\n", hscx->ip->name,
1325 bprotocol);
1326 return -ENOPROTOOPT;
1327 }
1328 } else
1329 return -EINVAL;
1330 hscx->bch.state = bprotocol;
1331 return 0;
1332}
1333
1334static int
1335hscx_l2l1(struct mISDNchannel *ch, struct sk_buff *skb)
1336{
1337 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1338 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1339 int ret = -EINVAL;
1340 struct mISDNhead *hh = mISDN_HEAD_P(skb);
1341 u32 id;
1342 u_long flags;
1343
1344 switch (hh->prim) {
1345 case PH_DATA_REQ:
1346 spin_lock_irqsave(hx->ip->hwlock, flags);
1347 ret = bchannel_senddata(bch, skb);
1348 if (ret > 0) { /* direct TX */
1349 id = hh->id; /* skb can be freed */
1350 ret = 0;
1351 hscx_fill_fifo(hx);
1352 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1353 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
1354 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
1355 } else
1356 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1357 return ret;
1358 case PH_ACTIVATE_REQ:
1359 spin_lock_irqsave(hx->ip->hwlock, flags);
1360 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
1361 ret = hscx_mode(hx, ch->protocol);
1362 else
1363 ret = 0;
1364 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1365 if (!ret)
1366 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
1367 NULL, GFP_KERNEL);
1368 break;
1369 case PH_DEACTIVATE_REQ:
1370 spin_lock_irqsave(hx->ip->hwlock, flags);
1371 mISDN_clear_bchannel(bch);
1372 hscx_mode(hx, ISDN_P_NONE);
1373 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1374 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
1375 NULL, GFP_KERNEL);
1376 ret = 0;
1377 break;
1378 default:
1379 pr_info("%s: %s unknown prim(%x,%x)\n",
1380 hx->ip->name, __func__, hh->prim, hh->id);
1381 ret = -EINVAL;
1382 }
1383 if (!ret)
1384 dev_kfree_skb(skb);
1385 return ret;
1386}
1387
1388static int
1389channel_bctrl(struct bchannel *bch, struct mISDN_ctrl_req *cq)
1390{
1391 int ret = 0;
1392
1393 switch (cq->op) {
1394 case MISDN_CTRL_GETOP:
1395 cq->op = 0;
1396 break;
1397 /* Nothing implemented yet */
1398 case MISDN_CTRL_FILL_EMPTY:
1399 default:
1400 pr_info("%s: unknown Op %x\n", __func__, cq->op);
1401 ret = -EINVAL;
1402 break;
1403 }
1404 return ret;
1405}
1406
1407static int
1408hscx_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1409{
1410 struct bchannel *bch = container_of(ch, struct bchannel, ch);
1411 struct hscx_hw *hx = container_of(bch, struct hscx_hw, bch);
1412 int ret = -EINVAL;
1413 u_long flags;
1414
1415 pr_debug("%s: %s cmd:%x %p\n", hx->ip->name, __func__, cmd, arg);
1416 switch (cmd) {
1417 case CLOSE_CHANNEL:
1418 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1419 if (test_bit(FLG_ACTIVE, &bch->Flags)) {
1420 spin_lock_irqsave(hx->ip->hwlock, flags);
1421 mISDN_freebchannel(bch);
1422 hscx_mode(hx, ISDN_P_NONE);
1423 spin_unlock_irqrestore(hx->ip->hwlock, flags);
1424 } else {
1425 skb_queue_purge(&bch->rqueue);
1426 bch->rcount = 0;
1427 }
1428 ch->protocol = ISDN_P_NONE;
1429 ch->peer = NULL;
1430 module_put(hx->ip->owner);
1431 ret = 0;
1432 break;
1433 case CONTROL_CHANNEL:
1434 ret = channel_bctrl(bch, arg);
1435 break;
1436 default:
1437 pr_info("%s: %s unknown prim(%x)\n",
1438 hx->ip->name, __func__, cmd);
1439 }
1440 return ret;
1441}
1442
1443static void
1444free_ipac(struct ipac_hw *ipac)
1445{
1446 isac_release(&ipac->isac);
1447}
1448
1449static const char *HSCXVer[] =
1450{"A1", "?1", "A2", "?3", "A3", "V2.1", "?6", "?7",
1451 "?8", "?9", "?10", "?11", "?12", "?13", "?14", "???"};
1452
1453
1454
1455static void
1456hscx_init(struct hscx_hw *hx)
1457{
1458 u8 val;
1459
1460 WriteHSCX(hx, IPAC_RAH2, 0xFF);
1461 WriteHSCX(hx, IPAC_XBCH, 0x00);
1462 WriteHSCX(hx, IPAC_RLCR, 0x00);
1463
1464 if (hx->ip->type & IPAC_TYPE_HSCX) {
1465 WriteHSCX(hx, IPAC_CCR1, 0x85);
1466 val = ReadHSCX(hx, HSCX_VSTR);
1467 pr_debug("%s: HSCX VSTR %02x\n", hx->ip->name, val);
1468 if (hx->bch.debug & DEBUG_HW)
1469 pr_notice("%s: HSCX version %s\n", hx->ip->name,
1470 HSCXVer[val & 0x0f]);
1471 } else
1472 WriteHSCX(hx, IPAC_CCR1, 0x82);
1473 WriteHSCX(hx, IPAC_CCR2, 0x30);
1474 WriteHSCX(hx, IPAC_XCCR, 0x07);
1475 WriteHSCX(hx, IPAC_RCCR, 0x07);
1476}
1477
1478static int
1479ipac_init(struct ipac_hw *ipac)
1480{
1481 u8 val;
1482
1483 if (ipac->type & IPAC_TYPE_HSCX) {
1484 hscx_init(&ipac->hscx[0]);
1485 hscx_init(&ipac->hscx[1]);
1486 val = ReadIPAC(ipac, IPAC_ID);
1487 } else if (ipac->type & IPAC_TYPE_IPAC) {
1488 hscx_init(&ipac->hscx[0]);
1489 hscx_init(&ipac->hscx[1]);
1490 WriteIPAC(ipac, IPAC_MASK, IPAC__ON);
1491 val = ReadIPAC(ipac, IPAC_CONF);
1492 /* conf is default 0, but can be overwritten by card setup */
1493 pr_debug("%s: IPAC CONF %02x/%02x\n", ipac->name,
1494 val, ipac->conf);
1495 WriteIPAC(ipac, IPAC_CONF, ipac->conf);
1496 val = ReadIPAC(ipac, IPAC_ID);
1497 if (ipac->hscx[0].bch.debug & DEBUG_HW)
1498 pr_notice("%s: IPAC Design ID %02x\n", ipac->name, val);
1499 }
1500 /* nothing special for IPACX to do here */
1501 return isac_init(&ipac->isac);
1502}
1503
1504static int
1505open_bchannel(struct ipac_hw *ipac, struct channel_req *rq)
1506{
1507 struct bchannel *bch;
1508
1509 if (rq->adr.channel > 2)
1510 return -EINVAL;
1511 if (rq->protocol == ISDN_P_NONE)
1512 return -EINVAL;
1513 bch = &ipac->hscx[rq->adr.channel - 1].bch;
1514 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
1515 return -EBUSY; /* b-channel can be only open once */
1516 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
1517 bch->ch.protocol = rq->protocol;
1518 rq->ch = &bch->ch;
1519 return 0;
1520}
1521
1522static int
1523channel_ctrl(struct ipac_hw *ipac, struct mISDN_ctrl_req *cq)
1524{
1525 int ret = 0;
1526
1527 switch (cq->op) {
1528 case MISDN_CTRL_GETOP:
1529 cq->op = MISDN_CTRL_LOOP;
1530 break;
1531 case MISDN_CTRL_LOOP:
1532 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
1533 if (cq->channel < 0 || cq->channel > 3) {
1534 ret = -EINVAL;
1535 break;
1536 }
1537 ret = ipac->ctrl(ipac, HW_TESTLOOP, cq->channel);
1538 break;
1539 default:
1540 pr_info("%s: unknown CTRL OP %x\n", ipac->name, cq->op);
1541 ret = -EINVAL;
1542 break;
1543 }
1544 return ret;
1545}
1546
1547static int
1548ipac_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
1549{
1550 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
1551 struct dchannel *dch = container_of(dev, struct dchannel, dev);
1552 struct isac_hw *isac = container_of(dch, struct isac_hw, dch);
1553 struct ipac_hw *ipac = container_of(isac, struct ipac_hw, isac);
1554 struct channel_req *rq;
1555 int err = 0;
1556
1557 pr_debug("%s: DCTRL: %x %p\n", ipac->name, cmd, arg);
1558 switch (cmd) {
1559 case OPEN_CHANNEL:
1560 rq = arg;
1561 if (rq->protocol == ISDN_P_TE_S0)
1562 err = open_dchannel(isac, rq);
1563 else
1564 err = open_bchannel(ipac, rq);
1565 if (err)
1566 break;
1567 if (!try_module_get(ipac->owner))
1568 pr_info("%s: cannot get module\n", ipac->name);
1569 break;
1570 case CLOSE_CHANNEL:
1571 pr_debug("%s: dev(%d) close from %p\n", ipac->name,
1572 dch->dev.id, __builtin_return_address(0));
1573 module_put(ipac->owner);
1574 break;
1575 case CONTROL_CHANNEL:
1576 err = channel_ctrl(ipac, arg);
1577 break;
1578 default:
1579 pr_debug("%s: unknown DCTRL command %x\n", ipac->name, cmd);
1580 return -EINVAL;
1581 }
1582 return err;
1583}
1584
1585u32
1586mISDNipac_init(struct ipac_hw *ipac, void *hw)
1587{
1588 u32 ret;
1589 u8 i;
1590
1591 ipac->hw = hw;
1592 if (ipac->isac.dch.debug & DEBUG_HW)
1593 pr_notice("%s: ipac type %x\n", ipac->name, ipac->type);
1594 if (ipac->type & IPAC_TYPE_HSCX) {
1595 ipac->isac.type = IPAC_TYPE_ISAC;
1596 ipac->hscx[0].off = 0;
1597 ipac->hscx[1].off = 0x40;
1598 ipac->hscx[0].fifo_size = 32;
1599 ipac->hscx[1].fifo_size = 32;
1600 } else if (ipac->type & IPAC_TYPE_IPAC) {
1601 ipac->isac.type = IPAC_TYPE_IPAC | IPAC_TYPE_ISAC;
1602 ipac->hscx[0].off = 0;
1603 ipac->hscx[1].off = 0x40;
1604 ipac->hscx[0].fifo_size = 64;
1605 ipac->hscx[1].fifo_size = 64;
1606 } else if (ipac->type & IPAC_TYPE_IPACX) {
1607 ipac->isac.type = IPAC_TYPE_IPACX | IPAC_TYPE_ISACX;
1608 ipac->hscx[0].off = IPACX_OFF_ICA;
1609 ipac->hscx[1].off = IPACX_OFF_ICB;
1610 ipac->hscx[0].fifo_size = 64;
1611 ipac->hscx[1].fifo_size = 64;
1612 } else
1613 return 0;
1614
1615 mISDNisac_init(&ipac->isac, hw);
1616
1617 ipac->isac.dch.dev.D.ctrl = ipac_dctrl;
1618
1619 for (i = 0; i < 2; i++) {
1620 ipac->hscx[i].bch.nr = i + 1;
1621 set_channelmap(i + 1, ipac->isac.dch.dev.channelmap);
1622 list_add(&ipac->hscx[i].bch.ch.list,
1623 &ipac->isac.dch.dev.bchannels);
1624 mISDN_initbchannel(&ipac->hscx[i].bch, MAX_DATA_MEM);
1625 ipac->hscx[i].bch.ch.nr = i + 1;
1626 ipac->hscx[i].bch.ch.send = &hscx_l2l1;
1627 ipac->hscx[i].bch.ch.ctrl = hscx_bctrl;
1628 ipac->hscx[i].bch.hw = hw;
1629 ipac->hscx[i].ip = ipac;
1630 /* default values for IOM time slots
1631 * can be overwriten by card */
1632 ipac->hscx[i].slot = (i == 0) ? 0x2f : 0x03;
1633 }
1634
1635 ipac->init = ipac_init;
1636 ipac->release = free_ipac;
1637
1638 ret = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1639 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1640 return ret;
1641}
1642EXPORT_SYMBOL(mISDNipac_init);
1643
1644static int __init
1645isac_mod_init(void)
1646{
1647 pr_notice("mISDNipac module version %s\n", ISAC_REV);
1648 return 0;
1649}
1650
1651static void __exit
1652isac_mod_cleanup(void)
1653{
1654 pr_notice("mISDNipac module unloaded\n");
1655}
1656module_init(isac_mod_init);
1657module_exit(isac_mod_cleanup);
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