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mISDN: Cleanup channel also if it already was deactivated
[mirror_ubuntu-artful-kernel.git] / drivers / isdn / hardware / mISDN / netjet.c
CommitLineData
a900845e
KK		 1/*
2 * NETJet mISDN driver
3 *
4 * Author Karsten Keil <keil@isdn4linux.de>
5 *
6 * Copyright 2009 by Karsten Keil <keil@isdn4linux.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 *
21 */
22
a6b7a407 23#include <linux/interrupt.h>
a900845e
KK		 24#include <linux/module.h>
25#include <linux/pci.h>
26#include <linux/delay.h>
27#include <linux/mISDNhw.h>
5a0e3ad6 28#include <linux/slab.h>
a900845e
KK		 29#include "ipac.h"
30#include "iohelper.h"
31#include "netjet.h"
32#include <linux/isdn/hdlc.h>
33
34#define NETJET_REV "2.0"
35
36enum nj_types {
37 NETJET_S_TJ300,
38 NETJET_S_TJ320,
39 ENTERNOW__TJ320,
40};
41
42struct tiger_dma {
43 size_t size;
44 u32 *start;
45 int idx;
46 u32 dmastart;
47 u32 dmairq;
48 u32 dmaend;
49 u32 dmacur;
50};
51
52struct tiger_hw;
53
54struct tiger_ch {
55 struct bchannel bch;
56 struct tiger_hw *nj;
57 int idx;
58 int free;
59 int lastrx;
60 u16 rxstate;
61 u16 txstate;
62 struct isdnhdlc_vars hsend;
63 struct isdnhdlc_vars hrecv;
64 u8 *hsbuf;
65 u8 *hrbuf;
66};
67
68#define TX_INIT 0x0001
69#define TX_IDLE 0x0002
70#define TX_RUN 0x0004
71#define TX_UNDERRUN 0x0100
72#define RX_OVERRUN 0x0100
73
74#define LOG_SIZE 64
75
76struct tiger_hw {
77 struct list_head list;
78 struct pci_dev *pdev;
79 char name[MISDN_MAX_IDLEN];
80 enum nj_types typ;
81 int irq;
82 u32 irqcnt;
83 u32 base;
84 size_t base_s;
85 dma_addr_t dma;
86 void *dma_p;
87 spinlock_t lock; /* lock HW */
88 struct isac_hw isac;
89 struct tiger_dma send;
90 struct tiger_dma recv;
91 struct tiger_ch bc[2];
92 u8 ctrlreg;
93 u8 dmactrl;
94 u8 auxd;
95 u8 last_is0;
96 u8 irqmask0;
97 char log[LOG_SIZE];
98};
99
100static LIST_HEAD(Cards);
101static DEFINE_RWLOCK(card_lock); /* protect Cards */
102static u32 debug;
103static int nj_cnt;
104
105static void
106_set_debug(struct tiger_hw *card)
107{
108 card->isac.dch.debug = debug;
109 card->bc[0].bch.debug = debug;
110 card->bc[1].bch.debug = debug;
111}
112
113static int
114set_debug(const char *val, struct kernel_param *kp)
115{
116 int ret;
117 struct tiger_hw *card;
118
119 ret = param_set_uint(val, kp);
120 if (!ret) {
121 read_lock(&card_lock);
122 list_for_each_entry(card, &Cards, list)
123 _set_debug(card);
124 read_unlock(&card_lock);
125 }
126 return ret;
127}
128
129MODULE_AUTHOR("Karsten Keil");
130MODULE_LICENSE("GPL v2");
131MODULE_VERSION(NETJET_REV);
132module_param_call(debug, set_debug, param_get_uint, &debug, S_IRUGO | S_IWUSR);
133MODULE_PARM_DESC(debug, "Netjet debug mask");
134
135static void
136nj_disable_hwirq(struct tiger_hw *card)
137{
138 outb(0, card->base + NJ_IRQMASK0);
139 outb(0, card->base + NJ_IRQMASK1);
140}
141
142
143static u8
144ReadISAC_nj(void *p, u8 offset)
145{
146 struct tiger_hw *card = p;
147 u8 ret;
148
149 card->auxd &= 0xfc;
150 card->auxd |= (offset >> 4) & 3;
151 outb(card->auxd, card->base + NJ_AUXDATA);
152 ret = inb(card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
153 return ret;
154}
155
156static void
157WriteISAC_nj(void *p, u8 offset, u8 value)
158{
159 struct tiger_hw *card = p;
160
161 card->auxd &= 0xfc;
162 card->auxd |= (offset >> 4) & 3;
163 outb(card->auxd, card->base + NJ_AUXDATA);
164 outb(value, card->base + NJ_ISAC_OFF + ((offset & 0x0f) << 2));
165}
166
167static void
168ReadFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
169{
170 struct tiger_hw *card = p;
171
172 card->auxd &= 0xfc;
173 outb(card->auxd, card->base + NJ_AUXDATA);
174 insb(card->base + NJ_ISAC_OFF, data, size);
175}
176
177static void
178WriteFiFoISAC_nj(void *p, u8 offset, u8 *data, int size)
179{
180 struct tiger_hw *card = p;
181
182 card->auxd &= 0xfc;
183 outb(card->auxd, card->base + NJ_AUXDATA);
184 outsb(card->base + NJ_ISAC_OFF, data, size);
185}
186
187static void
188fill_mem(struct tiger_ch *bc, u32 idx, u32 cnt, u32 fill)
189{
190 struct tiger_hw *card = bc->bch.hw;
191 u32 mask = 0xff, val;
192
193 pr_debug("%s: B%1d fill %02x len %d idx %d/%d\n", card->name,
475be4d8 194 bc->bch.nr, fill, cnt, idx, card->send.idx);
a900845e
KK		 195 if (bc->bch.nr & 2) {
196 fill <<= 8;
197 mask <<= 8;
198 }
199 mask ^= 0xffffffff;
200 while (cnt--) {
201 val = card->send.start[idx];
202 val &= mask;
203 val |= fill;
204 card->send.start[idx++] = val;
205 if (idx >= card->send.size)
206 idx = 0;
207 }
208}
209
210static int
211mode_tiger(struct tiger_ch *bc, u32 protocol)
212{
213 struct tiger_hw *card = bc->bch.hw;
214
215 pr_debug("%s: B%1d protocol %x-->%x\n", card->name,
475be4d8 216 bc->bch.nr, bc->bch.state, protocol);
a900845e
KK		 217 switch (protocol) {
218 case ISDN_P_NONE:
219 if (bc->bch.state == ISDN_P_NONE)
220 break;
221 fill_mem(bc, 0, card->send.size, 0xff);
222 bc->bch.state = protocol;
223 /* only stop dma and interrupts if both channels NULL */
224 if ((card->bc[0].bch.state == ISDN_P_NONE) &&
225 (card->bc[1].bch.state == ISDN_P_NONE)) {
226 card->dmactrl = 0;
227 outb(card->dmactrl, card->base + NJ_DMACTRL);
228 outb(0, card->base + NJ_IRQMASK0);
229 }
230 test_and_clear_bit(FLG_HDLC, &bc->bch.Flags);
231 test_and_clear_bit(FLG_TRANSPARENT, &bc->bch.Flags);
232 bc->txstate = 0;
233 bc->rxstate = 0;
234 bc->lastrx = -1;
235 break;
236 case ISDN_P_B_RAW:
237 test_and_set_bit(FLG_TRANSPARENT, &bc->bch.Flags);
238 bc->bch.state = protocol;
239 bc->idx = 0;
475be4d8 240 bc->free = card->send.size / 2;
a900845e
KK		 241 bc->rxstate = 0;
242 bc->txstate = TX_INIT | TX_IDLE;
243 bc->lastrx = -1;
244 if (!card->dmactrl) {
245 card->dmactrl = 1;
246 outb(card->dmactrl, card->base + NJ_DMACTRL);
247 outb(0x0f, card->base + NJ_IRQMASK0);
248 }
249 break;
250 case ISDN_P_B_HDLC:
251 test_and_set_bit(FLG_HDLC, &bc->bch.Flags);
252 bc->bch.state = protocol;
253 bc->idx = 0;
475be4d8 254 bc->free = card->send.size / 2;
a900845e
KK		 255 bc->rxstate = 0;
256 bc->txstate = TX_INIT | TX_IDLE;
257 isdnhdlc_rcv_init(&bc->hrecv, 0);
258 isdnhdlc_out_init(&bc->hsend, 0);
259 bc->lastrx = -1;
260 if (!card->dmactrl) {
261 card->dmactrl = 1;
262 outb(card->dmactrl, card->base + NJ_DMACTRL);
263 outb(0x0f, card->base + NJ_IRQMASK0);
264 }
265 break;
266 default:
267 pr_info("%s: %s protocol %x not handled\n", card->name,
268 __func__, protocol);
269 return -ENOPROTOOPT;
270 }
271 card->send.dmacur = inl(card->base + NJ_DMA_READ_ADR);
272 card->recv.dmacur = inl(card->base + NJ_DMA_WRITE_ADR);
273 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
274 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
275 pr_debug("%s: %s ctrl %x irq %02x/%02x idx %d/%d\n",
475be4d8
JP		 276 card->name, __func__,
277 inb(card->base + NJ_DMACTRL),
278 inb(card->base + NJ_IRQMASK0),
279 inb(card->base + NJ_IRQSTAT0),
280 card->send.idx,
281 card->recv.idx);
a900845e
KK		 282 return 0;
283}
284
285static void
286nj_reset(struct tiger_hw *card)
287{
288 outb(0xff, card->base + NJ_CTRL); /* Reset On */
289 mdelay(1);
290
291 /* now edge triggered for TJ320 GE 13/07/00 */
292 /* see comment in IRQ function */
293 if (card->typ == NETJET_S_TJ320) /* TJ320 */
294 card->ctrlreg = 0x40; /* Reset Off and status read clear */
295 else
296 card->ctrlreg = 0x00; /* Reset Off and status read clear */
297 outb(card->ctrlreg, card->base + NJ_CTRL);
298 mdelay(10);
299
300 /* configure AUX pins (all output except ISAC IRQ pin) */
301 card->auxd = 0;
302 card->dmactrl = 0;
303 outb(~NJ_ISACIRQ, card->base + NJ_AUXCTRL);
304 outb(NJ_ISACIRQ, card->base + NJ_IRQMASK1);
305 outb(card->auxd, card->base + NJ_AUXDATA);
306}
307
308static int
309inittiger(struct tiger_hw *card)
310{
311 int i;
312
313 card->dma_p = pci_alloc_consistent(card->pdev, NJ_DMA_SIZE,
475be4d8 314 &card->dma);
a900845e
KK		 315 if (!card->dma_p) {
316 pr_info("%s: No DMA memory\n", card->name);
317 return -ENOMEM;
318 }
319 if ((u64)card->dma > 0xffffffff) {
320 pr_info("%s: DMA outside 32 bit\n", card->name);
321 return -ENOMEM;
322 }
323 for (i = 0; i < 2; i++) {
b42d9165 324 card->bc[i].hsbuf = kmalloc(NJ_DMA_TXSIZE, GFP_ATOMIC);
a900845e
KK		 325 if (!card->bc[i].hsbuf) {
326 pr_info("%s: no B%d send buffer\n", card->name, i + 1);
327 return -ENOMEM;
328 }
b42d9165 329 card->bc[i].hrbuf = kmalloc(NJ_DMA_RXSIZE, GFP_ATOMIC);
a900845e
KK		 330 if (!card->bc[i].hrbuf) {
331 pr_info("%s: no B%d recv buffer\n", card->name, i + 1);
332 return -ENOMEM;
333 }
334 }
335 memset(card->dma_p, 0xff, NJ_DMA_SIZE);
336
337 card->send.start = card->dma_p;
338 card->send.dmastart = (u32)card->dma;
339 card->send.dmaend = card->send.dmastart +
340 (4 * (NJ_DMA_TXSIZE - 1));
341 card->send.dmairq = card->send.dmastart +
342 (4 * ((NJ_DMA_TXSIZE / 2) - 1));
343 card->send.size = NJ_DMA_TXSIZE;
344
345 if (debug & DEBUG_HW)
346 pr_notice("%s: send buffer phy %#x - %#x - %#x virt %p"
475be4d8
JP		 347 " size %zu u32\n", card->name,
348 card->send.dmastart, card->send.dmairq,
349 card->send.dmaend, card->send.start, card->send.size);
a900845e
KK		 350
351 outl(card->send.dmastart, card->base + NJ_DMA_READ_START);
352 outl(card->send.dmairq, card->base + NJ_DMA_READ_IRQ);
353 outl(card->send.dmaend, card->base + NJ_DMA_READ_END);
354
355 card->recv.start = card->dma_p + (NJ_DMA_SIZE / 2);
356 card->recv.dmastart = (u32)card->dma + (NJ_DMA_SIZE / 2);
357 card->recv.dmaend = card->recv.dmastart +
358 (4 * (NJ_DMA_RXSIZE - 1));
359 card->recv.dmairq = card->recv.dmastart +
360 (4 * ((NJ_DMA_RXSIZE / 2) - 1));
361 card->recv.size = NJ_DMA_RXSIZE;
362
363 if (debug & DEBUG_HW)
364 pr_notice("%s: recv buffer phy %#x - %#x - %#x virt %p"
475be4d8
JP		 365 " size %zu u32\n", card->name,
366 card->recv.dmastart, card->recv.dmairq,
367 card->recv.dmaend, card->recv.start, card->recv.size);
a900845e
KK		 368
369 outl(card->recv.dmastart, card->base + NJ_DMA_WRITE_START);
370 outl(card->recv.dmairq, card->base + NJ_DMA_WRITE_IRQ);
371 outl(card->recv.dmaend, card->base + NJ_DMA_WRITE_END);
372 return 0;
373}
374
375static void
376read_dma(struct tiger_ch *bc, u32 idx, int cnt)
377{
378 struct tiger_hw *card = bc->bch.hw;
379 int i, stat;
380 u32 val;
381 u8 *p, *pn;
382
383 if (bc->lastrx == idx) {
384 bc->rxstate |= RX_OVERRUN;
385 pr_info("%s: B%1d overrun at idx %d\n", card->name,
386 bc->bch.nr, idx);
387 }
388 bc->lastrx = idx;
389 if (!bc->bch.rx_skb) {
390 bc->bch.rx_skb = mI_alloc_skb(bc->bch.maxlen, GFP_ATOMIC);
391 if (!bc->bch.rx_skb) {
392 pr_info("%s: B%1d receive out of memory\n",
393 card->name, bc->bch.nr);
394 return;
395 }
396 }
397
398 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags)) {
399 if ((bc->bch.rx_skb->len + cnt) > bc->bch.maxlen) {
400 pr_debug("%s: B%1d overrun %d\n", card->name,
475be4d8 401 bc->bch.nr, bc->bch.rx_skb->len + cnt);
a900845e
KK		 402 skb_trim(bc->bch.rx_skb, 0);
403 return;
404 }
405 p = skb_put(bc->bch.rx_skb, cnt);
406 } else
407 p = bc->hrbuf;
408
409 for (i = 0; i < cnt; i++) {
410 val = card->recv.start[idx++];
411 if (bc->bch.nr & 2)
412 val >>= 8;
413 if (idx >= card->recv.size)
414 idx = 0;
415 p[i] = val & 0xff;
416 }
417 pn = bc->hrbuf;
418next_frame:
419 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
420 stat = isdnhdlc_decode(&bc->hrecv, pn, cnt, &i,
475be4d8
JP		 421 bc->bch.rx_skb->data, bc->bch.maxlen);
422 if (stat > 0) /* valid frame received */
a900845e
KK		 423 p = skb_put(bc->bch.rx_skb, stat);
424 else if (stat == -HDLC_CRC_ERROR)
425 pr_info("%s: B%1d receive frame CRC error\n",
426 card->name, bc->bch.nr);
427 else if (stat == -HDLC_FRAMING_ERROR)
428 pr_info("%s: B%1d receive framing error\n",
429 card->name, bc->bch.nr);
430 else if (stat == -HDLC_LENGTH_ERROR)
431 pr_info("%s: B%1d receive frame too long (> %d)\n",
432 card->name, bc->bch.nr, bc->bch.maxlen);
433 } else
475be4d8 434 stat = cnt;
a900845e
KK		 435
436 if (stat > 0) {
437 if (debug & DEBUG_HW_BFIFO) {
438 snprintf(card->log, LOG_SIZE, "B%1d-recv %s %d ",
475be4d8 439 bc->bch.nr, card->name, stat);
a900845e 440 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET,
475be4d8 441 p, stat);
a900845e
KK		 442 }
443 recv_Bchannel(&bc->bch, 0);
444 }
445 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
446 pn += i;
447 cnt -= i;
448 if (!bc->bch.rx_skb) {
449 bc->bch.rx_skb = mI_alloc_skb(bc->bch.maxlen,
475be4d8 450 GFP_ATOMIC);
a900845e
KK		 451 if (!bc->bch.rx_skb) {
452 pr_info("%s: B%1d receive out of memory\n",
453 card->name, bc->bch.nr);
454 return;
455 }
456 }
457 if (cnt > 0)
458 goto next_frame;
459 }
460}
461
462static void
463recv_tiger(struct tiger_hw *card, u8 irq_stat)
464{
465 u32 idx;
466 int cnt = card->recv.size / 2;
467
468 /* Note receive is via the WRITE DMA channel */
469 card->last_is0 &= ~NJ_IRQM0_WR_MASK;
470 card->last_is0 |= (irq_stat & NJ_IRQM0_WR_MASK);
471
472 if (irq_stat & NJ_IRQM0_WR_END)
473 idx = cnt - 1;
474 else
475 idx = card->recv.size - 1;
476
477 if (test_bit(FLG_ACTIVE, &card->bc[0].bch.Flags))
478 read_dma(&card->bc[0], idx, cnt);
479 if (test_bit(FLG_ACTIVE, &card->bc[1].bch.Flags))
480 read_dma(&card->bc[1], idx, cnt);
481}
482
483/* sync with current DMA address at start or after exception */
484static void
485resync(struct tiger_ch *bc, struct tiger_hw *card)
486{
487 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
488 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
489 if (bc->free > card->send.size / 2)
490 bc->free = card->send.size / 2;
491 /* currently we simple sync to the next complete free area
492 * this hast the advantage that we have always maximum time to
493 * handle TX irq
494 */
495 if (card->send.idx < ((card->send.size / 2) - 1))
496 bc->idx = (card->recv.size / 2) - 1;
497 else
498 bc->idx = card->recv.size - 1;
499 bc->txstate = TX_RUN;
500 pr_debug("%s: %s B%1d free %d idx %d/%d\n", card->name,
475be4d8 501 __func__, bc->bch.nr, bc->free, bc->idx, card->send.idx);
a900845e
KK		 502}
503
504static int bc_next_frame(struct tiger_ch *);
505
506static void
507fill_hdlc_flag(struct tiger_ch *bc)
508{
509 struct tiger_hw *card = bc->bch.hw;
510 int count, i;
511 u32 m, v;
512 u8 *p;
513
514 if (bc->free == 0)
515 return;
516 pr_debug("%s: %s B%1d %d state %x idx %d/%d\n", card->name,
475be4d8
JP		 517 __func__, bc->bch.nr, bc->free, bc->txstate,
518 bc->idx, card->send.idx);
a900845e
KK		 519 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
520 resync(bc, card);
521 count = isdnhdlc_encode(&bc->hsend, NULL, 0, &i,
475be4d8 522 bc->hsbuf, bc->free);
a900845e 523 pr_debug("%s: B%1d hdlc encoded %d flags\n", card->name,
475be4d8 524 bc->bch.nr, count);
a900845e
KK		 525 bc->free -= count;
526 p = bc->hsbuf;
527 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
528 for (i = 0; i < count; i++) {
529 if (bc->idx >= card->send.size)
530 bc->idx = 0;
531 v = card->send.start[bc->idx];
532 v &= m;
533 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
534 card->send.start[bc->idx++] = v;
535 }
536 if (debug & DEBUG_HW_BFIFO) {
537 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
475be4d8 538 bc->bch.nr, card->name, count);
a900845e
KK		 539 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
540 }
541}
542
543static void
544fill_dma(struct tiger_ch *bc)
545{
546 struct tiger_hw *card = bc->bch.hw;
547 int count, i;
548 u32 m, v;
549 u8 *p;
550
551 if (bc->free == 0)
552 return;
553 count = bc->bch.tx_skb->len - bc->bch.tx_idx;
554 if (count <= 0)
555 return;
556 pr_debug("%s: %s B%1d %d/%d/%d/%d state %x idx %d/%d\n", card->name,
475be4d8
JP		 557 __func__, bc->bch.nr, count, bc->free, bc->bch.tx_idx,
558 bc->bch.tx_skb->len, bc->txstate, bc->idx, card->send.idx);
a900845e
KK		 559 if (bc->txstate & (TX_IDLE | TX_INIT | TX_UNDERRUN))
560 resync(bc, card);
561 p = bc->bch.tx_skb->data + bc->bch.tx_idx;
562 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
563 count = isdnhdlc_encode(&bc->hsend, p, count, &i,
475be4d8 564 bc->hsbuf, bc->free);
a900845e 565 pr_debug("%s: B%1d hdlc encoded %d in %d\n", card->name,
475be4d8 566 bc->bch.nr, i, count);
a900845e
KK		 567 bc->bch.tx_idx += i;
568 bc->free -= count;
569 p = bc->hsbuf;
570 } else {
571 if (count > bc->free)
572 count = bc->free;
573 bc->bch.tx_idx += count;
574 bc->free -= count;
575 }
576 m = (bc->bch.nr & 1) ? 0xffffff00 : 0xffff00ff;
577 for (i = 0; i < count; i++) {
578 if (bc->idx >= card->send.size)
579 bc->idx = 0;
580 v = card->send.start[bc->idx];
581 v &= m;
582 v |= (bc->bch.nr & 1) ? (u32)(p[i]) : ((u32)(p[i])) << 8;
583 card->send.start[bc->idx++] = v;
584 }
585 if (debug & DEBUG_HW_BFIFO) {
586 snprintf(card->log, LOG_SIZE, "B%1d-send %s %d ",
475be4d8 587 bc->bch.nr, card->name, count);
a900845e
KK		 588 print_hex_dump_bytes(card->log, DUMP_PREFIX_OFFSET, p, count);
589 }
590 if (bc->free)
591 bc_next_frame(bc);
592}
593
594
595static int
596bc_next_frame(struct tiger_ch *bc)
597{
598 if (bc->bch.tx_skb && bc->bch.tx_idx < bc->bch.tx_skb->len)
599 fill_dma(bc);
600 else {
601 if (bc->bch.tx_skb) {
602 /* send confirm, on trans, free on hdlc. */
603 if (test_bit(FLG_TRANSPARENT, &bc->bch.Flags))
604 confirm_Bsend(&bc->bch);
605 dev_kfree_skb(bc->bch.tx_skb);
606 }
607 if (get_next_bframe(&bc->bch))
608 fill_dma(bc);
609 else
610 return 0;
611 }
612 return 1;
613}
614
615static void
616send_tiger_bc(struct tiger_hw *card, struct tiger_ch *bc)
617{
618 int ret;
619
620 bc->free += card->send.size / 2;
621 if (bc->free >= card->send.size) {
622 if (!(bc->txstate & (TX_UNDERRUN | TX_INIT))) {
623 pr_info("%s: B%1d TX underrun state %x\n", card->name,
624 bc->bch.nr, bc->txstate);
625 bc->txstate |= TX_UNDERRUN;
626 }
627 bc->free = card->send.size;
628 }
629 ret = bc_next_frame(bc);
630 if (!ret) {
631 if (test_bit(FLG_HDLC, &bc->bch.Flags)) {
632 fill_hdlc_flag(bc);
633 return;
634 }
635 pr_debug("%s: B%1d TX no data free %d idx %d/%d\n", card->name,
475be4d8 636 bc->bch.nr, bc->free, bc->idx, card->send.idx);
a900845e
KK		 637 if (!(bc->txstate & (TX_IDLE | TX_INIT))) {
638 fill_mem(bc, bc->idx, bc->free, 0xff);
639 if (bc->free == card->send.size)
640 bc->txstate |= TX_IDLE;
641 }
642 }
643}
644
645static void
646send_tiger(struct tiger_hw *card, u8 irq_stat)
647{
648 int i;
649
650 /* Note send is via the READ DMA channel */
651 if ((irq_stat & card->last_is0) & NJ_IRQM0_RD_MASK) {
652 pr_info("%s: tiger warn write double dma %x/%x\n",
653 card->name, irq_stat, card->last_is0);
654 return;
655 } else {
656 card->last_is0 &= ~NJ_IRQM0_RD_MASK;
657 card->last_is0 |= (irq_stat & NJ_IRQM0_RD_MASK);
658 }
659 for (i = 0; i < 2; i++) {
660 if (test_bit(FLG_ACTIVE, &card->bc[i].bch.Flags))
661 send_tiger_bc(card, &card->bc[i]);
662 }
663}
664
665static irqreturn_t
666nj_irq(int intno, void *dev_id)
667{
668 struct tiger_hw *card = dev_id;
669 u8 val, s1val, s0val;
670
671 spin_lock(&card->lock);
672 s0val = inb(card->base | NJ_IRQSTAT0);
673 s1val = inb(card->base | NJ_IRQSTAT1);
674 if ((s1val & NJ_ISACIRQ) && (s0val == 0)) {
675 /* shared IRQ */
676 spin_unlock(&card->lock);
677 return IRQ_NONE;
678 }
679 pr_debug("%s: IRQSTAT0 %02x IRQSTAT1 %02x\n", card->name, s0val, s1val);
680 card->irqcnt++;
681 if (!(s1val & NJ_ISACIRQ)) {
682 val = ReadISAC_nj(card, ISAC_ISTA);
683 if (val)
684 mISDNisac_irq(&card->isac, val);
685 }
686
687 if (s0val)
688 /* write to clear */
689 outb(s0val, card->base | NJ_IRQSTAT0);
690 else
691 goto end;
692 s1val = s0val;
693 /* set bits in sval to indicate which page is free */
694 card->recv.dmacur = inl(card->base | NJ_DMA_WRITE_ADR);
695 card->recv.idx = (card->recv.dmacur - card->recv.dmastart) >> 2;
696 if (card->recv.dmacur < card->recv.dmairq)
697 s0val = 0x08; /* the 2nd write area is free */
698 else
699 s0val = 0x04; /* the 1st write area is free */
700
701 card->send.dmacur = inl(card->base | NJ_DMA_READ_ADR);
702 card->send.idx = (card->send.dmacur - card->send.dmastart) >> 2;
703 if (card->send.dmacur < card->send.dmairq)
704 s0val |= 0x02; /* the 2nd read area is free */
705 else
706 s0val |= 0x01; /* the 1st read area is free */
707
708 pr_debug("%s: DMA Status %02x/%02x/%02x %d/%d\n", card->name,
475be4d8
JP		 709 s1val, s0val, card->last_is0,
710 card->recv.idx, card->send.idx);
a900845e
KK		 711 /* test if we have a DMA interrupt */
712 if (s0val != card->last_is0) {
713 if ((s0val & NJ_IRQM0_RD_MASK) !=
714 (card->last_is0 & NJ_IRQM0_RD_MASK))
715 /* got a write dma int */
716 send_tiger(card, s0val);
717 if ((s0val & NJ_IRQM0_WR_MASK) !=
718 (card->last_is0 & NJ_IRQM0_WR_MASK))
719 /* got a read dma int */
720 recv_tiger(card, s0val);
721 }
722end:
723 spin_unlock(&card->lock);
724 return IRQ_HANDLED;
725}
726
727static int
728nj_l2l1B(struct mISDNchannel *ch, struct sk_buff *skb)
729{
730 int ret = -EINVAL;
731 struct bchannel *bch = container_of(ch, struct bchannel, ch);
732 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
733 struct tiger_hw *card = bch->hw;
734 struct mISDNhead *hh = mISDN_HEAD_P(skb);
735 u32 id;
736 u_long flags;
737
738 switch (hh->prim) {
739 case PH_DATA_REQ:
740 spin_lock_irqsave(&card->lock, flags);
741 ret = bchannel_senddata(bch, skb);
742 if (ret > 0) { /* direct TX */
743 id = hh->id; /* skb can be freed */
744 fill_dma(bc);
745 ret = 0;
746 spin_unlock_irqrestore(&card->lock, flags);
747 if (!test_bit(FLG_TRANSPARENT, &bch->Flags))
748 queue_ch_frame(ch, PH_DATA_CNF, id, NULL);
749 } else
750 spin_unlock_irqrestore(&card->lock, flags);
751 return ret;
752 case PH_ACTIVATE_REQ:
753 spin_lock_irqsave(&card->lock, flags);
754 if (!test_and_set_bit(FLG_ACTIVE, &bch->Flags))
755 ret = mode_tiger(bc, ch->protocol);
756 else
757 ret = 0;
758 spin_unlock_irqrestore(&card->lock, flags);
759 if (!ret)
760 _queue_data(ch, PH_ACTIVATE_IND, MISDN_ID_ANY, 0,
475be4d8 761 NULL, GFP_KERNEL);
a900845e
KK		 762 break;
763 case PH_DEACTIVATE_REQ:
764 spin_lock_irqsave(&card->lock, flags);
765 mISDN_clear_bchannel(bch);
766 mode_tiger(bc, ISDN_P_NONE);
767 spin_unlock_irqrestore(&card->lock, flags);
768 _queue_data(ch, PH_DEACTIVATE_IND, MISDN_ID_ANY, 0,
475be4d8 769 NULL, GFP_KERNEL);
a900845e
KK		 770 ret = 0;
771 break;
772 }
773 if (!ret)
774 dev_kfree_skb(skb);
775 return ret;
776}
777
778static int
779channel_bctrl(struct tiger_ch *bc, struct mISDN_ctrl_req *cq)
780{
781 int ret = 0;
782 struct tiger_hw *card = bc->bch.hw;
783
784 switch (cq->op) {
785 case MISDN_CTRL_GETOP:
786 cq->op = 0;
787 break;
475be4d8 788 /* Nothing implemented yet */
a900845e
KK		 789 case MISDN_CTRL_FILL_EMPTY:
790 default:
791 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
792 ret = -EINVAL;
793 break;
794 }
795 return ret;
796}
797
798static int
799nj_bctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
800{
801 struct bchannel *bch = container_of(ch, struct bchannel, ch);
802 struct tiger_ch *bc = container_of(bch, struct tiger_ch, bch);
803 struct tiger_hw *card = bch->hw;
804 int ret = -EINVAL;
805 u_long flags;
806
807 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
808 switch (cmd) {
809 case CLOSE_CHANNEL:
810 test_and_clear_bit(FLG_OPEN, &bch->Flags);
1368112c
KK		 811 spin_lock_irqsave(&card->lock, flags);
812 mISDN_freebchannel(bch);
813 mode_tiger(bc, ISDN_P_NONE);
814 spin_unlock_irqrestore(&card->lock, flags);
a900845e
KK		 815 ch->protocol = ISDN_P_NONE;
816 ch->peer = NULL;
817 module_put(THIS_MODULE);
818 ret = 0;
819 break;
820 case CONTROL_CHANNEL:
821 ret = channel_bctrl(bc, arg);
822 break;
823 default:
824 pr_info("%s: %s unknown prim(%x)\n", card->name, __func__, cmd);
825 }
826 return ret;
827}
828
829static int
830channel_ctrl(struct tiger_hw *card, struct mISDN_ctrl_req *cq)
831{
832 int ret = 0;
833
834 switch (cq->op) {
835 case MISDN_CTRL_GETOP:
c626c127 836 cq->op = MISDN_CTRL_LOOP | MISDN_CTRL_L1_TIMER3;
a900845e
KK		 837 break;
838 case MISDN_CTRL_LOOP:
839 /* cq->channel: 0 disable, 1 B1 loop 2 B2 loop, 3 both */
840 if (cq->channel < 0 || cq->channel > 3) {
841 ret = -EINVAL;
842 break;
843 }
844 ret = card->isac.ctrl(&card->isac, HW_TESTLOOP, cq->channel);
845 break;
c626c127
KK		 846 case MISDN_CTRL_L1_TIMER3:
847 ret = card->isac.ctrl(&card->isac, HW_TIMER3_VALUE, cq->p1);
848 break;
a900845e
KK		 849 default:
850 pr_info("%s: %s unknown Op %x\n", card->name, __func__, cq->op);
851 ret = -EINVAL;
852 break;
853 }
854 return ret;
855}
856
857static int
858open_bchannel(struct tiger_hw *card, struct channel_req *rq)
859{
860 struct bchannel *bch;
861
819a1008 862 if (rq->adr.channel == 0 || rq->adr.channel > 2)
a900845e
KK		 863 return -EINVAL;
864 if (rq->protocol == ISDN_P_NONE)
865 return -EINVAL;
866 bch = &card->bc[rq->adr.channel - 1].bch;
867 if (test_and_set_bit(FLG_OPEN, &bch->Flags))
868 return -EBUSY; /* b-channel can be only open once */
869 test_and_clear_bit(FLG_FILLEMPTY, &bch->Flags);
870 bch->ch.protocol = rq->protocol;
871 rq->ch = &bch->ch;
872 return 0;
873}
874
875/*
876 * device control function
877 */
878static int
879nj_dctrl(struct mISDNchannel *ch, u32 cmd, void *arg)
880{
881 struct mISDNdevice *dev = container_of(ch, struct mISDNdevice, D);
882 struct dchannel *dch = container_of(dev, struct dchannel, dev);
883 struct tiger_hw *card = dch->hw;
884 struct channel_req *rq;
885 int err = 0;
886
887 pr_debug("%s: %s cmd:%x %p\n", card->name, __func__, cmd, arg);
888 switch (cmd) {
889 case OPEN_CHANNEL:
890 rq = arg;
891 if (rq->protocol == ISDN_P_TE_S0)
892 err = card->isac.open(&card->isac, rq);
893 else
894 err = open_bchannel(card, rq);
895 if (err)
896 break;
897 if (!try_module_get(THIS_MODULE))
898 pr_info("%s: cannot get module\n", card->name);
899 break;
900 case CLOSE_CHANNEL:
901 pr_debug("%s: dev(%d) close from %p\n", card->name, dch->dev.id,
475be4d8 902 __builtin_return_address(0));
a900845e
KK		 903 module_put(THIS_MODULE);
904 break;
905 case CONTROL_CHANNEL:
906 err = channel_ctrl(card, arg);
907 break;
908 default:
909 pr_debug("%s: %s unknown command %x\n",
475be4d8 910 card->name, __func__, cmd);
a900845e
KK		 911 return -EINVAL;
912 }
913 return err;
914}
915
916static int
917nj_init_card(struct tiger_hw *card)
918{
919 u_long flags;
920 int ret;
921
922 spin_lock_irqsave(&card->lock, flags);
923 nj_disable_hwirq(card);
924 spin_unlock_irqrestore(&card->lock, flags);
925
926 card->irq = card->pdev->irq;
927 if (request_irq(card->irq, nj_irq, IRQF_SHARED, card->name, card)) {
928 pr_info("%s: couldn't get interrupt %d\n",
929 card->name, card->irq);
930 card->irq = -1;
931 return -EIO;
932 }
933
934 spin_lock_irqsave(&card->lock, flags);
935 nj_reset(card);
936 ret = card->isac.init(&card->isac);
937 if (ret)
938 goto error;
939 ret = inittiger(card);
940 if (ret)
941 goto error;
942 mode_tiger(&card->bc[0], ISDN_P_NONE);
943 mode_tiger(&card->bc[1], ISDN_P_NONE);
944error:
945 spin_unlock_irqrestore(&card->lock, flags);
946 return ret;
947}
948
949
950static void
951nj_release(struct tiger_hw *card)
952{
953 u_long flags;
954 int i;
955
956 if (card->base_s) {
957 spin_lock_irqsave(&card->lock, flags);
958 nj_disable_hwirq(card);
959 mode_tiger(&card->bc[0], ISDN_P_NONE);
960 mode_tiger(&card->bc[1], ISDN_P_NONE);
961 card->isac.release(&card->isac);
962 spin_unlock_irqrestore(&card->lock, flags);
963 release_region(card->base, card->base_s);
964 card->base_s = 0;
965 }
966 if (card->irq > 0)
967 free_irq(card->irq, card);
968 if (card->isac.dch.dev.dev.class)
969 mISDN_unregister_device(&card->isac.dch.dev);
475be4d8 970
a900845e
KK		 971 for (i = 0; i < 2; i++) {
972 mISDN_freebchannel(&card->bc[i].bch);
973 kfree(card->bc[i].hsbuf);
974 kfree(card->bc[i].hrbuf);
975 }
976 if (card->dma_p)
977 pci_free_consistent(card->pdev, NJ_DMA_SIZE,
475be4d8 978 card->dma_p, card->dma);
a900845e
KK		 979 write_lock_irqsave(&card_lock, flags);
980 list_del(&card->list);
981 write_unlock_irqrestore(&card_lock, flags);
982 pci_clear_master(card->pdev);
983 pci_disable_device(card->pdev);
984 pci_set_drvdata(card->pdev, NULL);
985 kfree(card);
986}
987
988
989static int
990nj_setup(struct tiger_hw *card)
991{
992 card->base = pci_resource_start(card->pdev, 0);
993 card->base_s = pci_resource_len(card->pdev, 0);
994 if (!request_region(card->base, card->base_s, card->name)) {
995 pr_info("%s: NETjet config port %#x-%#x already in use\n",
996 card->name, card->base,
997 (u32)(card->base + card->base_s - 1));
998 card->base_s = 0;
999 return -EIO;
1000 }
1001 ASSIGN_FUNC(nj, ISAC, card->isac);
1002 return 0;
1003}
1004
1005
1006static int __devinit
1007setup_instance(struct tiger_hw *card)
1008{
1009 int i, err;
1010 u_long flags;
1011
1012 snprintf(card->name, MISDN_MAX_IDLEN - 1, "netjet.%d", nj_cnt + 1);
1013 write_lock_irqsave(&card_lock, flags);
1014 list_add_tail(&card->list, &Cards);
1015 write_unlock_irqrestore(&card_lock, flags);
1016
1017 _set_debug(card);
1018 card->isac.name = card->name;
1019 spin_lock_init(&card->lock);
1020 card->isac.hwlock = &card->lock;
1021 mISDNisac_init(&card->isac, card);
1022
1023 card->isac.dch.dev.Bprotocols = (1 << (ISDN_P_B_RAW & ISDN_P_B_MASK)) |
1024 (1 << (ISDN_P_B_HDLC & ISDN_P_B_MASK));
1025 card->isac.dch.dev.D.ctrl = nj_dctrl;
1026 for (i = 0; i < 2; i++) {
1027 card->bc[i].bch.nr = i + 1;
1028 set_channelmap(i + 1, card->isac.dch.dev.channelmap);
1029 mISDN_initbchannel(&card->bc[i].bch, MAX_DATA_MEM);
1030 card->bc[i].bch.hw = card;
1031 card->bc[i].bch.ch.send = nj_l2l1B;
1032 card->bc[i].bch.ch.ctrl = nj_bctrl;
1033 card->bc[i].bch.ch.nr = i + 1;
1034 list_add(&card->bc[i].bch.ch.list,
475be4d8 1035 &card->isac.dch.dev.bchannels);
a900845e
KK		 1036 card->bc[i].bch.hw = card;
1037 }
1038 err = nj_setup(card);
1039 if (err)
1040 goto error;
1041 err = mISDN_register_device(&card->isac.dch.dev, &card->pdev->dev,
475be4d8 1042 card->name);
a900845e
KK		 1043 if (err)
1044 goto error;
1045 err = nj_init_card(card);
1046 if (!err) {
1047 nj_cnt++;
1048 pr_notice("Netjet %d cards installed\n", nj_cnt);
1049 return 0;
1050 }
1051error:
1052 nj_release(card);
1053 return err;
1054}
1055
1056static int __devinit
1057nj_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1058{
1059 int err = -ENOMEM;
1060 int cfg;
1061 struct tiger_hw *card;
1062
1063 if (pdev->subsystem_vendor == 0x8086 &&
1064 pdev->subsystem_device == 0x0003) {
1065 pr_notice("Netjet: Digium X100P/X101P not handled\n");
1066 return -ENODEV;
1067 }
1068
1069 if (pdev->subsystem_vendor == 0x55 &&
1070 pdev->subsystem_device == 0x02) {
1071 pr_notice("Netjet: Enter!Now not handled yet\n");
1072 return -ENODEV;
1073 }
1074
367bbf2a 1075 if (pdev->subsystem_vendor == 0xb100 &&
475be4d8 1076 pdev->subsystem_device == 0x0003) {
367bbf2a
PB		 1077 pr_notice("Netjet: Digium TDM400P not handled yet\n");
1078 return -ENODEV;
1079 }
1080
a900845e
KK		 1081 card = kzalloc(sizeof(struct tiger_hw), GFP_ATOMIC);
1082 if (!card) {
1083 pr_info("No kmem for Netjet\n");
1084 return err;
1085 }
1086
1087 card->pdev = pdev;
1088
1089 err = pci_enable_device(pdev);
1090 if (err) {
1091 kfree(card);
1092 return err;
1093 }
1094
1095 printk(KERN_INFO "nj_probe(mISDN): found adapter at %s\n",
475be4d8 1096 pci_name(pdev));
a900845e
KK		 1097
1098 pci_set_master(pdev);
1099
1100 /* the TJ300 and TJ320 must be detected, the IRQ handling is different
1101 * unfortunately the chips use the same device ID, but the TJ320 has
1102 * the bit20 in status PCI cfg register set
1103 */
1104 pci_read_config_dword(pdev, 0x04, &cfg);
1105 if (cfg & 0x00100000)
1106 card->typ = NETJET_S_TJ320;
1107 else
1108 card->typ = NETJET_S_TJ300;
1109
1110 card->base = pci_resource_start(pdev, 0);
1111 card->irq = pdev->irq;
1112 pci_set_drvdata(pdev, card);
1113 err = setup_instance(card);
1114 if (err)
1115 pci_set_drvdata(pdev, NULL);
1116
1117 return err;
1118}
1119
1120
1121static void __devexit nj_remove(struct pci_dev *pdev)
1122{
1123 struct tiger_hw *card = pci_get_drvdata(pdev);
1124
1125 if (card)
1126 nj_release(card);
1127 else
1128 pr_info("%s drvdata already removed\n", __func__);
1129}
1130
1131/* We cannot select cards with PCI_SUB... IDs, since here are cards with
1132 * SUB IDs set to PCI_ANY_ID, so we need to match all and reject
1133 * known other cards which not work with this driver - see probe function */
1134static struct pci_device_id nj_pci_ids[] __devinitdata = {
1135 { PCI_VENDOR_ID_TIGERJET, PCI_DEVICE_ID_TIGERJET_300,
1136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1137 { }
1138};
1139MODULE_DEVICE_TABLE(pci, nj_pci_ids);
1140
1141static struct pci_driver nj_driver = {
1142 .name = "netjet",
1143 .probe = nj_probe,
1144 .remove = __devexit_p(nj_remove),
1145 .id_table = nj_pci_ids,
1146};
1147
1148static int __init nj_init(void)
1149{
1150 int err;
1151
1152 pr_notice("Netjet PCI driver Rev. %s\n", NETJET_REV);
1153 err = pci_register_driver(&nj_driver);
1154 return err;
1155}
1156
1157static void __exit nj_cleanup(void)
1158{
1159 pci_unregister_driver(&nj_driver);
1160}
1161
1162module_init(nj_init);
1163module_exit(nj_cleanup);
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