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KVM: VMX: Simplify vcpu_clear()
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CommitLineData
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
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19
20#include "vmx.h"
21#include "kvm.h"
22
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23#include <linux/types.h>
24#include <linux/string.h>
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25#include <linux/mm.h>
26#include <linux/highmem.h>
27#include <linux/module.h>
28
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29#include <asm/page.h>
30#include <asm/cmpxchg.h>
6aa8b732 31
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32#undef MMU_DEBUG
33
34#undef AUDIT
35
36#ifdef AUDIT
37static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
38#else
39static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
40#endif
41
42#ifdef MMU_DEBUG
43
44#define pgprintk(x...) do { if (dbg) printk(x); } while (0)
45#define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
46
47#else
48
49#define pgprintk(x...) do { } while (0)
50#define rmap_printk(x...) do { } while (0)
51
52#endif
53
54#if defined(MMU_DEBUG) || defined(AUDIT)
55static int dbg = 1;
56#endif
6aa8b732 57
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58#ifndef MMU_DEBUG
59#define ASSERT(x) do { } while (0)
60#else
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61#define ASSERT(x) \
62 if (!(x)) { \
63 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
64 __FILE__, __LINE__, #x); \
65 }
d6c69ee9 66#endif
6aa8b732 67
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68#define PT64_PT_BITS 9
69#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
70#define PT32_PT_BITS 10
71#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
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72
73#define PT_WRITABLE_SHIFT 1
74
75#define PT_PRESENT_MASK (1ULL << 0)
76#define PT_WRITABLE_MASK (1ULL << PT_WRITABLE_SHIFT)
77#define PT_USER_MASK (1ULL << 2)
78#define PT_PWT_MASK (1ULL << 3)
79#define PT_PCD_MASK (1ULL << 4)
80#define PT_ACCESSED_MASK (1ULL << 5)
81#define PT_DIRTY_MASK (1ULL << 6)
82#define PT_PAGE_SIZE_MASK (1ULL << 7)
83#define PT_PAT_MASK (1ULL << 7)
84#define PT_GLOBAL_MASK (1ULL << 8)
85#define PT64_NX_MASK (1ULL << 63)
86
87#define PT_PAT_SHIFT 7
88#define PT_DIR_PAT_SHIFT 12
89#define PT_DIR_PAT_MASK (1ULL << PT_DIR_PAT_SHIFT)
90
91#define PT32_DIR_PSE36_SIZE 4
92#define PT32_DIR_PSE36_SHIFT 13
93#define PT32_DIR_PSE36_MASK (((1ULL << PT32_DIR_PSE36_SIZE) - 1) << PT32_DIR_PSE36_SHIFT)
94
95
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96#define PT_FIRST_AVAIL_BITS_SHIFT 9
97#define PT64_SECOND_AVAIL_BITS_SHIFT 52
98
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99#define PT_SHADOW_IO_MARK (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
100
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101#define VALID_PAGE(x) ((x) != INVALID_PAGE)
102
103#define PT64_LEVEL_BITS 9
104
105#define PT64_LEVEL_SHIFT(level) \
106 ( PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS )
107
108#define PT64_LEVEL_MASK(level) \
109 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
110
111#define PT64_INDEX(address, level)\
112 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
113
114
115#define PT32_LEVEL_BITS 10
116
117#define PT32_LEVEL_SHIFT(level) \
118 ( PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS )
119
120#define PT32_LEVEL_MASK(level) \
121 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
122
123#define PT32_INDEX(address, level)\
124 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
125
126
27aba766 127#define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
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128#define PT64_DIR_BASE_ADDR_MASK \
129 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
130
131#define PT32_BASE_ADDR_MASK PAGE_MASK
132#define PT32_DIR_BASE_ADDR_MASK \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
134
135
136#define PFERR_PRESENT_MASK (1U << 0)
137#define PFERR_WRITE_MASK (1U << 1)
138#define PFERR_USER_MASK (1U << 2)
73b1087e 139#define PFERR_FETCH_MASK (1U << 4)
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140
141#define PT64_ROOT_LEVEL 4
142#define PT32_ROOT_LEVEL 2
143#define PT32E_ROOT_LEVEL 3
144
145#define PT_DIRECTORY_LEVEL 2
146#define PT_PAGE_TABLE_LEVEL 1
147
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148#define RMAP_EXT 4
149
150struct kvm_rmap_desc {
151 u64 *shadow_ptes[RMAP_EXT];
152 struct kvm_rmap_desc *more;
153};
154
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155static struct kmem_cache *pte_chain_cache;
156static struct kmem_cache *rmap_desc_cache;
d3d25b04 157static struct kmem_cache *mmu_page_header_cache;
b5a33a75 158
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159static u64 __read_mostly shadow_trap_nonpresent_pte;
160static u64 __read_mostly shadow_notrap_nonpresent_pte;
161
162void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
163{
164 shadow_trap_nonpresent_pte = trap_pte;
165 shadow_notrap_nonpresent_pte = notrap_pte;
166}
167EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
168
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169static int is_write_protection(struct kvm_vcpu *vcpu)
170{
707d92fa 171 return vcpu->cr0 & X86_CR0_WP;
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172}
173
174static int is_cpuid_PSE36(void)
175{
176 return 1;
177}
178
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179static int is_nx(struct kvm_vcpu *vcpu)
180{
181 return vcpu->shadow_efer & EFER_NX;
182}
183
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184static int is_present_pte(unsigned long pte)
185{
186 return pte & PT_PRESENT_MASK;
187}
188
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189static int is_shadow_present_pte(u64 pte)
190{
191 pte &= ~PT_SHADOW_IO_MARK;
192 return pte != shadow_trap_nonpresent_pte
193 && pte != shadow_notrap_nonpresent_pte;
194}
195
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196static int is_writeble_pte(unsigned long pte)
197{
198 return pte & PT_WRITABLE_MASK;
199}
200
201static int is_io_pte(unsigned long pte)
202{
203 return pte & PT_SHADOW_IO_MARK;
204}
205
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206static int is_rmap_pte(u64 pte)
207{
208 return (pte & (PT_WRITABLE_MASK | PT_PRESENT_MASK))
209 == (PT_WRITABLE_MASK | PT_PRESENT_MASK);
210}
211
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212static void set_shadow_pte(u64 *sptep, u64 spte)
213{
214#ifdef CONFIG_X86_64
215 set_64bit((unsigned long *)sptep, spte);
216#else
217 set_64bit((unsigned long long *)sptep, spte);
218#endif
219}
220
e2dec939 221static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
2e3e5882 222 struct kmem_cache *base_cache, int min)
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223{
224 void *obj;
225
226 if (cache->nobjs >= min)
e2dec939 227 return 0;
714b93da 228 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 229 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
714b93da 230 if (!obj)
e2dec939 231 return -ENOMEM;
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232 cache->objects[cache->nobjs++] = obj;
233 }
e2dec939 234 return 0;
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235}
236
237static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
238{
239 while (mc->nobjs)
240 kfree(mc->objects[--mc->nobjs]);
241}
242
c1158e63 243static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
2e3e5882 244 int min)
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245{
246 struct page *page;
247
248 if (cache->nobjs >= min)
249 return 0;
250 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
2e3e5882 251 page = alloc_page(GFP_KERNEL);
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252 if (!page)
253 return -ENOMEM;
254 set_page_private(page, 0);
255 cache->objects[cache->nobjs++] = page_address(page);
256 }
257 return 0;
258}
259
260static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
261{
262 while (mc->nobjs)
c4d198d5 263 free_page((unsigned long)mc->objects[--mc->nobjs]);
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264}
265
2e3e5882 266static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
714b93da 267{
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268 int r;
269
2e3e5882 270 kvm_mmu_free_some_pages(vcpu);
e2dec939 271 r = mmu_topup_memory_cache(&vcpu->mmu_pte_chain_cache,
2e3e5882 272 pte_chain_cache, 4);
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273 if (r)
274 goto out;
275 r = mmu_topup_memory_cache(&vcpu->mmu_rmap_desc_cache,
2e3e5882 276 rmap_desc_cache, 1);
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277 if (r)
278 goto out;
2e3e5882 279 r = mmu_topup_memory_cache_page(&vcpu->mmu_page_cache, 4);
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280 if (r)
281 goto out;
282 r = mmu_topup_memory_cache(&vcpu->mmu_page_header_cache,
2e3e5882 283 mmu_page_header_cache, 4);
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284out:
285 return r;
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286}
287
288static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
289{
290 mmu_free_memory_cache(&vcpu->mmu_pte_chain_cache);
291 mmu_free_memory_cache(&vcpu->mmu_rmap_desc_cache);
c1158e63 292 mmu_free_memory_cache_page(&vcpu->mmu_page_cache);
d3d25b04 293 mmu_free_memory_cache(&vcpu->mmu_page_header_cache);
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294}
295
296static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
297 size_t size)
298{
299 void *p;
300
301 BUG_ON(!mc->nobjs);
302 p = mc->objects[--mc->nobjs];
303 memset(p, 0, size);
304 return p;
305}
306
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307static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
308{
309 return mmu_memory_cache_alloc(&vcpu->mmu_pte_chain_cache,
310 sizeof(struct kvm_pte_chain));
311}
312
90cb0529 313static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
714b93da 314{
90cb0529 315 kfree(pc);
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316}
317
318static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
319{
320 return mmu_memory_cache_alloc(&vcpu->mmu_rmap_desc_cache,
321 sizeof(struct kvm_rmap_desc));
322}
323
90cb0529 324static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
714b93da 325{
90cb0529 326 kfree(rd);
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327}
328
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329/*
330 * Reverse mapping data structures:
331 *
332 * If page->private bit zero is zero, then page->private points to the
333 * shadow page table entry that points to page_address(page).
334 *
335 * If page->private bit zero is one, (then page->private & ~1) points
336 * to a struct kvm_rmap_desc containing more mappings.
337 */
714b93da 338static void rmap_add(struct kvm_vcpu *vcpu, u64 *spte)
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339{
340 struct page *page;
341 struct kvm_rmap_desc *desc;
342 int i;
343
344 if (!is_rmap_pte(*spte))
345 return;
346 page = pfn_to_page((*spte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT);
5972e953 347 if (!page_private(page)) {
cd4a4e53 348 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
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349 set_page_private(page,(unsigned long)spte);
350 } else if (!(page_private(page) & 1)) {
cd4a4e53 351 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
714b93da 352 desc = mmu_alloc_rmap_desc(vcpu);
5972e953 353 desc->shadow_ptes[0] = (u64 *)page_private(page);
cd4a4e53 354 desc->shadow_ptes[1] = spte;
5972e953 355 set_page_private(page,(unsigned long)desc | 1);
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356 } else {
357 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
5972e953 358 desc = (struct kvm_rmap_desc *)(page_private(page) & ~1ul);
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359 while (desc->shadow_ptes[RMAP_EXT-1] && desc->more)
360 desc = desc->more;
361 if (desc->shadow_ptes[RMAP_EXT-1]) {
714b93da 362 desc->more = mmu_alloc_rmap_desc(vcpu);
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363 desc = desc->more;
364 }
365 for (i = 0; desc->shadow_ptes[i]; ++i)
366 ;
367 desc->shadow_ptes[i] = spte;
368 }
369}
370
90cb0529 371static void rmap_desc_remove_entry(struct page *page,
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372 struct kvm_rmap_desc *desc,
373 int i,
374 struct kvm_rmap_desc *prev_desc)
375{
376 int j;
377
378 for (j = RMAP_EXT - 1; !desc->shadow_ptes[j] && j > i; --j)
379 ;
380 desc->shadow_ptes[i] = desc->shadow_ptes[j];
11718b4d 381 desc->shadow_ptes[j] = NULL;
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382 if (j != 0)
383 return;
384 if (!prev_desc && !desc->more)
5972e953 385 set_page_private(page,(unsigned long)desc->shadow_ptes[0]);
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386 else
387 if (prev_desc)
388 prev_desc->more = desc->more;
389 else
5972e953 390 set_page_private(page,(unsigned long)desc->more | 1);
90cb0529 391 mmu_free_rmap_desc(desc);
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392}
393
90cb0529 394static void rmap_remove(u64 *spte)
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395{
396 struct page *page;
397 struct kvm_rmap_desc *desc;
398 struct kvm_rmap_desc *prev_desc;
399 int i;
400
401 if (!is_rmap_pte(*spte))
402 return;
403 page = pfn_to_page((*spte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT);
5972e953 404 if (!page_private(page)) {
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405 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
406 BUG();
5972e953 407 } else if (!(page_private(page) & 1)) {
cd4a4e53 408 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
5972e953 409 if ((u64 *)page_private(page) != spte) {
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410 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
411 spte, *spte);
412 BUG();
413 }
5972e953 414 set_page_private(page,0);
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415 } else {
416 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
5972e953 417 desc = (struct kvm_rmap_desc *)(page_private(page) & ~1ul);
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418 prev_desc = NULL;
419 while (desc) {
420 for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i)
421 if (desc->shadow_ptes[i] == spte) {
90cb0529 422 rmap_desc_remove_entry(page,
714b93da 423 desc, i,
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424 prev_desc);
425 return;
426 }
427 prev_desc = desc;
428 desc = desc->more;
429 }
430 BUG();
431 }
432}
433
714b93da 434static void rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
374cbac0 435{
714b93da 436 struct kvm *kvm = vcpu->kvm;
374cbac0 437 struct page *page;
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438 struct kvm_rmap_desc *desc;
439 u64 *spte;
440
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441 page = gfn_to_page(kvm, gfn);
442 BUG_ON(!page);
374cbac0 443
5972e953
MR
444 while (page_private(page)) {
445 if (!(page_private(page) & 1))
446 spte = (u64 *)page_private(page);
374cbac0 447 else {
5972e953 448 desc = (struct kvm_rmap_desc *)(page_private(page) & ~1ul);
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449 spte = desc->shadow_ptes[0];
450 }
451 BUG_ON(!spte);
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452 BUG_ON((*spte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT
453 != page_to_pfn(page));
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454 BUG_ON(!(*spte & PT_PRESENT_MASK));
455 BUG_ON(!(*spte & PT_WRITABLE_MASK));
456 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
90cb0529 457 rmap_remove(spte);
e663ee64 458 set_shadow_pte(spte, *spte & ~PT_WRITABLE_MASK);
88a97f0b 459 kvm_flush_remote_tlbs(vcpu->kvm);
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460 }
461}
462
d6c69ee9 463#ifdef MMU_DEBUG
47ad8e68 464static int is_empty_shadow_page(u64 *spt)
6aa8b732 465{
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466 u64 *pos;
467 u64 *end;
468
47ad8e68 469 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
c7addb90 470 if ((*pos & ~PT_SHADOW_IO_MARK) != shadow_trap_nonpresent_pte) {
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471 printk(KERN_ERR "%s: %p %llx\n", __FUNCTION__,
472 pos, *pos);
6aa8b732 473 return 0;
139bdb2d 474 }
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475 return 1;
476}
d6c69ee9 477#endif
6aa8b732 478
90cb0529 479static void kvm_mmu_free_page(struct kvm *kvm,
4b02d6da 480 struct kvm_mmu_page *page_head)
260746c0 481{
47ad8e68 482 ASSERT(is_empty_shadow_page(page_head->spt));
d3d25b04 483 list_del(&page_head->link);
c1158e63 484 __free_page(virt_to_page(page_head->spt));
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485 kfree(page_head);
486 ++kvm->n_free_mmu_pages;
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487}
488
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489static unsigned kvm_page_table_hashfn(gfn_t gfn)
490{
491 return gfn;
492}
493
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494static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
495 u64 *parent_pte)
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496{
497 struct kvm_mmu_page *page;
498
d3d25b04 499 if (!vcpu->kvm->n_free_mmu_pages)
25c0de2c 500 return NULL;
6aa8b732 501
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502 page = mmu_memory_cache_alloc(&vcpu->mmu_page_header_cache,
503 sizeof *page);
504 page->spt = mmu_memory_cache_alloc(&vcpu->mmu_page_cache, PAGE_SIZE);
505 set_page_private(virt_to_page(page->spt), (unsigned long)page);
506 list_add(&page->link, &vcpu->kvm->active_mmu_pages);
47ad8e68 507 ASSERT(is_empty_shadow_page(page->spt));
6aa8b732 508 page->slot_bitmap = 0;
cea0f0e7 509 page->multimapped = 0;
6aa8b732 510 page->parent_pte = parent_pte;
ebeace86 511 --vcpu->kvm->n_free_mmu_pages;
25c0de2c 512 return page;
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513}
514
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515static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
516 struct kvm_mmu_page *page, u64 *parent_pte)
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517{
518 struct kvm_pte_chain *pte_chain;
519 struct hlist_node *node;
520 int i;
521
522 if (!parent_pte)
523 return;
524 if (!page->multimapped) {
525 u64 *old = page->parent_pte;
526
527 if (!old) {
528 page->parent_pte = parent_pte;
529 return;
530 }
531 page->multimapped = 1;
714b93da 532 pte_chain = mmu_alloc_pte_chain(vcpu);
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533 INIT_HLIST_HEAD(&page->parent_ptes);
534 hlist_add_head(&pte_chain->link, &page->parent_ptes);
535 pte_chain->parent_ptes[0] = old;
536 }
537 hlist_for_each_entry(pte_chain, node, &page->parent_ptes, link) {
538 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
539 continue;
540 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
541 if (!pte_chain->parent_ptes[i]) {
542 pte_chain->parent_ptes[i] = parent_pte;
543 return;
544 }
545 }
714b93da 546 pte_chain = mmu_alloc_pte_chain(vcpu);
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547 BUG_ON(!pte_chain);
548 hlist_add_head(&pte_chain->link, &page->parent_ptes);
549 pte_chain->parent_ptes[0] = parent_pte;
550}
551
90cb0529 552static void mmu_page_remove_parent_pte(struct kvm_mmu_page *page,
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553 u64 *parent_pte)
554{
555 struct kvm_pte_chain *pte_chain;
556 struct hlist_node *node;
557 int i;
558
559 if (!page->multimapped) {
560 BUG_ON(page->parent_pte != parent_pte);
561 page->parent_pte = NULL;
562 return;
563 }
564 hlist_for_each_entry(pte_chain, node, &page->parent_ptes, link)
565 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
566 if (!pte_chain->parent_ptes[i])
567 break;
568 if (pte_chain->parent_ptes[i] != parent_pte)
569 continue;
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570 while (i + 1 < NR_PTE_CHAIN_ENTRIES
571 && pte_chain->parent_ptes[i + 1]) {
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572 pte_chain->parent_ptes[i]
573 = pte_chain->parent_ptes[i + 1];
574 ++i;
575 }
576 pte_chain->parent_ptes[i] = NULL;
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577 if (i == 0) {
578 hlist_del(&pte_chain->link);
90cb0529 579 mmu_free_pte_chain(pte_chain);
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580 if (hlist_empty(&page->parent_ptes)) {
581 page->multimapped = 0;
582 page->parent_pte = NULL;
583 }
584 }
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585 return;
586 }
587 BUG();
588}
589
590static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm_vcpu *vcpu,
591 gfn_t gfn)
592{
593 unsigned index;
594 struct hlist_head *bucket;
595 struct kvm_mmu_page *page;
596 struct hlist_node *node;
597
598 pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn);
599 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
600 bucket = &vcpu->kvm->mmu_page_hash[index];
601 hlist_for_each_entry(page, node, bucket, hash_link)
602 if (page->gfn == gfn && !page->role.metaphysical) {
603 pgprintk("%s: found role %x\n",
604 __FUNCTION__, page->role.word);
605 return page;
606 }
607 return NULL;
608}
609
610static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
611 gfn_t gfn,
612 gva_t gaddr,
613 unsigned level,
614 int metaphysical,
d28c6cfb 615 unsigned hugepage_access,
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616 u64 *parent_pte)
617{
618 union kvm_mmu_page_role role;
619 unsigned index;
620 unsigned quadrant;
621 struct hlist_head *bucket;
622 struct kvm_mmu_page *page;
623 struct hlist_node *node;
624
625 role.word = 0;
626 role.glevels = vcpu->mmu.root_level;
627 role.level = level;
628 role.metaphysical = metaphysical;
d28c6cfb 629 role.hugepage_access = hugepage_access;
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630 if (vcpu->mmu.root_level <= PT32_ROOT_LEVEL) {
631 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
632 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
633 role.quadrant = quadrant;
634 }
635 pgprintk("%s: looking gfn %lx role %x\n", __FUNCTION__,
636 gfn, role.word);
637 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
638 bucket = &vcpu->kvm->mmu_page_hash[index];
639 hlist_for_each_entry(page, node, bucket, hash_link)
640 if (page->gfn == gfn && page->role.word == role.word) {
714b93da 641 mmu_page_add_parent_pte(vcpu, page, parent_pte);
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642 pgprintk("%s: found\n", __FUNCTION__);
643 return page;
644 }
645 page = kvm_mmu_alloc_page(vcpu, parent_pte);
646 if (!page)
647 return page;
648 pgprintk("%s: adding gfn %lx role %x\n", __FUNCTION__, gfn, role.word);
649 page->gfn = gfn;
650 page->role = role;
651 hlist_add_head(&page->hash_link, bucket);
c7addb90 652 vcpu->mmu.prefetch_page(vcpu, page);
374cbac0 653 if (!metaphysical)
714b93da 654 rmap_write_protect(vcpu, gfn);
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655 return page;
656}
657
90cb0529 658static void kvm_mmu_page_unlink_children(struct kvm *kvm,
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659 struct kvm_mmu_page *page)
660{
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661 unsigned i;
662 u64 *pt;
663 u64 ent;
664
47ad8e68 665 pt = page->spt;
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666
667 if (page->role.level == PT_PAGE_TABLE_LEVEL) {
668 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
c7addb90 669 if (is_shadow_present_pte(pt[i]))
90cb0529 670 rmap_remove(&pt[i]);
c7addb90 671 pt[i] = shadow_trap_nonpresent_pte;
697fe2e2 672 }
90cb0529 673 kvm_flush_remote_tlbs(kvm);
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674 return;
675 }
676
677 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
678 ent = pt[i];
679
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680 pt[i] = shadow_trap_nonpresent_pte;
681 if (!is_shadow_present_pte(ent))
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682 continue;
683 ent &= PT64_BASE_ADDR_MASK;
90cb0529 684 mmu_page_remove_parent_pte(page_header(ent), &pt[i]);
697fe2e2 685 }
90cb0529 686 kvm_flush_remote_tlbs(kvm);
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687}
688
90cb0529 689static void kvm_mmu_put_page(struct kvm_mmu_page *page,
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690 u64 *parent_pte)
691{
90cb0529 692 mmu_page_remove_parent_pte(page, parent_pte);
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693}
694
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695static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
696{
697 int i;
698
699 for (i = 0; i < KVM_MAX_VCPUS; ++i)
700 if (kvm->vcpus[i])
701 kvm->vcpus[i]->last_pte_updated = NULL;
702}
703
90cb0529 704static void kvm_mmu_zap_page(struct kvm *kvm,
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705 struct kvm_mmu_page *page)
706{
707 u64 *parent_pte;
708
709 while (page->multimapped || page->parent_pte) {
710 if (!page->multimapped)
711 parent_pte = page->parent_pte;
712 else {
713 struct kvm_pte_chain *chain;
714
715 chain = container_of(page->parent_ptes.first,
716 struct kvm_pte_chain, link);
717 parent_pte = chain->parent_ptes[0];
718 }
697fe2e2 719 BUG_ON(!parent_pte);
90cb0529 720 kvm_mmu_put_page(page, parent_pte);
c7addb90 721 set_shadow_pte(parent_pte, shadow_trap_nonpresent_pte);
a436036b 722 }
90cb0529 723 kvm_mmu_page_unlink_children(kvm, page);
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724 if (!page->root_count) {
725 hlist_del(&page->hash_link);
90cb0529 726 kvm_mmu_free_page(kvm, page);
36868f7b 727 } else
90cb0529 728 list_move(&page->link, &kvm->active_mmu_pages);
12b7d28f 729 kvm_mmu_reset_last_pte_updated(kvm);
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730}
731
732static int kvm_mmu_unprotect_page(struct kvm_vcpu *vcpu, gfn_t gfn)
733{
734 unsigned index;
735 struct hlist_head *bucket;
736 struct kvm_mmu_page *page;
737 struct hlist_node *node, *n;
738 int r;
739
740 pgprintk("%s: looking for gfn %lx\n", __FUNCTION__, gfn);
741 r = 0;
742 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
743 bucket = &vcpu->kvm->mmu_page_hash[index];
744 hlist_for_each_entry_safe(page, node, n, bucket, hash_link)
745 if (page->gfn == gfn && !page->role.metaphysical) {
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746 pgprintk("%s: gfn %lx role %x\n", __FUNCTION__, gfn,
747 page->role.word);
90cb0529 748 kvm_mmu_zap_page(vcpu->kvm, page);
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749 r = 1;
750 }
751 return r;
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752}
753
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754static void mmu_unshadow(struct kvm_vcpu *vcpu, gfn_t gfn)
755{
756 struct kvm_mmu_page *page;
757
758 while ((page = kvm_mmu_lookup_page(vcpu, gfn)) != NULL) {
759 pgprintk("%s: zap %lx %x\n",
760 __FUNCTION__, gfn, page->role.word);
90cb0529 761 kvm_mmu_zap_page(vcpu->kvm, page);
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762 }
763}
764
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765static void page_header_update_slot(struct kvm *kvm, void *pte, gpa_t gpa)
766{
767 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gpa >> PAGE_SHIFT));
768 struct kvm_mmu_page *page_head = page_header(__pa(pte));
769
770 __set_bit(slot, &page_head->slot_bitmap);
771}
772
773hpa_t safe_gpa_to_hpa(struct kvm_vcpu *vcpu, gpa_t gpa)
774{
775 hpa_t hpa = gpa_to_hpa(vcpu, gpa);
776
777 return is_error_hpa(hpa) ? bad_page_address | (gpa & ~PAGE_MASK): hpa;
778}
779
780hpa_t gpa_to_hpa(struct kvm_vcpu *vcpu, gpa_t gpa)
781{
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782 struct page *page;
783
784 ASSERT((gpa & HPA_ERR_MASK) == 0);
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785 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
786 if (!page)
6aa8b732 787 return gpa | HPA_ERR_MASK;
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788 return ((hpa_t)page_to_pfn(page) << PAGE_SHIFT)
789 | (gpa & (PAGE_SIZE-1));
790}
791
792hpa_t gva_to_hpa(struct kvm_vcpu *vcpu, gva_t gva)
793{
794 gpa_t gpa = vcpu->mmu.gva_to_gpa(vcpu, gva);
795
796 if (gpa == UNMAPPED_GVA)
797 return UNMAPPED_GVA;
798 return gpa_to_hpa(vcpu, gpa);
799}
800
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801struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
802{
803 gpa_t gpa = vcpu->mmu.gva_to_gpa(vcpu, gva);
804
805 if (gpa == UNMAPPED_GVA)
806 return NULL;
807 return pfn_to_page(gpa_to_hpa(vcpu, gpa) >> PAGE_SHIFT);
808}
809
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810static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
811{
812}
813
814static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, hpa_t p)
815{
816 int level = PT32E_ROOT_LEVEL;
817 hpa_t table_addr = vcpu->mmu.root_hpa;
818
819 for (; ; level--) {
820 u32 index = PT64_INDEX(v, level);
821 u64 *table;
cea0f0e7 822 u64 pte;
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823
824 ASSERT(VALID_PAGE(table_addr));
825 table = __va(table_addr);
826
827 if (level == 1) {
cea0f0e7 828 pte = table[index];
c7addb90 829 if (is_shadow_present_pte(pte) && is_writeble_pte(pte))
cea0f0e7 830 return 0;
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831 mark_page_dirty(vcpu->kvm, v >> PAGE_SHIFT);
832 page_header_update_slot(vcpu->kvm, table, v);
833 table[index] = p | PT_PRESENT_MASK | PT_WRITABLE_MASK |
834 PT_USER_MASK;
714b93da 835 rmap_add(vcpu, &table[index]);
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836 return 0;
837 }
838
c7addb90 839 if (table[index] == shadow_trap_nonpresent_pte) {
25c0de2c 840 struct kvm_mmu_page *new_table;
cea0f0e7 841 gfn_t pseudo_gfn;
6aa8b732 842
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843 pseudo_gfn = (v & PT64_DIR_BASE_ADDR_MASK)
844 >> PAGE_SHIFT;
845 new_table = kvm_mmu_get_page(vcpu, pseudo_gfn,
846 v, level - 1,
d28c6cfb 847 1, 0, &table[index]);
25c0de2c 848 if (!new_table) {
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849 pgprintk("nonpaging_map: ENOMEM\n");
850 return -ENOMEM;
851 }
852
47ad8e68 853 table[index] = __pa(new_table->spt) | PT_PRESENT_MASK
25c0de2c 854 | PT_WRITABLE_MASK | PT_USER_MASK;
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855 }
856 table_addr = table[index] & PT64_BASE_ADDR_MASK;
857 }
858}
859
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860static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
861 struct kvm_mmu_page *sp)
862{
863 int i;
864
865 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
866 sp->spt[i] = shadow_trap_nonpresent_pte;
867}
868
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869static void mmu_free_roots(struct kvm_vcpu *vcpu)
870{
871 int i;
3bb65a22 872 struct kvm_mmu_page *page;
17ac10ad 873
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874 if (!VALID_PAGE(vcpu->mmu.root_hpa))
875 return;
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876#ifdef CONFIG_X86_64
877 if (vcpu->mmu.shadow_root_level == PT64_ROOT_LEVEL) {
878 hpa_t root = vcpu->mmu.root_hpa;
879
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880 page = page_header(root);
881 --page->root_count;
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882 vcpu->mmu.root_hpa = INVALID_PAGE;
883 return;
884 }
885#endif
886 for (i = 0; i < 4; ++i) {
887 hpa_t root = vcpu->mmu.pae_root[i];
888
417726a3 889 if (root) {
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890 root &= PT64_BASE_ADDR_MASK;
891 page = page_header(root);
892 --page->root_count;
893 }
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894 vcpu->mmu.pae_root[i] = INVALID_PAGE;
895 }
896 vcpu->mmu.root_hpa = INVALID_PAGE;
897}
898
899static void mmu_alloc_roots(struct kvm_vcpu *vcpu)
900{
901 int i;
cea0f0e7 902 gfn_t root_gfn;
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903 struct kvm_mmu_page *page;
904
cea0f0e7 905 root_gfn = vcpu->cr3 >> PAGE_SHIFT;
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906
907#ifdef CONFIG_X86_64
908 if (vcpu->mmu.shadow_root_level == PT64_ROOT_LEVEL) {
909 hpa_t root = vcpu->mmu.root_hpa;
910
911 ASSERT(!VALID_PAGE(root));
68a99f6d 912 page = kvm_mmu_get_page(vcpu, root_gfn, 0,
d28c6cfb 913 PT64_ROOT_LEVEL, 0, 0, NULL);
47ad8e68 914 root = __pa(page->spt);
3bb65a22 915 ++page->root_count;
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916 vcpu->mmu.root_hpa = root;
917 return;
918 }
919#endif
920 for (i = 0; i < 4; ++i) {
921 hpa_t root = vcpu->mmu.pae_root[i];
922
923 ASSERT(!VALID_PAGE(root));
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924 if (vcpu->mmu.root_level == PT32E_ROOT_LEVEL) {
925 if (!is_present_pte(vcpu->pdptrs[i])) {
926 vcpu->mmu.pae_root[i] = 0;
927 continue;
928 }
cea0f0e7 929 root_gfn = vcpu->pdptrs[i] >> PAGE_SHIFT;
417726a3 930 } else if (vcpu->mmu.root_level == 0)
cea0f0e7 931 root_gfn = 0;
68a99f6d 932 page = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
cea0f0e7 933 PT32_ROOT_LEVEL, !is_paging(vcpu),
d28c6cfb 934 0, NULL);
47ad8e68 935 root = __pa(page->spt);
3bb65a22 936 ++page->root_count;
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937 vcpu->mmu.pae_root[i] = root | PT_PRESENT_MASK;
938 }
939 vcpu->mmu.root_hpa = __pa(vcpu->mmu.pae_root);
940}
941
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942static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr)
943{
944 return vaddr;
945}
946
947static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
948 u32 error_code)
949{
6aa8b732 950 gpa_t addr = gva;
ebeace86 951 hpa_t paddr;
e2dec939 952 int r;
6aa8b732 953
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954 r = mmu_topup_memory_caches(vcpu);
955 if (r)
956 return r;
714b93da 957
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958 ASSERT(vcpu);
959 ASSERT(VALID_PAGE(vcpu->mmu.root_hpa));
960
6aa8b732 961
ebeace86 962 paddr = gpa_to_hpa(vcpu , addr & PT64_BASE_ADDR_MASK);
6aa8b732 963
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964 if (is_error_hpa(paddr))
965 return 1;
6aa8b732 966
ebeace86 967 return nonpaging_map(vcpu, addr & PAGE_MASK, paddr);
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968}
969
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970static void nonpaging_free(struct kvm_vcpu *vcpu)
971{
17ac10ad 972 mmu_free_roots(vcpu);
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973}
974
975static int nonpaging_init_context(struct kvm_vcpu *vcpu)
976{
977 struct kvm_mmu *context = &vcpu->mmu;
978
979 context->new_cr3 = nonpaging_new_cr3;
980 context->page_fault = nonpaging_page_fault;
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981 context->gva_to_gpa = nonpaging_gva_to_gpa;
982 context->free = nonpaging_free;
c7addb90 983 context->prefetch_page = nonpaging_prefetch_page;
cea0f0e7 984 context->root_level = 0;
6aa8b732 985 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 986 context->root_hpa = INVALID_PAGE;
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987 return 0;
988}
989
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990static void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
991{
1165f5fe 992 ++vcpu->stat.tlb_flush;
cbdd1bea 993 kvm_x86_ops->tlb_flush(vcpu);
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994}
995
996static void paging_new_cr3(struct kvm_vcpu *vcpu)
997{
374cbac0 998 pgprintk("%s: cr3 %lx\n", __FUNCTION__, vcpu->cr3);
cea0f0e7 999 mmu_free_roots(vcpu);
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1000}
1001
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1002static void inject_page_fault(struct kvm_vcpu *vcpu,
1003 u64 addr,
1004 u32 err_code)
1005{
cbdd1bea 1006 kvm_x86_ops->inject_page_fault(vcpu, addr, err_code);
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1007}
1008
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1009static void paging_free(struct kvm_vcpu *vcpu)
1010{
1011 nonpaging_free(vcpu);
1012}
1013
1014#define PTTYPE 64
1015#include "paging_tmpl.h"
1016#undef PTTYPE
1017
1018#define PTTYPE 32
1019#include "paging_tmpl.h"
1020#undef PTTYPE
1021
17ac10ad 1022static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
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1023{
1024 struct kvm_mmu *context = &vcpu->mmu;
1025
1026 ASSERT(is_pae(vcpu));
1027 context->new_cr3 = paging_new_cr3;
1028 context->page_fault = paging64_page_fault;
6aa8b732 1029 context->gva_to_gpa = paging64_gva_to_gpa;
c7addb90 1030 context->prefetch_page = paging64_prefetch_page;
6aa8b732 1031 context->free = paging_free;
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1032 context->root_level = level;
1033 context->shadow_root_level = level;
17c3ba9d 1034 context->root_hpa = INVALID_PAGE;
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1035 return 0;
1036}
1037
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1038static int paging64_init_context(struct kvm_vcpu *vcpu)
1039{
1040 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
1041}
1042
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1043static int paging32_init_context(struct kvm_vcpu *vcpu)
1044{
1045 struct kvm_mmu *context = &vcpu->mmu;
1046
1047 context->new_cr3 = paging_new_cr3;
1048 context->page_fault = paging32_page_fault;
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1049 context->gva_to_gpa = paging32_gva_to_gpa;
1050 context->free = paging_free;
c7addb90 1051 context->prefetch_page = paging32_prefetch_page;
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1052 context->root_level = PT32_ROOT_LEVEL;
1053 context->shadow_root_level = PT32E_ROOT_LEVEL;
17c3ba9d 1054 context->root_hpa = INVALID_PAGE;
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1055 return 0;
1056}
1057
1058static int paging32E_init_context(struct kvm_vcpu *vcpu)
1059{
17ac10ad 1060 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
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1061}
1062
1063static int init_kvm_mmu(struct kvm_vcpu *vcpu)
1064{
1065 ASSERT(vcpu);
1066 ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
1067
1068 if (!is_paging(vcpu))
1069 return nonpaging_init_context(vcpu);
a9058ecd 1070 else if (is_long_mode(vcpu))
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1071 return paging64_init_context(vcpu);
1072 else if (is_pae(vcpu))
1073 return paging32E_init_context(vcpu);
1074 else
1075 return paging32_init_context(vcpu);
1076}
1077
1078static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
1079{
1080 ASSERT(vcpu);
1081 if (VALID_PAGE(vcpu->mmu.root_hpa)) {
1082 vcpu->mmu.free(vcpu);
1083 vcpu->mmu.root_hpa = INVALID_PAGE;
1084 }
1085}
1086
1087int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
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1088{
1089 destroy_kvm_mmu(vcpu);
1090 return init_kvm_mmu(vcpu);
1091}
8668a3c4 1092EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
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1093
1094int kvm_mmu_load(struct kvm_vcpu *vcpu)
6aa8b732 1095{
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1096 int r;
1097
11ec2804 1098 mutex_lock(&vcpu->kvm->lock);
e2dec939 1099 r = mmu_topup_memory_caches(vcpu);
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1100 if (r)
1101 goto out;
1102 mmu_alloc_roots(vcpu);
cbdd1bea 1103 kvm_x86_ops->set_cr3(vcpu, vcpu->mmu.root_hpa);
17c3ba9d 1104 kvm_mmu_flush_tlb(vcpu);
714b93da 1105out:
11ec2804 1106 mutex_unlock(&vcpu->kvm->lock);
714b93da 1107 return r;
6aa8b732 1108}
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1109EXPORT_SYMBOL_GPL(kvm_mmu_load);
1110
1111void kvm_mmu_unload(struct kvm_vcpu *vcpu)
1112{
1113 mmu_free_roots(vcpu);
1114}
6aa8b732 1115
09072daf 1116static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
ac1b714e
AK
1117 struct kvm_mmu_page *page,
1118 u64 *spte)
1119{
1120 u64 pte;
1121 struct kvm_mmu_page *child;
1122
1123 pte = *spte;
c7addb90 1124 if (is_shadow_present_pte(pte)) {
ac1b714e 1125 if (page->role.level == PT_PAGE_TABLE_LEVEL)
90cb0529 1126 rmap_remove(spte);
ac1b714e
AK
1127 else {
1128 child = page_header(pte & PT64_BASE_ADDR_MASK);
90cb0529 1129 mmu_page_remove_parent_pte(child, spte);
ac1b714e
AK
1130 }
1131 }
c7addb90 1132 set_shadow_pte(spte, shadow_trap_nonpresent_pte);
d9e368d6 1133 kvm_flush_remote_tlbs(vcpu->kvm);
ac1b714e
AK
1134}
1135
0028425f
AK
1136static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
1137 struct kvm_mmu_page *page,
1138 u64 *spte,
c7addb90
AK
1139 const void *new, int bytes,
1140 int offset_in_pte)
0028425f
AK
1141{
1142 if (page->role.level != PT_PAGE_TABLE_LEVEL)
1143 return;
1144
1145 if (page->role.glevels == PT32_ROOT_LEVEL)
c7addb90
AK
1146 paging32_update_pte(vcpu, page, spte, new, bytes,
1147 offset_in_pte);
0028425f 1148 else
c7addb90
AK
1149 paging64_update_pte(vcpu, page, spte, new, bytes,
1150 offset_in_pte);
0028425f
AK
1151}
1152
12b7d28f
AK
1153static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
1154{
1155 u64 *spte = vcpu->last_pte_updated;
1156
1157 return !!(spte && (*spte & PT_ACCESSED_MASK));
1158}
1159
09072daf 1160void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
fe551881 1161 const u8 *new, int bytes)
da4a00f0 1162{
9b7a0325
AK
1163 gfn_t gfn = gpa >> PAGE_SHIFT;
1164 struct kvm_mmu_page *page;
0e7bc4b9 1165 struct hlist_node *node, *n;
9b7a0325
AK
1166 struct hlist_head *bucket;
1167 unsigned index;
1168 u64 *spte;
9b7a0325 1169 unsigned offset = offset_in_page(gpa);
0e7bc4b9 1170 unsigned pte_size;
9b7a0325 1171 unsigned page_offset;
0e7bc4b9 1172 unsigned misaligned;
fce0657f 1173 unsigned quadrant;
9b7a0325 1174 int level;
86a5ba02 1175 int flooded = 0;
ac1b714e 1176 int npte;
9b7a0325 1177
da4a00f0 1178 pgprintk("%s: gpa %llx bytes %d\n", __FUNCTION__, gpa, bytes);
c7addb90 1179 kvm_mmu_audit(vcpu, "pre pte write");
12b7d28f
AK
1180 if (gfn == vcpu->last_pt_write_gfn
1181 && !last_updated_pte_accessed(vcpu)) {
86a5ba02
AK
1182 ++vcpu->last_pt_write_count;
1183 if (vcpu->last_pt_write_count >= 3)
1184 flooded = 1;
1185 } else {
1186 vcpu->last_pt_write_gfn = gfn;
1187 vcpu->last_pt_write_count = 1;
12b7d28f 1188 vcpu->last_pte_updated = NULL;
86a5ba02 1189 }
9b7a0325
AK
1190 index = kvm_page_table_hashfn(gfn) % KVM_NUM_MMU_PAGES;
1191 bucket = &vcpu->kvm->mmu_page_hash[index];
0e7bc4b9 1192 hlist_for_each_entry_safe(page, node, n, bucket, hash_link) {
9b7a0325
AK
1193 if (page->gfn != gfn || page->role.metaphysical)
1194 continue;
0e7bc4b9
AK
1195 pte_size = page->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
1196 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
e925c5ba 1197 misaligned |= bytes < 4;
86a5ba02 1198 if (misaligned || flooded) {
0e7bc4b9
AK
1199 /*
1200 * Misaligned accesses are too much trouble to fix
1201 * up; also, they usually indicate a page is not used
1202 * as a page table.
86a5ba02
AK
1203 *
1204 * If we're seeing too many writes to a page,
1205 * it may no longer be a page table, or we may be
1206 * forking, in which case it is better to unmap the
1207 * page.
0e7bc4b9
AK
1208 */
1209 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
1210 gpa, bytes, page->role.word);
90cb0529 1211 kvm_mmu_zap_page(vcpu->kvm, page);
0e7bc4b9
AK
1212 continue;
1213 }
9b7a0325
AK
1214 page_offset = offset;
1215 level = page->role.level;
ac1b714e 1216 npte = 1;
9b7a0325 1217 if (page->role.glevels == PT32_ROOT_LEVEL) {
ac1b714e
AK
1218 page_offset <<= 1; /* 32->64 */
1219 /*
1220 * A 32-bit pde maps 4MB while the shadow pdes map
1221 * only 2MB. So we need to double the offset again
1222 * and zap two pdes instead of one.
1223 */
1224 if (level == PT32_ROOT_LEVEL) {
6b8d0f9b 1225 page_offset &= ~7; /* kill rounding error */
ac1b714e
AK
1226 page_offset <<= 1;
1227 npte = 2;
1228 }
fce0657f 1229 quadrant = page_offset >> PAGE_SHIFT;
9b7a0325 1230 page_offset &= ~PAGE_MASK;
fce0657f
AK
1231 if (quadrant != page->role.quadrant)
1232 continue;
9b7a0325 1233 }
47ad8e68 1234 spte = &page->spt[page_offset / sizeof(*spte)];
ac1b714e 1235 while (npte--) {
09072daf 1236 mmu_pte_write_zap_pte(vcpu, page, spte);
c7addb90
AK
1237 mmu_pte_write_new_pte(vcpu, page, spte, new, bytes,
1238 page_offset & (pte_size - 1));
ac1b714e 1239 ++spte;
9b7a0325 1240 }
9b7a0325 1241 }
c7addb90 1242 kvm_mmu_audit(vcpu, "post pte write");
da4a00f0
AK
1243}
1244
a436036b
AK
1245int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
1246{
1247 gpa_t gpa = vcpu->mmu.gva_to_gpa(vcpu, gva);
1248
1249 return kvm_mmu_unprotect_page(vcpu, gpa >> PAGE_SHIFT);
1250}
1251
22d95b12 1252void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
ebeace86
AK
1253{
1254 while (vcpu->kvm->n_free_mmu_pages < KVM_REFILL_PAGES) {
1255 struct kvm_mmu_page *page;
1256
1257 page = container_of(vcpu->kvm->active_mmu_pages.prev,
1258 struct kvm_mmu_page, link);
90cb0529 1259 kvm_mmu_zap_page(vcpu->kvm, page);
ebeace86
AK
1260 }
1261}
ebeace86 1262
6aa8b732
AK
1263static void free_mmu_pages(struct kvm_vcpu *vcpu)
1264{
f51234c2 1265 struct kvm_mmu_page *page;
6aa8b732 1266
f51234c2
AK
1267 while (!list_empty(&vcpu->kvm->active_mmu_pages)) {
1268 page = container_of(vcpu->kvm->active_mmu_pages.next,
1269 struct kvm_mmu_page, link);
90cb0529 1270 kvm_mmu_zap_page(vcpu->kvm, page);
f51234c2 1271 }
17ac10ad 1272 free_page((unsigned long)vcpu->mmu.pae_root);
6aa8b732
AK
1273}
1274
1275static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
1276{
17ac10ad 1277 struct page *page;
6aa8b732
AK
1278 int i;
1279
1280 ASSERT(vcpu);
1281
d3d25b04 1282 vcpu->kvm->n_free_mmu_pages = KVM_NUM_MMU_PAGES;
17ac10ad
AK
1283
1284 /*
1285 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
1286 * Therefore we need to allocate shadow page tables in the first
1287 * 4GB of memory, which happens to fit the DMA32 zone.
1288 */
1289 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
1290 if (!page)
1291 goto error_1;
1292 vcpu->mmu.pae_root = page_address(page);
1293 for (i = 0; i < 4; ++i)
1294 vcpu->mmu.pae_root[i] = INVALID_PAGE;
1295
6aa8b732
AK
1296 return 0;
1297
1298error_1:
1299 free_mmu_pages(vcpu);
1300 return -ENOMEM;
1301}
1302
8018c27b 1303int kvm_mmu_create(struct kvm_vcpu *vcpu)
6aa8b732 1304{
6aa8b732
AK
1305 ASSERT(vcpu);
1306 ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
6aa8b732 1307
8018c27b
IM
1308 return alloc_mmu_pages(vcpu);
1309}
6aa8b732 1310
8018c27b
IM
1311int kvm_mmu_setup(struct kvm_vcpu *vcpu)
1312{
1313 ASSERT(vcpu);
1314 ASSERT(!VALID_PAGE(vcpu->mmu.root_hpa));
2c264957 1315
8018c27b 1316 return init_kvm_mmu(vcpu);
6aa8b732
AK
1317}
1318
1319void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
1320{
1321 ASSERT(vcpu);
1322
1323 destroy_kvm_mmu(vcpu);
1324 free_mmu_pages(vcpu);
714b93da 1325 mmu_free_memory_caches(vcpu);
6aa8b732
AK
1326}
1327
90cb0529 1328void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
6aa8b732
AK
1329{
1330 struct kvm_mmu_page *page;
1331
1332 list_for_each_entry(page, &kvm->active_mmu_pages, link) {
1333 int i;
1334 u64 *pt;
1335
1336 if (!test_bit(slot, &page->slot_bitmap))
1337 continue;
1338
47ad8e68 1339 pt = page->spt;
6aa8b732
AK
1340 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1341 /* avoid RMW */
cd4a4e53 1342 if (pt[i] & PT_WRITABLE_MASK) {
90cb0529 1343 rmap_remove(&pt[i]);
6aa8b732 1344 pt[i] &= ~PT_WRITABLE_MASK;
cd4a4e53 1345 }
6aa8b732
AK
1346 }
1347}
37a7d8b0 1348
90cb0529 1349void kvm_mmu_zap_all(struct kvm *kvm)
e0fa826f 1350{
90cb0529 1351 struct kvm_mmu_page *page, *node;
e0fa826f 1352
90cb0529
AK
1353 list_for_each_entry_safe(page, node, &kvm->active_mmu_pages, link)
1354 kvm_mmu_zap_page(kvm, page);
e0fa826f 1355
90cb0529 1356 kvm_flush_remote_tlbs(kvm);
e0fa826f
DL
1357}
1358
b5a33a75
AK
1359void kvm_mmu_module_exit(void)
1360{
1361 if (pte_chain_cache)
1362 kmem_cache_destroy(pte_chain_cache);
1363 if (rmap_desc_cache)
1364 kmem_cache_destroy(rmap_desc_cache);
d3d25b04
AK
1365 if (mmu_page_header_cache)
1366 kmem_cache_destroy(mmu_page_header_cache);
b5a33a75
AK
1367}
1368
1369int kvm_mmu_module_init(void)
1370{
1371 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
1372 sizeof(struct kvm_pte_chain),
20c2df83 1373 0, 0, NULL);
b5a33a75
AK
1374 if (!pte_chain_cache)
1375 goto nomem;
1376 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
1377 sizeof(struct kvm_rmap_desc),
20c2df83 1378 0, 0, NULL);
b5a33a75
AK
1379 if (!rmap_desc_cache)
1380 goto nomem;
1381
d3d25b04
AK
1382 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
1383 sizeof(struct kvm_mmu_page),
20c2df83 1384 0, 0, NULL);
d3d25b04
AK
1385 if (!mmu_page_header_cache)
1386 goto nomem;
1387
b5a33a75
AK
1388 return 0;
1389
1390nomem:
1391 kvm_mmu_module_exit();
1392 return -ENOMEM;
1393}
1394
37a7d8b0
AK
1395#ifdef AUDIT
1396
1397static const char *audit_msg;
1398
1399static gva_t canonicalize(gva_t gva)
1400{
1401#ifdef CONFIG_X86_64
1402 gva = (long long)(gva << 16) >> 16;
1403#endif
1404 return gva;
1405}
1406
1407static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
1408 gva_t va, int level)
1409{
1410 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
1411 int i;
1412 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
1413
1414 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
1415 u64 ent = pt[i];
1416
c7addb90 1417 if (ent == shadow_trap_nonpresent_pte)
37a7d8b0
AK
1418 continue;
1419
1420 va = canonicalize(va);
c7addb90
AK
1421 if (level > 1) {
1422 if (ent == shadow_notrap_nonpresent_pte)
1423 printk(KERN_ERR "audit: (%s) nontrapping pte"
1424 " in nonleaf level: levels %d gva %lx"
1425 " level %d pte %llx\n", audit_msg,
1426 vcpu->mmu.root_level, va, level, ent);
1427
37a7d8b0 1428 audit_mappings_page(vcpu, ent, va, level - 1);
c7addb90 1429 } else {
37a7d8b0
AK
1430 gpa_t gpa = vcpu->mmu.gva_to_gpa(vcpu, va);
1431 hpa_t hpa = gpa_to_hpa(vcpu, gpa);
1432
c7addb90 1433 if (is_shadow_present_pte(ent)
37a7d8b0 1434 && (ent & PT64_BASE_ADDR_MASK) != hpa)
c7addb90
AK
1435 printk(KERN_ERR "xx audit error: (%s) levels %d"
1436 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
37a7d8b0 1437 audit_msg, vcpu->mmu.root_level,
c7addb90
AK
1438 va, gpa, hpa, ent, is_shadow_present_pte(ent));
1439 else if (ent == shadow_notrap_nonpresent_pte
1440 && !is_error_hpa(hpa))
1441 printk(KERN_ERR "audit: (%s) notrap shadow,"
1442 " valid guest gva %lx\n", audit_msg, va);
1443
37a7d8b0
AK
1444 }
1445 }
1446}
1447
1448static void audit_mappings(struct kvm_vcpu *vcpu)
1449{
1ea252af 1450 unsigned i;
37a7d8b0
AK
1451
1452 if (vcpu->mmu.root_level == 4)
1453 audit_mappings_page(vcpu, vcpu->mmu.root_hpa, 0, 4);
1454 else
1455 for (i = 0; i < 4; ++i)
1456 if (vcpu->mmu.pae_root[i] & PT_PRESENT_MASK)
1457 audit_mappings_page(vcpu,
1458 vcpu->mmu.pae_root[i],
1459 i << 30,
1460 2);
1461}
1462
1463static int count_rmaps(struct kvm_vcpu *vcpu)
1464{
1465 int nmaps = 0;
1466 int i, j, k;
1467
1468 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
1469 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
1470 struct kvm_rmap_desc *d;
1471
1472 for (j = 0; j < m->npages; ++j) {
1473 struct page *page = m->phys_mem[j];
1474
1475 if (!page->private)
1476 continue;
1477 if (!(page->private & 1)) {
1478 ++nmaps;
1479 continue;
1480 }
1481 d = (struct kvm_rmap_desc *)(page->private & ~1ul);
1482 while (d) {
1483 for (k = 0; k < RMAP_EXT; ++k)
1484 if (d->shadow_ptes[k])
1485 ++nmaps;
1486 else
1487 break;
1488 d = d->more;
1489 }
1490 }
1491 }
1492 return nmaps;
1493}
1494
1495static int count_writable_mappings(struct kvm_vcpu *vcpu)
1496{
1497 int nmaps = 0;
1498 struct kvm_mmu_page *page;
1499 int i;
1500
1501 list_for_each_entry(page, &vcpu->kvm->active_mmu_pages, link) {
47ad8e68 1502 u64 *pt = page->spt;
37a7d8b0
AK
1503
1504 if (page->role.level != PT_PAGE_TABLE_LEVEL)
1505 continue;
1506
1507 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1508 u64 ent = pt[i];
1509
1510 if (!(ent & PT_PRESENT_MASK))
1511 continue;
1512 if (!(ent & PT_WRITABLE_MASK))
1513 continue;
1514 ++nmaps;
1515 }
1516 }
1517 return nmaps;
1518}
1519
1520static void audit_rmap(struct kvm_vcpu *vcpu)
1521{
1522 int n_rmap = count_rmaps(vcpu);
1523 int n_actual = count_writable_mappings(vcpu);
1524
1525 if (n_rmap != n_actual)
1526 printk(KERN_ERR "%s: (%s) rmap %d actual %d\n",
1527 __FUNCTION__, audit_msg, n_rmap, n_actual);
1528}
1529
1530static void audit_write_protection(struct kvm_vcpu *vcpu)
1531{
1532 struct kvm_mmu_page *page;
1533
1534 list_for_each_entry(page, &vcpu->kvm->active_mmu_pages, link) {
1535 hfn_t hfn;
1536 struct page *pg;
1537
1538 if (page->role.metaphysical)
1539 continue;
1540
1541 hfn = gpa_to_hpa(vcpu, (gpa_t)page->gfn << PAGE_SHIFT)
1542 >> PAGE_SHIFT;
1543 pg = pfn_to_page(hfn);
1544 if (pg->private)
1545 printk(KERN_ERR "%s: (%s) shadow page has writable"
1546 " mappings: gfn %lx role %x\n",
1547 __FUNCTION__, audit_msg, page->gfn,
1548 page->role.word);
1549 }
1550}
1551
1552static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
1553{
1554 int olddbg = dbg;
1555
1556 dbg = 0;
1557 audit_msg = msg;
1558 audit_rmap(vcpu);
1559 audit_write_protection(vcpu);
1560 audit_mappings(vcpu);
1561 dbg = olddbg;
1562}
1563
1564#endif