[mirror_ubuntu-hirsute-kernel.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
#else
	#error Invalid PTTYPE value
#endif

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn;
	pt_element_t *table;
	pt_element_t inherited_ar;
};

static void FNAME(init_walker)(struct guest_walker *walker,
			       struct kvm_vcpu *vcpu)
{
	hpa_t hpa;
	struct kvm_memory_slot *slot;

	walker->level = vcpu->mmu.root_level;
	walker->table_gfn = (vcpu->cr3 & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	slot = gfn_to_memslot(vcpu->kvm, walker->table_gfn);
	hpa = safe_gpa_to_hpa(vcpu, vcpu->cr3 & PT64_BASE_ADDR_MASK);
	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);

	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0);

	walker->table = (pt_element_t *)( (unsigned long)walker->table |
		(unsigned long)(vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) );
	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;
}

static void FNAME(release_walker)(struct guest_walker *walker)
{
	kunmap_atomic(walker->table, KM_USER0);
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte,
			   u64 *shadow_pte, u64 access_bits)
{
	ASSERT(*shadow_pte == 0);
	access_bits &= guest_pte;
	*shadow_pte = (guest_pte & PT_PTE_COPY_MASK);
	set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK,
		       guest_pte & PT_DIRTY_MASK, access_bits);
}

static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde,
			   u64 *shadow_pte, u64 access_bits,
			   int index)
{
	gpa_t gaddr;

	ASSERT(*shadow_pte == 0);
	access_bits &= guest_pde;
	gaddr = (guest_pde & PT_DIR_BASE_ADDR_MASK) + PAGE_SIZE * index;
	if (PTTYPE == 32 && is_cpuid_PSE36())
		gaddr |= (guest_pde & PT32_DIR_PSE36_MASK) <<
			(32 - PT32_DIR_PSE36_SHIFT);
	*shadow_pte = guest_pde & PT_PTE_COPY_MASK;
	set_pte_common(vcpu, shadow_pte, gaddr,
		       guest_pde & PT_DIRTY_MASK, access_bits);
}

/*
 * Fetch a guest pte from a specific level in the paging hierarchy.
 */
static pt_element_t *FNAME(fetch_guest)(struct kvm_vcpu *vcpu,
					struct guest_walker *walker,
					int level,
					gva_t addr)
{

	ASSERT(level > 0  && level <= walker->level);

	for (;;) {
		int index = PT_INDEX(addr, walker->level);
		hpa_t paddr;

		ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
		       ((unsigned long)&walker->table[index] & PAGE_MASK));
		if (level == walker->level ||
		    !is_present_pte(walker->table[index]) ||
		    (walker->level == PT_DIRECTORY_LEVEL &&
		     (walker->table[index] & PT_PAGE_SIZE_MASK) &&
		     (PTTYPE == 64 || is_pse(vcpu))))
			return &walker->table[index];
		if (walker->level != 3 || is_long_mode(vcpu))
			walker->inherited_ar &= walker->table[index];
		walker->table_gfn = (walker->table[index] & PT_BASE_ADDR_MASK)
			>> PAGE_SHIFT;
		paddr = safe_gpa_to_hpa(vcpu, walker->table[index] & PT_BASE_ADDR_MASK);
		kunmap_atomic(walker->table, KM_USER0);
		walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
					    KM_USER0);
		--walker->level;
	}
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			      struct guest_walker *walker)
{
	hpa_t shadow_addr;
	int level;
	u64 *prev_shadow_ent = NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		u64 *shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		pt_element_t *guest_ent;
		u64 shadow_pte;

		if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				return shadow_ent;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			prev_shadow_ent = shadow_ent;
			continue;
		}

		if (PTTYPE == 32 && level > PT32_ROOT_LEVEL) {
			ASSERT(level == PT32E_ROOT_LEVEL);
			guest_ent = FNAME(fetch_guest)(vcpu, walker,
						       PT32_ROOT_LEVEL, addr);
		} else
			guest_ent = FNAME(fetch_guest)(vcpu, walker,
						       level, addr);

		if (!is_present_pte(*guest_ent))
			return NULL;

		/* Don't set accessed bit on PAE PDPTRs */
		if (vcpu->mmu.root_level != 3 || walker->level != 3)
			*guest_ent |= PT_ACCESSED_MASK;

		if (level == PT_PAGE_TABLE_LEVEL) {

			if (walker->level == PT_DIRECTORY_LEVEL) {
				if (prev_shadow_ent)
					*prev_shadow_ent |= PT_SHADOW_PS_MARK;
				FNAME(set_pde)(vcpu, *guest_ent, shadow_ent,
					       walker->inherited_ar,
				          PT_INDEX(addr, PT_PAGE_TABLE_LEVEL));
			} else {
				ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
				FNAME(set_pte)(vcpu, *guest_ent, shadow_ent, walker->inherited_ar);
			}
			return shadow_ent;
		}

		shadow_addr = kvm_mmu_alloc_page(vcpu, shadow_ent);
		if (!VALID_PAGE(shadow_addr))
			return ERR_PTR(-ENOMEM);
		shadow_pte = shadow_addr | PT_PRESENT_MASK;
		if (vcpu->mmu.root_level > 3 || level != 3)
			shadow_pte |= PT_ACCESSED_MASK
				| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
		prev_shadow_ent = shadow_ent;
	}
}

/*
 * The guest faulted for write.  We need to
 *
 * - check write permissions
 * - update the guest pte dirty bit
 * - update our own dirty page tracking structures
 */
static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu,
			       u64 *shadow_ent,
			       struct guest_walker *walker,
			       gva_t addr,
			       int user)
{
	pt_element_t *guest_ent;
	int writable_shadow;
	gfn_t gfn;

	if (is_writeble_pte(*shadow_ent))
		return 0;

	writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK;
	if (user) {
		/*
		 * User mode access.  Fail if it's a kernel page or a read-only
		 * page.
		 */
		if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow)
			return 0;
		ASSERT(*shadow_ent & PT_USER_MASK);
	} else
		/*
		 * Kernel mode access.  Fail if it's a read-only page and
		 * supervisor write protection is enabled.
		 */
		if (!writable_shadow) {
			if (is_write_protection(vcpu))
				return 0;
			*shadow_ent &= ~PT_USER_MASK;
		}

	guest_ent = FNAME(fetch_guest)(vcpu, walker, PT_PAGE_TABLE_LEVEL, addr);

	if (!is_present_pte(*guest_ent)) {
		*shadow_ent = 0;
		return 0;
	}

	gfn = (*guest_ent & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	mark_page_dirty(vcpu->kvm, gfn);
	*shadow_ent |= PT_WRITABLE_MASK;
	*guest_ent |= PT_DIRTY_MASK;
	rmap_add(vcpu->kvm, shadow_ent);

	return 1;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int pte_present = error_code & PFERR_PRESENT_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int fixed;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	for (;;) {
		FNAME(init_walker)(&walker, vcpu);
		shadow_pte = FNAME(fetch)(vcpu, addr, &walker);
		if (IS_ERR(shadow_pte)) {  /* must be -ENOMEM */
			nonpaging_flush(vcpu);
			FNAME(release_walker)(&walker);
			continue;
		}
		break;
	}

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!shadow_pte) {
		inject_page_fault(vcpu, addr, error_code);
		FNAME(release_walker)(&walker);
		return 0;
	}

	/*
	 * Update the shadow pte.
	 */
	if (write_fault)
		fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr,
					    user_fault);
	else
		fixed = fix_read_pf(shadow_pte);

	FNAME(release_walker)(&walker);

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte)) {
		if (may_access(*shadow_pte, write_fault, user_fault))
			return 1;
		pgprintk("%s: io work, no access\n", __FUNCTION__);
		inject_page_fault(vcpu, addr,
				  error_code | PFERR_PRESENT_MASK);
		return 0;
	}

	/*
	 * pte not present, guest page fault.
	 */
	if (pte_present && !fixed) {
		inject_page_fault(vcpu, addr, error_code);
		return 0;
	}

	++kvm_stat.pf_fixed;

	return 0;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	pt_element_t guest_pte;
	gpa_t gpa;

	FNAME(init_walker)(&walker, vcpu);
	guest_pte = *FNAME(fetch_guest)(vcpu, &walker, PT_PAGE_TABLE_LEVEL,
					vaddr);
	FNAME(release_walker)(&walker);

	if (!is_present_pte(guest_pte))
		return UNMAPPED_GVA;

	if (walker.level == PT_DIRECTORY_LEVEL) {
		ASSERT((guest_pte & PT_PAGE_SIZE_MASK));
		ASSERT(PTTYPE == 64 || is_pse(vcpu));

		gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) | (vaddr &
			(PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) | ~PAGE_MASK));

		if (PTTYPE == 32 && is_cpuid_PSE36())
			gpa |= (guest_pte & PT32_DIR_PSE36_MASK) <<
					(32 - PT32_DIR_PSE36_SHIFT);
	} else {
		gpa = (guest_pte & PT_BASE_ADDR_MASK);
		gpa |= (vaddr & ~PAGE_MASK);
	}

	return gpa;
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_PTE_COPY_MASK
#undef PT_NON_PTE_COPY_MASK
#undef PT_DIR_BASE_ADDR_MASK
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	34	#define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK
6aa8b732 AK	35	#elif PTTYPE == 32
	36	#define pt_element_t u32
	37	#define guest_walker guest_walker32
	38	#define FNAME(name) paging##32_##name
	39	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	40	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	41	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	42	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	43	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	44	#define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK
6aa8b732 AK	45	#else
	46	#error Invalid PTTYPE value
	47	#endif
	48
	49	/*
	50	* The guest_walker structure emulates the behavior of the hardware page
	51	* table walker.
	52	*/
	53	struct guest_walker {
	54	int level;
6bcbd6ab	55	gfn_t table_gfn;
6aa8b732 AK	56	pt_element_t *table;
	57	pt_element_t inherited_ar;
	58	};
	59
	60	static void FNAME(init_walker)(struct guest_walker *walker,
	61	struct kvm_vcpu *vcpu)
	62	{
	63	hpa_t hpa;
	64	struct kvm_memory_slot *slot;
	65
	66	walker->level = vcpu->mmu.root_level;
6bcbd6ab AK	67	walker->table_gfn = (vcpu->cr3 & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
6bcbd6ab AK	68	slot = gfn_to_memslot(vcpu->kvm, walker->table_gfn);
6aa8b732 AK	69	hpa = safe_gpa_to_hpa(vcpu, vcpu->cr3 & PT64_BASE_ADDR_MASK);
	70	walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0);
	71
a9058ecd	72	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
6aa8b732 AK	73	(vcpu->cr3 & ~(PAGE_MASK \| CR3_FLAGS_MASK)) == 0);
	74
	75	walker->table = (pt_element_t *)( (unsigned long)walker->table \|
	76	(unsigned long)(vcpu->cr3 & ~(PAGE_MASK \| CR3_FLAGS_MASK)) );
	77	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
	78	}
	79
	80	static void FNAME(release_walker)(struct guest_walker *walker)
	81	{
	82	kunmap_atomic(walker->table, KM_USER0);
	83	}
	84
	85	static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte,
	86	u64 *shadow_pte, u64 access_bits)
	87	{
	88	ASSERT(*shadow_pte == 0);
	89	access_bits &= guest_pte;
	90	*shadow_pte = (guest_pte & PT_PTE_COPY_MASK);
	91	set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK,
	92	guest_pte & PT_DIRTY_MASK, access_bits);
	93	}
	94
	95	static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde,
	96	u64 *shadow_pte, u64 access_bits,
	97	int index)
	98	{
	99	gpa_t gaddr;
	100
	101	ASSERT(*shadow_pte == 0);
	102	access_bits &= guest_pde;
	103	gaddr = (guest_pde & PT_DIR_BASE_ADDR_MASK) + PAGE_SIZE * index;
	104	if (PTTYPE == 32 && is_cpuid_PSE36())
	105	gaddr \|= (guest_pde & PT32_DIR_PSE36_MASK) <<
	106	(32 - PT32_DIR_PSE36_SHIFT);
8c7bb723	107	*shadow_pte = guest_pde & PT_PTE_COPY_MASK;
6aa8b732 AK	108	set_pte_common(vcpu, shadow_pte, gaddr,
	109	guest_pde & PT_DIRTY_MASK, access_bits);
	110	}
	111
	112	/*
	113	* Fetch a guest pte from a specific level in the paging hierarchy.
	114	*/
	115	static pt_element_t FNAME(fetch_guest)(struct kvm_vcpu vcpu,
	116	struct guest_walker *walker,
	117	int level,
	118	gva_t addr)
	119	{
	120
	121	ASSERT(level > 0 && level <= walker->level);
	122
	123	for (;;) {
	124	int index = PT_INDEX(addr, walker->level);
	125	hpa_t paddr;
	126
	127	ASSERT(((unsigned long)walker->table & PAGE_MASK) ==
	128	((unsigned long)&walker->table[index] & PAGE_MASK));
	129	if (level == walker->level \|\|
	130	!is_present_pte(walker->table[index]) \|\|
	131	(walker->level == PT_DIRECTORY_LEVEL &&
	132	(walker->table[index] & PT_PAGE_SIZE_MASK) &&
	133	(PTTYPE == 64 \|\| is_pse(vcpu))))
	134	return &walker->table[index];
a9058ecd	135	if (walker->level != 3 \|\| is_long_mode(vcpu))
6aa8b732	136	walker->inherited_ar &= walker->table[index];
6bcbd6ab AK	137	walker->table_gfn = (walker->table[index] & PT_BASE_ADDR_MASK)
6bcbd6ab AK	138	>> PAGE_SHIFT;
6aa8b732 AK	139	paddr = safe_gpa_to_hpa(vcpu, walker->table[index] & PT_BASE_ADDR_MASK);
	140	kunmap_atomic(walker->table, KM_USER0);
	141	walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT),
	142	KM_USER0);
	143	--walker->level;
	144	}
	145	}
	146
	147	/*
	148	* Fetch a shadow pte for a specific level in the paging hierarchy.
	149	*/
	150	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
	151	struct guest_walker *walker)
	152	{
	153	hpa_t shadow_addr;
	154	int level;
	155	u64 *prev_shadow_ent = NULL;
	156
	157	shadow_addr = vcpu->mmu.root_hpa;
	158	level = vcpu->mmu.shadow_root_level;
	159
	160	for (; ; level--) {
	161	u32 index = SHADOW_PT_INDEX(addr, level);
	162	u64 shadow_ent = ((u64 )__va(shadow_addr)) + index;
	163	pt_element_t *guest_ent;
8c7bb723	164	u64 shadow_pte;
6aa8b732 AK	165
	166	if (is_present_pte(shadow_ent) \|\| is_io_pte(shadow_ent)) {
	167	if (level == PT_PAGE_TABLE_LEVEL)
	168	return shadow_ent;
	169	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
	170	prev_shadow_ent = shadow_ent;
	171	continue;
	172	}
	173
	174	if (PTTYPE == 32 && level > PT32_ROOT_LEVEL) {
	175	ASSERT(level == PT32E_ROOT_LEVEL);
	176	guest_ent = FNAME(fetch_guest)(vcpu, walker,
	177	PT32_ROOT_LEVEL, addr);
	178	} else
	179	guest_ent = FNAME(fetch_guest)(vcpu, walker,
	180	level, addr);
	181
	182	if (!is_present_pte(*guest_ent))
	183	return NULL;
	184
	185	/* Don't set accessed bit on PAE PDPTRs */
	186	if (vcpu->mmu.root_level != 3 \|\| walker->level != 3)
	187	*guest_ent \|= PT_ACCESSED_MASK;
	188
	189	if (level == PT_PAGE_TABLE_LEVEL) {
	190
	191	if (walker->level == PT_DIRECTORY_LEVEL) {
	192	if (prev_shadow_ent)
	193	*prev_shadow_ent \|= PT_SHADOW_PS_MARK;
	194	FNAME(set_pde)(vcpu, *guest_ent, shadow_ent,
	195	walker->inherited_ar,
	196	PT_INDEX(addr, PT_PAGE_TABLE_LEVEL));
	197	} else {
	198	ASSERT(walker->level == PT_PAGE_TABLE_LEVEL);
	199	FNAME(set_pte)(vcpu, *guest_ent, shadow_ent, walker->inherited_ar);
	200	}
	201	return shadow_ent;
	202	}
	203
	204	shadow_addr = kvm_mmu_alloc_page(vcpu, shadow_ent);
	205	if (!VALID_PAGE(shadow_addr))
	206	return ERR_PTR(-ENOMEM);
8c7bb723 AK	207	shadow_pte = shadow_addr \| PT_PRESENT_MASK;
	208	if (vcpu->mmu.root_level > 3 \|\| level != 3)
	209	shadow_pte \|= PT_ACCESSED_MASK
	210	\| PT_WRITABLE_MASK \| PT_USER_MASK;
	211	*shadow_ent = shadow_pte;
6aa8b732 AK	212	prev_shadow_ent = shadow_ent;
	213	}
	214	}
	215
	216	/*
	217	* The guest faulted for write. We need to
	218	*
	219	* - check write permissions
	220	* - update the guest pte dirty bit
	221	* - update our own dirty page tracking structures
	222	*/
	223	static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu,
	224	u64 *shadow_ent,
	225	struct guest_walker *walker,
	226	gva_t addr,
	227	int user)
	228	{
	229	pt_element_t *guest_ent;
	230	int writable_shadow;
	231	gfn_t gfn;
	232
	233	if (is_writeble_pte(*shadow_ent))
	234	return 0;
	235
	236	writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK;
	237	if (user) {
	238	/*
	239	* User mode access. Fail if it's a kernel page or a read-only
	240	* page.
	241	*/
	242	if (!(*shadow_ent & PT_SHADOW_USER_MASK) \|\| !writable_shadow)
	243	return 0;
	244	ASSERT(*shadow_ent & PT_USER_MASK);
	245	} else
	246	/*
	247	* Kernel mode access. Fail if it's a read-only page and
	248	* supervisor write protection is enabled.
	249	*/
	250	if (!writable_shadow) {
	251	if (is_write_protection(vcpu))
	252	return 0;
	253	*shadow_ent &= ~PT_USER_MASK;
	254	}
	255
	256	guest_ent = FNAME(fetch_guest)(vcpu, walker, PT_PAGE_TABLE_LEVEL, addr);
	257
	258	if (!is_present_pte(*guest_ent)) {
	259	*shadow_ent = 0;
	260	return 0;
	261	}
	262
	263	gfn = (*guest_ent & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
	264	mark_page_dirty(vcpu->kvm, gfn);
	265	*shadow_ent \|= PT_WRITABLE_MASK;
	266	*guest_ent \|= PT_DIRTY_MASK;
cd4a4e53	267	rmap_add(vcpu->kvm, shadow_ent);
6aa8b732 AK	268
	269	return 1;
	270	}
	271
	272	/*
	273	* Page fault handler. There are several causes for a page fault:
	274	* - there is no shadow pte for the guest pte
	275	* - write access through a shadow pte marked read only so that we can set
	276	* the dirty bit
	277	* - write access to a shadow pte marked read only so we can update the page
	278	* dirty bitmap, when userspace requests it
	279	* - mmio access; in this case we will never install a present shadow pte
	280	* - normal guest page fault due to the guest pte marked not present, not
	281	* writable, or not executable
	282	*
	283	* Returns: 1 if we need to emulate the instruction, 0 otherwise
	284	*/
	285	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	286	u32 error_code)
	287	{
	288	int write_fault = error_code & PFERR_WRITE_MASK;
	289	int pte_present = error_code & PFERR_PRESENT_MASK;
	290	int user_fault = error_code & PFERR_USER_MASK;
	291	struct guest_walker walker;
	292	u64 *shadow_pte;
	293	int fixed;
	294
	295	/*
	296	* Look up the shadow pte for the faulting address.
	297	*/
	298	for (;;) {
	299	FNAME(init_walker)(&walker, vcpu);
	300	shadow_pte = FNAME(fetch)(vcpu, addr, &walker);
	301	if (IS_ERR(shadow_pte)) { /* must be -ENOMEM */
	302	nonpaging_flush(vcpu);
	303	FNAME(release_walker)(&walker);
	304	continue;
	305	}
	306	break;
	307	}
	308
	309	/*
	310	* The page is not mapped by the guest. Let the guest handle it.
	311	*/
	312	if (!shadow_pte) {
	313	inject_page_fault(vcpu, addr, error_code);
	314	FNAME(release_walker)(&walker);
	315	return 0;
	316	}
	317
	318	/*
	319	* Update the shadow pte.
	320	*/
	321	if (write_fault)
	322	fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr,
	323	user_fault);
	324	else
	325	fixed = fix_read_pf(shadow_pte);
	326
	327	FNAME(release_walker)(&walker);
	328
	329	/*
	330	* mmio: emulate if accessible, otherwise its a guest fault.
	331	*/
332	if (is_io_pte(*shadow_pte)) {
333	if (may_access(*shadow_pte, write_fault, user_fault))
334	return 1;
335	pgprintk("%s: io work, no access\n", __FUNCTION__);
336	inject_page_fault(vcpu, addr,
337	error_code \| PFERR_PRESENT_MASK);
338	return 0;
339	}
340
341	/*
342	* pte not present, guest page fault.
343	*/
344	if (pte_present && !fixed) {
345	inject_page_fault(vcpu, addr, error_code);
346	return 0;
347	}
348
349	++kvm_stat.pf_fixed;
350
351	return 0;
352	}
353
354	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
355	{
356	struct guest_walker walker;
357	pt_element_t guest_pte;
358	gpa_t gpa;
359
360	FNAME(init_walker)(&walker, vcpu);
361	guest_pte = *FNAME(fetch_guest)(vcpu, &walker, PT_PAGE_TABLE_LEVEL,
362	vaddr);
363	FNAME(release_walker)(&walker);
364
365	if (!is_present_pte(guest_pte))
366	return UNMAPPED_GVA;
367
368	if (walker.level == PT_DIRECTORY_LEVEL) {
369	ASSERT((guest_pte & PT_PAGE_SIZE_MASK));
370	ASSERT(PTTYPE == 64 \|\| is_pse(vcpu));
371
372	gpa = (guest_pte & PT_DIR_BASE_ADDR_MASK) \| (vaddr &
373	(PT_LEVEL_MASK(PT_PAGE_TABLE_LEVEL) \| ~PAGE_MASK));
374
375	if (PTTYPE == 32 && is_cpuid_PSE36())
376	gpa \|= (guest_pte & PT32_DIR_PSE36_MASK) <<
377	(32 - PT32_DIR_PSE36_SHIFT);
378	} else {
379	gpa = (guest_pte & PT_BASE_ADDR_MASK);
380	gpa \|= (vaddr & ~PAGE_MASK);
381	}
382
383	return gpa;
384	}
385
386	#undef pt_element_t
387	#undef guest_walker
388	#undef FNAME
389	#undef PT_BASE_ADDR_MASK
390	#undef PT_INDEX
391	#undef SHADOW_PT_INDEX
392	#undef PT_LEVEL_MASK
393	#undef PT_PTE_COPY_MASK
394	#undef PT_NON_PTE_COPY_MASK
395	#undef PT_DIR_BASE_ADDR_MASK