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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
c7addb90 | 34 | #define PT_LEVEL_BITS PT64_LEVEL_BITS |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
37 | #else | |
38 | #define PT_MAX_FULL_LEVELS 2 | |
39 | #endif | |
6aa8b732 AK |
40 | #elif PTTYPE == 32 |
41 | #define pt_element_t u32 | |
42 | #define guest_walker guest_walker32 | |
43 | #define FNAME(name) paging##32_##name | |
44 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
45 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
46 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
47 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
48 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
c7addb90 | 49 | #define PT_LEVEL_BITS PT32_LEVEL_BITS |
cea0f0e7 | 50 | #define PT_MAX_FULL_LEVELS 2 |
6aa8b732 AK |
51 | #else |
52 | #error Invalid PTTYPE value | |
53 | #endif | |
54 | ||
55 | /* | |
56 | * The guest_walker structure emulates the behavior of the hardware page | |
57 | * table walker. | |
58 | */ | |
59 | struct guest_walker { | |
60 | int level; | |
cea0f0e7 | 61 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
6aa8b732 | 62 | pt_element_t *table; |
fe551881 | 63 | pt_element_t pte; |
ac79c978 | 64 | pt_element_t *ptep; |
fe551881 SL |
65 | struct page *page; |
66 | int index; | |
6aa8b732 | 67 | pt_element_t inherited_ar; |
815af8d4 | 68 | gfn_t gfn; |
7993ba43 | 69 | u32 error_code; |
6aa8b732 AK |
70 | }; |
71 | ||
ac79c978 AK |
72 | /* |
73 | * Fetch a guest pte for a guest virtual address | |
74 | */ | |
7993ba43 AK |
75 | static int FNAME(walk_addr)(struct guest_walker *walker, |
76 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 77 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 AK |
78 | { |
79 | hpa_t hpa; | |
80 | struct kvm_memory_slot *slot; | |
ac79c978 | 81 | pt_element_t *ptep; |
1b0973bd | 82 | pt_element_t root; |
cea0f0e7 | 83 | gfn_t table_gfn; |
6aa8b732 | 84 | |
cea0f0e7 | 85 | pgprintk("%s: addr %lx\n", __FUNCTION__, addr); |
6aa8b732 | 86 | walker->level = vcpu->mmu.root_level; |
1b0973bd | 87 | walker->table = NULL; |
fe551881 SL |
88 | walker->page = NULL; |
89 | walker->ptep = NULL; | |
1b0973bd AK |
90 | root = vcpu->cr3; |
91 | #if PTTYPE == 64 | |
92 | if (!is_long_mode(vcpu)) { | |
93 | walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3]; | |
94 | root = *walker->ptep; | |
fe551881 | 95 | walker->pte = root; |
1b0973bd | 96 | if (!(root & PT_PRESENT_MASK)) |
7993ba43 | 97 | goto not_present; |
1b0973bd AK |
98 | --walker->level; |
99 | } | |
100 | #endif | |
cea0f0e7 AK |
101 | table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
102 | walker->table_gfn[walker->level - 1] = table_gfn; | |
103 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
104 | walker->level - 1, table_gfn); | |
105 | slot = gfn_to_memslot(vcpu->kvm, table_gfn); | |
1b0973bd | 106 | hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK); |
fe551881 SL |
107 | walker->page = pfn_to_page(hpa >> PAGE_SHIFT); |
108 | walker->table = kmap_atomic(walker->page, KM_USER0); | |
6aa8b732 | 109 | |
a9058ecd | 110 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
f802a307 | 111 | (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0); |
6aa8b732 | 112 | |
6aa8b732 | 113 | walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK; |
ac79c978 AK |
114 | |
115 | for (;;) { | |
116 | int index = PT_INDEX(addr, walker->level); | |
117 | hpa_t paddr; | |
118 | ||
119 | ptep = &walker->table[index]; | |
fe551881 | 120 | walker->index = index; |
ac79c978 AK |
121 | ASSERT(((unsigned long)walker->table & PAGE_MASK) == |
122 | ((unsigned long)ptep & PAGE_MASK)); | |
123 | ||
815af8d4 | 124 | if (!is_present_pte(*ptep)) |
7993ba43 AK |
125 | goto not_present; |
126 | ||
127 | if (write_fault && !is_writeble_pte(*ptep)) | |
128 | if (user_fault || is_write_protection(vcpu)) | |
129 | goto access_error; | |
130 | ||
131 | if (user_fault && !(*ptep & PT_USER_MASK)) | |
132 | goto access_error; | |
133 | ||
73b1087e AK |
134 | #if PTTYPE == 64 |
135 | if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK)) | |
136 | goto access_error; | |
137 | #endif | |
138 | ||
bf3f8e86 AK |
139 | if (!(*ptep & PT_ACCESSED_MASK)) { |
140 | mark_page_dirty(vcpu->kvm, table_gfn); | |
141 | *ptep |= PT_ACCESSED_MASK; | |
142 | } | |
815af8d4 AK |
143 | |
144 | if (walker->level == PT_PAGE_TABLE_LEVEL) { | |
145 | walker->gfn = (*ptep & PT_BASE_ADDR_MASK) | |
146 | >> PAGE_SHIFT; | |
147 | break; | |
148 | } | |
149 | ||
150 | if (walker->level == PT_DIRECTORY_LEVEL | |
151 | && (*ptep & PT_PAGE_SIZE_MASK) | |
152 | && (PTTYPE == 64 || is_pse(vcpu))) { | |
153 | walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK) | |
154 | >> PAGE_SHIFT; | |
155 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); | |
ac79c978 | 156 | break; |
815af8d4 | 157 | } |
ac79c978 | 158 | |
ca5aac1f | 159 | walker->inherited_ar &= walker->table[index]; |
cea0f0e7 | 160 | table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; |
ac79c978 | 161 | kunmap_atomic(walker->table, KM_USER0); |
fe551881 SL |
162 | paddr = safe_gpa_to_hpa(vcpu, table_gfn << PAGE_SHIFT); |
163 | walker->page = pfn_to_page(paddr >> PAGE_SHIFT); | |
164 | walker->table = kmap_atomic(walker->page, KM_USER0); | |
ac79c978 | 165 | --walker->level; |
cea0f0e7 AK |
166 | walker->table_gfn[walker->level - 1 ] = table_gfn; |
167 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
168 | walker->level - 1, table_gfn); | |
ac79c978 | 169 | } |
fe551881 SL |
170 | walker->pte = *ptep; |
171 | if (walker->page) | |
172 | walker->ptep = NULL; | |
173 | if (walker->table) | |
174 | kunmap_atomic(walker->table, KM_USER0); | |
374cbac0 | 175 | pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep); |
7993ba43 AK |
176 | return 1; |
177 | ||
178 | not_present: | |
179 | walker->error_code = 0; | |
180 | goto err; | |
181 | ||
182 | access_error: | |
183 | walker->error_code = PFERR_PRESENT_MASK; | |
184 | ||
185 | err: | |
186 | if (write_fault) | |
187 | walker->error_code |= PFERR_WRITE_MASK; | |
188 | if (user_fault) | |
189 | walker->error_code |= PFERR_USER_MASK; | |
73b1087e AK |
190 | if (fetch_fault) |
191 | walker->error_code |= PFERR_FETCH_MASK; | |
1b0973bd AK |
192 | if (walker->table) |
193 | kunmap_atomic(walker->table, KM_USER0); | |
fe551881 | 194 | return 0; |
6aa8b732 AK |
195 | } |
196 | ||
bf3f8e86 AK |
197 | static void FNAME(mark_pagetable_dirty)(struct kvm *kvm, |
198 | struct guest_walker *walker) | |
199 | { | |
200 | mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]); | |
201 | } | |
202 | ||
e60d75ea AK |
203 | static void FNAME(set_pte_common)(struct kvm_vcpu *vcpu, |
204 | u64 *shadow_pte, | |
205 | gpa_t gaddr, | |
fe551881 | 206 | pt_element_t gpte, |
e60d75ea | 207 | u64 access_bits, |
97a0a01e | 208 | int user_fault, |
63b1ad24 | 209 | int write_fault, |
97a0a01e AK |
210 | int *ptwrite, |
211 | struct guest_walker *walker, | |
e60d75ea AK |
212 | gfn_t gfn) |
213 | { | |
214 | hpa_t paddr; | |
fe551881 | 215 | int dirty = gpte & PT_DIRTY_MASK; |
c7addb90 AK |
216 | u64 spte; |
217 | int was_rmapped = is_rmap_pte(*shadow_pte); | |
97a0a01e AK |
218 | |
219 | pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d" | |
220 | " user_fault %d gfn %lx\n", | |
c7addb90 | 221 | __FUNCTION__, *shadow_pte, (u64)gpte, access_bits, |
97a0a01e AK |
222 | write_fault, user_fault, gfn); |
223 | ||
224 | if (write_fault && !dirty) { | |
fe551881 SL |
225 | pt_element_t *guest_ent, *tmp = NULL; |
226 | ||
227 | if (walker->ptep) | |
228 | guest_ent = walker->ptep; | |
229 | else { | |
230 | tmp = kmap_atomic(walker->page, KM_USER0); | |
231 | guest_ent = &tmp[walker->index]; | |
232 | } | |
233 | ||
234 | *guest_ent |= PT_DIRTY_MASK; | |
235 | if (!walker->ptep) | |
236 | kunmap_atomic(tmp, KM_USER0); | |
97a0a01e AK |
237 | dirty = 1; |
238 | FNAME(mark_pagetable_dirty)(vcpu->kvm, walker); | |
239 | } | |
e60d75ea | 240 | |
12b7d28f AK |
241 | /* |
242 | * We don't set the accessed bit, since we sometimes want to see | |
243 | * whether the guest actually used the pte (in order to detect | |
244 | * demand paging). | |
245 | */ | |
246 | spte = PT_PRESENT_MASK | PT_DIRTY_MASK; | |
fe551881 | 247 | spte |= gpte & PT64_NX_MASK; |
e60d75ea AK |
248 | if (!dirty) |
249 | access_bits &= ~PT_WRITABLE_MASK; | |
250 | ||
251 | paddr = gpa_to_hpa(vcpu, gaddr & PT64_BASE_ADDR_MASK); | |
252 | ||
0d551bb6 | 253 | spte |= PT_PRESENT_MASK; |
97a0a01e | 254 | if (access_bits & PT_USER_MASK) |
0d551bb6 | 255 | spte |= PT_USER_MASK; |
e60d75ea AK |
256 | |
257 | if (is_error_hpa(paddr)) { | |
c7addb90 AK |
258 | set_shadow_pte(shadow_pte, |
259 | shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK); | |
e60d75ea AK |
260 | return; |
261 | } | |
262 | ||
0d551bb6 | 263 | spte |= paddr; |
e60d75ea | 264 | |
97a0a01e AK |
265 | if ((access_bits & PT_WRITABLE_MASK) |
266 | || (write_fault && !is_write_protection(vcpu) && !user_fault)) { | |
e60d75ea AK |
267 | struct kvm_mmu_page *shadow; |
268 | ||
0d551bb6 | 269 | spte |= PT_WRITABLE_MASK; |
97a0a01e AK |
270 | if (user_fault) { |
271 | mmu_unshadow(vcpu, gfn); | |
272 | goto unshadowed; | |
273 | } | |
274 | ||
e60d75ea AK |
275 | shadow = kvm_mmu_lookup_page(vcpu, gfn); |
276 | if (shadow) { | |
277 | pgprintk("%s: found shadow page for %lx, marking ro\n", | |
278 | __FUNCTION__, gfn); | |
279 | access_bits &= ~PT_WRITABLE_MASK; | |
0d551bb6 AK |
280 | if (is_writeble_pte(spte)) { |
281 | spte &= ~PT_WRITABLE_MASK; | |
cbdd1bea | 282 | kvm_x86_ops->tlb_flush(vcpu); |
e60d75ea | 283 | } |
97a0a01e AK |
284 | if (write_fault) |
285 | *ptwrite = 1; | |
e60d75ea AK |
286 | } |
287 | } | |
288 | ||
97a0a01e AK |
289 | unshadowed: |
290 | ||
e60d75ea AK |
291 | if (access_bits & PT_WRITABLE_MASK) |
292 | mark_page_dirty(vcpu->kvm, gaddr >> PAGE_SHIFT); | |
293 | ||
c7addb90 | 294 | pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte); |
e663ee64 | 295 | set_shadow_pte(shadow_pte, spte); |
e60d75ea | 296 | page_header_update_slot(vcpu->kvm, shadow_pte, gaddr); |
97a0a01e | 297 | if (!was_rmapped) |
290fc38d IE |
298 | rmap_add(vcpu, shadow_pte, (gaddr & PT64_BASE_ADDR_MASK) |
299 | >> PAGE_SHIFT); | |
12b7d28f AK |
300 | if (!ptwrite || !*ptwrite) |
301 | vcpu->last_pte_updated = shadow_pte; | |
e60d75ea AK |
302 | } |
303 | ||
fe551881 | 304 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte, |
63b1ad24 | 305 | u64 *shadow_pte, u64 access_bits, |
97a0a01e AK |
306 | int user_fault, int write_fault, int *ptwrite, |
307 | struct guest_walker *walker, gfn_t gfn) | |
6aa8b732 | 308 | { |
fe551881 SL |
309 | access_bits &= gpte; |
310 | FNAME(set_pte_common)(vcpu, shadow_pte, gpte & PT_BASE_ADDR_MASK, | |
97a0a01e AK |
311 | gpte, access_bits, user_fault, write_fault, |
312 | ptwrite, walker, gfn); | |
6aa8b732 AK |
313 | } |
314 | ||
0028425f | 315 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page, |
c7addb90 AK |
316 | u64 *spte, const void *pte, int bytes, |
317 | int offset_in_pte) | |
0028425f AK |
318 | { |
319 | pt_element_t gpte; | |
320 | ||
0028425f | 321 | gpte = *(const pt_element_t *)pte; |
c7addb90 AK |
322 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) { |
323 | if (!offset_in_pte && !is_present_pte(gpte)) | |
324 | set_shadow_pte(spte, shadow_notrap_nonpresent_pte); | |
325 | return; | |
326 | } | |
327 | if (bytes < sizeof(pt_element_t)) | |
0028425f AK |
328 | return; |
329 | pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte); | |
fe551881 | 330 | FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0, |
97a0a01e | 331 | 0, NULL, NULL, |
0028425f AK |
332 | (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT); |
333 | } | |
334 | ||
fe551881 | 335 | static void FNAME(set_pde)(struct kvm_vcpu *vcpu, pt_element_t gpde, |
97a0a01e AK |
336 | u64 *shadow_pte, u64 access_bits, |
337 | int user_fault, int write_fault, int *ptwrite, | |
338 | struct guest_walker *walker, gfn_t gfn) | |
6aa8b732 AK |
339 | { |
340 | gpa_t gaddr; | |
341 | ||
fe551881 | 342 | access_bits &= gpde; |
815af8d4 | 343 | gaddr = (gpa_t)gfn << PAGE_SHIFT; |
6aa8b732 | 344 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
fe551881 | 345 | gaddr |= (gpde & PT32_DIR_PSE36_MASK) << |
6aa8b732 | 346 | (32 - PT32_DIR_PSE36_SHIFT); |
e60d75ea | 347 | FNAME(set_pte_common)(vcpu, shadow_pte, gaddr, |
97a0a01e AK |
348 | gpde, access_bits, user_fault, write_fault, |
349 | ptwrite, walker, gfn); | |
6aa8b732 AK |
350 | } |
351 | ||
6aa8b732 AK |
352 | /* |
353 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
354 | */ | |
355 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
97a0a01e AK |
356 | struct guest_walker *walker, |
357 | int user_fault, int write_fault, int *ptwrite) | |
6aa8b732 AK |
358 | { |
359 | hpa_t shadow_addr; | |
360 | int level; | |
ef0197e8 | 361 | u64 *shadow_ent; |
6aa8b732 | 362 | u64 *prev_shadow_ent = NULL; |
ac79c978 | 363 | |
fe551881 | 364 | if (!is_present_pte(walker->pte)) |
ac79c978 | 365 | return NULL; |
6aa8b732 AK |
366 | |
367 | shadow_addr = vcpu->mmu.root_hpa; | |
368 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
369 | if (level == PT32E_ROOT_LEVEL) { |
370 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
371 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
372 | --level; | |
373 | } | |
6aa8b732 AK |
374 | |
375 | for (; ; level--) { | |
376 | u32 index = SHADOW_PT_INDEX(addr, level); | |
25c0de2c | 377 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 378 | u64 shadow_pte; |
cea0f0e7 AK |
379 | int metaphysical; |
380 | gfn_t table_gfn; | |
d28c6cfb | 381 | unsigned hugepage_access = 0; |
6aa8b732 | 382 | |
ef0197e8 | 383 | shadow_ent = ((u64 *)__va(shadow_addr)) + index; |
c7addb90 | 384 | if (is_shadow_present_pte(*shadow_ent)) { |
6aa8b732 | 385 | if (level == PT_PAGE_TABLE_LEVEL) |
97a0a01e | 386 | break; |
6aa8b732 AK |
387 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; |
388 | prev_shadow_ent = shadow_ent; | |
389 | continue; | |
390 | } | |
391 | ||
ef0197e8 AK |
392 | if (level == PT_PAGE_TABLE_LEVEL) |
393 | break; | |
6aa8b732 | 394 | |
cea0f0e7 AK |
395 | if (level - 1 == PT_PAGE_TABLE_LEVEL |
396 | && walker->level == PT_DIRECTORY_LEVEL) { | |
397 | metaphysical = 1; | |
fe551881 | 398 | hugepage_access = walker->pte; |
d28c6cfb | 399 | hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK; |
fe551881 | 400 | if (walker->pte & PT64_NX_MASK) |
d55e2cb2 | 401 | hugepage_access |= (1 << 2); |
d28c6cfb | 402 | hugepage_access >>= PT_WRITABLE_SHIFT; |
fe551881 | 403 | table_gfn = (walker->pte & PT_BASE_ADDR_MASK) |
cea0f0e7 AK |
404 | >> PAGE_SHIFT; |
405 | } else { | |
406 | metaphysical = 0; | |
407 | table_gfn = walker->table_gfn[level - 2]; | |
408 | } | |
409 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, | |
d28c6cfb AK |
410 | metaphysical, hugepage_access, |
411 | shadow_ent); | |
47ad8e68 | 412 | shadow_addr = __pa(shadow_page->spt); |
aef3d3fe AK |
413 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
414 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 415 | *shadow_ent = shadow_pte; |
6aa8b732 AK |
416 | prev_shadow_ent = shadow_ent; |
417 | } | |
ef0197e8 AK |
418 | |
419 | if (walker->level == PT_DIRECTORY_LEVEL) { | |
fe551881 | 420 | FNAME(set_pde)(vcpu, walker->pte, shadow_ent, |
97a0a01e AK |
421 | walker->inherited_ar, user_fault, write_fault, |
422 | ptwrite, walker, walker->gfn); | |
ef0197e8 AK |
423 | } else { |
424 | ASSERT(walker->level == PT_PAGE_TABLE_LEVEL); | |
fe551881 | 425 | FNAME(set_pte)(vcpu, walker->pte, shadow_ent, |
97a0a01e AK |
426 | walker->inherited_ar, user_fault, write_fault, |
427 | ptwrite, walker, walker->gfn); | |
ef0197e8 AK |
428 | } |
429 | return shadow_ent; | |
6aa8b732 AK |
430 | } |
431 | ||
6aa8b732 AK |
432 | /* |
433 | * Page fault handler. There are several causes for a page fault: | |
434 | * - there is no shadow pte for the guest pte | |
435 | * - write access through a shadow pte marked read only so that we can set | |
436 | * the dirty bit | |
437 | * - write access to a shadow pte marked read only so we can update the page | |
438 | * dirty bitmap, when userspace requests it | |
439 | * - mmio access; in this case we will never install a present shadow pte | |
440 | * - normal guest page fault due to the guest pte marked not present, not | |
441 | * writable, or not executable | |
442 | * | |
e2dec939 AK |
443 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
444 | * a negative value on error. | |
6aa8b732 AK |
445 | */ |
446 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
447 | u32 error_code) | |
448 | { | |
449 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 450 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 451 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 AK |
452 | struct guest_walker walker; |
453 | u64 *shadow_pte; | |
cea0f0e7 | 454 | int write_pt = 0; |
e2dec939 | 455 | int r; |
6aa8b732 | 456 | |
cea0f0e7 | 457 | pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code); |
37a7d8b0 | 458 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 459 | |
e2dec939 AK |
460 | r = mmu_topup_memory_caches(vcpu); |
461 | if (r) | |
462 | return r; | |
714b93da | 463 | |
6aa8b732 AK |
464 | /* |
465 | * Look up the shadow pte for the faulting address. | |
466 | */ | |
73b1087e AK |
467 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
468 | fetch_fault); | |
6aa8b732 AK |
469 | |
470 | /* | |
471 | * The page is not mapped by the guest. Let the guest handle it. | |
472 | */ | |
7993ba43 AK |
473 | if (!r) { |
474 | pgprintk("%s: guest page fault\n", __FUNCTION__); | |
475 | inject_page_fault(vcpu, addr, walker.error_code); | |
a25f7e1f | 476 | vcpu->last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
477 | return 0; |
478 | } | |
479 | ||
97a0a01e AK |
480 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault, |
481 | &write_pt); | |
482 | pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__, | |
483 | shadow_pte, *shadow_pte, write_pt); | |
cea0f0e7 | 484 | |
a25f7e1f AK |
485 | if (!write_pt) |
486 | vcpu->last_pt_write_count = 0; /* reset fork detector */ | |
487 | ||
6aa8b732 AK |
488 | /* |
489 | * mmio: emulate if accessible, otherwise its a guest fault. | |
490 | */ | |
d27d4aca | 491 | if (is_io_pte(*shadow_pte)) |
7993ba43 | 492 | return 1; |
6aa8b732 | 493 | |
1165f5fe | 494 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 495 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
6aa8b732 | 496 | |
cea0f0e7 | 497 | return write_pt; |
6aa8b732 AK |
498 | } |
499 | ||
500 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
501 | { | |
502 | struct guest_walker walker; | |
e119d117 AK |
503 | gpa_t gpa = UNMAPPED_GVA; |
504 | int r; | |
6aa8b732 | 505 | |
e119d117 | 506 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0); |
6aa8b732 | 507 | |
e119d117 AK |
508 | if (r) { |
509 | gpa = (gpa_t)walker.gfn << PAGE_SHIFT; | |
510 | gpa |= vaddr & ~PAGE_MASK; | |
6aa8b732 AK |
511 | } |
512 | ||
513 | return gpa; | |
514 | } | |
515 | ||
c7addb90 AK |
516 | static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu, |
517 | struct kvm_mmu_page *sp) | |
518 | { | |
519 | int i; | |
520 | pt_element_t *gpt; | |
521 | ||
522 | if (sp->role.metaphysical || PTTYPE == 32) { | |
523 | nonpaging_prefetch_page(vcpu, sp); | |
524 | return; | |
525 | } | |
526 | ||
527 | gpt = kmap_atomic(gfn_to_page(vcpu->kvm, sp->gfn), KM_USER0); | |
528 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) | |
529 | if (is_present_pte(gpt[i])) | |
530 | sp->spt[i] = shadow_trap_nonpresent_pte; | |
531 | else | |
532 | sp->spt[i] = shadow_notrap_nonpresent_pte; | |
533 | kunmap_atomic(gpt, KM_USER0); | |
534 | } | |
535 | ||
6aa8b732 AK |
536 | #undef pt_element_t |
537 | #undef guest_walker | |
538 | #undef FNAME | |
539 | #undef PT_BASE_ADDR_MASK | |
540 | #undef PT_INDEX | |
541 | #undef SHADOW_PT_INDEX | |
542 | #undef PT_LEVEL_MASK | |
6aa8b732 | 543 | #undef PT_DIR_BASE_ADDR_MASK |
c7addb90 | 544 | #undef PT_LEVEL_BITS |
cea0f0e7 | 545 | #undef PT_MAX_FULL_LEVELS |