[mirror_ubuntu-zesty-kernel.git] / drivers / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#else
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
#else
	#error Invalid PTTYPE value
#endif

#define gpte_to_gfn FNAME(gpte_to_gfn)
#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t pte;
	pt_element_t inherited_ar;
	gfn_t gfn;
	u32 error_code;
};

static gfn_t gpte_to_gfn(pt_element_t gpte)
{
	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
{
	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	pt_element_t pte;
	gfn_t table_gfn;
	unsigned index;
	gpa_t pte_gpa;

	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
	walker->level = vcpu->mmu.root_level;
	pte = vcpu->cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		pte = vcpu->pdptrs[(addr >> 30) & 3];
		if (!is_present_pte(pte))
			goto not_present;
		--walker->level;
	}
#endif
	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK;

	for (;;) {
		index = PT_INDEX(addr, walker->level);

		table_gfn = gpte_to_gfn(pte);
		pte_gpa = gfn_to_gpa(table_gfn);
		pte_gpa += index * sizeof(pt_element_t);
		walker->table_gfn[walker->level - 1] = table_gfn;
		pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
			 walker->level - 1, table_gfn);

		kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));

		if (!is_present_pte(pte))
			goto not_present;

		if (write_fault && !is_writeble_pte(pte))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(pte & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(pte & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			pte |= PT_ACCESSED_MASK;
			kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
		}

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = gpte_to_gfn(pte);
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (pte & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = gpte_to_gfn_pde(pte);
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			if (PTTYPE == 32 && is_cpuid_PSE36())
				walker->gfn += pse36_gfn_delta(pte);
			break;
		}

		walker->inherited_ar &= pte;
		--walker->level;
	}

	if (write_fault && !is_dirty_pte(pte)) {
		mark_page_dirty(vcpu->kvm, table_gfn);
		pte |= PT_DIRTY_MASK;
		kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
		kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
	}

	walker->pte = pte;
	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
			   u64 *shadow_pte, u64 access_bits,
			   int user_fault, int write_fault,
			   int *ptwrite, struct guest_walker *walker,
			   gfn_t gfn)
{
	int dirty = gpte & PT_DIRTY_MASK;
	u64 spte;
	int was_rmapped = is_rmap_pte(*shadow_pte);
	struct page *page;

	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
		 " user_fault %d gfn %lx\n",
		 __FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
		 write_fault, user_fault, gfn);

	access_bits &= gpte;
	/*
	 * We don't set the accessed bit, since we sometimes want to see
	 * whether the guest actually used the pte (in order to detect
	 * demand paging).
	 */
	spte = PT_PRESENT_MASK | PT_DIRTY_MASK;
	spte |= gpte & PT64_NX_MASK;
	if (!dirty)
		access_bits &= ~PT_WRITABLE_MASK;

	page = gfn_to_page(vcpu->kvm, gfn);

	spte |= PT_PRESENT_MASK;
	if (access_bits & PT_USER_MASK)
		spte |= PT_USER_MASK;

	if (is_error_page(page)) {
		set_shadow_pte(shadow_pte,
			       shadow_trap_nonpresent_pte | PT_SHADOW_IO_MARK);
		kvm_release_page_clean(page);
		return;
	}

	spte |= page_to_phys(page);

	if ((access_bits & PT_WRITABLE_MASK)
	    || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
		struct kvm_mmu_page *shadow;

		spte |= PT_WRITABLE_MASK;
		if (user_fault) {
			mmu_unshadow(vcpu->kvm, gfn);
			goto unshadowed;
		}

		shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
		if (shadow) {
			pgprintk("%s: found shadow page for %lx, marking ro\n",
				 __FUNCTION__, gfn);
			access_bits &= ~PT_WRITABLE_MASK;
			if (is_writeble_pte(spte)) {
				spte &= ~PT_WRITABLE_MASK;
				kvm_x86_ops->tlb_flush(vcpu);
			}
			if (write_fault)
				*ptwrite = 1;
		}
	}

unshadowed:

	if (access_bits & PT_WRITABLE_MASK)
		mark_page_dirty(vcpu->kvm, gfn);

	pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
	set_shadow_pte(shadow_pte, spte);
	page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
	if (!was_rmapped) {
		rmap_add(vcpu, shadow_pte, gfn);
		if (!is_rmap_pte(*shadow_pte))
			kvm_release_page_clean(page);
	}
	else
		kvm_release_page_clean(page);
	if (!ptwrite || !*ptwrite)
		vcpu->last_pte_updated = shadow_pte;
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte, int bytes,
			      int offset_in_pte)
{
	pt_element_t gpte;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!offset_in_pte && !is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	if (bytes < sizeof(pt_element_t))
		return;
	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, 0,
		       0, NULL, NULL, gpte_to_gfn(gpte));
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *walker,
			 int user_fault, int write_fault, int *ptwrite)
{
	hpa_t shadow_addr;
	int level;
	u64 *shadow_ent;

	if (!is_present_pte(walker->pte))
		return NULL;

	shadow_addr = vcpu->mmu.root_hpa;
	level = vcpu->mmu.shadow_root_level;
	if (level == PT32E_ROOT_LEVEL) {
		shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
		shadow_addr &= PT64_BASE_ADDR_MASK;
		--level;
	}

	for (; ; level--) {
		u32 index = SHADOW_PT_INDEX(addr, level);
		struct kvm_mmu_page *shadow_page;
		u64 shadow_pte;
		int metaphysical;
		gfn_t table_gfn;
		unsigned hugepage_access = 0;

		shadow_ent = ((u64 *)__va(shadow_addr)) + index;
		if (is_shadow_present_pte(*shadow_ent)) {
			if (level == PT_PAGE_TABLE_LEVEL)
				break;
			shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
			continue;
		}

		if (level == PT_PAGE_TABLE_LEVEL)
			break;

		if (level - 1 == PT_PAGE_TABLE_LEVEL
		    && walker->level == PT_DIRECTORY_LEVEL) {
			metaphysical = 1;
			hugepage_access = walker->pte;
			hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK;
			if (!is_dirty_pte(walker->pte))
				hugepage_access &= ~PT_WRITABLE_MASK;
			hugepage_access >>= PT_WRITABLE_SHIFT;
			if (walker->pte & PT64_NX_MASK)
				hugepage_access |= (1 << 2);
			table_gfn = gpte_to_gfn(walker->pte);
		} else {
			metaphysical = 0;
			table_gfn = walker->table_gfn[level - 2];
		}
		shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
					       metaphysical, hugepage_access,
					       shadow_ent);
		shadow_addr = __pa(shadow_page->spt);
		shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
			| PT_WRITABLE_MASK | PT_USER_MASK;
		*shadow_ent = shadow_pte;
	}

	FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
		       walker->inherited_ar, user_fault, write_fault,
		       ptwrite, walker, walker->gfn);

	return shadow_ent;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;

	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __FUNCTION__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  &write_pt);
	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->last_pt_write_count = 0; /* reset fork detector */

	/*
	 * mmio: emulate if accessible, otherwise its a guest fault.
	 */
	if (is_io_pte(*shadow_pte))
		return 1;

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");

	return write_pt;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = gfn_to_gpa(walker.gfn);
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i, offset = 0;
	pt_element_t *gpt;
	struct page *page;

	if (sp->role.metaphysical
	    || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	if (PTTYPE == 32)
		offset = sp->role.quadrant << PT64_LEVEL_BITS;
	page = gfn_to_page(vcpu->kvm, sp->gfn);
	gpt = kmap_atomic(page, KM_USER0);
	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
		if (is_present_pte(gpt[offset + i]))
			sp->spt[i] = shadow_trap_nonpresent_pte;
		else
			sp->spt[i] = shadow_notrap_nonpresent_pte;
	kunmap_atomic(gpt, KM_USER0);
	kvm_release_page_clean(page);
}

#undef pt_element_t
#undef guest_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef SHADOW_PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
#undef gpte_to_gfn
#undef gpte_to_gfn_pde
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
	28	#define FNAME(name) paging##64_##name
	29	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	30	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	31	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	32	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90	34	#define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7 AK	35	#ifdef CONFIG_X86_64
	36	#define PT_MAX_FULL_LEVELS 4
	37	#else
	38	#define PT_MAX_FULL_LEVELS 2
	39	#endif
6aa8b732 AK	40	#elif PTTYPE == 32
	41	#define pt_element_t u32
	42	#define guest_walker guest_walker32
	43	#define FNAME(name) paging##32_##name
	44	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	45	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	46	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	47	#define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
	48	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90	49	#define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7	50	#define PT_MAX_FULL_LEVELS 2
6aa8b732 AK	51	#else
	52	#error Invalid PTTYPE value
	53	#endif
	54
5fb07ddb AK	55	#define gpte_to_gfn FNAME(gpte_to_gfn)
	56	#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
	57
6aa8b732 AK	58	/*
	59	* The guest_walker structure emulates the behavior of the hardware page
	60	* table walker.
	61	*/
	62	struct guest_walker {
	63	int level;
cea0f0e7	64	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
fe551881	65	pt_element_t pte;
6aa8b732	66	pt_element_t inherited_ar;
815af8d4	67	gfn_t gfn;
7993ba43	68	u32 error_code;
6aa8b732 AK	69	};
6aa8b732 AK	70
5fb07ddb AK	71	static gfn_t gpte_to_gfn(pt_element_t gpte)
	72	{
	73	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
	74	}
	75
	76	static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
	77	{
	78	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
	79	}
	80
ac79c978 AK	81	/*
	82	* Fetch a guest pte for a guest virtual address
	83	*/
7993ba43 AK	84	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	85	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	86	int write_fault, int user_fault, int fetch_fault)
6aa8b732	87	{
42bf3f0a	88	pt_element_t pte;
cea0f0e7	89	gfn_t table_gfn;
42bf3f0a AK	90	unsigned index;
42bf3f0a AK	91	gpa_t pte_gpa;
6aa8b732	92
cea0f0e7	93	pgprintk("%s: addr %lx\n", __FUNCTION__, addr);
6aa8b732	94	walker->level = vcpu->mmu.root_level;
42bf3f0a	95	pte = vcpu->cr3;
1b0973bd AK	96	#if PTTYPE == 64
1b0973bd AK	97	if (!is_long_mode(vcpu)) {
42bf3f0a AK	98	pte = vcpu->pdptrs[(addr >> 30) & 3];
42bf3f0a AK	99	if (!is_present_pte(pte))
7993ba43	100	goto not_present;
1b0973bd AK	101	--walker->level;
	102	}
	103	#endif
a9058ecd	104	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
f802a307	105	(vcpu->cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	106
6aa8b732	107	walker->inherited_ar = PT_USER_MASK \| PT_WRITABLE_MASK;
ac79c978 AK	108
ac79c978 AK	109	for (;;) {
42bf3f0a	110	index = PT_INDEX(addr, walker->level);
ac79c978	111
5fb07ddb	112	table_gfn = gpte_to_gfn(pte);
1755fbcc	113	pte_gpa = gfn_to_gpa(table_gfn);
ec8d4eae	114	pte_gpa += index * sizeof(pt_element_t);
42bf3f0a AK	115	walker->table_gfn[walker->level - 1] = table_gfn;
	116	pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__,
	117	walker->level - 1, table_gfn);
	118
ec8d4eae	119	kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	120
42bf3f0a AK	121	if (!is_present_pte(pte))
7993ba43 AK	122	goto not_present;
7993ba43 AK	123
42bf3f0a	124	if (write_fault && !is_writeble_pte(pte))
7993ba43 AK	125	if (user_fault \|\| is_write_protection(vcpu))
	126	goto access_error;
	127
42bf3f0a	128	if (user_fault && !(pte & PT_USER_MASK))
7993ba43 AK	129	goto access_error;
7993ba43 AK	130
73b1087e	131	#if PTTYPE == 64
42bf3f0a	132	if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
73b1087e AK	133	goto access_error;
	134	#endif
	135
42bf3f0a	136	if (!(pte & PT_ACCESSED_MASK)) {
bf3f8e86	137	mark_page_dirty(vcpu->kvm, table_gfn);
42bf3f0a	138	pte \|= PT_ACCESSED_MASK;
ec8d4eae	139	kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
bf3f8e86	140	}
815af8d4 AK	141
815af8d4 AK	142	if (walker->level == PT_PAGE_TABLE_LEVEL) {
5fb07ddb	143	walker->gfn = gpte_to_gfn(pte);
815af8d4 AK	144	break;
	145	}
	146
	147	if (walker->level == PT_DIRECTORY_LEVEL
42bf3f0a	148	&& (pte & PT_PAGE_SIZE_MASK)
815af8d4	149	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
5fb07ddb	150	walker->gfn = gpte_to_gfn_pde(pte);
815af8d4	151	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
da928521 AK	152	if (PTTYPE == 32 && is_cpuid_PSE36())
da928521 AK	153	walker->gfn += pse36_gfn_delta(pte);
ac79c978	154	break;
815af8d4	155	}
ac79c978	156
42bf3f0a	157	walker->inherited_ar &= pte;
ac79c978 AK	158	--walker->level;
ac79c978 AK	159	}
42bf3f0a AK	160
	161	if (write_fault && !is_dirty_pte(pte)) {
	162	mark_page_dirty(vcpu->kvm, table_gfn);
	163	pte \|= PT_DIRTY_MASK;
ec8d4eae	164	kvm_write_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	165	kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
	166	}
	167
	168	walker->pte = pte;
	169	pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)pte);
7993ba43 AK	170	return 1;
	171
	172	not_present:
	173	walker->error_code = 0;
	174	goto err;
	175
	176	access_error:
	177	walker->error_code = PFERR_PRESENT_MASK;
	178
	179	err:
	180	if (write_fault)
	181	walker->error_code \|= PFERR_WRITE_MASK;
	182	if (user_fault)
	183	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	184	if (fetch_fault)
73b1087e AK	185	walker->error_code \|= PFERR_FETCH_MASK;
fe551881	186	return 0;
6aa8b732 AK	187	}
6aa8b732 AK	188
230c9a8f AK	189	static void FNAME(set_pte)(struct kvm_vcpu *vcpu, pt_element_t gpte,
	190	u64 *shadow_pte, u64 access_bits,
	191	int user_fault, int write_fault,
	192	int ptwrite, struct guest_walker walker,
	193	gfn_t gfn)
e60d75ea	194	{
fe551881	195	int dirty = gpte & PT_DIRTY_MASK;
c7addb90 AK	196	u64 spte;
c7addb90 AK	197	int was_rmapped = is_rmap_pte(*shadow_pte);
b238f7bc	198	struct page *page;
97a0a01e AK	199
	200	pgprintk("%s: spte %llx gpte %llx access %llx write_fault %d"
	201	" user_fault %d gfn %lx\n",
c7addb90	202	__FUNCTION__, *shadow_pte, (u64)gpte, access_bits,
97a0a01e AK	203	write_fault, user_fault, gfn);
97a0a01e AK	204
230c9a8f	205	access_bits &= gpte;
12b7d28f AK	206	/*
	207	* We don't set the accessed bit, since we sometimes want to see
	208	* whether the guest actually used the pte (in order to detect
	209	* demand paging).
	210	*/
	211	spte = PT_PRESENT_MASK \| PT_DIRTY_MASK;
fe551881	212	spte \|= gpte & PT64_NX_MASK;
e60d75ea AK	213	if (!dirty)
	214	access_bits &= ~PT_WRITABLE_MASK;
	215
4e542370	216	page = gfn_to_page(vcpu->kvm, gfn);
b238f7bc	217
0d551bb6	218	spte \|= PT_PRESENT_MASK;
97a0a01e	219	if (access_bits & PT_USER_MASK)
0d551bb6	220	spte \|= PT_USER_MASK;
e60d75ea	221
4e542370	222	if (is_error_page(page)) {
c7addb90 AK	223	set_shadow_pte(shadow_pte,
c7addb90 AK	224	shadow_trap_nonpresent_pte \| PT_SHADOW_IO_MARK);
b238f7bc	225	kvm_release_page_clean(page);
e60d75ea AK	226	return;
	227	}
	228
4e542370	229	spte \|= page_to_phys(page);
e60d75ea	230
97a0a01e AK	231	if ((access_bits & PT_WRITABLE_MASK)
97a0a01e AK	232	\|\| (write_fault && !is_write_protection(vcpu) && !user_fault)) {
e60d75ea AK	233	struct kvm_mmu_page *shadow;
e60d75ea AK	234
0d551bb6	235	spte \|= PT_WRITABLE_MASK;
97a0a01e	236	if (user_fault) {
f67a46f4	237	mmu_unshadow(vcpu->kvm, gfn);
97a0a01e AK	238	goto unshadowed;
	239	}
	240
f67a46f4	241	shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
e60d75ea AK	242	if (shadow) {
	243	pgprintk("%s: found shadow page for %lx, marking ro\n",
	244	__FUNCTION__, gfn);
	245	access_bits &= ~PT_WRITABLE_MASK;
0d551bb6 AK	246	if (is_writeble_pte(spte)) {
0d551bb6 AK	247	spte &= ~PT_WRITABLE_MASK;
cbdd1bea	248	kvm_x86_ops->tlb_flush(vcpu);
e60d75ea	249	}
97a0a01e AK	250	if (write_fault)
97a0a01e AK	251	*ptwrite = 1;
e60d75ea AK	252	}
	253	}
	254
97a0a01e AK	255	unshadowed:
97a0a01e AK	256
e60d75ea	257	if (access_bits & PT_WRITABLE_MASK)
4e542370	258	mark_page_dirty(vcpu->kvm, gfn);
e60d75ea	259
c7addb90	260	pgprintk("%s: setting spte %llx\n", __FUNCTION__, spte);
e663ee64	261	set_shadow_pte(shadow_pte, spte);
38c335f1	262	page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
8a7ae055	263	if (!was_rmapped) {
4e542370	264	rmap_add(vcpu, shadow_pte, gfn);
b238f7bc	265	if (!is_rmap_pte(*shadow_pte))
b4231d61	266	kvm_release_page_clean(page);
8a7ae055 IE	267	}
8a7ae055 IE	268	else
b238f7bc	269	kvm_release_page_clean(page);
12b7d28f AK	270	if (!ptwrite \|\| !*ptwrite)
12b7d28f AK	271	vcpu->last_pte_updated = shadow_pte;
e60d75ea AK	272	}
e60d75ea AK	273
0028425f	274	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
c7addb90 AK	275	u64 spte, const void pte, int bytes,
c7addb90 AK	276	int offset_in_pte)
0028425f AK	277	{
	278	pt_element_t gpte;
	279
0028425f	280	gpte = (const pt_element_t )pte;
c7addb90 AK	281	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
	282	if (!offset_in_pte && !is_present_pte(gpte))
	283	set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
	284	return;
	285	}
	286	if (bytes < sizeof(pt_element_t))
0028425f AK	287	return;
0028425f AK	288	pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte);
fe551881	289	FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK \| PT_WRITABLE_MASK, 0,
5fb07ddb	290	0, NULL, NULL, gpte_to_gfn(gpte));
0028425f AK	291	}
0028425f AK	292
6aa8b732 AK	293	/*
	294	* Fetch a shadow pte for a specific level in the paging hierarchy.
	295	*/
	296	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
97a0a01e AK	297	struct guest_walker *walker,
97a0a01e AK	298	int user_fault, int write_fault, int *ptwrite)
6aa8b732 AK	299	{
	300	hpa_t shadow_addr;
	301	int level;
ef0197e8	302	u64 *shadow_ent;
ac79c978	303
fe551881	304	if (!is_present_pte(walker->pte))
ac79c978	305	return NULL;
6aa8b732 AK	306
	307	shadow_addr = vcpu->mmu.root_hpa;
	308	level = vcpu->mmu.shadow_root_level;
aef3d3fe AK	309	if (level == PT32E_ROOT_LEVEL) {
	310	shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3];
	311	shadow_addr &= PT64_BASE_ADDR_MASK;
	312	--level;
	313	}
6aa8b732 AK	314
	315	for (; ; level--) {
	316	u32 index = SHADOW_PT_INDEX(addr, level);
25c0de2c	317	struct kvm_mmu_page *shadow_page;
8c7bb723	318	u64 shadow_pte;
cea0f0e7 AK	319	int metaphysical;
cea0f0e7 AK	320	gfn_t table_gfn;
d28c6cfb	321	unsigned hugepage_access = 0;
6aa8b732	322
ef0197e8	323	shadow_ent = ((u64 *)__va(shadow_addr)) + index;
c7addb90	324	if (is_shadow_present_pte(*shadow_ent)) {
6aa8b732	325	if (level == PT_PAGE_TABLE_LEVEL)
97a0a01e	326	break;
6aa8b732	327	shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
6aa8b732 AK	328	continue;
	329	}
	330
ef0197e8 AK	331	if (level == PT_PAGE_TABLE_LEVEL)
ef0197e8 AK	332	break;
6aa8b732	333
cea0f0e7 AK	334	if (level - 1 == PT_PAGE_TABLE_LEVEL
	335	&& walker->level == PT_DIRECTORY_LEVEL) {
	336	metaphysical = 1;
fe551881	337	hugepage_access = walker->pte;
d28c6cfb	338	hugepage_access &= PT_USER_MASK \| PT_WRITABLE_MASK;
cc70e737 AK	339	if (!is_dirty_pte(walker->pte))
cc70e737 AK	340	hugepage_access &= ~PT_WRITABLE_MASK;
c22e3514	341	hugepage_access >>= PT_WRITABLE_SHIFT;
fe551881	342	if (walker->pte & PT64_NX_MASK)
d55e2cb2	343	hugepage_access \|= (1 << 2);
5fb07ddb	344	table_gfn = gpte_to_gfn(walker->pte);
cea0f0e7 AK	345	} else {
	346	metaphysical = 0;
	347	table_gfn = walker->table_gfn[level - 2];
	348	}
	349	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
d28c6cfb AK	350	metaphysical, hugepage_access,
d28c6cfb AK	351	shadow_ent);
47ad8e68	352	shadow_addr = __pa(shadow_page->spt);
aef3d3fe AK	353	shadow_pte = shadow_addr \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
aef3d3fe AK	354	\| PT_WRITABLE_MASK \| PT_USER_MASK;
8c7bb723	355	*shadow_ent = shadow_pte;
6aa8b732	356	}
ef0197e8	357
050e6499 AK	358	FNAME(set_pte)(vcpu, walker->pte, shadow_ent,
	359	walker->inherited_ar, user_fault, write_fault,
	360	ptwrite, walker, walker->gfn);
	361
ef0197e8	362	return shadow_ent;
6aa8b732 AK	363	}
6aa8b732 AK	364
6aa8b732 AK	365	/*
	366	* Page fault handler. There are several causes for a page fault:
	367	* - there is no shadow pte for the guest pte
	368	* - write access through a shadow pte marked read only so that we can set
	369	* the dirty bit
	370	* - write access to a shadow pte marked read only so we can update the page
	371	* dirty bitmap, when userspace requests it
	372	* - mmio access; in this case we will never install a present shadow pte
	373	* - normal guest page fault due to the guest pte marked not present, not
	374	* writable, or not executable
	375	*
e2dec939 AK	376	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	377	* a negative value on error.
6aa8b732 AK	378	*/
	379	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	380	u32 error_code)
	381	{
	382	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	383	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	384	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	385	struct guest_walker walker;
6aa8b732 AK	386	u64 *shadow_pte;
cea0f0e7	387	int write_pt = 0;
e2dec939	388	int r;
6aa8b732	389
cea0f0e7	390	pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code);
37a7d8b0	391	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	392
e2dec939 AK	393	r = mmu_topup_memory_caches(vcpu);
	394	if (r)
	395	return r;
714b93da	396
6aa8b732 AK	397	/*
	398	* Look up the shadow pte for the faulting address.
	399	*/
73b1087e AK	400	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	401	fetch_fault);
6aa8b732 AK	402
	403	/*
	404	* The page is not mapped by the guest. Let the guest handle it.
	405	*/
7993ba43 AK	406	if (!r) {
	407	pgprintk("%s: guest page fault\n", __FUNCTION__);
	408	inject_page_fault(vcpu, addr, walker.error_code);
a25f7e1f	409	vcpu->last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	410	return 0;
	411	}
	412
97a0a01e AK	413	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
	414	&write_pt);
	415	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __FUNCTION__,
	416	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	417
a25f7e1f AK	418	if (!write_pt)
	419	vcpu->last_pt_write_count = 0; /* reset fork detector */
	420
6aa8b732 AK	421	/*
	422	* mmio: emulate if accessible, otherwise its a guest fault.
	423	*/
d27d4aca	424	if (is_io_pte(*shadow_pte))
7993ba43	425	return 1;
6aa8b732	426
1165f5fe	427	++vcpu->stat.pf_fixed;
37a7d8b0	428	kvm_mmu_audit(vcpu, "post page fault (fixed)");
6aa8b732	429
cea0f0e7	430	return write_pt;
6aa8b732 AK	431	}
	432
	433	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	434	{
	435	struct guest_walker walker;
e119d117 AK	436	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	437	int r;
6aa8b732	438
e119d117	439	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	440
e119d117	441	if (r) {
1755fbcc	442	gpa = gfn_to_gpa(walker.gfn);
e119d117	443	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	444	}
	445
	446	return gpa;
	447	}
	448
c7addb90 AK	449	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	450	struct kvm_mmu_page *sp)
	451	{
e5a4c8ca	452	int i, offset = 0;
c7addb90	453	pt_element_t *gpt;
8a7ae055	454	struct page *page;
c7addb90	455
e5a4c8ca AK	456	if (sp->role.metaphysical
e5a4c8ca AK	457	\|\| (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
c7addb90 AK	458	nonpaging_prefetch_page(vcpu, sp);
	459	return;
	460	}
	461
e5a4c8ca AK	462	if (PTTYPE == 32)
e5a4c8ca AK	463	offset = sp->role.quadrant << PT64_LEVEL_BITS;
8a7ae055 IE	464	page = gfn_to_page(vcpu->kvm, sp->gfn);
8a7ae055 IE	465	gpt = kmap_atomic(page, KM_USER0);
c7addb90	466	for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
e5a4c8ca	467	if (is_present_pte(gpt[offset + i]))
c7addb90 AK	468	sp->spt[i] = shadow_trap_nonpresent_pte;
	469	else
	470	sp->spt[i] = shadow_notrap_nonpresent_pte;
	471	kunmap_atomic(gpt, KM_USER0);
b4231d61	472	kvm_release_page_clean(page);
c7addb90 AK	473	}
c7addb90 AK	474
6aa8b732 AK	475	#undef pt_element_t
	476	#undef guest_walker
	477	#undef FNAME
	478	#undef PT_BASE_ADDR_MASK
	479	#undef PT_INDEX
	480	#undef SHADOW_PT_INDEX
	481	#undef PT_LEVEL_MASK
6aa8b732	482	#undef PT_DIR_BASE_ADDR_MASK
c7addb90	483	#undef PT_LEVEL_BITS
cea0f0e7	484	#undef PT_MAX_FULL_LEVELS
5fb07ddb AK	485	#undef gpte_to_gfn
5fb07ddb AK	486	#undef gpte_to_gfn_pde