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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
10 | * | |
11 | * Authors: | |
12 | * Yaniv Kamay <yaniv@qumranet.com> | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * | |
15 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
16 | * the COPYING file in the top-level directory. | |
17 | * | |
18 | */ | |
19 | ||
20 | /* | |
21 | * We need the mmu code to access both 32-bit and 64-bit guest ptes, | |
22 | * so the code in this file is compiled twice, once per pte size. | |
23 | */ | |
24 | ||
25 | #if PTTYPE == 64 | |
26 | #define pt_element_t u64 | |
27 | #define guest_walker guest_walker64 | |
28 | #define FNAME(name) paging##64_##name | |
29 | #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK | |
30 | #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK | |
31 | #define PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
32 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
33 | #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level) | |
34 | #define PT_PTE_COPY_MASK PT64_PTE_COPY_MASK | |
cea0f0e7 AK |
35 | #ifdef CONFIG_X86_64 |
36 | #define PT_MAX_FULL_LEVELS 4 | |
37 | #else | |
38 | #define PT_MAX_FULL_LEVELS 2 | |
39 | #endif | |
6aa8b732 AK |
40 | #elif PTTYPE == 32 |
41 | #define pt_element_t u32 | |
42 | #define guest_walker guest_walker32 | |
43 | #define FNAME(name) paging##32_##name | |
44 | #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK | |
45 | #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK | |
46 | #define PT_INDEX(addr, level) PT32_INDEX(addr, level) | |
47 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) | |
48 | #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level) | |
49 | #define PT_PTE_COPY_MASK PT32_PTE_COPY_MASK | |
cea0f0e7 | 50 | #define PT_MAX_FULL_LEVELS 2 |
6aa8b732 AK |
51 | #else |
52 | #error Invalid PTTYPE value | |
53 | #endif | |
54 | ||
55 | /* | |
56 | * The guest_walker structure emulates the behavior of the hardware page | |
57 | * table walker. | |
58 | */ | |
59 | struct guest_walker { | |
60 | int level; | |
cea0f0e7 | 61 | gfn_t table_gfn[PT_MAX_FULL_LEVELS]; |
6aa8b732 | 62 | pt_element_t *table; |
ac79c978 | 63 | pt_element_t *ptep; |
6aa8b732 | 64 | pt_element_t inherited_ar; |
815af8d4 | 65 | gfn_t gfn; |
7993ba43 | 66 | u32 error_code; |
6aa8b732 AK |
67 | }; |
68 | ||
ac79c978 AK |
69 | /* |
70 | * Fetch a guest pte for a guest virtual address | |
71 | */ | |
7993ba43 AK |
72 | static int FNAME(walk_addr)(struct guest_walker *walker, |
73 | struct kvm_vcpu *vcpu, gva_t addr, | |
73b1087e | 74 | int write_fault, int user_fault, int fetch_fault) |
6aa8b732 AK |
75 | { |
76 | hpa_t hpa; | |
77 | struct kvm_memory_slot *slot; | |
ac79c978 | 78 | pt_element_t *ptep; |
1b0973bd | 79 | pt_element_t root; |
cea0f0e7 | 80 | gfn_t table_gfn; |
6aa8b732 | 81 | |
cea0f0e7 | 82 | pgprintk("%s: addr %lx\n", __FUNCTION__, addr); |
6aa8b732 | 83 | walker->level = vcpu->mmu.root_level; |
1b0973bd AK |
84 | walker->table = NULL; |
85 | root = vcpu->cr3; | |
86 | #if PTTYPE == 64 | |
87 | if (!is_long_mode(vcpu)) { | |
88 | walker->ptep = &vcpu->pdptrs[(addr >> 30) & 3]; | |
89 | root = *walker->ptep; | |
90 | if (!(root & PT_PRESENT_MASK)) | |
7993ba43 | 91 | goto not_present; |
1b0973bd AK |
92 | --walker->level; |
93 | } | |
94 | #endif | |
cea0f0e7 AK |
95 | table_gfn = (root & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
96 | walker->table_gfn[walker->level - 1] = table_gfn; | |
97 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
98 | walker->level - 1, table_gfn); | |
99 | slot = gfn_to_memslot(vcpu->kvm, table_gfn); | |
1b0973bd | 100 | hpa = safe_gpa_to_hpa(vcpu, root & PT64_BASE_ADDR_MASK); |
6aa8b732 AK |
101 | walker->table = kmap_atomic(pfn_to_page(hpa >> PAGE_SHIFT), KM_USER0); |
102 | ||
a9058ecd | 103 | ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) || |
6aa8b732 AK |
104 | (vcpu->cr3 & ~(PAGE_MASK | CR3_FLAGS_MASK)) == 0); |
105 | ||
6aa8b732 | 106 | walker->inherited_ar = PT_USER_MASK | PT_WRITABLE_MASK; |
ac79c978 AK |
107 | |
108 | for (;;) { | |
109 | int index = PT_INDEX(addr, walker->level); | |
110 | hpa_t paddr; | |
111 | ||
112 | ptep = &walker->table[index]; | |
113 | ASSERT(((unsigned long)walker->table & PAGE_MASK) == | |
114 | ((unsigned long)ptep & PAGE_MASK)); | |
115 | ||
815af8d4 | 116 | if (!is_present_pte(*ptep)) |
7993ba43 AK |
117 | goto not_present; |
118 | ||
119 | if (write_fault && !is_writeble_pte(*ptep)) | |
120 | if (user_fault || is_write_protection(vcpu)) | |
121 | goto access_error; | |
122 | ||
123 | if (user_fault && !(*ptep & PT_USER_MASK)) | |
124 | goto access_error; | |
125 | ||
73b1087e AK |
126 | #if PTTYPE == 64 |
127 | if (fetch_fault && is_nx(vcpu) && (*ptep & PT64_NX_MASK)) | |
128 | goto access_error; | |
129 | #endif | |
130 | ||
bf3f8e86 AK |
131 | if (!(*ptep & PT_ACCESSED_MASK)) { |
132 | mark_page_dirty(vcpu->kvm, table_gfn); | |
133 | *ptep |= PT_ACCESSED_MASK; | |
134 | } | |
815af8d4 AK |
135 | |
136 | if (walker->level == PT_PAGE_TABLE_LEVEL) { | |
137 | walker->gfn = (*ptep & PT_BASE_ADDR_MASK) | |
138 | >> PAGE_SHIFT; | |
139 | break; | |
140 | } | |
141 | ||
142 | if (walker->level == PT_DIRECTORY_LEVEL | |
143 | && (*ptep & PT_PAGE_SIZE_MASK) | |
144 | && (PTTYPE == 64 || is_pse(vcpu))) { | |
145 | walker->gfn = (*ptep & PT_DIR_BASE_ADDR_MASK) | |
146 | >> PAGE_SHIFT; | |
147 | walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL); | |
ac79c978 | 148 | break; |
815af8d4 | 149 | } |
ac79c978 | 150 | |
ca5aac1f | 151 | walker->inherited_ar &= walker->table[index]; |
cea0f0e7 | 152 | table_gfn = (*ptep & PT_BASE_ADDR_MASK) >> PAGE_SHIFT; |
ac79c978 AK |
153 | paddr = safe_gpa_to_hpa(vcpu, *ptep & PT_BASE_ADDR_MASK); |
154 | kunmap_atomic(walker->table, KM_USER0); | |
155 | walker->table = kmap_atomic(pfn_to_page(paddr >> PAGE_SHIFT), | |
156 | KM_USER0); | |
157 | --walker->level; | |
cea0f0e7 AK |
158 | walker->table_gfn[walker->level - 1 ] = table_gfn; |
159 | pgprintk("%s: table_gfn[%d] %lx\n", __FUNCTION__, | |
160 | walker->level - 1, table_gfn); | |
ac79c978 AK |
161 | } |
162 | walker->ptep = ptep; | |
374cbac0 | 163 | pgprintk("%s: pte %llx\n", __FUNCTION__, (u64)*ptep); |
7993ba43 AK |
164 | return 1; |
165 | ||
166 | not_present: | |
167 | walker->error_code = 0; | |
168 | goto err; | |
169 | ||
170 | access_error: | |
171 | walker->error_code = PFERR_PRESENT_MASK; | |
172 | ||
173 | err: | |
174 | if (write_fault) | |
175 | walker->error_code |= PFERR_WRITE_MASK; | |
176 | if (user_fault) | |
177 | walker->error_code |= PFERR_USER_MASK; | |
73b1087e AK |
178 | if (fetch_fault) |
179 | walker->error_code |= PFERR_FETCH_MASK; | |
7993ba43 | 180 | return 0; |
6aa8b732 AK |
181 | } |
182 | ||
183 | static void FNAME(release_walker)(struct guest_walker *walker) | |
184 | { | |
1b0973bd AK |
185 | if (walker->table) |
186 | kunmap_atomic(walker->table, KM_USER0); | |
6aa8b732 AK |
187 | } |
188 | ||
bf3f8e86 AK |
189 | static void FNAME(mark_pagetable_dirty)(struct kvm *kvm, |
190 | struct guest_walker *walker) | |
191 | { | |
192 | mark_page_dirty(kvm, walker->table_gfn[walker->level - 1]); | |
193 | } | |
194 | ||
6aa8b732 | 195 | static void FNAME(set_pte)(struct kvm_vcpu *vcpu, u64 guest_pte, |
815af8d4 | 196 | u64 *shadow_pte, u64 access_bits, gfn_t gfn) |
6aa8b732 AK |
197 | { |
198 | ASSERT(*shadow_pte == 0); | |
199 | access_bits &= guest_pte; | |
200 | *shadow_pte = (guest_pte & PT_PTE_COPY_MASK); | |
201 | set_pte_common(vcpu, shadow_pte, guest_pte & PT_BASE_ADDR_MASK, | |
815af8d4 | 202 | guest_pte & PT_DIRTY_MASK, access_bits, gfn); |
6aa8b732 AK |
203 | } |
204 | ||
0028425f AK |
205 | static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page, |
206 | u64 *spte, const void *pte, int bytes) | |
207 | { | |
208 | pt_element_t gpte; | |
209 | ||
210 | if (bytes < sizeof(pt_element_t)) | |
211 | return; | |
212 | gpte = *(const pt_element_t *)pte; | |
213 | if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) | |
214 | return; | |
215 | pgprintk("%s: gpte %llx spte %p\n", __FUNCTION__, (u64)gpte, spte); | |
8d728203 | 216 | FNAME(set_pte)(vcpu, gpte, spte, PT_USER_MASK | PT_WRITABLE_MASK, |
0028425f AK |
217 | (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT); |
218 | } | |
219 | ||
6aa8b732 | 220 | static void FNAME(set_pde)(struct kvm_vcpu *vcpu, u64 guest_pde, |
815af8d4 | 221 | u64 *shadow_pte, u64 access_bits, gfn_t gfn) |
6aa8b732 AK |
222 | { |
223 | gpa_t gaddr; | |
224 | ||
225 | ASSERT(*shadow_pte == 0); | |
226 | access_bits &= guest_pde; | |
815af8d4 | 227 | gaddr = (gpa_t)gfn << PAGE_SHIFT; |
6aa8b732 AK |
228 | if (PTTYPE == 32 && is_cpuid_PSE36()) |
229 | gaddr |= (guest_pde & PT32_DIR_PSE36_MASK) << | |
230 | (32 - PT32_DIR_PSE36_SHIFT); | |
8c7bb723 | 231 | *shadow_pte = guest_pde & PT_PTE_COPY_MASK; |
6aa8b732 | 232 | set_pte_common(vcpu, shadow_pte, gaddr, |
815af8d4 | 233 | guest_pde & PT_DIRTY_MASK, access_bits, gfn); |
6aa8b732 AK |
234 | } |
235 | ||
6aa8b732 AK |
236 | /* |
237 | * Fetch a shadow pte for a specific level in the paging hierarchy. | |
238 | */ | |
239 | static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr, | |
240 | struct guest_walker *walker) | |
241 | { | |
242 | hpa_t shadow_addr; | |
243 | int level; | |
ef0197e8 | 244 | u64 *shadow_ent; |
6aa8b732 | 245 | u64 *prev_shadow_ent = NULL; |
ac79c978 AK |
246 | pt_element_t *guest_ent = walker->ptep; |
247 | ||
248 | if (!is_present_pte(*guest_ent)) | |
249 | return NULL; | |
6aa8b732 AK |
250 | |
251 | shadow_addr = vcpu->mmu.root_hpa; | |
252 | level = vcpu->mmu.shadow_root_level; | |
aef3d3fe AK |
253 | if (level == PT32E_ROOT_LEVEL) { |
254 | shadow_addr = vcpu->mmu.pae_root[(addr >> 30) & 3]; | |
255 | shadow_addr &= PT64_BASE_ADDR_MASK; | |
256 | --level; | |
257 | } | |
6aa8b732 AK |
258 | |
259 | for (; ; level--) { | |
260 | u32 index = SHADOW_PT_INDEX(addr, level); | |
25c0de2c | 261 | struct kvm_mmu_page *shadow_page; |
8c7bb723 | 262 | u64 shadow_pte; |
cea0f0e7 AK |
263 | int metaphysical; |
264 | gfn_t table_gfn; | |
d28c6cfb | 265 | unsigned hugepage_access = 0; |
6aa8b732 | 266 | |
ef0197e8 | 267 | shadow_ent = ((u64 *)__va(shadow_addr)) + index; |
6aa8b732 AK |
268 | if (is_present_pte(*shadow_ent) || is_io_pte(*shadow_ent)) { |
269 | if (level == PT_PAGE_TABLE_LEVEL) | |
270 | return shadow_ent; | |
271 | shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK; | |
272 | prev_shadow_ent = shadow_ent; | |
273 | continue; | |
274 | } | |
275 | ||
ef0197e8 AK |
276 | if (level == PT_PAGE_TABLE_LEVEL) |
277 | break; | |
6aa8b732 | 278 | |
cea0f0e7 AK |
279 | if (level - 1 == PT_PAGE_TABLE_LEVEL |
280 | && walker->level == PT_DIRECTORY_LEVEL) { | |
281 | metaphysical = 1; | |
d28c6cfb AK |
282 | hugepage_access = *guest_ent; |
283 | hugepage_access &= PT_USER_MASK | PT_WRITABLE_MASK; | |
284 | hugepage_access >>= PT_WRITABLE_SHIFT; | |
cea0f0e7 AK |
285 | table_gfn = (*guest_ent & PT_BASE_ADDR_MASK) |
286 | >> PAGE_SHIFT; | |
287 | } else { | |
288 | metaphysical = 0; | |
289 | table_gfn = walker->table_gfn[level - 2]; | |
290 | } | |
291 | shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1, | |
d28c6cfb AK |
292 | metaphysical, hugepage_access, |
293 | shadow_ent); | |
47ad8e68 | 294 | shadow_addr = __pa(shadow_page->spt); |
aef3d3fe AK |
295 | shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK |
296 | | PT_WRITABLE_MASK | PT_USER_MASK; | |
8c7bb723 | 297 | *shadow_ent = shadow_pte; |
6aa8b732 AK |
298 | prev_shadow_ent = shadow_ent; |
299 | } | |
ef0197e8 AK |
300 | |
301 | if (walker->level == PT_DIRECTORY_LEVEL) { | |
302 | if (prev_shadow_ent) | |
303 | *prev_shadow_ent |= PT_SHADOW_PS_MARK; | |
304 | FNAME(set_pde)(vcpu, *guest_ent, shadow_ent, | |
305 | walker->inherited_ar, walker->gfn); | |
306 | } else { | |
307 | ASSERT(walker->level == PT_PAGE_TABLE_LEVEL); | |
308 | FNAME(set_pte)(vcpu, *guest_ent, shadow_ent, | |
309 | walker->inherited_ar, | |
310 | walker->gfn); | |
311 | } | |
312 | return shadow_ent; | |
6aa8b732 AK |
313 | } |
314 | ||
315 | /* | |
316 | * The guest faulted for write. We need to | |
317 | * | |
318 | * - check write permissions | |
319 | * - update the guest pte dirty bit | |
320 | * - update our own dirty page tracking structures | |
321 | */ | |
322 | static int FNAME(fix_write_pf)(struct kvm_vcpu *vcpu, | |
323 | u64 *shadow_ent, | |
324 | struct guest_walker *walker, | |
325 | gva_t addr, | |
cea0f0e7 AK |
326 | int user, |
327 | int *write_pt) | |
6aa8b732 AK |
328 | { |
329 | pt_element_t *guest_ent; | |
330 | int writable_shadow; | |
331 | gfn_t gfn; | |
14364656 | 332 | struct kvm_mmu_page *page; |
6aa8b732 AK |
333 | |
334 | if (is_writeble_pte(*shadow_ent)) | |
fc3dffe1 | 335 | return !user || (*shadow_ent & PT_USER_MASK); |
6aa8b732 AK |
336 | |
337 | writable_shadow = *shadow_ent & PT_SHADOW_WRITABLE_MASK; | |
338 | if (user) { | |
339 | /* | |
340 | * User mode access. Fail if it's a kernel page or a read-only | |
341 | * page. | |
342 | */ | |
343 | if (!(*shadow_ent & PT_SHADOW_USER_MASK) || !writable_shadow) | |
344 | return 0; | |
345 | ASSERT(*shadow_ent & PT_USER_MASK); | |
346 | } else | |
347 | /* | |
348 | * Kernel mode access. Fail if it's a read-only page and | |
349 | * supervisor write protection is enabled. | |
350 | */ | |
351 | if (!writable_shadow) { | |
352 | if (is_write_protection(vcpu)) | |
353 | return 0; | |
354 | *shadow_ent &= ~PT_USER_MASK; | |
355 | } | |
356 | ||
ac79c978 | 357 | guest_ent = walker->ptep; |
6aa8b732 AK |
358 | |
359 | if (!is_present_pte(*guest_ent)) { | |
360 | *shadow_ent = 0; | |
361 | return 0; | |
362 | } | |
363 | ||
815af8d4 | 364 | gfn = walker->gfn; |
14364656 AK |
365 | |
366 | if (user) { | |
367 | /* | |
368 | * Usermode page faults won't be for page table updates. | |
369 | */ | |
370 | while ((page = kvm_mmu_lookup_page(vcpu, gfn)) != NULL) { | |
371 | pgprintk("%s: zap %lx %x\n", | |
372 | __FUNCTION__, gfn, page->role.word); | |
373 | kvm_mmu_zap_page(vcpu, page); | |
374 | } | |
375 | } else if (kvm_mmu_lookup_page(vcpu, gfn)) { | |
cea0f0e7 AK |
376 | pgprintk("%s: found shadow page for %lx, marking ro\n", |
377 | __FUNCTION__, gfn); | |
bf3f8e86 AK |
378 | mark_page_dirty(vcpu->kvm, gfn); |
379 | FNAME(mark_pagetable_dirty)(vcpu->kvm, walker); | |
760db773 | 380 | *guest_ent |= PT_DIRTY_MASK; |
cea0f0e7 AK |
381 | *write_pt = 1; |
382 | return 0; | |
383 | } | |
6aa8b732 AK |
384 | mark_page_dirty(vcpu->kvm, gfn); |
385 | *shadow_ent |= PT_WRITABLE_MASK; | |
bf3f8e86 | 386 | FNAME(mark_pagetable_dirty)(vcpu->kvm, walker); |
6aa8b732 | 387 | *guest_ent |= PT_DIRTY_MASK; |
714b93da | 388 | rmap_add(vcpu, shadow_ent); |
6aa8b732 AK |
389 | |
390 | return 1; | |
391 | } | |
392 | ||
393 | /* | |
394 | * Page fault handler. There are several causes for a page fault: | |
395 | * - there is no shadow pte for the guest pte | |
396 | * - write access through a shadow pte marked read only so that we can set | |
397 | * the dirty bit | |
398 | * - write access to a shadow pte marked read only so we can update the page | |
399 | * dirty bitmap, when userspace requests it | |
400 | * - mmio access; in this case we will never install a present shadow pte | |
401 | * - normal guest page fault due to the guest pte marked not present, not | |
402 | * writable, or not executable | |
403 | * | |
e2dec939 AK |
404 | * Returns: 1 if we need to emulate the instruction, 0 otherwise, or |
405 | * a negative value on error. | |
6aa8b732 AK |
406 | */ |
407 | static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, | |
408 | u32 error_code) | |
409 | { | |
410 | int write_fault = error_code & PFERR_WRITE_MASK; | |
6aa8b732 | 411 | int user_fault = error_code & PFERR_USER_MASK; |
73b1087e | 412 | int fetch_fault = error_code & PFERR_FETCH_MASK; |
6aa8b732 AK |
413 | struct guest_walker walker; |
414 | u64 *shadow_pte; | |
415 | int fixed; | |
cea0f0e7 | 416 | int write_pt = 0; |
e2dec939 | 417 | int r; |
6aa8b732 | 418 | |
cea0f0e7 | 419 | pgprintk("%s: addr %lx err %x\n", __FUNCTION__, addr, error_code); |
37a7d8b0 | 420 | kvm_mmu_audit(vcpu, "pre page fault"); |
714b93da | 421 | |
e2dec939 AK |
422 | r = mmu_topup_memory_caches(vcpu); |
423 | if (r) | |
424 | return r; | |
714b93da | 425 | |
6aa8b732 AK |
426 | /* |
427 | * Look up the shadow pte for the faulting address. | |
428 | */ | |
73b1087e AK |
429 | r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault, |
430 | fetch_fault); | |
6aa8b732 AK |
431 | |
432 | /* | |
433 | * The page is not mapped by the guest. Let the guest handle it. | |
434 | */ | |
7993ba43 AK |
435 | if (!r) { |
436 | pgprintk("%s: guest page fault\n", __FUNCTION__); | |
437 | inject_page_fault(vcpu, addr, walker.error_code); | |
6aa8b732 | 438 | FNAME(release_walker)(&walker); |
a25f7e1f | 439 | vcpu->last_pt_write_count = 0; /* reset fork detector */ |
6aa8b732 AK |
440 | return 0; |
441 | } | |
442 | ||
7993ba43 | 443 | shadow_pte = FNAME(fetch)(vcpu, addr, &walker); |
cea0f0e7 AK |
444 | pgprintk("%s: shadow pte %p %llx\n", __FUNCTION__, |
445 | shadow_pte, *shadow_pte); | |
446 | ||
6aa8b732 AK |
447 | /* |
448 | * Update the shadow pte. | |
449 | */ | |
450 | if (write_fault) | |
451 | fixed = FNAME(fix_write_pf)(vcpu, shadow_pte, &walker, addr, | |
cea0f0e7 | 452 | user_fault, &write_pt); |
6aa8b732 AK |
453 | else |
454 | fixed = fix_read_pf(shadow_pte); | |
455 | ||
cea0f0e7 AK |
456 | pgprintk("%s: updated shadow pte %p %llx\n", __FUNCTION__, |
457 | shadow_pte, *shadow_pte); | |
458 | ||
6aa8b732 AK |
459 | FNAME(release_walker)(&walker); |
460 | ||
a25f7e1f AK |
461 | if (!write_pt) |
462 | vcpu->last_pt_write_count = 0; /* reset fork detector */ | |
463 | ||
6aa8b732 AK |
464 | /* |
465 | * mmio: emulate if accessible, otherwise its a guest fault. | |
466 | */ | |
d27d4aca | 467 | if (is_io_pte(*shadow_pte)) |
7993ba43 | 468 | return 1; |
6aa8b732 | 469 | |
1165f5fe | 470 | ++vcpu->stat.pf_fixed; |
37a7d8b0 | 471 | kvm_mmu_audit(vcpu, "post page fault (fixed)"); |
6aa8b732 | 472 | |
cea0f0e7 | 473 | return write_pt; |
6aa8b732 AK |
474 | } |
475 | ||
476 | static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr) | |
477 | { | |
478 | struct guest_walker walker; | |
e119d117 AK |
479 | gpa_t gpa = UNMAPPED_GVA; |
480 | int r; | |
6aa8b732 | 481 | |
e119d117 | 482 | r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0); |
6aa8b732 | 483 | |
e119d117 AK |
484 | if (r) { |
485 | gpa = (gpa_t)walker.gfn << PAGE_SHIFT; | |
486 | gpa |= vaddr & ~PAGE_MASK; | |
6aa8b732 AK |
487 | } |
488 | ||
e119d117 | 489 | FNAME(release_walker)(&walker); |
6aa8b732 AK |
490 | return gpa; |
491 | } | |
492 | ||
493 | #undef pt_element_t | |
494 | #undef guest_walker | |
495 | #undef FNAME | |
496 | #undef PT_BASE_ADDR_MASK | |
497 | #undef PT_INDEX | |
498 | #undef SHADOW_PT_INDEX | |
499 | #undef PT_LEVEL_MASK | |
500 | #undef PT_PTE_COPY_MASK | |
501 | #undef PT_NON_PTE_COPY_MASK | |
502 | #undef PT_DIR_BASE_ADDR_MASK | |
cea0f0e7 | 503 | #undef PT_MAX_FULL_LEVELS |