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[PATCH] KVM: AMD SVM: handle MSR_STAR in 32-bit mode
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17#include <linux/module.h>
18#include <linux/vmalloc.h>
19#include <linux/highmem.h>
20#include <asm/desc.h>
21
22#include "kvm_svm.h"
23#include "x86_emulate.h"
24
25MODULE_AUTHOR("Qumranet");
26MODULE_LICENSE("GPL");
27
28#define IOPM_ALLOC_ORDER 2
29#define MSRPM_ALLOC_ORDER 1
30
31#define DB_VECTOR 1
32#define UD_VECTOR 6
33#define GP_VECTOR 13
34
35#define DR7_GD_MASK (1 << 13)
36#define DR6_BD_MASK (1 << 13)
37#define CR4_DE_MASK (1UL << 3)
38
39#define SEG_TYPE_LDT 2
40#define SEG_TYPE_BUSY_TSS16 3
41
42#define KVM_EFER_LMA (1 << 10)
43#define KVM_EFER_LME (1 << 8)
44
45unsigned long iopm_base;
46unsigned long msrpm_base;
47
48struct kvm_ldttss_desc {
49 u16 limit0;
50 u16 base0;
51 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
52 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
53 u32 base3;
54 u32 zero1;
55} __attribute__((packed));
56
57struct svm_cpu_data {
58 int cpu;
59
60 uint64_t asid_generation;
61 uint32_t max_asid;
62 uint32_t next_asid;
63 struct kvm_ldttss_desc *tss_desc;
64
65 struct page *save_area;
66};
67
68static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
69
70struct svm_init_data {
71 int cpu;
72 int r;
73};
74
75static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
76
77#define NUM_MSR_MAPS (sizeof(msrpm_ranges) / sizeof(*msrpm_ranges))
78#define MSRS_RANGE_SIZE 2048
79#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
80
81#define MAX_INST_SIZE 15
82
83static unsigned get_addr_size(struct kvm_vcpu *vcpu)
84{
85 struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
86 u16 cs_attrib;
87
88 if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM))
89 return 2;
90
91 cs_attrib = sa->cs.attrib;
92
93 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
94 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
95}
96
97static inline u8 pop_irq(struct kvm_vcpu *vcpu)
98{
99 int word_index = __ffs(vcpu->irq_summary);
100 int bit_index = __ffs(vcpu->irq_pending[word_index]);
101 int irq = word_index * BITS_PER_LONG + bit_index;
102
103 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
104 if (!vcpu->irq_pending[word_index])
105 clear_bit(word_index, &vcpu->irq_summary);
106 return irq;
107}
108
109static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
110{
111 set_bit(irq, vcpu->irq_pending);
112 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
113}
114
115static inline void clgi(void)
116{
117 asm volatile (SVM_CLGI);
118}
119
120static inline void stgi(void)
121{
122 asm volatile (SVM_STGI);
123}
124
125static inline void invlpga(unsigned long addr, u32 asid)
126{
127 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
128}
129
130static inline unsigned long kvm_read_cr2(void)
131{
132 unsigned long cr2;
133
134 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
135 return cr2;
136}
137
138static inline void kvm_write_cr2(unsigned long val)
139{
140 asm volatile ("mov %0, %%cr2" :: "r" (val));
141}
142
143static inline unsigned long read_dr6(void)
144{
145 unsigned long dr6;
146
147 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
148 return dr6;
149}
150
151static inline void write_dr6(unsigned long val)
152{
153 asm volatile ("mov %0, %%dr6" :: "r" (val));
154}
155
156static inline unsigned long read_dr7(void)
157{
158 unsigned long dr7;
159
160 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
161 return dr7;
162}
163
164static inline void write_dr7(unsigned long val)
165{
166 asm volatile ("mov %0, %%dr7" :: "r" (val));
167}
168
169static inline int svm_is_long_mode(struct kvm_vcpu *vcpu)
170{
171 return vcpu->svm->vmcb->save.efer & KVM_EFER_LMA;
172}
173
174static inline void force_new_asid(struct kvm_vcpu *vcpu)
175{
176 vcpu->svm->asid_generation--;
177}
178
179static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
180{
181 force_new_asid(vcpu);
182}
183
184static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
185{
186 if (!(efer & KVM_EFER_LMA))
187 efer &= ~KVM_EFER_LME;
188
189 vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
190 vcpu->shadow_efer = efer;
191}
192
193static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
194{
195 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
196 SVM_EVTINJ_VALID_ERR |
197 SVM_EVTINJ_TYPE_EXEPT |
198 GP_VECTOR;
199 vcpu->svm->vmcb->control.event_inj_err = error_code;
200}
201
202static void inject_ud(struct kvm_vcpu *vcpu)
203{
204 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
205 SVM_EVTINJ_TYPE_EXEPT |
206 UD_VECTOR;
207}
208
209static void inject_db(struct kvm_vcpu *vcpu)
210{
211 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
212 SVM_EVTINJ_TYPE_EXEPT |
213 DB_VECTOR;
214}
215
216static int is_page_fault(uint32_t info)
217{
218 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
219 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
220}
221
222static int is_external_interrupt(u32 info)
223{
224 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
225 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
226}
227
228static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
229{
230 if (!vcpu->svm->next_rip) {
231 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
232 return;
233 }
234 if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
235 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
236 __FUNCTION__,
237 vcpu->svm->vmcb->save.rip,
238 vcpu->svm->next_rip);
239 }
240
241 vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
242 vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
243}
244
245static int has_svm(void)
246{
247 uint32_t eax, ebx, ecx, edx;
248
249 if (current_cpu_data.x86_vendor != X86_VENDOR_AMD) {
250 printk(KERN_INFO "has_svm: not amd\n");
251 return 0;
252 }
253
254 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
255 if (eax < SVM_CPUID_FUNC) {
256 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
257 return 0;
258 }
259
260 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
261 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
262 printk(KERN_DEBUG "has_svm: svm not available\n");
263 return 0;
264 }
265 return 1;
266}
267
268static void svm_hardware_disable(void *garbage)
269{
270 struct svm_cpu_data *svm_data
271 = per_cpu(svm_data, raw_smp_processor_id());
272
273 if (svm_data) {
274 uint64_t efer;
275
276 wrmsrl(MSR_VM_HSAVE_PA, 0);
277 rdmsrl(MSR_EFER, efer);
278 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
279 per_cpu(svm_data, raw_smp_processor_id()) = 0;
280 __free_page(svm_data->save_area);
281 kfree(svm_data);
282 }
283}
284
285static void svm_hardware_enable(void *garbage)
286{
287
288 struct svm_cpu_data *svm_data;
289 uint64_t efer;
05b3e0c2 290#ifdef CONFIG_X86_64
6aa8b732
AK		 291 struct desc_ptr gdt_descr;
292#else
293 struct Xgt_desc_struct gdt_descr;
294#endif
295 struct desc_struct *gdt;
296 int me = raw_smp_processor_id();
297
298 if (!has_svm()) {
299 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
300 return;
301 }
302 svm_data = per_cpu(svm_data, me);
303
304 if (!svm_data) {
305 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
306 me);
307 return;
308 }
309
310 svm_data->asid_generation = 1;
311 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
312 svm_data->next_asid = svm_data->max_asid + 1;
313
314 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
315 gdt = (struct desc_struct *)gdt_descr.address;
316 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
317
318 rdmsrl(MSR_EFER, efer);
319 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
320
321 wrmsrl(MSR_VM_HSAVE_PA,
322 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
323}
324
325static int svm_cpu_init(int cpu)
326{
327 struct svm_cpu_data *svm_data;
328 int r;
329
330 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
331 if (!svm_data)
332 return -ENOMEM;
333 svm_data->cpu = cpu;
334 svm_data->save_area = alloc_page(GFP_KERNEL);
335 r = -ENOMEM;
336 if (!svm_data->save_area)
337 goto err_1;
338
339 per_cpu(svm_data, cpu) = svm_data;
340
341 return 0;
342
343err_1:
344 kfree(svm_data);
345 return r;
346
347}
348
349static int set_msr_interception(u32 *msrpm, unsigned msr,
350 int read, int write)
351{
352 int i;
353
354 for (i = 0; i < NUM_MSR_MAPS; i++) {
355 if (msr >= msrpm_ranges[i] &&
356 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
357 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
358 msrpm_ranges[i]) * 2;
359
360 u32 *base = msrpm + (msr_offset / 32);
361 u32 msr_shift = msr_offset % 32;
362 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
363 *base = (*base & ~(0x3 << msr_shift)) |
364 (mask << msr_shift);
365 return 1;
366 }
367 }
368 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
369 return 0;
370}
371
372static __init int svm_hardware_setup(void)
373{
374 int cpu;
375 struct page *iopm_pages;
376 struct page *msrpm_pages;
377 void *msrpm_va;
378 int r;
379
873a7c42 380 kvm_emulator_want_group7_invlpg();
6aa8b732
AK		 381
382 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
383
384 if (!iopm_pages)
385 return -ENOMEM;
386 memset(page_address(iopm_pages), 0xff,
387 PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
388 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
389
390
391 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
392
393 r = -ENOMEM;
394 if (!msrpm_pages)
395 goto err_1;
396
397 msrpm_va = page_address(msrpm_pages);
398 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
399 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
400
05b3e0c2 401#ifdef CONFIG_X86_64
6aa8b732
AK		 402 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
403 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
404 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
6aa8b732
AK		 405 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
406 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
407 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
408#endif
0e859cac 409 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
6aa8b732
AK		 410 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
411 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
412 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
413
414 for_each_online_cpu(cpu) {
415 r = svm_cpu_init(cpu);
416 if (r)
417 goto err_2;
418 }
419 return 0;
420
421err_2:
422 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
423 msrpm_base = 0;
424err_1:
425 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
426 iopm_base = 0;
427 return r;
428}
429
430static __exit void svm_hardware_unsetup(void)
431{
432 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
433 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
434 iopm_base = msrpm_base = 0;
435}
436
437static void init_seg(struct vmcb_seg *seg)
438{
439 seg->selector = 0;
440 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
441 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
442 seg->limit = 0xffff;
443 seg->base = 0;
444}
445
446static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
447{
448 seg->selector = 0;
449 seg->attrib = SVM_SELECTOR_P_MASK | type;
450 seg->limit = 0xffff;
451 seg->base = 0;
452}
453
454static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
455{
456 return 0;
457}
458
459static void init_vmcb(struct vmcb *vmcb)
460{
461 struct vmcb_control_area *control = &vmcb->control;
462 struct vmcb_save_area *save = &vmcb->save;
463 u64 tsc;
464
465 control->intercept_cr_read = INTERCEPT_CR0_MASK |
466 INTERCEPT_CR3_MASK |
467 INTERCEPT_CR4_MASK;
468
469 control->intercept_cr_write = INTERCEPT_CR0_MASK |
470 INTERCEPT_CR3_MASK |
471 INTERCEPT_CR4_MASK;
472
473 control->intercept_dr_read = INTERCEPT_DR0_MASK |
474 INTERCEPT_DR1_MASK |
475 INTERCEPT_DR2_MASK |
476 INTERCEPT_DR3_MASK;
477
478 control->intercept_dr_write = INTERCEPT_DR0_MASK |
479 INTERCEPT_DR1_MASK |
480 INTERCEPT_DR2_MASK |
481 INTERCEPT_DR3_MASK |
482 INTERCEPT_DR5_MASK |
483 INTERCEPT_DR7_MASK;
484
485 control->intercept_exceptions = 1 << PF_VECTOR;
486
487
488 control->intercept = (1ULL << INTERCEPT_INTR) |
489 (1ULL << INTERCEPT_NMI) |
490 /*
491 * selective cr0 intercept bug?
492 * 0: 0f 22 d8 mov %eax,%cr3
493 * 3: 0f 20 c0 mov %cr0,%eax
494 * 6: 0d 00 00 00 80 or $0x80000000,%eax
495 * b: 0f 22 c0 mov %eax,%cr0
496 * set cr3 ->interception
497 * get cr0 ->interception
498 * set cr0 -> no interception
499 */
500 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
501 (1ULL << INTERCEPT_CPUID) |
502 (1ULL << INTERCEPT_HLT) |
503 (1ULL << INTERCEPT_INVLPG) |
504 (1ULL << INTERCEPT_INVLPGA) |
505 (1ULL << INTERCEPT_IOIO_PROT) |
506 (1ULL << INTERCEPT_MSR_PROT) |
507 (1ULL << INTERCEPT_TASK_SWITCH) |
508 (1ULL << INTERCEPT_VMRUN) |
509 (1ULL << INTERCEPT_VMMCALL) |
510 (1ULL << INTERCEPT_VMLOAD) |
511 (1ULL << INTERCEPT_VMSAVE) |
512 (1ULL << INTERCEPT_STGI) |
513 (1ULL << INTERCEPT_CLGI) |
514 (1ULL << INTERCEPT_SKINIT);
515
516 control->iopm_base_pa = iopm_base;
517 control->msrpm_base_pa = msrpm_base;
518 rdtscll(tsc);
519 control->tsc_offset = -tsc;
520 control->int_ctl = V_INTR_MASKING_MASK;
521
522 init_seg(&save->es);
523 init_seg(&save->ss);
524 init_seg(&save->ds);
525 init_seg(&save->fs);
526 init_seg(&save->gs);
527
528 save->cs.selector = 0xf000;
529 /* Executable/Readable Code Segment */
530 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
531 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
532 save->cs.limit = 0xffff;
533 save->cs.base = 0xffff0000;
534
535 save->gdtr.limit = 0xffff;
536 save->idtr.limit = 0xffff;
537
538 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
539 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
540
541 save->efer = MSR_EFER_SVME_MASK;
542
543 save->dr6 = 0xffff0ff0;
544 save->dr7 = 0x400;
545 save->rflags = 2;
546 save->rip = 0x0000fff0;
547
548 /*
549 * cr0 val on cpu init should be 0x60000010, we enable cpu
550 * cache by default. the orderly way is to enable cache in bios.
551 */
552 save->cr0 = 0x00000010 | CR0_PG_MASK;
553 save->cr4 = CR4_PAE_MASK;
554 /* rdx = ?? */
555}
556
557static int svm_create_vcpu(struct kvm_vcpu *vcpu)
558{
559 struct page *page;
560 int r;
561
562 r = -ENOMEM;
563 vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
564 if (!vcpu->svm)
565 goto out1;
566 page = alloc_page(GFP_KERNEL);
567 if (!page)
568 goto out2;
569
570 vcpu->svm->vmcb = page_address(page);
571 memset(vcpu->svm->vmcb, 0, PAGE_SIZE);
572 vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
573 vcpu->svm->cr0 = 0x00000010;
574 vcpu->svm->asid_generation = 0;
575 memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
576 init_vmcb(vcpu->svm->vmcb);
577
578 return 0;
579
580out2:
581 kfree(vcpu->svm);
582out1:
583 return r;
584}
585
586static void svm_free_vcpu(struct kvm_vcpu *vcpu)
587{
588 if (!vcpu->svm)
589 return;
590 if (vcpu->svm->vmcb)
591 __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
592 kfree(vcpu->svm);
593}
594
595static struct kvm_vcpu *svm_vcpu_load(struct kvm_vcpu *vcpu)
596{
597 get_cpu();
598 return vcpu;
599}
600
601static void svm_vcpu_put(struct kvm_vcpu *vcpu)
602{
603 put_cpu();
604}
605
606static void svm_cache_regs(struct kvm_vcpu *vcpu)
607{
608 vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
609 vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
610 vcpu->rip = vcpu->svm->vmcb->save.rip;
611}
612
613static void svm_decache_regs(struct kvm_vcpu *vcpu)
614{
615 vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
616 vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
617 vcpu->svm->vmcb->save.rip = vcpu->rip;
618}
619
620static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
621{
622 return vcpu->svm->vmcb->save.rflags;
623}
624
625static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
626{
627 vcpu->svm->vmcb->save.rflags = rflags;
628}
629
630static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
631{
632 struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
633
634 switch (seg) {
635 case VCPU_SREG_CS: return &save->cs;
636 case VCPU_SREG_DS: return &save->ds;
637 case VCPU_SREG_ES: return &save->es;
638 case VCPU_SREG_FS: return &save->fs;
639 case VCPU_SREG_GS: return &save->gs;
640 case VCPU_SREG_SS: return &save->ss;
641 case VCPU_SREG_TR: return &save->tr;
642 case VCPU_SREG_LDTR: return &save->ldtr;
643 }
644 BUG();
645 return 0;
646}
647
648static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
649{
650 struct vmcb_seg *s = svm_seg(vcpu, seg);
651
652 return s->base;
653}
654
655static void svm_get_segment(struct kvm_vcpu *vcpu,
656 struct kvm_segment *var, int seg)
657{
658 struct vmcb_seg *s = svm_seg(vcpu, seg);
659
660 var->base = s->base;
661 var->limit = s->limit;
662 var->selector = s->selector;
663 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
664 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
665 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
666 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
667 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
668 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
669 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
670 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
671 var->unusable = !var->present;
672}
673
674static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
675{
676 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
677
678 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
679 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
680}
681
682static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
683{
684 dt->limit = vcpu->svm->vmcb->save.ldtr.limit;
685 dt->base = vcpu->svm->vmcb->save.ldtr.base;
686}
687
688static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
689{
690 vcpu->svm->vmcb->save.ldtr.limit = dt->limit;
691 vcpu->svm->vmcb->save.ldtr.base = dt->base ;
692}
693
694static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
695{
696 dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
697 dt->base = vcpu->svm->vmcb->save.gdtr.base;
698}
699
700static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
701{
702 vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
703 vcpu->svm->vmcb->save.gdtr.base = dt->base ;
704}
705
706static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
707{
05b3e0c2 708#ifdef CONFIG_X86_64
6aa8b732
AK		 709 if (vcpu->shadow_efer & KVM_EFER_LME) {
710 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) {
711 vcpu->shadow_efer |= KVM_EFER_LMA;
712 vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
713 }
714
715 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) {
716 vcpu->shadow_efer &= ~KVM_EFER_LMA;
717 vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
718 }
719 }
720#endif
721 vcpu->svm->cr0 = cr0;
722 vcpu->svm->vmcb->save.cr0 = cr0 | CR0_PG_MASK;
723 vcpu->cr0 = cr0;
724}
725
726static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
727{
728 vcpu->cr4 = cr4;
729 vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK;
730}
731
732static void svm_set_segment(struct kvm_vcpu *vcpu,
733 struct kvm_segment *var, int seg)
734{
735 struct vmcb_seg *s = svm_seg(vcpu, seg);
736
737 s->base = var->base;
738 s->limit = var->limit;
739 s->selector = var->selector;
740 if (var->unusable)
741 s->attrib = 0;
742 else {
743 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
744 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
745 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
746 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
747 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
748 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
749 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
750 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
751 }
752 if (seg == VCPU_SREG_CS)
753 vcpu->svm->vmcb->save.cpl
754 = (vcpu->svm->vmcb->save.cs.attrib
755 >> SVM_SELECTOR_DPL_SHIFT) & 3;
756
757}
758
759/* FIXME:
760
761 vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
762 vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
763
764*/
765
766static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
767{
768 return -EOPNOTSUPP;
769}
770
771static void load_host_msrs(struct kvm_vcpu *vcpu)
772{
773 int i;
774
775 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
776 wrmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
777}
778
779static void save_host_msrs(struct kvm_vcpu *vcpu)
780{
781 int i;
782
783 for ( i = 0; i < NR_HOST_SAVE_MSRS; i++)
784 rdmsrl(host_save_msrs[i], vcpu->svm->host_msrs[i]);
785}
786
787static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
788{
789 if (svm_data->next_asid > svm_data->max_asid) {
790 ++svm_data->asid_generation;
791 svm_data->next_asid = 1;
792 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
793 }
794
795 vcpu->cpu = svm_data->cpu;
796 vcpu->svm->asid_generation = svm_data->asid_generation;
797 vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
798}
799
800static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
801{
802 invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
803}
804
805static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
806{
807 return vcpu->svm->db_regs[dr];
808}
809
810static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
811 int *exception)
812{
813 *exception = 0;
814
815 if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
816 vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
817 vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
818 *exception = DB_VECTOR;
819 return;
820 }
821
822 switch (dr) {
823 case 0 ... 3:
824 vcpu->svm->db_regs[dr] = value;
825 return;
826 case 4 ... 5:
827 if (vcpu->cr4 & CR4_DE_MASK) {
828 *exception = UD_VECTOR;
829 return;
830 }
831 case 7: {
832 if (value & ~((1ULL << 32) - 1)) {
833 *exception = GP_VECTOR;
834 return;
835 }
836 vcpu->svm->vmcb->save.dr7 = value;
837 return;
838 }
839 default:
840 printk(KERN_DEBUG "%s: unexpected dr %u\n",
841 __FUNCTION__, dr);
842 *exception = UD_VECTOR;
843 return;
844 }
845}
846
847static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
848{
849 u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
850 u64 fault_address;
851 u32 error_code;
852 enum emulation_result er;
853
854 if (is_external_interrupt(exit_int_info))
855 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
856
857 spin_lock(&vcpu->kvm->lock);
858
859 fault_address = vcpu->svm->vmcb->control.exit_info_2;
860 error_code = vcpu->svm->vmcb->control.exit_info_1;
861 if (!vcpu->mmu.page_fault(vcpu, fault_address, error_code)) {
862 spin_unlock(&vcpu->kvm->lock);
863 return 1;
864 }
865 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
866 spin_unlock(&vcpu->kvm->lock);
867
868 switch (er) {
869 case EMULATE_DONE:
870 return 1;
871 case EMULATE_DO_MMIO:
872 ++kvm_stat.mmio_exits;
873 kvm_run->exit_reason = KVM_EXIT_MMIO;
874 return 0;
875 case EMULATE_FAIL:
876 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
877 break;
878 default:
879 BUG();
880 }
881
882 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
883 return 0;
884}
885
886static int io_get_override(struct kvm_vcpu *vcpu,
887 struct vmcb_seg **seg,
888 int *addr_override)
889{
890 u8 inst[MAX_INST_SIZE];
891 unsigned ins_length;
892 gva_t rip;
893 int i;
894
895 rip = vcpu->svm->vmcb->save.rip;
896 ins_length = vcpu->svm->next_rip - rip;
897 rip += vcpu->svm->vmcb->save.cs.base;
898
899 if (ins_length > MAX_INST_SIZE)
900 printk(KERN_DEBUG
901 "%s: inst length err, cs base 0x%llx rip 0x%llx "
902 "next rip 0x%llx ins_length %u\n",
903 __FUNCTION__,
904 vcpu->svm->vmcb->save.cs.base,
905 vcpu->svm->vmcb->save.rip,
906 vcpu->svm->vmcb->control.exit_info_2,
907 ins_length);
908
909 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
910 /* #PF */
911 return 0;
912
913 *addr_override = 0;
914 *seg = 0;
915 for (i = 0; i < ins_length; i++)
916 switch (inst[i]) {
917 case 0xf0:
918 case 0xf2:
919 case 0xf3:
920 case 0x66:
921 continue;
922 case 0x67:
923 *addr_override = 1;
924 continue;
925 case 0x2e:
926 *seg = &vcpu->svm->vmcb->save.cs;
927 continue;
928 case 0x36:
929 *seg = &vcpu->svm->vmcb->save.ss;
930 continue;
931 case 0x3e:
932 *seg = &vcpu->svm->vmcb->save.ds;
933 continue;
934 case 0x26:
935 *seg = &vcpu->svm->vmcb->save.es;
936 continue;
937 case 0x64:
938 *seg = &vcpu->svm->vmcb->save.fs;
939 continue;
940 case 0x65:
941 *seg = &vcpu->svm->vmcb->save.gs;
942 continue;
943 default:
944 return 1;
945 }
946 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
947 return 0;
948}
949
950static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, u64 *address)
951{
952 unsigned long addr_mask;
953 unsigned long *reg;
954 struct vmcb_seg *seg;
955 int addr_override;
956 struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
957 u16 cs_attrib = save_area->cs.attrib;
958 unsigned addr_size = get_addr_size(vcpu);
959
960 if (!io_get_override(vcpu, &seg, &addr_override))
961 return 0;
962
963 if (addr_override)
964 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
965
966 if (ins) {
967 reg = &vcpu->regs[VCPU_REGS_RDI];
968 seg = &vcpu->svm->vmcb->save.es;
969 } else {
970 reg = &vcpu->regs[VCPU_REGS_RSI];
971 seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
972 }
973
974 addr_mask = ~0ULL >> (64 - (addr_size * 8));
975
976 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
977 !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
978 *address = (*reg & addr_mask);
979 return addr_mask;
980 }
981
982 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
983 svm_inject_gp(vcpu, 0);
984 return 0;
985 }
986
987 *address = (*reg & addr_mask) + seg->base;
988 return addr_mask;
989}
990
991static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
992{
993 u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
994 int _in = io_info & SVM_IOIO_TYPE_MASK;
995
996 ++kvm_stat.io_exits;
997
998 vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
999
1000 kvm_run->exit_reason = KVM_EXIT_IO;
1001 kvm_run->io.port = io_info >> 16;
1002 kvm_run->io.direction = (_in) ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
1003 kvm_run->io.size = ((io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT);
1004 kvm_run->io.string = (io_info & SVM_IOIO_STR_MASK) != 0;
1005 kvm_run->io.rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1006
1007 if (kvm_run->io.string) {
1008 unsigned addr_mask;
1009
1010 addr_mask = io_adress(vcpu, _in, &kvm_run->io.address);
1011 if (!addr_mask) {
1012 printk(KERN_DEBUG "%s: get io address failed\n", __FUNCTION__);
1013 return 1;
1014 }
1015
1016 if (kvm_run->io.rep) {
1017 kvm_run->io.count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1018 kvm_run->io.string_down = (vcpu->svm->vmcb->save.rflags
1019 & X86_EFLAGS_DF) != 0;
1020 }
1021 } else {
1022 kvm_run->io.value = vcpu->svm->vmcb->save.rax;
1023 }
1024 return 0;
1025}
1026
1027
1028static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1029{
1030 return 1;
1031}
1032
1033static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1034{
1035 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
1036 skip_emulated_instruction(vcpu);
1037 if (vcpu->irq_summary && (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF))
1038 return 1;
1039
1040 kvm_run->exit_reason = KVM_EXIT_HLT;
1041 return 0;
1042}
1043
1044static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1045{
1046 inject_ud(vcpu);
1047 return 1;
1048}
1049
1050static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1051{
1052 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1053 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1054 return 0;
1055}
1056
1057static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1058{
1059 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1060 kvm_run->exit_reason = KVM_EXIT_CPUID;
1061 return 0;
1062}
1063
1064static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1065{
1066 if (emulate_instruction(vcpu, 0, 0, 0) != EMULATE_DONE)
1067 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1068 return 1;
1069}
1070
1071static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1072{
1073 switch (ecx) {
1074 case MSR_IA32_MC0_CTL:
1075 case MSR_IA32_MCG_STATUS:
1076 case MSR_IA32_MCG_CAP:
1077 case MSR_IA32_MC0_MISC:
1078 case MSR_IA32_MC0_MISC+4:
1079 case MSR_IA32_MC0_MISC+8:
1080 case MSR_IA32_MC0_MISC+12:
1081 case MSR_IA32_MC0_MISC+16:
1082 case MSR_IA32_UCODE_REV:
1083 /* MTRR registers */
1084 case 0xfe:
1085 case 0x200 ... 0x2ff:
1086 *data = 0;
1087 break;
1088 case MSR_IA32_TIME_STAMP_COUNTER: {
1089 u64 tsc;
1090
1091 rdtscll(tsc);
1092 *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
1093 break;
1094 }
1095 case MSR_EFER:
1096 *data = vcpu->shadow_efer;
1097 break;
1098 case MSR_IA32_APICBASE:
1099 *data = vcpu->apic_base;
1100 break;
0e859cac 1101 case MSR_K6_STAR:
6aa8b732
AK		 1102 *data = vcpu->svm->vmcb->save.star;
1103 break;
0e859cac 1104#ifdef CONFIG_X86_64
6aa8b732
AK		 1105 case MSR_LSTAR:
1106 *data = vcpu->svm->vmcb->save.lstar;
1107 break;
1108 case MSR_CSTAR:
1109 *data = vcpu->svm->vmcb->save.cstar;
1110 break;
1111 case MSR_KERNEL_GS_BASE:
1112 *data = vcpu->svm->vmcb->save.kernel_gs_base;
1113 break;
1114 case MSR_SYSCALL_MASK:
1115 *data = vcpu->svm->vmcb->save.sfmask;
1116 break;
1117#endif
1118 case MSR_IA32_SYSENTER_CS:
1119 *data = vcpu->svm->vmcb->save.sysenter_cs;
1120 break;
1121 case MSR_IA32_SYSENTER_EIP:
1122 *data = vcpu->svm->vmcb->save.sysenter_eip;
1123 break;
1124 case MSR_IA32_SYSENTER_ESP:
1125 *data = vcpu->svm->vmcb->save.sysenter_esp;
1126 break;
1127 default:
1128 printk(KERN_ERR "kvm: unhandled rdmsr: 0x%x\n", ecx);
1129 return 1;
1130 }
1131 return 0;
1132}
1133
1134static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1135{
1136 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1137 u64 data;
1138
1139 if (svm_get_msr(vcpu, ecx, &data))
1140 svm_inject_gp(vcpu, 0);
1141 else {
1142 vcpu->svm->vmcb->save.rax = data & 0xffffffff;
1143 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1144 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1145 skip_emulated_instruction(vcpu);
1146 }
1147 return 1;
1148}
1149
1150static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1151{
1152 switch (ecx) {
05b3e0c2 1153#ifdef CONFIG_X86_64
6aa8b732
AK		 1154 case MSR_EFER:
1155 set_efer(vcpu, data);
1156 break;
1157#endif
1158 case MSR_IA32_MC0_STATUS:
1159 printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n"
1160 , __FUNCTION__, data);
1161 break;
1162 case MSR_IA32_TIME_STAMP_COUNTER: {
1163 u64 tsc;
1164
1165 rdtscll(tsc);
1166 vcpu->svm->vmcb->control.tsc_offset = data - tsc;
1167 break;
1168 }
1169 case MSR_IA32_UCODE_REV:
1170 case MSR_IA32_UCODE_WRITE:
1171 case 0x200 ... 0x2ff: /* MTRRs */
1172 break;
1173 case MSR_IA32_APICBASE:
1174 vcpu->apic_base = data;
1175 break;
0e859cac 1176 case MSR_K6_STAR:
6aa8b732
AK		 1177 vcpu->svm->vmcb->save.star = data;
1178 break;
0e859cac 1179#ifdef CONFIG_X86_64_
6aa8b732
AK		 1180 case MSR_LSTAR:
1181 vcpu->svm->vmcb->save.lstar = data;
1182 break;
1183 case MSR_CSTAR:
1184 vcpu->svm->vmcb->save.cstar = data;
1185 break;
1186 case MSR_KERNEL_GS_BASE:
1187 vcpu->svm->vmcb->save.kernel_gs_base = data;
1188 break;
1189 case MSR_SYSCALL_MASK:
1190 vcpu->svm->vmcb->save.sfmask = data;
1191 break;
1192#endif
1193 case MSR_IA32_SYSENTER_CS:
1194 vcpu->svm->vmcb->save.sysenter_cs = data;
1195 break;
1196 case MSR_IA32_SYSENTER_EIP:
1197 vcpu->svm->vmcb->save.sysenter_eip = data;
1198 break;
1199 case MSR_IA32_SYSENTER_ESP:
1200 vcpu->svm->vmcb->save.sysenter_esp = data;
1201 break;
1202 default:
1203 printk(KERN_ERR "kvm: unhandled wrmsr: %x\n", ecx);
1204 return 1;
1205 }
1206 return 0;
1207}
1208
1209static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1210{
1211 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1212 u64 data = (vcpu->svm->vmcb->save.rax & -1u)
1213 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1214 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1215 if (svm_set_msr(vcpu, ecx, data))
1216 svm_inject_gp(vcpu, 0);
1217 else
1218 skip_emulated_instruction(vcpu);
1219 return 1;
1220}
1221
1222static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1223{
1224 if (vcpu->svm->vmcb->control.exit_info_1)
1225 return wrmsr_interception(vcpu, kvm_run);
1226 else
1227 return rdmsr_interception(vcpu, kvm_run);
1228}
1229
1230static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1231 struct kvm_run *kvm_run) = {
1232 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1233 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1234 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1235 /* for now: */
1236 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1237 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1238 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1239 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1240 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1241 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1242 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1243 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1244 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1245 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1246 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1247 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1248 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1249 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1250 [SVM_EXIT_INTR] = nop_on_interception,
1251 [SVM_EXIT_NMI] = nop_on_interception,
1252 [SVM_EXIT_SMI] = nop_on_interception,
1253 [SVM_EXIT_INIT] = nop_on_interception,
1254 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1255 [SVM_EXIT_CPUID] = cpuid_interception,
1256 [SVM_EXIT_HLT] = halt_interception,
1257 [SVM_EXIT_INVLPG] = emulate_on_interception,
1258 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1259 [SVM_EXIT_IOIO] = io_interception,
1260 [SVM_EXIT_MSR] = msr_interception,
1261 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1262 [SVM_EXIT_VMRUN] = invalid_op_interception,
1263 [SVM_EXIT_VMMCALL] = invalid_op_interception,
1264 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1265 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1266 [SVM_EXIT_STGI] = invalid_op_interception,
1267 [SVM_EXIT_CLGI] = invalid_op_interception,
1268 [SVM_EXIT_SKINIT] = invalid_op_interception,
1269};
1270
1271
1272static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1273{
1274 u32 exit_code = vcpu->svm->vmcb->control.exit_code;
1275
1276 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1277
1278 if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
1279 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1280 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1281 "exit_code 0x%x\n",
1282 __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
1283 exit_code);
1284
1285 if (exit_code >= sizeof(svm_exit_handlers) / sizeof(*svm_exit_handlers)
1286 || svm_exit_handlers[exit_code] == 0) {
1287 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1288 printk(KERN_ERR "%s: 0x%x @ 0x%llx cr0 0x%lx rflags 0x%llx\n",
1289 __FUNCTION__,
1290 exit_code,
1291 vcpu->svm->vmcb->save.rip,
1292 vcpu->cr0,
1293 vcpu->svm->vmcb->save.rflags);
1294 return 0;
1295 }
1296
1297 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1298}
1299
1300static void reload_tss(struct kvm_vcpu *vcpu)
1301{
1302 int cpu = raw_smp_processor_id();
1303
1304 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1305 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1306 load_TR_desc();
1307}
1308
1309static void pre_svm_run(struct kvm_vcpu *vcpu)
1310{
1311 int cpu = raw_smp_processor_id();
1312
1313 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1314
1315 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1316 if (vcpu->cpu != cpu ||
1317 vcpu->svm->asid_generation != svm_data->asid_generation)
1318 new_asid(vcpu, svm_data);
1319}
1320
1321
1322static inline void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
1323{
1324 struct vmcb_control_area *control;
1325
1326 if (!vcpu->irq_summary)
1327 return;
1328
1329 control = &vcpu->svm->vmcb->control;
1330
1331 control->int_vector = pop_irq(vcpu);
1332 control->int_ctl &= ~V_INTR_PRIO_MASK;
1333 control->int_ctl |= V_IRQ_MASK |
1334 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1335}
1336
1337static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1338{
1339 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1340
1341 if (control->int_ctl & V_IRQ_MASK) {
1342 control->int_ctl &= ~V_IRQ_MASK;
1343 push_irq(vcpu, control->int_vector);
1344 }
1345}
1346
1347static void save_db_regs(unsigned long *db_regs)
1348{
5aff458e
AK		 1349 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1350 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1351 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1352 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
6aa8b732
AK		 1353}
1354
1355static void load_db_regs(unsigned long *db_regs)
1356{
5aff458e
AK		 1357 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1358 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1359 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1360 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
6aa8b732
AK		 1361}
1362
1363static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1364{
1365 u16 fs_selector;
1366 u16 gs_selector;
1367 u16 ldt_selector;
1368
1369again:
1370 kvm_try_inject_irq(vcpu);
1371
1372 clgi();
1373
1374 pre_svm_run(vcpu);
1375
1376 save_host_msrs(vcpu);
1377 fs_selector = read_fs();
1378 gs_selector = read_gs();
1379 ldt_selector = read_ldt();
1380 vcpu->svm->host_cr2 = kvm_read_cr2();
1381 vcpu->svm->host_dr6 = read_dr6();
1382 vcpu->svm->host_dr7 = read_dr7();
1383 vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
1384
1385 if (vcpu->svm->vmcb->save.dr7 & 0xff) {
1386 write_dr7(0);
1387 save_db_regs(vcpu->svm->host_db_regs);
1388 load_db_regs(vcpu->svm->db_regs);
1389 }
1390 asm volatile (
05b3e0c2 1391#ifdef CONFIG_X86_64
6aa8b732
AK		 1392 "push %%rbx; push %%rcx; push %%rdx;"
1393 "push %%rsi; push %%rdi; push %%rbp;"
1394 "push %%r8; push %%r9; push %%r10; push %%r11;"
1395 "push %%r12; push %%r13; push %%r14; push %%r15;"
1396#else
1397 "push %%ebx; push %%ecx; push %%edx;"
1398 "push %%esi; push %%edi; push %%ebp;"
1399#endif
1400
05b3e0c2 1401#ifdef CONFIG_X86_64
6aa8b732
AK		 1402 "mov %c[rbx](%[vcpu]), %%rbx \n\t"
1403 "mov %c[rcx](%[vcpu]), %%rcx \n\t"
1404 "mov %c[rdx](%[vcpu]), %%rdx \n\t"
1405 "mov %c[rsi](%[vcpu]), %%rsi \n\t"
1406 "mov %c[rdi](%[vcpu]), %%rdi \n\t"
1407 "mov %c[rbp](%[vcpu]), %%rbp \n\t"
1408 "mov %c[r8](%[vcpu]), %%r8 \n\t"
1409 "mov %c[r9](%[vcpu]), %%r9 \n\t"
1410 "mov %c[r10](%[vcpu]), %%r10 \n\t"
1411 "mov %c[r11](%[vcpu]), %%r11 \n\t"
1412 "mov %c[r12](%[vcpu]), %%r12 \n\t"
1413 "mov %c[r13](%[vcpu]), %%r13 \n\t"
1414 "mov %c[r14](%[vcpu]), %%r14 \n\t"
1415 "mov %c[r15](%[vcpu]), %%r15 \n\t"
1416#else
1417 "mov %c[rbx](%[vcpu]), %%ebx \n\t"
1418 "mov %c[rcx](%[vcpu]), %%ecx \n\t"
1419 "mov %c[rdx](%[vcpu]), %%edx \n\t"
1420 "mov %c[rsi](%[vcpu]), %%esi \n\t"
1421 "mov %c[rdi](%[vcpu]), %%edi \n\t"
1422 "mov %c[rbp](%[vcpu]), %%ebp \n\t"
1423#endif
1424
05b3e0c2 1425#ifdef CONFIG_X86_64
6aa8b732
AK		 1426 /* Enter guest mode */
1427 "push %%rax \n\t"
1428 "mov %c[svm](%[vcpu]), %%rax \n\t"
1429 "mov %c[vmcb](%%rax), %%rax \n\t"
1430 SVM_VMLOAD "\n\t"
1431 SVM_VMRUN "\n\t"
1432 SVM_VMSAVE "\n\t"
1433 "pop %%rax \n\t"
1434#else
1435 /* Enter guest mode */
1436 "push %%eax \n\t"
1437 "mov %c[svm](%[vcpu]), %%eax \n\t"
1438 "mov %c[vmcb](%%eax), %%eax \n\t"
1439 SVM_VMLOAD "\n\t"
1440 SVM_VMRUN "\n\t"
1441 SVM_VMSAVE "\n\t"
1442 "pop %%eax \n\t"
1443#endif
1444
1445 /* Save guest registers, load host registers */
05b3e0c2 1446#ifdef CONFIG_X86_64
6aa8b732
AK		 1447 "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
1448 "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
1449 "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
1450 "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
1451 "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
1452 "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
1453 "mov %%r8, %c[r8](%[vcpu]) \n\t"
1454 "mov %%r9, %c[r9](%[vcpu]) \n\t"
1455 "mov %%r10, %c[r10](%[vcpu]) \n\t"
1456 "mov %%r11, %c[r11](%[vcpu]) \n\t"
1457 "mov %%r12, %c[r12](%[vcpu]) \n\t"
1458 "mov %%r13, %c[r13](%[vcpu]) \n\t"
1459 "mov %%r14, %c[r14](%[vcpu]) \n\t"
1460 "mov %%r15, %c[r15](%[vcpu]) \n\t"
1461
1462 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1463 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1464 "pop %%rbp; pop %%rdi; pop %%rsi;"
1465 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1466#else
1467 "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
1468 "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
1469 "mov %%edx, %c[rdx](%[vcpu]) \n\t"
1470 "mov %%esi, %c[rsi](%[vcpu]) \n\t"
1471 "mov %%edi, %c[rdi](%[vcpu]) \n\t"
1472 "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
1473
1474 "pop %%ebp; pop %%edi; pop %%esi;"
1475 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1476#endif
1477 :
1478 : [vcpu]"a"(vcpu),
1479 [svm]"i"(offsetof(struct kvm_vcpu, svm)),
1480 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1481 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1482 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1483 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1484 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1485 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1486 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
05b3e0c2 1487#ifdef CONFIG_X86_64
6aa8b732
AK		 1488 ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1489 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1490 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1491 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1492 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1493 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1494 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1495 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
1496#endif
1497 : "cc", "memory" );
1498
1499 if ((vcpu->svm->vmcb->save.dr7 & 0xff))
1500 load_db_regs(vcpu->svm->host_db_regs);
1501
1502 vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
1503
1504 write_dr6(vcpu->svm->host_dr6);
1505 write_dr7(vcpu->svm->host_dr7);
1506 kvm_write_cr2(vcpu->svm->host_cr2);
1507
1508 load_fs(fs_selector);
1509 load_gs(gs_selector);
1510 load_ldt(ldt_selector);
1511 load_host_msrs(vcpu);
1512
1513 reload_tss(vcpu);
1514
1515 stgi();
1516
1517 kvm_reput_irq(vcpu);
1518
1519 vcpu->svm->next_rip = 0;
1520
1521 if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1522 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1523 kvm_run->exit_reason = vcpu->svm->vmcb->control.exit_code;
1524 return 0;
1525 }
1526
1527 if (handle_exit(vcpu, kvm_run)) {
1528 if (signal_pending(current)) {
1529 ++kvm_stat.signal_exits;
1530 return -EINTR;
1531 }
1532 kvm_resched(vcpu);
1533 goto again;
1534 }
1535 return 0;
1536}
1537
1538static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1539{
1540 force_new_asid(vcpu);
1541}
1542
1543static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1544{
1545 vcpu->svm->vmcb->save.cr3 = root;
1546 force_new_asid(vcpu);
1547}
1548
1549static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1550 unsigned long addr,
1551 uint32_t err_code)
1552{
1553 uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
1554
1555 ++kvm_stat.pf_guest;
1556
1557 if (is_page_fault(exit_int_info)) {
1558
1559 vcpu->svm->vmcb->control.event_inj_err = 0;
1560 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1561 SVM_EVTINJ_VALID_ERR |
1562 SVM_EVTINJ_TYPE_EXEPT |
1563 DF_VECTOR;
1564 return;
1565 }
1566 vcpu->cr2 = addr;
1567 vcpu->svm->vmcb->save.cr2 = addr;
1568 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1569 SVM_EVTINJ_VALID_ERR |
1570 SVM_EVTINJ_TYPE_EXEPT |
1571 PF_VECTOR;
1572 vcpu->svm->vmcb->control.event_inj_err = err_code;
1573}
1574
1575
1576static int is_disabled(void)
1577{
1578 return 0;
1579}
1580
1581static struct kvm_arch_ops svm_arch_ops = {
1582 .cpu_has_kvm_support = has_svm,
1583 .disabled_by_bios = is_disabled,
1584 .hardware_setup = svm_hardware_setup,
1585 .hardware_unsetup = svm_hardware_unsetup,
1586 .hardware_enable = svm_hardware_enable,
1587 .hardware_disable = svm_hardware_disable,
1588
1589 .vcpu_create = svm_create_vcpu,
1590 .vcpu_free = svm_free_vcpu,
1591
1592 .vcpu_load = svm_vcpu_load,
1593 .vcpu_put = svm_vcpu_put,
1594
1595 .set_guest_debug = svm_guest_debug,
1596 .get_msr = svm_get_msr,
1597 .set_msr = svm_set_msr,
1598 .get_segment_base = svm_get_segment_base,
1599 .get_segment = svm_get_segment,
1600 .set_segment = svm_set_segment,
1601 .is_long_mode = svm_is_long_mode,
1602 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
1603 .set_cr0 = svm_set_cr0,
1604 .set_cr0_no_modeswitch = svm_set_cr0,
1605 .set_cr3 = svm_set_cr3,
1606 .set_cr4 = svm_set_cr4,
1607 .set_efer = svm_set_efer,
1608 .get_idt = svm_get_idt,
1609 .set_idt = svm_set_idt,
1610 .get_gdt = svm_get_gdt,
1611 .set_gdt = svm_set_gdt,
1612 .get_dr = svm_get_dr,
1613 .set_dr = svm_set_dr,
1614 .cache_regs = svm_cache_regs,
1615 .decache_regs = svm_decache_regs,
1616 .get_rflags = svm_get_rflags,
1617 .set_rflags = svm_set_rflags,
1618
1619 .invlpg = svm_invlpg,
1620 .tlb_flush = svm_flush_tlb,
1621 .inject_page_fault = svm_inject_page_fault,
1622
1623 .inject_gp = svm_inject_gp,
1624
1625 .run = svm_vcpu_run,
1626 .skip_emulated_instruction = skip_emulated_instruction,
1627 .vcpu_setup = svm_vcpu_setup,
1628};
1629
1630static int __init svm_init(void)
1631{
873a7c42 1632 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
6aa8b732
AK		 1633}
1634
1635static void __exit svm_exit(void)
1636{
1637 kvm_exit_arch();
1638}
1639
1640module_init(svm_init)
1641module_exit(svm_exit)
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