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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
e495606d AK |
17 | #include "kvm_svm.h" |
18 | #include "x86_emulate.h" | |
19 | ||
6aa8b732 | 20 | #include <linux/module.h> |
9d8f549d | 21 | #include <linux/kernel.h> |
6aa8b732 AK |
22 | #include <linux/vmalloc.h> |
23 | #include <linux/highmem.h> | |
07031e14 | 24 | #include <linux/profile.h> |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | |
e495606d | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | MODULE_AUTHOR("Qumranet"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | #define IOPM_ALLOC_ORDER 2 | |
33 | #define MSRPM_ALLOC_ORDER 1 | |
34 | ||
35 | #define DB_VECTOR 1 | |
36 | #define UD_VECTOR 6 | |
37 | #define GP_VECTOR 13 | |
38 | ||
39 | #define DR7_GD_MASK (1 << 13) | |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
45 | #define KVM_EFER_LMA (1 << 10) | |
46 | #define KVM_EFER_LME (1 << 8) | |
47 | ||
80b7706e JR |
48 | #define SVM_FEATURE_NPT (1 << 0) |
49 | #define SVM_FEATURE_LBRV (1 << 1) | |
50 | #define SVM_DEATURE_SVML (1 << 2) | |
51 | ||
a2fa3e9f GH |
52 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
53 | { | |
fb3f0f51 | 54 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
55 | } |
56 | ||
6aa8b732 AK |
57 | unsigned long iopm_base; |
58 | unsigned long msrpm_base; | |
59 | ||
60 | struct kvm_ldttss_desc { | |
61 | u16 limit0; | |
62 | u16 base0; | |
63 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
64 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
65 | u32 base3; | |
66 | u32 zero1; | |
67 | } __attribute__((packed)); | |
68 | ||
69 | struct svm_cpu_data { | |
70 | int cpu; | |
71 | ||
5008fdf5 AK |
72 | u64 asid_generation; |
73 | u32 max_asid; | |
74 | u32 next_asid; | |
6aa8b732 AK |
75 | struct kvm_ldttss_desc *tss_desc; |
76 | ||
77 | struct page *save_area; | |
78 | }; | |
79 | ||
80 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 81 | static uint32_t svm_features; |
6aa8b732 AK |
82 | |
83 | struct svm_init_data { | |
84 | int cpu; | |
85 | int r; | |
86 | }; | |
87 | ||
88 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
89 | ||
9d8f549d | 90 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
91 | #define MSRS_RANGE_SIZE 2048 |
92 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
93 | ||
94 | #define MAX_INST_SIZE 15 | |
95 | ||
80b7706e JR |
96 | static inline u32 svm_has(u32 feat) |
97 | { | |
98 | return svm_features & feat; | |
99 | } | |
100 | ||
6aa8b732 AK |
101 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
102 | { | |
103 | int word_index = __ffs(vcpu->irq_summary); | |
104 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
105 | int irq = word_index * BITS_PER_LONG + bit_index; | |
106 | ||
107 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
108 | if (!vcpu->irq_pending[word_index]) | |
109 | clear_bit(word_index, &vcpu->irq_summary); | |
110 | return irq; | |
111 | } | |
112 | ||
113 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
114 | { | |
115 | set_bit(irq, vcpu->irq_pending); | |
116 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
117 | } | |
118 | ||
119 | static inline void clgi(void) | |
120 | { | |
121 | asm volatile (SVM_CLGI); | |
122 | } | |
123 | ||
124 | static inline void stgi(void) | |
125 | { | |
126 | asm volatile (SVM_STGI); | |
127 | } | |
128 | ||
129 | static inline void invlpga(unsigned long addr, u32 asid) | |
130 | { | |
131 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
132 | } | |
133 | ||
134 | static inline unsigned long kvm_read_cr2(void) | |
135 | { | |
136 | unsigned long cr2; | |
137 | ||
138 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
139 | return cr2; | |
140 | } | |
141 | ||
142 | static inline void kvm_write_cr2(unsigned long val) | |
143 | { | |
144 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
145 | } | |
146 | ||
147 | static inline unsigned long read_dr6(void) | |
148 | { | |
149 | unsigned long dr6; | |
150 | ||
151 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
152 | return dr6; | |
153 | } | |
154 | ||
155 | static inline void write_dr6(unsigned long val) | |
156 | { | |
157 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
158 | } | |
159 | ||
160 | static inline unsigned long read_dr7(void) | |
161 | { | |
162 | unsigned long dr7; | |
163 | ||
164 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
165 | return dr7; | |
166 | } | |
167 | ||
168 | static inline void write_dr7(unsigned long val) | |
169 | { | |
170 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
171 | } | |
172 | ||
6aa8b732 AK |
173 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
174 | { | |
a2fa3e9f | 175 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
176 | } |
177 | ||
178 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
179 | { | |
180 | force_new_asid(vcpu); | |
181 | } | |
182 | ||
183 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
184 | { | |
185 | if (!(efer & KVM_EFER_LMA)) | |
186 | efer &= ~KVM_EFER_LME; | |
187 | ||
a2fa3e9f | 188 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
6aa8b732 AK |
189 | vcpu->shadow_efer = efer; |
190 | } | |
191 | ||
192 | static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
193 | { | |
a2fa3e9f GH |
194 | struct vcpu_svm *svm = to_svm(vcpu); |
195 | ||
196 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
6aa8b732 AK |
197 | SVM_EVTINJ_VALID_ERR | |
198 | SVM_EVTINJ_TYPE_EXEPT | | |
199 | GP_VECTOR; | |
a2fa3e9f | 200 | svm->vmcb->control.event_inj_err = error_code; |
6aa8b732 AK |
201 | } |
202 | ||
203 | static void inject_ud(struct kvm_vcpu *vcpu) | |
204 | { | |
a2fa3e9f | 205 | to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID | |
6aa8b732 AK |
206 | SVM_EVTINJ_TYPE_EXEPT | |
207 | UD_VECTOR; | |
208 | } | |
209 | ||
6aa8b732 AK |
210 | static int is_page_fault(uint32_t info) |
211 | { | |
212 | info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
213 | return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT); | |
214 | } | |
215 | ||
216 | static int is_external_interrupt(u32 info) | |
217 | { | |
218 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
219 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
220 | } | |
221 | ||
222 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
223 | { | |
a2fa3e9f GH |
224 | struct vcpu_svm *svm = to_svm(vcpu); |
225 | ||
226 | if (!svm->next_rip) { | |
6aa8b732 AK |
227 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
228 | return; | |
229 | } | |
3077c451 | 230 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) { |
6aa8b732 AK |
231 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
232 | __FUNCTION__, | |
a2fa3e9f GH |
233 | svm->vmcb->save.rip, |
234 | svm->next_rip); | |
6aa8b732 AK |
235 | } |
236 | ||
a2fa3e9f GH |
237 | vcpu->rip = svm->vmcb->save.rip = svm->next_rip; |
238 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
239 | |
240 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
241 | } |
242 | ||
243 | static int has_svm(void) | |
244 | { | |
245 | uint32_t eax, ebx, ecx, edx; | |
246 | ||
1e885461 | 247 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
248 | printk(KERN_INFO "has_svm: not amd\n"); |
249 | return 0; | |
250 | } | |
251 | ||
252 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
253 | if (eax < SVM_CPUID_FUNC) { | |
254 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
255 | return 0; | |
256 | } | |
257 | ||
258 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
259 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
260 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
261 | return 0; | |
262 | } | |
263 | return 1; | |
264 | } | |
265 | ||
266 | static void svm_hardware_disable(void *garbage) | |
267 | { | |
268 | struct svm_cpu_data *svm_data | |
269 | = per_cpu(svm_data, raw_smp_processor_id()); | |
270 | ||
271 | if (svm_data) { | |
272 | uint64_t efer; | |
273 | ||
274 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
275 | rdmsrl(MSR_EFER, efer); | |
276 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 277 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
278 | __free_page(svm_data->save_area); |
279 | kfree(svm_data); | |
280 | } | |
281 | } | |
282 | ||
283 | static void svm_hardware_enable(void *garbage) | |
284 | { | |
285 | ||
286 | struct svm_cpu_data *svm_data; | |
287 | uint64_t efer; | |
05b3e0c2 | 288 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
289 | struct desc_ptr gdt_descr; |
290 | #else | |
291 | struct Xgt_desc_struct gdt_descr; | |
292 | #endif | |
293 | struct desc_struct *gdt; | |
294 | int me = raw_smp_processor_id(); | |
295 | ||
296 | if (!has_svm()) { | |
297 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
298 | return; | |
299 | } | |
300 | svm_data = per_cpu(svm_data, me); | |
301 | ||
302 | if (!svm_data) { | |
303 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
304 | me); | |
305 | return; | |
306 | } | |
307 | ||
308 | svm_data->asid_generation = 1; | |
309 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
310 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 311 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 AK |
312 | |
313 | asm volatile ( "sgdt %0" : "=m"(gdt_descr) ); | |
314 | gdt = (struct desc_struct *)gdt_descr.address; | |
315 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
316 | ||
317 | rdmsrl(MSR_EFER, efer); | |
318 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
319 | ||
320 | wrmsrl(MSR_VM_HSAVE_PA, | |
321 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
322 | } | |
323 | ||
324 | static int svm_cpu_init(int cpu) | |
325 | { | |
326 | struct svm_cpu_data *svm_data; | |
327 | int r; | |
328 | ||
329 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
330 | if (!svm_data) | |
331 | return -ENOMEM; | |
332 | svm_data->cpu = cpu; | |
333 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
334 | r = -ENOMEM; | |
335 | if (!svm_data->save_area) | |
336 | goto err_1; | |
337 | ||
338 | per_cpu(svm_data, cpu) = svm_data; | |
339 | ||
340 | return 0; | |
341 | ||
342 | err_1: | |
343 | kfree(svm_data); | |
344 | return r; | |
345 | ||
346 | } | |
347 | ||
bfc733a7 RR |
348 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
349 | int read, int write) | |
6aa8b732 AK |
350 | { |
351 | int i; | |
352 | ||
353 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
354 | if (msr >= msrpm_ranges[i] && | |
355 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
356 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
357 | msrpm_ranges[i]) * 2; | |
358 | ||
359 | u32 *base = msrpm + (msr_offset / 32); | |
360 | u32 msr_shift = msr_offset % 32; | |
361 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
362 | *base = (*base & ~(0x3 << msr_shift)) | | |
363 | (mask << msr_shift); | |
bfc733a7 | 364 | return; |
6aa8b732 AK |
365 | } |
366 | } | |
bfc733a7 | 367 | BUG(); |
6aa8b732 AK |
368 | } |
369 | ||
370 | static __init int svm_hardware_setup(void) | |
371 | { | |
372 | int cpu; | |
373 | struct page *iopm_pages; | |
374 | struct page *msrpm_pages; | |
c8681339 | 375 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
376 | int r; |
377 | ||
873a7c42 | 378 | kvm_emulator_want_group7_invlpg(); |
6aa8b732 AK |
379 | |
380 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); | |
381 | ||
382 | if (!iopm_pages) | |
383 | return -ENOMEM; | |
c8681339 AL |
384 | |
385 | iopm_va = page_address(iopm_pages); | |
386 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
387 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
388 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
389 | ||
390 | ||
391 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
392 | ||
393 | r = -ENOMEM; | |
394 | if (!msrpm_pages) | |
395 | goto err_1; | |
396 | ||
397 | msrpm_va = page_address(msrpm_pages); | |
398 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
399 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
400 | ||
05b3e0c2 | 401 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
402 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
403 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
404 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
405 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
406 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
407 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
408 | #endif | |
0e859cac | 409 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
410 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
411 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
412 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
413 | ||
414 | for_each_online_cpu(cpu) { | |
415 | r = svm_cpu_init(cpu); | |
416 | if (r) | |
417 | goto err_2; | |
418 | } | |
419 | return 0; | |
420 | ||
421 | err_2: | |
422 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
423 | msrpm_base = 0; | |
424 | err_1: | |
425 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
426 | iopm_base = 0; | |
427 | return r; | |
428 | } | |
429 | ||
430 | static __exit void svm_hardware_unsetup(void) | |
431 | { | |
432 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
433 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
434 | iopm_base = msrpm_base = 0; | |
435 | } | |
436 | ||
437 | static void init_seg(struct vmcb_seg *seg) | |
438 | { | |
439 | seg->selector = 0; | |
440 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
441 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
442 | seg->limit = 0xffff; | |
443 | seg->base = 0; | |
444 | } | |
445 | ||
446 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
447 | { | |
448 | seg->selector = 0; | |
449 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
450 | seg->limit = 0xffff; | |
451 | seg->base = 0; | |
452 | } | |
453 | ||
6aa8b732 AK |
454 | static void init_vmcb(struct vmcb *vmcb) |
455 | { | |
456 | struct vmcb_control_area *control = &vmcb->control; | |
457 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
458 | |
459 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
460 | INTERCEPT_CR3_MASK | | |
461 | INTERCEPT_CR4_MASK; | |
462 | ||
463 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
464 | INTERCEPT_CR3_MASK | | |
465 | INTERCEPT_CR4_MASK; | |
466 | ||
467 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
468 | INTERCEPT_DR1_MASK | | |
469 | INTERCEPT_DR2_MASK | | |
470 | INTERCEPT_DR3_MASK; | |
471 | ||
472 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
473 | INTERCEPT_DR1_MASK | | |
474 | INTERCEPT_DR2_MASK | | |
475 | INTERCEPT_DR3_MASK | | |
476 | INTERCEPT_DR5_MASK | | |
477 | INTERCEPT_DR7_MASK; | |
478 | ||
479 | control->intercept_exceptions = 1 << PF_VECTOR; | |
480 | ||
481 | ||
482 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
483 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 484 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
485 | /* |
486 | * selective cr0 intercept bug? | |
487 | * 0: 0f 22 d8 mov %eax,%cr3 | |
488 | * 3: 0f 20 c0 mov %cr0,%eax | |
489 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
490 | * b: 0f 22 c0 mov %eax,%cr0 | |
491 | * set cr3 ->interception | |
492 | * get cr0 ->interception | |
493 | * set cr0 -> no interception | |
494 | */ | |
495 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
496 | (1ULL << INTERCEPT_CPUID) | | |
497 | (1ULL << INTERCEPT_HLT) | | |
6aa8b732 AK |
498 | (1ULL << INTERCEPT_INVLPGA) | |
499 | (1ULL << INTERCEPT_IOIO_PROT) | | |
500 | (1ULL << INTERCEPT_MSR_PROT) | | |
501 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 502 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
503 | (1ULL << INTERCEPT_VMRUN) | |
504 | (1ULL << INTERCEPT_VMMCALL) | | |
505 | (1ULL << INTERCEPT_VMLOAD) | | |
506 | (1ULL << INTERCEPT_VMSAVE) | | |
507 | (1ULL << INTERCEPT_STGI) | | |
508 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 JR |
509 | (1ULL << INTERCEPT_SKINIT) | |
510 | (1ULL << INTERCEPT_MONITOR) | | |
511 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
512 | |
513 | control->iopm_base_pa = iopm_base; | |
514 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 515 | control->tsc_offset = 0; |
6aa8b732 AK |
516 | control->int_ctl = V_INTR_MASKING_MASK; |
517 | ||
518 | init_seg(&save->es); | |
519 | init_seg(&save->ss); | |
520 | init_seg(&save->ds); | |
521 | init_seg(&save->fs); | |
522 | init_seg(&save->gs); | |
523 | ||
524 | save->cs.selector = 0xf000; | |
525 | /* Executable/Readable Code Segment */ | |
526 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
527 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
528 | save->cs.limit = 0xffff; | |
d92899a0 AK |
529 | /* |
530 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
531 | * be consistent with it. | |
532 | * | |
533 | * Replace when we have real mode working for vmx. | |
534 | */ | |
535 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
536 | |
537 | save->gdtr.limit = 0xffff; | |
538 | save->idtr.limit = 0xffff; | |
539 | ||
540 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
541 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
542 | ||
543 | save->efer = MSR_EFER_SVME_MASK; | |
544 | ||
545 | save->dr6 = 0xffff0ff0; | |
546 | save->dr7 = 0x400; | |
547 | save->rflags = 2; | |
548 | save->rip = 0x0000fff0; | |
549 | ||
550 | /* | |
551 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
552 | * cache by default. the orderly way is to enable cache in bios. | |
553 | */ | |
707d92fa | 554 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 555 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
556 | /* rdx = ?? */ |
557 | } | |
558 | ||
fb3f0f51 | 559 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 560 | { |
a2fa3e9f | 561 | struct vcpu_svm *svm; |
6aa8b732 | 562 | struct page *page; |
fb3f0f51 | 563 | int err; |
6aa8b732 | 564 | |
c16f862d | 565 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
566 | if (!svm) { |
567 | err = -ENOMEM; | |
568 | goto out; | |
569 | } | |
570 | ||
571 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
572 | if (err) | |
573 | goto free_svm; | |
574 | ||
6aa8b732 | 575 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
576 | if (!page) { |
577 | err = -ENOMEM; | |
578 | goto uninit; | |
579 | } | |
6aa8b732 | 580 | |
a2fa3e9f GH |
581 | svm->vmcb = page_address(page); |
582 | clear_page(svm->vmcb); | |
583 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
584 | svm->asid_generation = 0; | |
585 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
586 | init_vmcb(svm->vmcb); | |
587 | ||
fb3f0f51 RR |
588 | fx_init(&svm->vcpu); |
589 | svm->vcpu.fpu_active = 1; | |
590 | svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
591 | if (svm->vcpu.vcpu_id == 0) | |
592 | svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 593 | |
fb3f0f51 | 594 | return &svm->vcpu; |
36241b8c | 595 | |
fb3f0f51 RR |
596 | uninit: |
597 | kvm_vcpu_uninit(&svm->vcpu); | |
598 | free_svm: | |
a4770347 | 599 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
600 | out: |
601 | return ERR_PTR(err); | |
6aa8b732 AK |
602 | } |
603 | ||
604 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
605 | { | |
a2fa3e9f GH |
606 | struct vcpu_svm *svm = to_svm(vcpu); |
607 | ||
fb3f0f51 RR |
608 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
609 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 610 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
611 | } |
612 | ||
15ad7146 | 613 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 614 | { |
a2fa3e9f | 615 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 616 | int i; |
0cc5064d | 617 | |
0cc5064d AK |
618 | if (unlikely(cpu != vcpu->cpu)) { |
619 | u64 tsc_this, delta; | |
620 | ||
621 | /* | |
622 | * Make sure that the guest sees a monotonically | |
623 | * increasing TSC. | |
624 | */ | |
625 | rdtscll(tsc_this); | |
626 | delta = vcpu->host_tsc - tsc_this; | |
a2fa3e9f | 627 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d AK |
628 | vcpu->cpu = cpu; |
629 | } | |
94dfbdb3 AL |
630 | |
631 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 632 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
633 | } |
634 | ||
635 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
636 | { | |
a2fa3e9f | 637 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
638 | int i; |
639 | ||
640 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 641 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 642 | |
0cc5064d | 643 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
644 | } |
645 | ||
774c47f1 AK |
646 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
647 | { | |
648 | } | |
649 | ||
6aa8b732 AK |
650 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
651 | { | |
a2fa3e9f GH |
652 | struct vcpu_svm *svm = to_svm(vcpu); |
653 | ||
654 | vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
655 | vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
656 | vcpu->rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
657 | } |
658 | ||
659 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
660 | { | |
a2fa3e9f GH |
661 | struct vcpu_svm *svm = to_svm(vcpu); |
662 | svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
663 | svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
664 | svm->vmcb->save.rip = vcpu->rip; | |
6aa8b732 AK |
665 | } |
666 | ||
667 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
668 | { | |
a2fa3e9f | 669 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
670 | } |
671 | ||
672 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
673 | { | |
a2fa3e9f | 674 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
675 | } |
676 | ||
677 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
678 | { | |
a2fa3e9f | 679 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
680 | |
681 | switch (seg) { | |
682 | case VCPU_SREG_CS: return &save->cs; | |
683 | case VCPU_SREG_DS: return &save->ds; | |
684 | case VCPU_SREG_ES: return &save->es; | |
685 | case VCPU_SREG_FS: return &save->fs; | |
686 | case VCPU_SREG_GS: return &save->gs; | |
687 | case VCPU_SREG_SS: return &save->ss; | |
688 | case VCPU_SREG_TR: return &save->tr; | |
689 | case VCPU_SREG_LDTR: return &save->ldtr; | |
690 | } | |
691 | BUG(); | |
8b6d44c7 | 692 | return NULL; |
6aa8b732 AK |
693 | } |
694 | ||
695 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
696 | { | |
697 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
698 | ||
699 | return s->base; | |
700 | } | |
701 | ||
702 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
703 | struct kvm_segment *var, int seg) | |
704 | { | |
705 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
706 | ||
707 | var->base = s->base; | |
708 | var->limit = s->limit; | |
709 | var->selector = s->selector; | |
710 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
711 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
712 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
713 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
714 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
715 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
716 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
717 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
718 | var->unusable = !var->present; | |
719 | } | |
720 | ||
721 | static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
722 | { | |
723 | struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS); | |
724 | ||
725 | *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
726 | *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
727 | } | |
728 | ||
729 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
730 | { | |
a2fa3e9f GH |
731 | struct vcpu_svm *svm = to_svm(vcpu); |
732 | ||
733 | dt->limit = svm->vmcb->save.idtr.limit; | |
734 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
735 | } |
736 | ||
737 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
738 | { | |
a2fa3e9f GH |
739 | struct vcpu_svm *svm = to_svm(vcpu); |
740 | ||
741 | svm->vmcb->save.idtr.limit = dt->limit; | |
742 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
743 | } |
744 | ||
745 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
746 | { | |
a2fa3e9f GH |
747 | struct vcpu_svm *svm = to_svm(vcpu); |
748 | ||
749 | dt->limit = svm->vmcb->save.gdtr.limit; | |
750 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
751 | } |
752 | ||
753 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
754 | { | |
a2fa3e9f GH |
755 | struct vcpu_svm *svm = to_svm(vcpu); |
756 | ||
757 | svm->vmcb->save.gdtr.limit = dt->limit; | |
758 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
759 | } |
760 | ||
25c4c276 | 761 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
762 | { |
763 | } | |
764 | ||
6aa8b732 AK |
765 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
766 | { | |
a2fa3e9f GH |
767 | struct vcpu_svm *svm = to_svm(vcpu); |
768 | ||
05b3e0c2 | 769 | #ifdef CONFIG_X86_64 |
6aa8b732 | 770 | if (vcpu->shadow_efer & KVM_EFER_LME) { |
707d92fa | 771 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
6aa8b732 | 772 | vcpu->shadow_efer |= KVM_EFER_LMA; |
a2fa3e9f | 773 | svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME; |
6aa8b732 AK |
774 | } |
775 | ||
707d92fa | 776 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) { |
6aa8b732 | 777 | vcpu->shadow_efer &= ~KVM_EFER_LMA; |
a2fa3e9f | 778 | svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME); |
6aa8b732 AK |
779 | } |
780 | } | |
781 | #endif | |
707d92fa | 782 | if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 783 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
784 | vcpu->fpu_active = 1; |
785 | } | |
786 | ||
6aa8b732 | 787 | vcpu->cr0 = cr0; |
707d92fa RR |
788 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
789 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 790 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
791 | } |
792 | ||
793 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
794 | { | |
795 | vcpu->cr4 = cr4; | |
a2fa3e9f | 796 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
797 | } |
798 | ||
799 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
800 | struct kvm_segment *var, int seg) | |
801 | { | |
a2fa3e9f | 802 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
803 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
804 | ||
805 | s->base = var->base; | |
806 | s->limit = var->limit; | |
807 | s->selector = var->selector; | |
808 | if (var->unusable) | |
809 | s->attrib = 0; | |
810 | else { | |
811 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
812 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
813 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
814 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
815 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
816 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
817 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
818 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
819 | } | |
820 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
821 | svm->vmcb->save.cpl |
822 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
823 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
824 | ||
825 | } | |
826 | ||
827 | /* FIXME: | |
828 | ||
a2fa3e9f GH |
829 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
830 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
831 | |
832 | */ | |
833 | ||
834 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
835 | { | |
836 | return -EOPNOTSUPP; | |
837 | } | |
838 | ||
839 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
840 | { | |
94dfbdb3 | 841 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 842 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 843 | #endif |
6aa8b732 AK |
844 | } |
845 | ||
846 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
847 | { | |
94dfbdb3 | 848 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 849 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 850 | #endif |
6aa8b732 AK |
851 | } |
852 | ||
e756fc62 | 853 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
854 | { |
855 | if (svm_data->next_asid > svm_data->max_asid) { | |
856 | ++svm_data->asid_generation; | |
857 | svm_data->next_asid = 1; | |
a2fa3e9f | 858 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
859 | } |
860 | ||
e756fc62 | 861 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
862 | svm->asid_generation = svm_data->asid_generation; |
863 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
864 | } |
865 | ||
866 | static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
867 | { | |
a2fa3e9f | 868 | invlpga(address, to_svm(vcpu)->vmcb->control.asid); // is needed? |
6aa8b732 AK |
869 | } |
870 | ||
871 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) | |
872 | { | |
a2fa3e9f | 873 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
874 | } |
875 | ||
876 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
877 | int *exception) | |
878 | { | |
a2fa3e9f GH |
879 | struct vcpu_svm *svm = to_svm(vcpu); |
880 | ||
6aa8b732 AK |
881 | *exception = 0; |
882 | ||
a2fa3e9f GH |
883 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
884 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
885 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
886 | *exception = DB_VECTOR; |
887 | return; | |
888 | } | |
889 | ||
890 | switch (dr) { | |
891 | case 0 ... 3: | |
a2fa3e9f | 892 | svm->db_regs[dr] = value; |
6aa8b732 AK |
893 | return; |
894 | case 4 ... 5: | |
66aee91a | 895 | if (vcpu->cr4 & X86_CR4_DE) { |
6aa8b732 AK |
896 | *exception = UD_VECTOR; |
897 | return; | |
898 | } | |
899 | case 7: { | |
900 | if (value & ~((1ULL << 32) - 1)) { | |
901 | *exception = GP_VECTOR; | |
902 | return; | |
903 | } | |
a2fa3e9f | 904 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
905 | return; |
906 | } | |
907 | default: | |
908 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
909 | __FUNCTION__, dr); | |
910 | *exception = UD_VECTOR; | |
911 | return; | |
912 | } | |
913 | } | |
914 | ||
e756fc62 | 915 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 916 | { |
a2fa3e9f | 917 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 918 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
919 | u64 fault_address; |
920 | u32 error_code; | |
921 | enum emulation_result er; | |
e2dec939 | 922 | int r; |
6aa8b732 AK |
923 | |
924 | if (is_external_interrupt(exit_int_info)) | |
e756fc62 | 925 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 926 | |
e756fc62 | 927 | mutex_lock(&kvm->lock); |
6aa8b732 | 928 | |
a2fa3e9f GH |
929 | fault_address = svm->vmcb->control.exit_info_2; |
930 | error_code = svm->vmcb->control.exit_info_1; | |
e756fc62 | 931 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
e2dec939 | 932 | if (r < 0) { |
e756fc62 | 933 | mutex_unlock(&kvm->lock); |
e2dec939 AK |
934 | return r; |
935 | } | |
936 | if (!r) { | |
e756fc62 | 937 | mutex_unlock(&kvm->lock); |
6aa8b732 AK |
938 | return 1; |
939 | } | |
e756fc62 RR |
940 | er = emulate_instruction(&svm->vcpu, kvm_run, fault_address, |
941 | error_code); | |
942 | mutex_unlock(&kvm->lock); | |
6aa8b732 AK |
943 | |
944 | switch (er) { | |
945 | case EMULATE_DONE: | |
946 | return 1; | |
947 | case EMULATE_DO_MMIO: | |
e756fc62 | 948 | ++svm->vcpu.stat.mmio_exits; |
6aa8b732 AK |
949 | return 0; |
950 | case EMULATE_FAIL: | |
e756fc62 | 951 | vcpu_printf(&svm->vcpu, "%s: emulate fail\n", __FUNCTION__); |
6aa8b732 AK |
952 | break; |
953 | default: | |
954 | BUG(); | |
955 | } | |
956 | ||
957 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
958 | return 0; | |
959 | } | |
960 | ||
e756fc62 | 961 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 962 | { |
a2fa3e9f | 963 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 964 | if (!(svm->vcpu.cr0 & X86_CR0_TS)) |
a2fa3e9f | 965 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 966 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
967 | |
968 | return 1; | |
7807fa6c AL |
969 | } |
970 | ||
e756fc62 | 971 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
972 | { |
973 | /* | |
974 | * VMCB is undefined after a SHUTDOWN intercept | |
975 | * so reinitialize it. | |
976 | */ | |
a2fa3e9f GH |
977 | clear_page(svm->vmcb); |
978 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
979 | |
980 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
981 | return 0; | |
982 | } | |
983 | ||
e756fc62 | 984 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 985 | { |
a2fa3e9f | 986 | u32 io_info = svm->vmcb->control.exit_info_1; //address size bug? |
039576c0 AK |
987 | int size, down, in, string, rep; |
988 | unsigned port; | |
6aa8b732 | 989 | |
e756fc62 | 990 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 991 | |
a2fa3e9f | 992 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 993 | |
e70669ab LV |
994 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
995 | ||
996 | if (string) { | |
997 | if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0) == EMULATE_DO_MMIO) | |
998 | return 0; | |
999 | return 1; | |
1000 | } | |
1001 | ||
039576c0 AK |
1002 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1003 | port = io_info >> 16; | |
1004 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1005 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1006 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1007 | |
3090dd73 | 1008 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1009 | } |
1010 | ||
e756fc62 | 1011 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1012 | { |
1013 | return 1; | |
1014 | } | |
1015 | ||
e756fc62 | 1016 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1017 | { |
a2fa3e9f | 1018 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1019 | skip_emulated_instruction(&svm->vcpu); |
1020 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1021 | } |
1022 | ||
e756fc62 | 1023 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1024 | { |
a2fa3e9f | 1025 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 RR |
1026 | skip_emulated_instruction(&svm->vcpu); |
1027 | return kvm_hypercall(&svm->vcpu, kvm_run); | |
02e235bc AK |
1028 | } |
1029 | ||
e756fc62 RR |
1030 | static int invalid_op_interception(struct vcpu_svm *svm, |
1031 | struct kvm_run *kvm_run) | |
6aa8b732 | 1032 | { |
e756fc62 | 1033 | inject_ud(&svm->vcpu); |
6aa8b732 AK |
1034 | return 1; |
1035 | } | |
1036 | ||
e756fc62 RR |
1037 | static int task_switch_interception(struct vcpu_svm *svm, |
1038 | struct kvm_run *kvm_run) | |
6aa8b732 | 1039 | { |
f0242478 | 1040 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1041 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1042 | return 0; | |
1043 | } | |
1044 | ||
e756fc62 | 1045 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1046 | { |
a2fa3e9f | 1047 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1048 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1049 | return 1; |
6aa8b732 AK |
1050 | } |
1051 | ||
e756fc62 RR |
1052 | static int emulate_on_interception(struct vcpu_svm *svm, |
1053 | struct kvm_run *kvm_run) | |
6aa8b732 | 1054 | { |
e756fc62 | 1055 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE) |
f0242478 | 1056 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1057 | return 1; |
1058 | } | |
1059 | ||
1060 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1061 | { | |
a2fa3e9f GH |
1062 | struct vcpu_svm *svm = to_svm(vcpu); |
1063 | ||
6aa8b732 | 1064 | switch (ecx) { |
6aa8b732 AK |
1065 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1066 | u64 tsc; | |
1067 | ||
1068 | rdtscll(tsc); | |
a2fa3e9f | 1069 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1070 | break; |
1071 | } | |
0e859cac | 1072 | case MSR_K6_STAR: |
a2fa3e9f | 1073 | *data = svm->vmcb->save.star; |
6aa8b732 | 1074 | break; |
0e859cac | 1075 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1076 | case MSR_LSTAR: |
a2fa3e9f | 1077 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1078 | break; |
1079 | case MSR_CSTAR: | |
a2fa3e9f | 1080 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1081 | break; |
1082 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1083 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1084 | break; |
1085 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1086 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1087 | break; |
1088 | #endif | |
1089 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1090 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1091 | break; |
1092 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1093 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1094 | break; |
1095 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1096 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1097 | break; |
1098 | default: | |
3bab1f5d | 1099 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1100 | } |
1101 | return 0; | |
1102 | } | |
1103 | ||
e756fc62 | 1104 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1105 | { |
e756fc62 | 1106 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1107 | u64 data; |
1108 | ||
e756fc62 RR |
1109 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
1110 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1111 | else { |
a2fa3e9f | 1112 | svm->vmcb->save.rax = data & 0xffffffff; |
e756fc62 | 1113 | svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1114 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1115 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1116 | } |
1117 | return 1; | |
1118 | } | |
1119 | ||
1120 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1121 | { | |
a2fa3e9f GH |
1122 | struct vcpu_svm *svm = to_svm(vcpu); |
1123 | ||
6aa8b732 | 1124 | switch (ecx) { |
6aa8b732 AK |
1125 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1126 | u64 tsc; | |
1127 | ||
1128 | rdtscll(tsc); | |
a2fa3e9f | 1129 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1130 | break; |
1131 | } | |
0e859cac | 1132 | case MSR_K6_STAR: |
a2fa3e9f | 1133 | svm->vmcb->save.star = data; |
6aa8b732 | 1134 | break; |
49b14f24 | 1135 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1136 | case MSR_LSTAR: |
a2fa3e9f | 1137 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1138 | break; |
1139 | case MSR_CSTAR: | |
a2fa3e9f | 1140 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1141 | break; |
1142 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1143 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1144 | break; |
1145 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1146 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1147 | break; |
1148 | #endif | |
1149 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1150 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1151 | break; |
1152 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1153 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1154 | break; |
1155 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1156 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 AK |
1157 | break; |
1158 | default: | |
3bab1f5d | 1159 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1160 | } |
1161 | return 0; | |
1162 | } | |
1163 | ||
e756fc62 | 1164 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1165 | { |
e756fc62 | 1166 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1167 | u64 data = (svm->vmcb->save.rax & -1u) |
e756fc62 | 1168 | | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1169 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 RR |
1170 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
1171 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1172 | else |
e756fc62 | 1173 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1174 | return 1; |
1175 | } | |
1176 | ||
e756fc62 | 1177 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1178 | { |
e756fc62 RR |
1179 | if (svm->vmcb->control.exit_info_1) |
1180 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1181 | else |
e756fc62 | 1182 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1183 | } |
1184 | ||
e756fc62 | 1185 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1186 | struct kvm_run *kvm_run) |
1187 | { | |
1188 | /* | |
1189 | * If the user space waits to inject interrupts, exit as soon as | |
1190 | * possible | |
1191 | */ | |
1192 | if (kvm_run->request_interrupt_window && | |
e756fc62 RR |
1193 | !svm->vcpu.irq_summary) { |
1194 | ++svm->vcpu.stat.irq_window_exits; | |
c1150d8c DL |
1195 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1196 | return 0; | |
1197 | } | |
1198 | ||
1199 | return 1; | |
1200 | } | |
1201 | ||
e756fc62 | 1202 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1203 | struct kvm_run *kvm_run) = { |
1204 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1205 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1206 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
1207 | /* for now: */ | |
1208 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1209 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1210 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1211 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
1212 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1213 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1214 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1215 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1216 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1217 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1218 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1219 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1220 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
1221 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, | |
7807fa6c | 1222 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1223 | [SVM_EXIT_INTR] = nop_on_interception, |
1224 | [SVM_EXIT_NMI] = nop_on_interception, | |
1225 | [SVM_EXIT_SMI] = nop_on_interception, | |
1226 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1227 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1228 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1229 | [SVM_EXIT_CPUID] = cpuid_interception, | |
1230 | [SVM_EXIT_HLT] = halt_interception, | |
1231 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1232 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1233 | [SVM_EXIT_IOIO] = io_interception, | |
1234 | [SVM_EXIT_MSR] = msr_interception, | |
1235 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1236 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1237 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1238 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1239 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1240 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1241 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1242 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1243 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
916ce236 JR |
1244 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1245 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1246 | }; |
1247 | ||
1248 | ||
e756fc62 | 1249 | static int handle_exit(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1250 | { |
a2fa3e9f | 1251 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1252 | |
a2fa3e9f | 1253 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1254 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1255 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1256 | "exit_code 0x%x\n", | |
a2fa3e9f | 1257 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1258 | exit_code); |
1259 | ||
9d8f549d | 1260 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
6aa8b732 AK |
1261 | || svm_exit_handlers[exit_code] == 0) { |
1262 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
364b625b | 1263 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1264 | return 0; |
1265 | } | |
1266 | ||
e756fc62 | 1267 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1268 | } |
1269 | ||
1270 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1271 | { | |
1272 | int cpu = raw_smp_processor_id(); | |
1273 | ||
1274 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1275 | svm_data->tss_desc->type = 9; //available 32/64-bit TSS | |
1276 | load_TR_desc(); | |
1277 | } | |
1278 | ||
e756fc62 | 1279 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1280 | { |
1281 | int cpu = raw_smp_processor_id(); | |
1282 | ||
1283 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1284 | ||
a2fa3e9f | 1285 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1286 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1287 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1288 | new_asid(svm, svm_data); |
6aa8b732 AK |
1289 | } |
1290 | ||
1291 | ||
0e5017d4 | 1292 | static inline void inject_irq(struct vcpu_svm *svm) |
6aa8b732 AK |
1293 | { |
1294 | struct vmcb_control_area *control; | |
1295 | ||
e756fc62 RR |
1296 | control = &svm->vmcb->control; |
1297 | control->int_vector = pop_irq(&svm->vcpu); | |
6aa8b732 AK |
1298 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1299 | control->int_ctl |= V_IRQ_MASK | | |
1300 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1301 | } | |
1302 | ||
0e5017d4 | 1303 | static void reput_irq(struct vcpu_svm *svm) |
6aa8b732 | 1304 | { |
e756fc62 | 1305 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 AK |
1306 | |
1307 | if (control->int_ctl & V_IRQ_MASK) { | |
1308 | control->int_ctl &= ~V_IRQ_MASK; | |
e756fc62 | 1309 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1310 | } |
c1150d8c | 1311 | |
e756fc62 | 1312 | svm->vcpu.interrupt_window_open = |
c1150d8c DL |
1313 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1314 | } | |
1315 | ||
e756fc62 | 1316 | static void do_interrupt_requests(struct vcpu_svm *svm, |
c1150d8c DL |
1317 | struct kvm_run *kvm_run) |
1318 | { | |
a2fa3e9f | 1319 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1320 | |
e756fc62 | 1321 | svm->vcpu.interrupt_window_open = |
c1150d8c | 1322 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1323 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1324 | |
e756fc62 | 1325 | if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary) |
c1150d8c DL |
1326 | /* |
1327 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1328 | */ | |
0e5017d4 | 1329 | inject_irq(svm); |
c1150d8c DL |
1330 | |
1331 | /* | |
1332 | * Interrupts blocked. Wait for unblock. | |
1333 | */ | |
e756fc62 RR |
1334 | if (!svm->vcpu.interrupt_window_open && |
1335 | (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) { | |
c1150d8c DL |
1336 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
1337 | } else | |
1338 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1339 | } | |
1340 | ||
e756fc62 | 1341 | static void post_kvm_run_save(struct vcpu_svm *svm, |
c1150d8c DL |
1342 | struct kvm_run *kvm_run) |
1343 | { | |
e756fc62 RR |
1344 | kvm_run->ready_for_interrupt_injection |
1345 | = (svm->vcpu.interrupt_window_open && | |
1346 | svm->vcpu.irq_summary == 0); | |
a2fa3e9f | 1347 | kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0; |
e756fc62 RR |
1348 | kvm_run->cr8 = svm->vcpu.cr8; |
1349 | kvm_run->apic_base = svm->vcpu.apic_base; | |
c1150d8c DL |
1350 | } |
1351 | ||
1352 | /* | |
1353 | * Check if userspace requested an interrupt window, and that the | |
1354 | * interrupt window is open. | |
1355 | * | |
1356 | * No need to exit to userspace if we already have an interrupt queued. | |
1357 | */ | |
e756fc62 | 1358 | static int dm_request_for_irq_injection(struct vcpu_svm *svm, |
c1150d8c DL |
1359 | struct kvm_run *kvm_run) |
1360 | { | |
e756fc62 | 1361 | return (!svm->vcpu.irq_summary && |
c1150d8c | 1362 | kvm_run->request_interrupt_window && |
e756fc62 RR |
1363 | svm->vcpu.interrupt_window_open && |
1364 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); | |
6aa8b732 AK |
1365 | } |
1366 | ||
1367 | static void save_db_regs(unsigned long *db_regs) | |
1368 | { | |
5aff458e AK |
1369 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1370 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1371 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1372 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1373 | } |
1374 | ||
1375 | static void load_db_regs(unsigned long *db_regs) | |
1376 | { | |
5aff458e AK |
1377 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1378 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1379 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1380 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1381 | } |
1382 | ||
d9e368d6 AK |
1383 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1384 | { | |
1385 | force_new_asid(vcpu); | |
1386 | } | |
1387 | ||
6aa8b732 AK |
1388 | static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1389 | { | |
a2fa3e9f | 1390 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1391 | u16 fs_selector; |
1392 | u16 gs_selector; | |
1393 | u16 ldt_selector; | |
e2dec939 | 1394 | int r; |
6aa8b732 AK |
1395 | |
1396 | again: | |
17c3ba9d AK |
1397 | r = kvm_mmu_reload(vcpu); |
1398 | if (unlikely(r)) | |
1399 | return r; | |
1400 | ||
cccf748b | 1401 | if (!vcpu->mmio_read_completed) |
e756fc62 | 1402 | do_interrupt_requests(svm, kvm_run); |
6aa8b732 AK |
1403 | |
1404 | clgi(); | |
1405 | ||
d9e368d6 AK |
1406 | vcpu->guest_mode = 1; |
1407 | if (vcpu->requests) | |
1408 | if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests)) | |
1409 | svm_flush_tlb(vcpu); | |
1410 | ||
e756fc62 | 1411 | pre_svm_run(svm); |
6aa8b732 AK |
1412 | |
1413 | save_host_msrs(vcpu); | |
1414 | fs_selector = read_fs(); | |
1415 | gs_selector = read_gs(); | |
1416 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1417 | svm->host_cr2 = kvm_read_cr2(); |
1418 | svm->host_dr6 = read_dr6(); | |
1419 | svm->host_dr7 = read_dr7(); | |
1420 | svm->vmcb->save.cr2 = vcpu->cr2; | |
6aa8b732 | 1421 | |
a2fa3e9f | 1422 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1423 | write_dr7(0); |
a2fa3e9f GH |
1424 | save_db_regs(svm->host_db_regs); |
1425 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1426 | } |
36241b8c | 1427 | |
7807fa6c | 1428 | if (vcpu->fpu_active) { |
b114b080 RR |
1429 | fx_save(&vcpu->host_fx_image); |
1430 | fx_restore(&vcpu->guest_fx_image); | |
7807fa6c | 1431 | } |
36241b8c | 1432 | |
6aa8b732 | 1433 | asm volatile ( |
05b3e0c2 | 1434 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1435 | "push %%rbx; push %%rcx; push %%rdx;" |
1436 | "push %%rsi; push %%rdi; push %%rbp;" | |
1437 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
1438 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
1439 | #else | |
1440 | "push %%ebx; push %%ecx; push %%edx;" | |
1441 | "push %%esi; push %%edi; push %%ebp;" | |
1442 | #endif | |
1443 | ||
05b3e0c2 | 1444 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1445 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1446 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1447 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1448 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1449 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1450 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1451 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1452 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1453 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1454 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1455 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1456 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1457 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1458 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1459 | #else |
fb3f0f51 RR |
1460 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1461 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1462 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1463 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1464 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1465 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1466 | #endif |
1467 | ||
05b3e0c2 | 1468 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1469 | /* Enter guest mode */ |
1470 | "push %%rax \n\t" | |
fb3f0f51 | 1471 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1472 | SVM_VMLOAD "\n\t" |
1473 | SVM_VMRUN "\n\t" | |
1474 | SVM_VMSAVE "\n\t" | |
1475 | "pop %%rax \n\t" | |
1476 | #else | |
1477 | /* Enter guest mode */ | |
1478 | "push %%eax \n\t" | |
fb3f0f51 | 1479 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1480 | SVM_VMLOAD "\n\t" |
1481 | SVM_VMRUN "\n\t" | |
1482 | SVM_VMSAVE "\n\t" | |
1483 | "pop %%eax \n\t" | |
1484 | #endif | |
1485 | ||
1486 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1487 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1488 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1489 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1490 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1491 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1492 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1493 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1494 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1495 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1496 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1497 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1498 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1499 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1500 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1501 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 AK |
1502 | |
1503 | "pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
1504 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
1505 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
1506 | "pop %%rdx; pop %%rcx; pop %%rbx; \n\t" | |
1507 | #else | |
fb3f0f51 RR |
1508 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1509 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1510 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1511 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1512 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1513 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 AK |
1514 | |
1515 | "pop %%ebp; pop %%edi; pop %%esi;" | |
1516 | "pop %%edx; pop %%ecx; pop %%ebx; \n\t" | |
1517 | #endif | |
1518 | : | |
fb3f0f51 | 1519 | : [svm]"a"(svm), |
6aa8b732 | 1520 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
fb3f0f51 RR |
1521 | [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])), |
1522 | [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])), | |
1523 | [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])), | |
1524 | [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])), | |
1525 | [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])), | |
1526 | [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1527 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1528 | ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])), |
1529 | [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])), | |
1530 | [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])), | |
1531 | [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])), | |
1532 | [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])), | |
1533 | [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])), | |
1534 | [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])), | |
1535 | [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15])) | |
6aa8b732 AK |
1536 | #endif |
1537 | : "cc", "memory" ); | |
1538 | ||
d9e368d6 AK |
1539 | vcpu->guest_mode = 0; |
1540 | ||
7807fa6c | 1541 | if (vcpu->fpu_active) { |
b114b080 RR |
1542 | fx_save(&vcpu->guest_fx_image); |
1543 | fx_restore(&vcpu->host_fx_image); | |
7807fa6c | 1544 | } |
36241b8c | 1545 | |
a2fa3e9f GH |
1546 | if ((svm->vmcb->save.dr7 & 0xff)) |
1547 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1548 | |
a2fa3e9f | 1549 | vcpu->cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1550 | |
a2fa3e9f GH |
1551 | write_dr6(svm->host_dr6); |
1552 | write_dr7(svm->host_dr7); | |
1553 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1554 | |
1555 | load_fs(fs_selector); | |
1556 | load_gs(gs_selector); | |
1557 | load_ldt(ldt_selector); | |
1558 | load_host_msrs(vcpu); | |
1559 | ||
1560 | reload_tss(vcpu); | |
1561 | ||
07031e14 IM |
1562 | /* |
1563 | * Profile KVM exit RIPs: | |
1564 | */ | |
1565 | if (unlikely(prof_on == KVM_PROFILING)) | |
1566 | profile_hit(KVM_PROFILING, | |
a2fa3e9f | 1567 | (void *)(unsigned long)svm->vmcb->save.rip); |
07031e14 | 1568 | |
6aa8b732 AK |
1569 | stgi(); |
1570 | ||
0e5017d4 | 1571 | reput_irq(svm); |
6aa8b732 | 1572 | |
a2fa3e9f | 1573 | svm->next_rip = 0; |
6aa8b732 | 1574 | |
a2fa3e9f | 1575 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
8eb7d334 AK |
1576 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
1577 | kvm_run->fail_entry.hardware_entry_failure_reason | |
a2fa3e9f | 1578 | = svm->vmcb->control.exit_code; |
e756fc62 | 1579 | post_kvm_run_save(svm, kvm_run); |
6aa8b732 AK |
1580 | return 0; |
1581 | } | |
1582 | ||
e756fc62 | 1583 | r = handle_exit(svm, kvm_run); |
e2dec939 | 1584 | if (r > 0) { |
6aa8b732 | 1585 | if (signal_pending(current)) { |
1165f5fe | 1586 | ++vcpu->stat.signal_exits; |
e756fc62 | 1587 | post_kvm_run_save(svm, kvm_run); |
1b19f3e6 | 1588 | kvm_run->exit_reason = KVM_EXIT_INTR; |
c1150d8c DL |
1589 | return -EINTR; |
1590 | } | |
1591 | ||
e756fc62 | 1592 | if (dm_request_for_irq_injection(svm, kvm_run)) { |
1165f5fe | 1593 | ++vcpu->stat.request_irq_exits; |
e756fc62 | 1594 | post_kvm_run_save(svm, kvm_run); |
1b19f3e6 | 1595 | kvm_run->exit_reason = KVM_EXIT_INTR; |
6aa8b732 AK |
1596 | return -EINTR; |
1597 | } | |
1598 | kvm_resched(vcpu); | |
1599 | goto again; | |
1600 | } | |
e756fc62 | 1601 | post_kvm_run_save(svm, kvm_run); |
e2dec939 | 1602 | return r; |
6aa8b732 AK |
1603 | } |
1604 | ||
6aa8b732 AK |
1605 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1606 | { | |
a2fa3e9f GH |
1607 | struct vcpu_svm *svm = to_svm(vcpu); |
1608 | ||
1609 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1610 | force_new_asid(vcpu); |
7807fa6c AL |
1611 | |
1612 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1613 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1614 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1615 | vcpu->fpu_active = 0; |
1616 | } | |
6aa8b732 AK |
1617 | } |
1618 | ||
1619 | static void svm_inject_page_fault(struct kvm_vcpu *vcpu, | |
1620 | unsigned long addr, | |
1621 | uint32_t err_code) | |
1622 | { | |
a2fa3e9f GH |
1623 | struct vcpu_svm *svm = to_svm(vcpu); |
1624 | uint32_t exit_int_info = svm->vmcb->control.exit_int_info; | |
6aa8b732 | 1625 | |
1165f5fe | 1626 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
1627 | |
1628 | if (is_page_fault(exit_int_info)) { | |
1629 | ||
a2fa3e9f GH |
1630 | svm->vmcb->control.event_inj_err = 0; |
1631 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1632 | SVM_EVTINJ_VALID_ERR | | |
1633 | SVM_EVTINJ_TYPE_EXEPT | | |
1634 | DF_VECTOR; | |
6aa8b732 AK |
1635 | return; |
1636 | } | |
1637 | vcpu->cr2 = addr; | |
a2fa3e9f GH |
1638 | svm->vmcb->save.cr2 = addr; |
1639 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1640 | SVM_EVTINJ_VALID_ERR | | |
1641 | SVM_EVTINJ_TYPE_EXEPT | | |
1642 | PF_VECTOR; | |
1643 | svm->vmcb->control.event_inj_err = err_code; | |
6aa8b732 AK |
1644 | } |
1645 | ||
1646 | ||
1647 | static int is_disabled(void) | |
1648 | { | |
6031a61c JR |
1649 | u64 vm_cr; |
1650 | ||
1651 | rdmsrl(MSR_VM_CR, vm_cr); | |
1652 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1653 | return 1; | |
1654 | ||
6aa8b732 AK |
1655 | return 0; |
1656 | } | |
1657 | ||
102d8325 IM |
1658 | static void |
1659 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1660 | { | |
1661 | /* | |
1662 | * Patch in the VMMCALL instruction: | |
1663 | */ | |
1664 | hypercall[0] = 0x0f; | |
1665 | hypercall[1] = 0x01; | |
1666 | hypercall[2] = 0xd9; | |
1667 | hypercall[3] = 0xc3; | |
1668 | } | |
1669 | ||
002c7f7c YS |
1670 | static void svm_check_processor_compat(void *rtn) |
1671 | { | |
1672 | *(int *)rtn = 0; | |
1673 | } | |
1674 | ||
6aa8b732 AK |
1675 | static struct kvm_arch_ops svm_arch_ops = { |
1676 | .cpu_has_kvm_support = has_svm, | |
1677 | .disabled_by_bios = is_disabled, | |
1678 | .hardware_setup = svm_hardware_setup, | |
1679 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1680 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1681 | .hardware_enable = svm_hardware_enable, |
1682 | .hardware_disable = svm_hardware_disable, | |
1683 | ||
1684 | .vcpu_create = svm_create_vcpu, | |
1685 | .vcpu_free = svm_free_vcpu, | |
1686 | ||
1687 | .vcpu_load = svm_vcpu_load, | |
1688 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1689 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1690 | |
1691 | .set_guest_debug = svm_guest_debug, | |
1692 | .get_msr = svm_get_msr, | |
1693 | .set_msr = svm_set_msr, | |
1694 | .get_segment_base = svm_get_segment_base, | |
1695 | .get_segment = svm_get_segment, | |
1696 | .set_segment = svm_set_segment, | |
6aa8b732 | 1697 | .get_cs_db_l_bits = svm_get_cs_db_l_bits, |
25c4c276 | 1698 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1699 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1700 | .set_cr3 = svm_set_cr3, |
1701 | .set_cr4 = svm_set_cr4, | |
1702 | .set_efer = svm_set_efer, | |
1703 | .get_idt = svm_get_idt, | |
1704 | .set_idt = svm_set_idt, | |
1705 | .get_gdt = svm_get_gdt, | |
1706 | .set_gdt = svm_set_gdt, | |
1707 | .get_dr = svm_get_dr, | |
1708 | .set_dr = svm_set_dr, | |
1709 | .cache_regs = svm_cache_regs, | |
1710 | .decache_regs = svm_decache_regs, | |
1711 | .get_rflags = svm_get_rflags, | |
1712 | .set_rflags = svm_set_rflags, | |
1713 | ||
1714 | .invlpg = svm_invlpg, | |
1715 | .tlb_flush = svm_flush_tlb, | |
1716 | .inject_page_fault = svm_inject_page_fault, | |
1717 | ||
1718 | .inject_gp = svm_inject_gp, | |
1719 | ||
1720 | .run = svm_vcpu_run, | |
1721 | .skip_emulated_instruction = skip_emulated_instruction, | |
102d8325 | 1722 | .patch_hypercall = svm_patch_hypercall, |
6aa8b732 AK |
1723 | }; |
1724 | ||
1725 | static int __init svm_init(void) | |
1726 | { | |
c16f862d RR |
1727 | return kvm_init_arch(&svm_arch_ops, sizeof(struct vcpu_svm), |
1728 | THIS_MODULE); | |
6aa8b732 AK |
1729 | } |
1730 | ||
1731 | static void __exit svm_exit(void) | |
1732 | { | |
1733 | kvm_exit_arch(); | |
1734 | } | |
1735 | ||
1736 | module_init(svm_init) | |
1737 | module_exit(svm_exit) |