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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
16 | ||
e495606d AK |
17 | #include "kvm_svm.h" |
18 | #include "x86_emulate.h" | |
19 | ||
6aa8b732 | 20 | #include <linux/module.h> |
9d8f549d | 21 | #include <linux/kernel.h> |
6aa8b732 AK |
22 | #include <linux/vmalloc.h> |
23 | #include <linux/highmem.h> | |
07031e14 | 24 | #include <linux/profile.h> |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | |
e495606d | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | MODULE_AUTHOR("Qumranet"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | #define IOPM_ALLOC_ORDER 2 | |
33 | #define MSRPM_ALLOC_ORDER 1 | |
34 | ||
35 | #define DB_VECTOR 1 | |
36 | #define UD_VECTOR 6 | |
37 | #define GP_VECTOR 13 | |
38 | ||
39 | #define DR7_GD_MASK (1 << 13) | |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
45 | #define KVM_EFER_LMA (1 << 10) | |
46 | #define KVM_EFER_LME (1 << 8) | |
47 | ||
80b7706e JR |
48 | #define SVM_FEATURE_NPT (1 << 0) |
49 | #define SVM_FEATURE_LBRV (1 << 1) | |
50 | #define SVM_DEATURE_SVML (1 << 2) | |
51 | ||
a2fa3e9f GH |
52 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
53 | { | |
fb3f0f51 | 54 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
55 | } |
56 | ||
6aa8b732 AK |
57 | unsigned long iopm_base; |
58 | unsigned long msrpm_base; | |
59 | ||
60 | struct kvm_ldttss_desc { | |
61 | u16 limit0; | |
62 | u16 base0; | |
63 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
64 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
65 | u32 base3; | |
66 | u32 zero1; | |
67 | } __attribute__((packed)); | |
68 | ||
69 | struct svm_cpu_data { | |
70 | int cpu; | |
71 | ||
5008fdf5 AK |
72 | u64 asid_generation; |
73 | u32 max_asid; | |
74 | u32 next_asid; | |
6aa8b732 AK |
75 | struct kvm_ldttss_desc *tss_desc; |
76 | ||
77 | struct page *save_area; | |
78 | }; | |
79 | ||
80 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 81 | static uint32_t svm_features; |
6aa8b732 AK |
82 | |
83 | struct svm_init_data { | |
84 | int cpu; | |
85 | int r; | |
86 | }; | |
87 | ||
88 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
89 | ||
9d8f549d | 90 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
91 | #define MSRS_RANGE_SIZE 2048 |
92 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
93 | ||
94 | #define MAX_INST_SIZE 15 | |
95 | ||
80b7706e JR |
96 | static inline u32 svm_has(u32 feat) |
97 | { | |
98 | return svm_features & feat; | |
99 | } | |
100 | ||
e756fc62 | 101 | static unsigned get_addr_size(struct vcpu_svm *svm) |
6aa8b732 | 102 | { |
e756fc62 | 103 | struct vmcb_save_area *sa = &svm->vmcb->save; |
6aa8b732 AK |
104 | u16 cs_attrib; |
105 | ||
707d92fa | 106 | if (!(sa->cr0 & X86_CR0_PE) || (sa->rflags & X86_EFLAGS_VM)) |
6aa8b732 AK |
107 | return 2; |
108 | ||
109 | cs_attrib = sa->cs.attrib; | |
110 | ||
111 | return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 : | |
112 | (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2; | |
113 | } | |
114 | ||
115 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) | |
116 | { | |
117 | int word_index = __ffs(vcpu->irq_summary); | |
118 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
119 | int irq = word_index * BITS_PER_LONG + bit_index; | |
120 | ||
121 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
122 | if (!vcpu->irq_pending[word_index]) | |
123 | clear_bit(word_index, &vcpu->irq_summary); | |
124 | return irq; | |
125 | } | |
126 | ||
127 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
128 | { | |
129 | set_bit(irq, vcpu->irq_pending); | |
130 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
131 | } | |
132 | ||
133 | static inline void clgi(void) | |
134 | { | |
135 | asm volatile (SVM_CLGI); | |
136 | } | |
137 | ||
138 | static inline void stgi(void) | |
139 | { | |
140 | asm volatile (SVM_STGI); | |
141 | } | |
142 | ||
143 | static inline void invlpga(unsigned long addr, u32 asid) | |
144 | { | |
145 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
146 | } | |
147 | ||
148 | static inline unsigned long kvm_read_cr2(void) | |
149 | { | |
150 | unsigned long cr2; | |
151 | ||
152 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
153 | return cr2; | |
154 | } | |
155 | ||
156 | static inline void kvm_write_cr2(unsigned long val) | |
157 | { | |
158 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
159 | } | |
160 | ||
161 | static inline unsigned long read_dr6(void) | |
162 | { | |
163 | unsigned long dr6; | |
164 | ||
165 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
166 | return dr6; | |
167 | } | |
168 | ||
169 | static inline void write_dr6(unsigned long val) | |
170 | { | |
171 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
172 | } | |
173 | ||
174 | static inline unsigned long read_dr7(void) | |
175 | { | |
176 | unsigned long dr7; | |
177 | ||
178 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
179 | return dr7; | |
180 | } | |
181 | ||
182 | static inline void write_dr7(unsigned long val) | |
183 | { | |
184 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
185 | } | |
186 | ||
6aa8b732 AK |
187 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
188 | { | |
a2fa3e9f | 189 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
190 | } |
191 | ||
192 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
193 | { | |
194 | force_new_asid(vcpu); | |
195 | } | |
196 | ||
197 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
198 | { | |
199 | if (!(efer & KVM_EFER_LMA)) | |
200 | efer &= ~KVM_EFER_LME; | |
201 | ||
a2fa3e9f | 202 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
6aa8b732 AK |
203 | vcpu->shadow_efer = efer; |
204 | } | |
205 | ||
206 | static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code) | |
207 | { | |
a2fa3e9f GH |
208 | struct vcpu_svm *svm = to_svm(vcpu); |
209 | ||
210 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
6aa8b732 AK |
211 | SVM_EVTINJ_VALID_ERR | |
212 | SVM_EVTINJ_TYPE_EXEPT | | |
213 | GP_VECTOR; | |
a2fa3e9f | 214 | svm->vmcb->control.event_inj_err = error_code; |
6aa8b732 AK |
215 | } |
216 | ||
217 | static void inject_ud(struct kvm_vcpu *vcpu) | |
218 | { | |
a2fa3e9f | 219 | to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID | |
6aa8b732 AK |
220 | SVM_EVTINJ_TYPE_EXEPT | |
221 | UD_VECTOR; | |
222 | } | |
223 | ||
6aa8b732 AK |
224 | static int is_page_fault(uint32_t info) |
225 | { | |
226 | info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
227 | return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT); | |
228 | } | |
229 | ||
230 | static int is_external_interrupt(u32 info) | |
231 | { | |
232 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
233 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
234 | } | |
235 | ||
236 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
237 | { | |
a2fa3e9f GH |
238 | struct vcpu_svm *svm = to_svm(vcpu); |
239 | ||
240 | if (!svm->next_rip) { | |
6aa8b732 AK |
241 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
242 | return; | |
243 | } | |
3077c451 | 244 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) { |
6aa8b732 AK |
245 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
246 | __FUNCTION__, | |
a2fa3e9f GH |
247 | svm->vmcb->save.rip, |
248 | svm->next_rip); | |
6aa8b732 AK |
249 | } |
250 | ||
a2fa3e9f GH |
251 | vcpu->rip = svm->vmcb->save.rip = svm->next_rip; |
252 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
253 | |
254 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
255 | } |
256 | ||
257 | static int has_svm(void) | |
258 | { | |
259 | uint32_t eax, ebx, ecx, edx; | |
260 | ||
1e885461 | 261 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
262 | printk(KERN_INFO "has_svm: not amd\n"); |
263 | return 0; | |
264 | } | |
265 | ||
266 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
267 | if (eax < SVM_CPUID_FUNC) { | |
268 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
269 | return 0; | |
270 | } | |
271 | ||
272 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
273 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
274 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
275 | return 0; | |
276 | } | |
277 | return 1; | |
278 | } | |
279 | ||
280 | static void svm_hardware_disable(void *garbage) | |
281 | { | |
282 | struct svm_cpu_data *svm_data | |
283 | = per_cpu(svm_data, raw_smp_processor_id()); | |
284 | ||
285 | if (svm_data) { | |
286 | uint64_t efer; | |
287 | ||
288 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
289 | rdmsrl(MSR_EFER, efer); | |
290 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 291 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
292 | __free_page(svm_data->save_area); |
293 | kfree(svm_data); | |
294 | } | |
295 | } | |
296 | ||
297 | static void svm_hardware_enable(void *garbage) | |
298 | { | |
299 | ||
300 | struct svm_cpu_data *svm_data; | |
301 | uint64_t efer; | |
05b3e0c2 | 302 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
303 | struct desc_ptr gdt_descr; |
304 | #else | |
305 | struct Xgt_desc_struct gdt_descr; | |
306 | #endif | |
307 | struct desc_struct *gdt; | |
308 | int me = raw_smp_processor_id(); | |
309 | ||
310 | if (!has_svm()) { | |
311 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
312 | return; | |
313 | } | |
314 | svm_data = per_cpu(svm_data, me); | |
315 | ||
316 | if (!svm_data) { | |
317 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
318 | me); | |
319 | return; | |
320 | } | |
321 | ||
322 | svm_data->asid_generation = 1; | |
323 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
324 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 325 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 AK |
326 | |
327 | asm volatile ( "sgdt %0" : "=m"(gdt_descr) ); | |
328 | gdt = (struct desc_struct *)gdt_descr.address; | |
329 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
330 | ||
331 | rdmsrl(MSR_EFER, efer); | |
332 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
333 | ||
334 | wrmsrl(MSR_VM_HSAVE_PA, | |
335 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
336 | } | |
337 | ||
338 | static int svm_cpu_init(int cpu) | |
339 | { | |
340 | struct svm_cpu_data *svm_data; | |
341 | int r; | |
342 | ||
343 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
344 | if (!svm_data) | |
345 | return -ENOMEM; | |
346 | svm_data->cpu = cpu; | |
347 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
348 | r = -ENOMEM; | |
349 | if (!svm_data->save_area) | |
350 | goto err_1; | |
351 | ||
352 | per_cpu(svm_data, cpu) = svm_data; | |
353 | ||
354 | return 0; | |
355 | ||
356 | err_1: | |
357 | kfree(svm_data); | |
358 | return r; | |
359 | ||
360 | } | |
361 | ||
362 | static int set_msr_interception(u32 *msrpm, unsigned msr, | |
363 | int read, int write) | |
364 | { | |
365 | int i; | |
366 | ||
367 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
368 | if (msr >= msrpm_ranges[i] && | |
369 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
370 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
371 | msrpm_ranges[i]) * 2; | |
372 | ||
373 | u32 *base = msrpm + (msr_offset / 32); | |
374 | u32 msr_shift = msr_offset % 32; | |
375 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
376 | *base = (*base & ~(0x3 << msr_shift)) | | |
377 | (mask << msr_shift); | |
378 | return 1; | |
379 | } | |
380 | } | |
381 | printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr); | |
382 | return 0; | |
383 | } | |
384 | ||
385 | static __init int svm_hardware_setup(void) | |
386 | { | |
387 | int cpu; | |
388 | struct page *iopm_pages; | |
389 | struct page *msrpm_pages; | |
c8681339 | 390 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
391 | int r; |
392 | ||
873a7c42 | 393 | kvm_emulator_want_group7_invlpg(); |
6aa8b732 AK |
394 | |
395 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); | |
396 | ||
397 | if (!iopm_pages) | |
398 | return -ENOMEM; | |
c8681339 AL |
399 | |
400 | iopm_va = page_address(iopm_pages); | |
401 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
402 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
403 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
404 | ||
405 | ||
406 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
407 | ||
408 | r = -ENOMEM; | |
409 | if (!msrpm_pages) | |
410 | goto err_1; | |
411 | ||
412 | msrpm_va = page_address(msrpm_pages); | |
413 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
414 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
415 | ||
05b3e0c2 | 416 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
417 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
418 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
419 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
420 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
421 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
422 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
423 | #endif | |
0e859cac | 424 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
425 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
426 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
427 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
428 | ||
429 | for_each_online_cpu(cpu) { | |
430 | r = svm_cpu_init(cpu); | |
431 | if (r) | |
432 | goto err_2; | |
433 | } | |
434 | return 0; | |
435 | ||
436 | err_2: | |
437 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
438 | msrpm_base = 0; | |
439 | err_1: | |
440 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
441 | iopm_base = 0; | |
442 | return r; | |
443 | } | |
444 | ||
445 | static __exit void svm_hardware_unsetup(void) | |
446 | { | |
447 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
448 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
449 | iopm_base = msrpm_base = 0; | |
450 | } | |
451 | ||
452 | static void init_seg(struct vmcb_seg *seg) | |
453 | { | |
454 | seg->selector = 0; | |
455 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
456 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
457 | seg->limit = 0xffff; | |
458 | seg->base = 0; | |
459 | } | |
460 | ||
461 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
462 | { | |
463 | seg->selector = 0; | |
464 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
465 | seg->limit = 0xffff; | |
466 | seg->base = 0; | |
467 | } | |
468 | ||
6aa8b732 AK |
469 | static void init_vmcb(struct vmcb *vmcb) |
470 | { | |
471 | struct vmcb_control_area *control = &vmcb->control; | |
472 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
473 | |
474 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
475 | INTERCEPT_CR3_MASK | | |
476 | INTERCEPT_CR4_MASK; | |
477 | ||
478 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
479 | INTERCEPT_CR3_MASK | | |
480 | INTERCEPT_CR4_MASK; | |
481 | ||
482 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
483 | INTERCEPT_DR1_MASK | | |
484 | INTERCEPT_DR2_MASK | | |
485 | INTERCEPT_DR3_MASK; | |
486 | ||
487 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
488 | INTERCEPT_DR1_MASK | | |
489 | INTERCEPT_DR2_MASK | | |
490 | INTERCEPT_DR3_MASK | | |
491 | INTERCEPT_DR5_MASK | | |
492 | INTERCEPT_DR7_MASK; | |
493 | ||
494 | control->intercept_exceptions = 1 << PF_VECTOR; | |
495 | ||
496 | ||
497 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
498 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 499 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
500 | /* |
501 | * selective cr0 intercept bug? | |
502 | * 0: 0f 22 d8 mov %eax,%cr3 | |
503 | * 3: 0f 20 c0 mov %cr0,%eax | |
504 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
505 | * b: 0f 22 c0 mov %eax,%cr0 | |
506 | * set cr3 ->interception | |
507 | * get cr0 ->interception | |
508 | * set cr0 -> no interception | |
509 | */ | |
510 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
511 | (1ULL << INTERCEPT_CPUID) | | |
512 | (1ULL << INTERCEPT_HLT) | | |
6aa8b732 AK |
513 | (1ULL << INTERCEPT_INVLPGA) | |
514 | (1ULL << INTERCEPT_IOIO_PROT) | | |
515 | (1ULL << INTERCEPT_MSR_PROT) | | |
516 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 517 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
518 | (1ULL << INTERCEPT_VMRUN) | |
519 | (1ULL << INTERCEPT_VMMCALL) | | |
520 | (1ULL << INTERCEPT_VMLOAD) | | |
521 | (1ULL << INTERCEPT_VMSAVE) | | |
522 | (1ULL << INTERCEPT_STGI) | | |
523 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 JR |
524 | (1ULL << INTERCEPT_SKINIT) | |
525 | (1ULL << INTERCEPT_MONITOR) | | |
526 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
527 | |
528 | control->iopm_base_pa = iopm_base; | |
529 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 530 | control->tsc_offset = 0; |
6aa8b732 AK |
531 | control->int_ctl = V_INTR_MASKING_MASK; |
532 | ||
533 | init_seg(&save->es); | |
534 | init_seg(&save->ss); | |
535 | init_seg(&save->ds); | |
536 | init_seg(&save->fs); | |
537 | init_seg(&save->gs); | |
538 | ||
539 | save->cs.selector = 0xf000; | |
540 | /* Executable/Readable Code Segment */ | |
541 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
542 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
543 | save->cs.limit = 0xffff; | |
d92899a0 AK |
544 | /* |
545 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
546 | * be consistent with it. | |
547 | * | |
548 | * Replace when we have real mode working for vmx. | |
549 | */ | |
550 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
551 | |
552 | save->gdtr.limit = 0xffff; | |
553 | save->idtr.limit = 0xffff; | |
554 | ||
555 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
556 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
557 | ||
558 | save->efer = MSR_EFER_SVME_MASK; | |
559 | ||
560 | save->dr6 = 0xffff0ff0; | |
561 | save->dr7 = 0x400; | |
562 | save->rflags = 2; | |
563 | save->rip = 0x0000fff0; | |
564 | ||
565 | /* | |
566 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
567 | * cache by default. the orderly way is to enable cache in bios. | |
568 | */ | |
707d92fa | 569 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 570 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
571 | /* rdx = ?? */ |
572 | } | |
573 | ||
fb3f0f51 | 574 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 575 | { |
a2fa3e9f | 576 | struct vcpu_svm *svm; |
6aa8b732 | 577 | struct page *page; |
fb3f0f51 | 578 | int err; |
6aa8b732 | 579 | |
c16f862d | 580 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
581 | if (!svm) { |
582 | err = -ENOMEM; | |
583 | goto out; | |
584 | } | |
585 | ||
586 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
587 | if (err) | |
588 | goto free_svm; | |
589 | ||
6aa8b732 | 590 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
591 | if (!page) { |
592 | err = -ENOMEM; | |
593 | goto uninit; | |
594 | } | |
6aa8b732 | 595 | |
a2fa3e9f GH |
596 | svm->vmcb = page_address(page); |
597 | clear_page(svm->vmcb); | |
598 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
599 | svm->asid_generation = 0; | |
600 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
601 | init_vmcb(svm->vmcb); | |
602 | ||
fb3f0f51 RR |
603 | fx_init(&svm->vcpu); |
604 | svm->vcpu.fpu_active = 1; | |
605 | svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
606 | if (svm->vcpu.vcpu_id == 0) | |
607 | svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 608 | |
fb3f0f51 | 609 | return &svm->vcpu; |
36241b8c | 610 | |
fb3f0f51 RR |
611 | uninit: |
612 | kvm_vcpu_uninit(&svm->vcpu); | |
613 | free_svm: | |
a2fa3e9f | 614 | kfree(svm); |
fb3f0f51 RR |
615 | out: |
616 | return ERR_PTR(err); | |
6aa8b732 AK |
617 | } |
618 | ||
619 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
620 | { | |
a2fa3e9f GH |
621 | struct vcpu_svm *svm = to_svm(vcpu); |
622 | ||
fb3f0f51 RR |
623 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
624 | kvm_vcpu_uninit(vcpu); | |
a2fa3e9f | 625 | kfree(svm); |
6aa8b732 AK |
626 | } |
627 | ||
15ad7146 | 628 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 629 | { |
a2fa3e9f | 630 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 631 | int i; |
0cc5064d | 632 | |
0cc5064d AK |
633 | if (unlikely(cpu != vcpu->cpu)) { |
634 | u64 tsc_this, delta; | |
635 | ||
636 | /* | |
637 | * Make sure that the guest sees a monotonically | |
638 | * increasing TSC. | |
639 | */ | |
640 | rdtscll(tsc_this); | |
641 | delta = vcpu->host_tsc - tsc_this; | |
a2fa3e9f | 642 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d AK |
643 | vcpu->cpu = cpu; |
644 | } | |
94dfbdb3 AL |
645 | |
646 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 647 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
648 | } |
649 | ||
650 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
651 | { | |
a2fa3e9f | 652 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
653 | int i; |
654 | ||
655 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 656 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 657 | |
0cc5064d | 658 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
659 | } |
660 | ||
774c47f1 AK |
661 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
662 | { | |
663 | } | |
664 | ||
6aa8b732 AK |
665 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
666 | { | |
a2fa3e9f GH |
667 | struct vcpu_svm *svm = to_svm(vcpu); |
668 | ||
669 | vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
670 | vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
671 | vcpu->rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
672 | } |
673 | ||
674 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
675 | { | |
a2fa3e9f GH |
676 | struct vcpu_svm *svm = to_svm(vcpu); |
677 | svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
678 | svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
679 | svm->vmcb->save.rip = vcpu->rip; | |
6aa8b732 AK |
680 | } |
681 | ||
682 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
683 | { | |
a2fa3e9f | 684 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
685 | } |
686 | ||
687 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
688 | { | |
a2fa3e9f | 689 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
690 | } |
691 | ||
692 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
693 | { | |
a2fa3e9f | 694 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
695 | |
696 | switch (seg) { | |
697 | case VCPU_SREG_CS: return &save->cs; | |
698 | case VCPU_SREG_DS: return &save->ds; | |
699 | case VCPU_SREG_ES: return &save->es; | |
700 | case VCPU_SREG_FS: return &save->fs; | |
701 | case VCPU_SREG_GS: return &save->gs; | |
702 | case VCPU_SREG_SS: return &save->ss; | |
703 | case VCPU_SREG_TR: return &save->tr; | |
704 | case VCPU_SREG_LDTR: return &save->ldtr; | |
705 | } | |
706 | BUG(); | |
8b6d44c7 | 707 | return NULL; |
6aa8b732 AK |
708 | } |
709 | ||
710 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
711 | { | |
712 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
713 | ||
714 | return s->base; | |
715 | } | |
716 | ||
717 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
718 | struct kvm_segment *var, int seg) | |
719 | { | |
720 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
721 | ||
722 | var->base = s->base; | |
723 | var->limit = s->limit; | |
724 | var->selector = s->selector; | |
725 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
726 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
727 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
728 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
729 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
730 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
731 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
732 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
733 | var->unusable = !var->present; | |
734 | } | |
735 | ||
736 | static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) | |
737 | { | |
738 | struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS); | |
739 | ||
740 | *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
741 | *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
742 | } | |
743 | ||
744 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
745 | { | |
a2fa3e9f GH |
746 | struct vcpu_svm *svm = to_svm(vcpu); |
747 | ||
748 | dt->limit = svm->vmcb->save.idtr.limit; | |
749 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
750 | } |
751 | ||
752 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
753 | { | |
a2fa3e9f GH |
754 | struct vcpu_svm *svm = to_svm(vcpu); |
755 | ||
756 | svm->vmcb->save.idtr.limit = dt->limit; | |
757 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
758 | } |
759 | ||
760 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
761 | { | |
a2fa3e9f GH |
762 | struct vcpu_svm *svm = to_svm(vcpu); |
763 | ||
764 | dt->limit = svm->vmcb->save.gdtr.limit; | |
765 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
766 | } |
767 | ||
768 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
769 | { | |
a2fa3e9f GH |
770 | struct vcpu_svm *svm = to_svm(vcpu); |
771 | ||
772 | svm->vmcb->save.gdtr.limit = dt->limit; | |
773 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
774 | } |
775 | ||
25c4c276 | 776 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
777 | { |
778 | } | |
779 | ||
6aa8b732 AK |
780 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
781 | { | |
a2fa3e9f GH |
782 | struct vcpu_svm *svm = to_svm(vcpu); |
783 | ||
05b3e0c2 | 784 | #ifdef CONFIG_X86_64 |
6aa8b732 | 785 | if (vcpu->shadow_efer & KVM_EFER_LME) { |
707d92fa | 786 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
6aa8b732 | 787 | vcpu->shadow_efer |= KVM_EFER_LMA; |
a2fa3e9f | 788 | svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME; |
6aa8b732 AK |
789 | } |
790 | ||
707d92fa | 791 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) { |
6aa8b732 | 792 | vcpu->shadow_efer &= ~KVM_EFER_LMA; |
a2fa3e9f | 793 | svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME); |
6aa8b732 AK |
794 | } |
795 | } | |
796 | #endif | |
707d92fa | 797 | if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 798 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
799 | vcpu->fpu_active = 1; |
800 | } | |
801 | ||
6aa8b732 | 802 | vcpu->cr0 = cr0; |
707d92fa RR |
803 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
804 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 805 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
806 | } |
807 | ||
808 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
809 | { | |
810 | vcpu->cr4 = cr4; | |
a2fa3e9f | 811 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
812 | } |
813 | ||
814 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
815 | struct kvm_segment *var, int seg) | |
816 | { | |
a2fa3e9f | 817 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
818 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
819 | ||
820 | s->base = var->base; | |
821 | s->limit = var->limit; | |
822 | s->selector = var->selector; | |
823 | if (var->unusable) | |
824 | s->attrib = 0; | |
825 | else { | |
826 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
827 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
828 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
829 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
830 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
831 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
832 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
833 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
834 | } | |
835 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
836 | svm->vmcb->save.cpl |
837 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
838 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
839 | ||
840 | } | |
841 | ||
842 | /* FIXME: | |
843 | ||
a2fa3e9f GH |
844 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
845 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
846 | |
847 | */ | |
848 | ||
849 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
850 | { | |
851 | return -EOPNOTSUPP; | |
852 | } | |
853 | ||
854 | static void load_host_msrs(struct kvm_vcpu *vcpu) | |
855 | { | |
94dfbdb3 | 856 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 857 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 858 | #endif |
6aa8b732 AK |
859 | } |
860 | ||
861 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
862 | { | |
94dfbdb3 | 863 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 864 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 865 | #endif |
6aa8b732 AK |
866 | } |
867 | ||
e756fc62 | 868 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
869 | { |
870 | if (svm_data->next_asid > svm_data->max_asid) { | |
871 | ++svm_data->asid_generation; | |
872 | svm_data->next_asid = 1; | |
a2fa3e9f | 873 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
874 | } |
875 | ||
e756fc62 | 876 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
877 | svm->asid_generation = svm_data->asid_generation; |
878 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
879 | } |
880 | ||
881 | static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address) | |
882 | { | |
a2fa3e9f | 883 | invlpga(address, to_svm(vcpu)->vmcb->control.asid); // is needed? |
6aa8b732 AK |
884 | } |
885 | ||
886 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) | |
887 | { | |
a2fa3e9f | 888 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
889 | } |
890 | ||
891 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
892 | int *exception) | |
893 | { | |
a2fa3e9f GH |
894 | struct vcpu_svm *svm = to_svm(vcpu); |
895 | ||
6aa8b732 AK |
896 | *exception = 0; |
897 | ||
a2fa3e9f GH |
898 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
899 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
900 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
901 | *exception = DB_VECTOR; |
902 | return; | |
903 | } | |
904 | ||
905 | switch (dr) { | |
906 | case 0 ... 3: | |
a2fa3e9f | 907 | svm->db_regs[dr] = value; |
6aa8b732 AK |
908 | return; |
909 | case 4 ... 5: | |
66aee91a | 910 | if (vcpu->cr4 & X86_CR4_DE) { |
6aa8b732 AK |
911 | *exception = UD_VECTOR; |
912 | return; | |
913 | } | |
914 | case 7: { | |
915 | if (value & ~((1ULL << 32) - 1)) { | |
916 | *exception = GP_VECTOR; | |
917 | return; | |
918 | } | |
a2fa3e9f | 919 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
920 | return; |
921 | } | |
922 | default: | |
923 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
924 | __FUNCTION__, dr); | |
925 | *exception = UD_VECTOR; | |
926 | return; | |
927 | } | |
928 | } | |
929 | ||
e756fc62 | 930 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 931 | { |
a2fa3e9f | 932 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 933 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
934 | u64 fault_address; |
935 | u32 error_code; | |
936 | enum emulation_result er; | |
e2dec939 | 937 | int r; |
6aa8b732 AK |
938 | |
939 | if (is_external_interrupt(exit_int_info)) | |
e756fc62 | 940 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 941 | |
e756fc62 | 942 | mutex_lock(&kvm->lock); |
6aa8b732 | 943 | |
a2fa3e9f GH |
944 | fault_address = svm->vmcb->control.exit_info_2; |
945 | error_code = svm->vmcb->control.exit_info_1; | |
e756fc62 | 946 | r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
e2dec939 | 947 | if (r < 0) { |
e756fc62 | 948 | mutex_unlock(&kvm->lock); |
e2dec939 AK |
949 | return r; |
950 | } | |
951 | if (!r) { | |
e756fc62 | 952 | mutex_unlock(&kvm->lock); |
6aa8b732 AK |
953 | return 1; |
954 | } | |
e756fc62 RR |
955 | er = emulate_instruction(&svm->vcpu, kvm_run, fault_address, |
956 | error_code); | |
957 | mutex_unlock(&kvm->lock); | |
6aa8b732 AK |
958 | |
959 | switch (er) { | |
960 | case EMULATE_DONE: | |
961 | return 1; | |
962 | case EMULATE_DO_MMIO: | |
e756fc62 | 963 | ++svm->vcpu.stat.mmio_exits; |
6aa8b732 AK |
964 | return 0; |
965 | case EMULATE_FAIL: | |
e756fc62 | 966 | vcpu_printf(&svm->vcpu, "%s: emulate fail\n", __FUNCTION__); |
6aa8b732 AK |
967 | break; |
968 | default: | |
969 | BUG(); | |
970 | } | |
971 | ||
972 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
973 | return 0; | |
974 | } | |
975 | ||
e756fc62 | 976 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 977 | { |
a2fa3e9f | 978 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 979 | if (!(svm->vcpu.cr0 & X86_CR0_TS)) |
a2fa3e9f | 980 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 981 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
982 | |
983 | return 1; | |
7807fa6c AL |
984 | } |
985 | ||
e756fc62 | 986 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
987 | { |
988 | /* | |
989 | * VMCB is undefined after a SHUTDOWN intercept | |
990 | * so reinitialize it. | |
991 | */ | |
a2fa3e9f GH |
992 | clear_page(svm->vmcb); |
993 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
994 | |
995 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
996 | return 0; | |
997 | } | |
998 | ||
e756fc62 | 999 | static int io_get_override(struct vcpu_svm *svm, |
6aa8b732 AK |
1000 | struct vmcb_seg **seg, |
1001 | int *addr_override) | |
1002 | { | |
1003 | u8 inst[MAX_INST_SIZE]; | |
1004 | unsigned ins_length; | |
1005 | gva_t rip; | |
1006 | int i; | |
1007 | ||
a2fa3e9f GH |
1008 | rip = svm->vmcb->save.rip; |
1009 | ins_length = svm->next_rip - rip; | |
1010 | rip += svm->vmcb->save.cs.base; | |
6aa8b732 AK |
1011 | |
1012 | if (ins_length > MAX_INST_SIZE) | |
1013 | printk(KERN_DEBUG | |
1014 | "%s: inst length err, cs base 0x%llx rip 0x%llx " | |
1015 | "next rip 0x%llx ins_length %u\n", | |
1016 | __FUNCTION__, | |
a2fa3e9f GH |
1017 | svm->vmcb->save.cs.base, |
1018 | svm->vmcb->save.rip, | |
1019 | svm->vmcb->control.exit_info_2, | |
6aa8b732 AK |
1020 | ins_length); |
1021 | ||
e7d5d76c LV |
1022 | if (emulator_read_std(rip, inst, ins_length, &svm->vcpu) |
1023 | != X86EMUL_CONTINUE) | |
6aa8b732 AK |
1024 | /* #PF */ |
1025 | return 0; | |
1026 | ||
1027 | *addr_override = 0; | |
8b6d44c7 | 1028 | *seg = NULL; |
6aa8b732 AK |
1029 | for (i = 0; i < ins_length; i++) |
1030 | switch (inst[i]) { | |
1031 | case 0xf0: | |
1032 | case 0xf2: | |
1033 | case 0xf3: | |
1034 | case 0x66: | |
1035 | continue; | |
1036 | case 0x67: | |
1037 | *addr_override = 1; | |
1038 | continue; | |
1039 | case 0x2e: | |
a2fa3e9f | 1040 | *seg = &svm->vmcb->save.cs; |
6aa8b732 AK |
1041 | continue; |
1042 | case 0x36: | |
a2fa3e9f | 1043 | *seg = &svm->vmcb->save.ss; |
6aa8b732 AK |
1044 | continue; |
1045 | case 0x3e: | |
a2fa3e9f | 1046 | *seg = &svm->vmcb->save.ds; |
6aa8b732 AK |
1047 | continue; |
1048 | case 0x26: | |
a2fa3e9f | 1049 | *seg = &svm->vmcb->save.es; |
6aa8b732 AK |
1050 | continue; |
1051 | case 0x64: | |
a2fa3e9f | 1052 | *seg = &svm->vmcb->save.fs; |
6aa8b732 AK |
1053 | continue; |
1054 | case 0x65: | |
a2fa3e9f | 1055 | *seg = &svm->vmcb->save.gs; |
6aa8b732 AK |
1056 | continue; |
1057 | default: | |
1058 | return 1; | |
1059 | } | |
1060 | printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__); | |
1061 | return 0; | |
1062 | } | |
1063 | ||
0e5017d4 | 1064 | static unsigned long io_address(struct vcpu_svm *svm, int ins, gva_t *address) |
6aa8b732 AK |
1065 | { |
1066 | unsigned long addr_mask; | |
1067 | unsigned long *reg; | |
1068 | struct vmcb_seg *seg; | |
1069 | int addr_override; | |
a2fa3e9f | 1070 | struct vmcb_save_area *save_area = &svm->vmcb->save; |
6aa8b732 | 1071 | u16 cs_attrib = save_area->cs.attrib; |
e756fc62 | 1072 | unsigned addr_size = get_addr_size(svm); |
6aa8b732 | 1073 | |
e756fc62 | 1074 | if (!io_get_override(svm, &seg, &addr_override)) |
6aa8b732 AK |
1075 | return 0; |
1076 | ||
1077 | if (addr_override) | |
1078 | addr_size = (addr_size == 2) ? 4: (addr_size >> 1); | |
1079 | ||
1080 | if (ins) { | |
e756fc62 | 1081 | reg = &svm->vcpu.regs[VCPU_REGS_RDI]; |
a2fa3e9f | 1082 | seg = &svm->vmcb->save.es; |
6aa8b732 | 1083 | } else { |
e756fc62 | 1084 | reg = &svm->vcpu.regs[VCPU_REGS_RSI]; |
a2fa3e9f | 1085 | seg = (seg) ? seg : &svm->vmcb->save.ds; |
6aa8b732 AK |
1086 | } |
1087 | ||
1088 | addr_mask = ~0ULL >> (64 - (addr_size * 8)); | |
1089 | ||
1090 | if ((cs_attrib & SVM_SELECTOR_L_MASK) && | |
a2fa3e9f | 1091 | !(svm->vmcb->save.rflags & X86_EFLAGS_VM)) { |
6aa8b732 AK |
1092 | *address = (*reg & addr_mask); |
1093 | return addr_mask; | |
1094 | } | |
1095 | ||
1096 | if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) { | |
e756fc62 | 1097 | svm_inject_gp(&svm->vcpu, 0); |
6aa8b732 AK |
1098 | return 0; |
1099 | } | |
1100 | ||
1101 | *address = (*reg & addr_mask) + seg->base; | |
1102 | return addr_mask; | |
1103 | } | |
1104 | ||
e756fc62 | 1105 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1106 | { |
a2fa3e9f | 1107 | u32 io_info = svm->vmcb->control.exit_info_1; //address size bug? |
039576c0 AK |
1108 | int size, down, in, string, rep; |
1109 | unsigned port; | |
1110 | unsigned long count; | |
1111 | gva_t address = 0; | |
6aa8b732 | 1112 | |
e756fc62 | 1113 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 1114 | |
a2fa3e9f | 1115 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 1116 | |
039576c0 AK |
1117 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
1118 | port = io_info >> 16; | |
1119 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
1120 | string = (io_info & SVM_IOIO_STR_MASK) != 0; | |
1121 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; | |
1122 | count = 1; | |
a2fa3e9f | 1123 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1124 | |
039576c0 | 1125 | if (string) { |
6aa8b732 AK |
1126 | unsigned addr_mask; |
1127 | ||
0e5017d4 | 1128 | addr_mask = io_address(svm, in, &address); |
6aa8b732 | 1129 | if (!addr_mask) { |
d27d4aca AK |
1130 | printk(KERN_DEBUG "%s: get io address failed\n", |
1131 | __FUNCTION__); | |
6aa8b732 AK |
1132 | return 1; |
1133 | } | |
1134 | ||
039576c0 | 1135 | if (rep) |
e756fc62 | 1136 | count = svm->vcpu.regs[VCPU_REGS_RCX] & addr_mask; |
039576c0 | 1137 | } |
e756fc62 RR |
1138 | return kvm_setup_pio(&svm->vcpu, kvm_run, in, size, count, string, |
1139 | down, address, rep, port); | |
6aa8b732 AK |
1140 | } |
1141 | ||
e756fc62 | 1142 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1143 | { |
1144 | return 1; | |
1145 | } | |
1146 | ||
e756fc62 | 1147 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1148 | { |
a2fa3e9f | 1149 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1150 | skip_emulated_instruction(&svm->vcpu); |
1151 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1152 | } |
1153 | ||
e756fc62 | 1154 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1155 | { |
a2fa3e9f | 1156 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 RR |
1157 | skip_emulated_instruction(&svm->vcpu); |
1158 | return kvm_hypercall(&svm->vcpu, kvm_run); | |
02e235bc AK |
1159 | } |
1160 | ||
e756fc62 RR |
1161 | static int invalid_op_interception(struct vcpu_svm *svm, |
1162 | struct kvm_run *kvm_run) | |
6aa8b732 | 1163 | { |
e756fc62 | 1164 | inject_ud(&svm->vcpu); |
6aa8b732 AK |
1165 | return 1; |
1166 | } | |
1167 | ||
e756fc62 RR |
1168 | static int task_switch_interception(struct vcpu_svm *svm, |
1169 | struct kvm_run *kvm_run) | |
6aa8b732 AK |
1170 | { |
1171 | printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__); | |
1172 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
1173 | return 0; | |
1174 | } | |
1175 | ||
e756fc62 | 1176 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1177 | { |
a2fa3e9f | 1178 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1179 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1180 | return 1; |
6aa8b732 AK |
1181 | } |
1182 | ||
e756fc62 RR |
1183 | static int emulate_on_interception(struct vcpu_svm *svm, |
1184 | struct kvm_run *kvm_run) | |
6aa8b732 | 1185 | { |
e756fc62 | 1186 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0) != EMULATE_DONE) |
6aa8b732 AK |
1187 | printk(KERN_ERR "%s: failed\n", __FUNCTION__); |
1188 | return 1; | |
1189 | } | |
1190 | ||
1191 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1192 | { | |
a2fa3e9f GH |
1193 | struct vcpu_svm *svm = to_svm(vcpu); |
1194 | ||
6aa8b732 | 1195 | switch (ecx) { |
6aa8b732 AK |
1196 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1197 | u64 tsc; | |
1198 | ||
1199 | rdtscll(tsc); | |
a2fa3e9f | 1200 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1201 | break; |
1202 | } | |
0e859cac | 1203 | case MSR_K6_STAR: |
a2fa3e9f | 1204 | *data = svm->vmcb->save.star; |
6aa8b732 | 1205 | break; |
0e859cac | 1206 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1207 | case MSR_LSTAR: |
a2fa3e9f | 1208 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1209 | break; |
1210 | case MSR_CSTAR: | |
a2fa3e9f | 1211 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1212 | break; |
1213 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1214 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1215 | break; |
1216 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1217 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1218 | break; |
1219 | #endif | |
1220 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1221 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1222 | break; |
1223 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1224 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1225 | break; |
1226 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1227 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1228 | break; |
1229 | default: | |
3bab1f5d | 1230 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1231 | } |
1232 | return 0; | |
1233 | } | |
1234 | ||
e756fc62 | 1235 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1236 | { |
e756fc62 | 1237 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1238 | u64 data; |
1239 | ||
e756fc62 RR |
1240 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
1241 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1242 | else { |
a2fa3e9f | 1243 | svm->vmcb->save.rax = data & 0xffffffff; |
e756fc62 | 1244 | svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1245 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1246 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1247 | } |
1248 | return 1; | |
1249 | } | |
1250 | ||
1251 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1252 | { | |
a2fa3e9f GH |
1253 | struct vcpu_svm *svm = to_svm(vcpu); |
1254 | ||
6aa8b732 | 1255 | switch (ecx) { |
6aa8b732 AK |
1256 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1257 | u64 tsc; | |
1258 | ||
1259 | rdtscll(tsc); | |
a2fa3e9f | 1260 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1261 | break; |
1262 | } | |
0e859cac | 1263 | case MSR_K6_STAR: |
a2fa3e9f | 1264 | svm->vmcb->save.star = data; |
6aa8b732 | 1265 | break; |
49b14f24 | 1266 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1267 | case MSR_LSTAR: |
a2fa3e9f | 1268 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1269 | break; |
1270 | case MSR_CSTAR: | |
a2fa3e9f | 1271 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1272 | break; |
1273 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1274 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1275 | break; |
1276 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1277 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1278 | break; |
1279 | #endif | |
1280 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1281 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1282 | break; |
1283 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1284 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1285 | break; |
1286 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1287 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 AK |
1288 | break; |
1289 | default: | |
3bab1f5d | 1290 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1291 | } |
1292 | return 0; | |
1293 | } | |
1294 | ||
e756fc62 | 1295 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1296 | { |
e756fc62 | 1297 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1298 | u64 data = (svm->vmcb->save.rax & -1u) |
e756fc62 | 1299 | | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1300 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 RR |
1301 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
1302 | svm_inject_gp(&svm->vcpu, 0); | |
6aa8b732 | 1303 | else |
e756fc62 | 1304 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1305 | return 1; |
1306 | } | |
1307 | ||
e756fc62 | 1308 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1309 | { |
e756fc62 RR |
1310 | if (svm->vmcb->control.exit_info_1) |
1311 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1312 | else |
e756fc62 | 1313 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1314 | } |
1315 | ||
e756fc62 | 1316 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1317 | struct kvm_run *kvm_run) |
1318 | { | |
1319 | /* | |
1320 | * If the user space waits to inject interrupts, exit as soon as | |
1321 | * possible | |
1322 | */ | |
1323 | if (kvm_run->request_interrupt_window && | |
e756fc62 RR |
1324 | !svm->vcpu.irq_summary) { |
1325 | ++svm->vcpu.stat.irq_window_exits; | |
c1150d8c DL |
1326 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1327 | return 0; | |
1328 | } | |
1329 | ||
1330 | return 1; | |
1331 | } | |
1332 | ||
e756fc62 | 1333 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1334 | struct kvm_run *kvm_run) = { |
1335 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1336 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1337 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
1338 | /* for now: */ | |
1339 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1340 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1341 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1342 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
1343 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1344 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1345 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1346 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1347 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1348 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1349 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1350 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1351 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
1352 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, | |
7807fa6c | 1353 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1354 | [SVM_EXIT_INTR] = nop_on_interception, |
1355 | [SVM_EXIT_NMI] = nop_on_interception, | |
1356 | [SVM_EXIT_SMI] = nop_on_interception, | |
1357 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1358 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1359 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1360 | [SVM_EXIT_CPUID] = cpuid_interception, | |
1361 | [SVM_EXIT_HLT] = halt_interception, | |
1362 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1363 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1364 | [SVM_EXIT_IOIO] = io_interception, | |
1365 | [SVM_EXIT_MSR] = msr_interception, | |
1366 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1367 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1368 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1369 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1370 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1371 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1372 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1373 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1374 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
916ce236 JR |
1375 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1376 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1377 | }; |
1378 | ||
1379 | ||
e756fc62 | 1380 | static int handle_exit(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1381 | { |
a2fa3e9f | 1382 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1383 | |
a2fa3e9f | 1384 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1385 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1386 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1387 | "exit_code 0x%x\n", | |
a2fa3e9f | 1388 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1389 | exit_code); |
1390 | ||
9d8f549d | 1391 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
6aa8b732 AK |
1392 | || svm_exit_handlers[exit_code] == 0) { |
1393 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
364b625b | 1394 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1395 | return 0; |
1396 | } | |
1397 | ||
e756fc62 | 1398 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1399 | } |
1400 | ||
1401 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1402 | { | |
1403 | int cpu = raw_smp_processor_id(); | |
1404 | ||
1405 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1406 | svm_data->tss_desc->type = 9; //available 32/64-bit TSS | |
1407 | load_TR_desc(); | |
1408 | } | |
1409 | ||
e756fc62 | 1410 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1411 | { |
1412 | int cpu = raw_smp_processor_id(); | |
1413 | ||
1414 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1415 | ||
a2fa3e9f | 1416 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1417 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1418 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1419 | new_asid(svm, svm_data); |
6aa8b732 AK |
1420 | } |
1421 | ||
1422 | ||
0e5017d4 | 1423 | static inline void inject_irq(struct vcpu_svm *svm) |
6aa8b732 AK |
1424 | { |
1425 | struct vmcb_control_area *control; | |
1426 | ||
e756fc62 RR |
1427 | control = &svm->vmcb->control; |
1428 | control->int_vector = pop_irq(&svm->vcpu); | |
6aa8b732 AK |
1429 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1430 | control->int_ctl |= V_IRQ_MASK | | |
1431 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1432 | } | |
1433 | ||
0e5017d4 | 1434 | static void reput_irq(struct vcpu_svm *svm) |
6aa8b732 | 1435 | { |
e756fc62 | 1436 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 AK |
1437 | |
1438 | if (control->int_ctl & V_IRQ_MASK) { | |
1439 | control->int_ctl &= ~V_IRQ_MASK; | |
e756fc62 | 1440 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1441 | } |
c1150d8c | 1442 | |
e756fc62 | 1443 | svm->vcpu.interrupt_window_open = |
c1150d8c DL |
1444 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1445 | } | |
1446 | ||
e756fc62 | 1447 | static void do_interrupt_requests(struct vcpu_svm *svm, |
c1150d8c DL |
1448 | struct kvm_run *kvm_run) |
1449 | { | |
a2fa3e9f | 1450 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1451 | |
e756fc62 | 1452 | svm->vcpu.interrupt_window_open = |
c1150d8c | 1453 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1454 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1455 | |
e756fc62 | 1456 | if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary) |
c1150d8c DL |
1457 | /* |
1458 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1459 | */ | |
0e5017d4 | 1460 | inject_irq(svm); |
c1150d8c DL |
1461 | |
1462 | /* | |
1463 | * Interrupts blocked. Wait for unblock. | |
1464 | */ | |
e756fc62 RR |
1465 | if (!svm->vcpu.interrupt_window_open && |
1466 | (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) { | |
c1150d8c DL |
1467 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
1468 | } else | |
1469 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); | |
1470 | } | |
1471 | ||
e756fc62 | 1472 | static void post_kvm_run_save(struct vcpu_svm *svm, |
c1150d8c DL |
1473 | struct kvm_run *kvm_run) |
1474 | { | |
e756fc62 RR |
1475 | kvm_run->ready_for_interrupt_injection |
1476 | = (svm->vcpu.interrupt_window_open && | |
1477 | svm->vcpu.irq_summary == 0); | |
a2fa3e9f | 1478 | kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0; |
e756fc62 RR |
1479 | kvm_run->cr8 = svm->vcpu.cr8; |
1480 | kvm_run->apic_base = svm->vcpu.apic_base; | |
c1150d8c DL |
1481 | } |
1482 | ||
1483 | /* | |
1484 | * Check if userspace requested an interrupt window, and that the | |
1485 | * interrupt window is open. | |
1486 | * | |
1487 | * No need to exit to userspace if we already have an interrupt queued. | |
1488 | */ | |
e756fc62 | 1489 | static int dm_request_for_irq_injection(struct vcpu_svm *svm, |
c1150d8c DL |
1490 | struct kvm_run *kvm_run) |
1491 | { | |
e756fc62 | 1492 | return (!svm->vcpu.irq_summary && |
c1150d8c | 1493 | kvm_run->request_interrupt_window && |
e756fc62 RR |
1494 | svm->vcpu.interrupt_window_open && |
1495 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); | |
6aa8b732 AK |
1496 | } |
1497 | ||
1498 | static void save_db_regs(unsigned long *db_regs) | |
1499 | { | |
5aff458e AK |
1500 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1501 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1502 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1503 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1504 | } |
1505 | ||
1506 | static void load_db_regs(unsigned long *db_regs) | |
1507 | { | |
5aff458e AK |
1508 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1509 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1510 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1511 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1512 | } |
1513 | ||
d9e368d6 AK |
1514 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1515 | { | |
1516 | force_new_asid(vcpu); | |
1517 | } | |
1518 | ||
6aa8b732 AK |
1519 | static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
1520 | { | |
a2fa3e9f | 1521 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1522 | u16 fs_selector; |
1523 | u16 gs_selector; | |
1524 | u16 ldt_selector; | |
e2dec939 | 1525 | int r; |
6aa8b732 AK |
1526 | |
1527 | again: | |
17c3ba9d AK |
1528 | r = kvm_mmu_reload(vcpu); |
1529 | if (unlikely(r)) | |
1530 | return r; | |
1531 | ||
cccf748b | 1532 | if (!vcpu->mmio_read_completed) |
e756fc62 | 1533 | do_interrupt_requests(svm, kvm_run); |
6aa8b732 AK |
1534 | |
1535 | clgi(); | |
1536 | ||
d9e368d6 AK |
1537 | vcpu->guest_mode = 1; |
1538 | if (vcpu->requests) | |
1539 | if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests)) | |
1540 | svm_flush_tlb(vcpu); | |
1541 | ||
e756fc62 | 1542 | pre_svm_run(svm); |
6aa8b732 AK |
1543 | |
1544 | save_host_msrs(vcpu); | |
1545 | fs_selector = read_fs(); | |
1546 | gs_selector = read_gs(); | |
1547 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1548 | svm->host_cr2 = kvm_read_cr2(); |
1549 | svm->host_dr6 = read_dr6(); | |
1550 | svm->host_dr7 = read_dr7(); | |
1551 | svm->vmcb->save.cr2 = vcpu->cr2; | |
6aa8b732 | 1552 | |
a2fa3e9f | 1553 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1554 | write_dr7(0); |
a2fa3e9f GH |
1555 | save_db_regs(svm->host_db_regs); |
1556 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1557 | } |
36241b8c | 1558 | |
7807fa6c | 1559 | if (vcpu->fpu_active) { |
b114b080 RR |
1560 | fx_save(&vcpu->host_fx_image); |
1561 | fx_restore(&vcpu->guest_fx_image); | |
7807fa6c | 1562 | } |
36241b8c | 1563 | |
6aa8b732 | 1564 | asm volatile ( |
05b3e0c2 | 1565 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1566 | "push %%rbx; push %%rcx; push %%rdx;" |
1567 | "push %%rsi; push %%rdi; push %%rbp;" | |
1568 | "push %%r8; push %%r9; push %%r10; push %%r11;" | |
1569 | "push %%r12; push %%r13; push %%r14; push %%r15;" | |
1570 | #else | |
1571 | "push %%ebx; push %%ecx; push %%edx;" | |
1572 | "push %%esi; push %%edi; push %%ebp;" | |
1573 | #endif | |
1574 | ||
05b3e0c2 | 1575 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1576 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1577 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1578 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1579 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1580 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1581 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1582 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1583 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1584 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1585 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1586 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1587 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1588 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1589 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1590 | #else |
fb3f0f51 RR |
1591 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1592 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1593 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1594 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1595 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1596 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1597 | #endif |
1598 | ||
05b3e0c2 | 1599 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1600 | /* Enter guest mode */ |
1601 | "push %%rax \n\t" | |
fb3f0f51 | 1602 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1603 | SVM_VMLOAD "\n\t" |
1604 | SVM_VMRUN "\n\t" | |
1605 | SVM_VMSAVE "\n\t" | |
1606 | "pop %%rax \n\t" | |
1607 | #else | |
1608 | /* Enter guest mode */ | |
1609 | "push %%eax \n\t" | |
fb3f0f51 | 1610 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1611 | SVM_VMLOAD "\n\t" |
1612 | SVM_VMRUN "\n\t" | |
1613 | SVM_VMSAVE "\n\t" | |
1614 | "pop %%eax \n\t" | |
1615 | #endif | |
1616 | ||
1617 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1618 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1619 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1620 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1621 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1622 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1623 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1624 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1625 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1626 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1627 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1628 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1629 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1630 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1631 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1632 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 AK |
1633 | |
1634 | "pop %%r15; pop %%r14; pop %%r13; pop %%r12;" | |
1635 | "pop %%r11; pop %%r10; pop %%r9; pop %%r8;" | |
1636 | "pop %%rbp; pop %%rdi; pop %%rsi;" | |
1637 | "pop %%rdx; pop %%rcx; pop %%rbx; \n\t" | |
1638 | #else | |
fb3f0f51 RR |
1639 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1640 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1641 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1642 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1643 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1644 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 AK |
1645 | |
1646 | "pop %%ebp; pop %%edi; pop %%esi;" | |
1647 | "pop %%edx; pop %%ecx; pop %%ebx; \n\t" | |
1648 | #endif | |
1649 | : | |
fb3f0f51 | 1650 | : [svm]"a"(svm), |
6aa8b732 | 1651 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
fb3f0f51 RR |
1652 | [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])), |
1653 | [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])), | |
1654 | [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])), | |
1655 | [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])), | |
1656 | [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])), | |
1657 | [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1658 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1659 | ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])), |
1660 | [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])), | |
1661 | [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])), | |
1662 | [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])), | |
1663 | [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])), | |
1664 | [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])), | |
1665 | [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])), | |
1666 | [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15])) | |
6aa8b732 AK |
1667 | #endif |
1668 | : "cc", "memory" ); | |
1669 | ||
d9e368d6 AK |
1670 | vcpu->guest_mode = 0; |
1671 | ||
7807fa6c | 1672 | if (vcpu->fpu_active) { |
b114b080 RR |
1673 | fx_save(&vcpu->guest_fx_image); |
1674 | fx_restore(&vcpu->host_fx_image); | |
7807fa6c | 1675 | } |
36241b8c | 1676 | |
a2fa3e9f GH |
1677 | if ((svm->vmcb->save.dr7 & 0xff)) |
1678 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1679 | |
a2fa3e9f | 1680 | vcpu->cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1681 | |
a2fa3e9f GH |
1682 | write_dr6(svm->host_dr6); |
1683 | write_dr7(svm->host_dr7); | |
1684 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1685 | |
1686 | load_fs(fs_selector); | |
1687 | load_gs(gs_selector); | |
1688 | load_ldt(ldt_selector); | |
1689 | load_host_msrs(vcpu); | |
1690 | ||
1691 | reload_tss(vcpu); | |
1692 | ||
07031e14 IM |
1693 | /* |
1694 | * Profile KVM exit RIPs: | |
1695 | */ | |
1696 | if (unlikely(prof_on == KVM_PROFILING)) | |
1697 | profile_hit(KVM_PROFILING, | |
a2fa3e9f | 1698 | (void *)(unsigned long)svm->vmcb->save.rip); |
07031e14 | 1699 | |
6aa8b732 AK |
1700 | stgi(); |
1701 | ||
0e5017d4 | 1702 | reput_irq(svm); |
6aa8b732 | 1703 | |
a2fa3e9f | 1704 | svm->next_rip = 0; |
6aa8b732 | 1705 | |
a2fa3e9f | 1706 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { |
8eb7d334 AK |
1707 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; |
1708 | kvm_run->fail_entry.hardware_entry_failure_reason | |
a2fa3e9f | 1709 | = svm->vmcb->control.exit_code; |
e756fc62 | 1710 | post_kvm_run_save(svm, kvm_run); |
6aa8b732 AK |
1711 | return 0; |
1712 | } | |
1713 | ||
e756fc62 | 1714 | r = handle_exit(svm, kvm_run); |
e2dec939 | 1715 | if (r > 0) { |
6aa8b732 | 1716 | if (signal_pending(current)) { |
1165f5fe | 1717 | ++vcpu->stat.signal_exits; |
e756fc62 | 1718 | post_kvm_run_save(svm, kvm_run); |
1b19f3e6 | 1719 | kvm_run->exit_reason = KVM_EXIT_INTR; |
c1150d8c DL |
1720 | return -EINTR; |
1721 | } | |
1722 | ||
e756fc62 | 1723 | if (dm_request_for_irq_injection(svm, kvm_run)) { |
1165f5fe | 1724 | ++vcpu->stat.request_irq_exits; |
e756fc62 | 1725 | post_kvm_run_save(svm, kvm_run); |
1b19f3e6 | 1726 | kvm_run->exit_reason = KVM_EXIT_INTR; |
6aa8b732 AK |
1727 | return -EINTR; |
1728 | } | |
1729 | kvm_resched(vcpu); | |
1730 | goto again; | |
1731 | } | |
e756fc62 | 1732 | post_kvm_run_save(svm, kvm_run); |
e2dec939 | 1733 | return r; |
6aa8b732 AK |
1734 | } |
1735 | ||
6aa8b732 AK |
1736 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1737 | { | |
a2fa3e9f GH |
1738 | struct vcpu_svm *svm = to_svm(vcpu); |
1739 | ||
1740 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1741 | force_new_asid(vcpu); |
7807fa6c AL |
1742 | |
1743 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1744 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1745 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1746 | vcpu->fpu_active = 0; |
1747 | } | |
6aa8b732 AK |
1748 | } |
1749 | ||
1750 | static void svm_inject_page_fault(struct kvm_vcpu *vcpu, | |
1751 | unsigned long addr, | |
1752 | uint32_t err_code) | |
1753 | { | |
a2fa3e9f GH |
1754 | struct vcpu_svm *svm = to_svm(vcpu); |
1755 | uint32_t exit_int_info = svm->vmcb->control.exit_int_info; | |
6aa8b732 | 1756 | |
1165f5fe | 1757 | ++vcpu->stat.pf_guest; |
6aa8b732 AK |
1758 | |
1759 | if (is_page_fault(exit_int_info)) { | |
1760 | ||
a2fa3e9f GH |
1761 | svm->vmcb->control.event_inj_err = 0; |
1762 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1763 | SVM_EVTINJ_VALID_ERR | | |
1764 | SVM_EVTINJ_TYPE_EXEPT | | |
1765 | DF_VECTOR; | |
6aa8b732 AK |
1766 | return; |
1767 | } | |
1768 | vcpu->cr2 = addr; | |
a2fa3e9f GH |
1769 | svm->vmcb->save.cr2 = addr; |
1770 | svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | | |
1771 | SVM_EVTINJ_VALID_ERR | | |
1772 | SVM_EVTINJ_TYPE_EXEPT | | |
1773 | PF_VECTOR; | |
1774 | svm->vmcb->control.event_inj_err = err_code; | |
6aa8b732 AK |
1775 | } |
1776 | ||
1777 | ||
1778 | static int is_disabled(void) | |
1779 | { | |
6031a61c JR |
1780 | u64 vm_cr; |
1781 | ||
1782 | rdmsrl(MSR_VM_CR, vm_cr); | |
1783 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1784 | return 1; | |
1785 | ||
6aa8b732 AK |
1786 | return 0; |
1787 | } | |
1788 | ||
102d8325 IM |
1789 | static void |
1790 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1791 | { | |
1792 | /* | |
1793 | * Patch in the VMMCALL instruction: | |
1794 | */ | |
1795 | hypercall[0] = 0x0f; | |
1796 | hypercall[1] = 0x01; | |
1797 | hypercall[2] = 0xd9; | |
1798 | hypercall[3] = 0xc3; | |
1799 | } | |
1800 | ||
6aa8b732 AK |
1801 | static struct kvm_arch_ops svm_arch_ops = { |
1802 | .cpu_has_kvm_support = has_svm, | |
1803 | .disabled_by_bios = is_disabled, | |
1804 | .hardware_setup = svm_hardware_setup, | |
1805 | .hardware_unsetup = svm_hardware_unsetup, | |
1806 | .hardware_enable = svm_hardware_enable, | |
1807 | .hardware_disable = svm_hardware_disable, | |
1808 | ||
1809 | .vcpu_create = svm_create_vcpu, | |
1810 | .vcpu_free = svm_free_vcpu, | |
1811 | ||
1812 | .vcpu_load = svm_vcpu_load, | |
1813 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1814 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1815 | |
1816 | .set_guest_debug = svm_guest_debug, | |
1817 | .get_msr = svm_get_msr, | |
1818 | .set_msr = svm_set_msr, | |
1819 | .get_segment_base = svm_get_segment_base, | |
1820 | .get_segment = svm_get_segment, | |
1821 | .set_segment = svm_set_segment, | |
6aa8b732 | 1822 | .get_cs_db_l_bits = svm_get_cs_db_l_bits, |
25c4c276 | 1823 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1824 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1825 | .set_cr3 = svm_set_cr3, |
1826 | .set_cr4 = svm_set_cr4, | |
1827 | .set_efer = svm_set_efer, | |
1828 | .get_idt = svm_get_idt, | |
1829 | .set_idt = svm_set_idt, | |
1830 | .get_gdt = svm_get_gdt, | |
1831 | .set_gdt = svm_set_gdt, | |
1832 | .get_dr = svm_get_dr, | |
1833 | .set_dr = svm_set_dr, | |
1834 | .cache_regs = svm_cache_regs, | |
1835 | .decache_regs = svm_decache_regs, | |
1836 | .get_rflags = svm_get_rflags, | |
1837 | .set_rflags = svm_set_rflags, | |
1838 | ||
1839 | .invlpg = svm_invlpg, | |
1840 | .tlb_flush = svm_flush_tlb, | |
1841 | .inject_page_fault = svm_inject_page_fault, | |
1842 | ||
1843 | .inject_gp = svm_inject_gp, | |
1844 | ||
1845 | .run = svm_vcpu_run, | |
1846 | .skip_emulated_instruction = skip_emulated_instruction, | |
102d8325 | 1847 | .patch_hypercall = svm_patch_hypercall, |
6aa8b732 AK |
1848 | }; |
1849 | ||
1850 | static int __init svm_init(void) | |
1851 | { | |
c16f862d RR |
1852 | return kvm_init_arch(&svm_arch_ops, sizeof(struct vcpu_svm), |
1853 | THIS_MODULE); | |
6aa8b732 AK |
1854 | } |
1855 | ||
1856 | static void __exit svm_exit(void) | |
1857 | { | |
1858 | kvm_exit_arch(); | |
1859 | } | |
1860 | ||
1861 | module_init(svm_init) | |
1862 | module_exit(svm_exit) |