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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * AMD SVM support | |
5 | * | |
6 | * Copyright (C) 2006 Qumranet, Inc. | |
7 | * | |
8 | * Authors: | |
9 | * Yaniv Kamay <yaniv@qumranet.com> | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * | |
12 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
13 | * the COPYING file in the top-level directory. | |
14 | * | |
15 | */ | |
34c16eec | 16 | #include "x86.h" |
e495606d AK |
17 | #include "kvm_svm.h" |
18 | #include "x86_emulate.h" | |
85f455f7 | 19 | #include "irq.h" |
e495606d | 20 | |
6aa8b732 | 21 | #include <linux/module.h> |
9d8f549d | 22 | #include <linux/kernel.h> |
6aa8b732 AK |
23 | #include <linux/vmalloc.h> |
24 | #include <linux/highmem.h> | |
e8edc6e0 | 25 | #include <linux/sched.h> |
6aa8b732 | 26 | |
e495606d | 27 | #include <asm/desc.h> |
6aa8b732 AK |
28 | |
29 | MODULE_AUTHOR("Qumranet"); | |
30 | MODULE_LICENSE("GPL"); | |
31 | ||
32 | #define IOPM_ALLOC_ORDER 2 | |
33 | #define MSRPM_ALLOC_ORDER 1 | |
34 | ||
35 | #define DB_VECTOR 1 | |
36 | #define UD_VECTOR 6 | |
37 | #define GP_VECTOR 13 | |
38 | ||
39 | #define DR7_GD_MASK (1 << 13) | |
40 | #define DR6_BD_MASK (1 << 13) | |
6aa8b732 AK |
41 | |
42 | #define SEG_TYPE_LDT 2 | |
43 | #define SEG_TYPE_BUSY_TSS16 3 | |
44 | ||
80b7706e JR |
45 | #define SVM_FEATURE_NPT (1 << 0) |
46 | #define SVM_FEATURE_LBRV (1 << 1) | |
47 | #define SVM_DEATURE_SVML (1 << 2) | |
48 | ||
04d2cc77 AK |
49 | static void kvm_reput_irq(struct vcpu_svm *svm); |
50 | ||
a2fa3e9f GH |
51 | static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu) |
52 | { | |
fb3f0f51 | 53 | return container_of(vcpu, struct vcpu_svm, vcpu); |
a2fa3e9f GH |
54 | } |
55 | ||
6aa8b732 AK |
56 | unsigned long iopm_base; |
57 | unsigned long msrpm_base; | |
58 | ||
59 | struct kvm_ldttss_desc { | |
60 | u16 limit0; | |
61 | u16 base0; | |
62 | unsigned base1 : 8, type : 5, dpl : 2, p : 1; | |
63 | unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8; | |
64 | u32 base3; | |
65 | u32 zero1; | |
66 | } __attribute__((packed)); | |
67 | ||
68 | struct svm_cpu_data { | |
69 | int cpu; | |
70 | ||
5008fdf5 AK |
71 | u64 asid_generation; |
72 | u32 max_asid; | |
73 | u32 next_asid; | |
6aa8b732 AK |
74 | struct kvm_ldttss_desc *tss_desc; |
75 | ||
76 | struct page *save_area; | |
77 | }; | |
78 | ||
79 | static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data); | |
80b7706e | 80 | static uint32_t svm_features; |
6aa8b732 AK |
81 | |
82 | struct svm_init_data { | |
83 | int cpu; | |
84 | int r; | |
85 | }; | |
86 | ||
87 | static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000}; | |
88 | ||
9d8f549d | 89 | #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges) |
6aa8b732 AK |
90 | #define MSRS_RANGE_SIZE 2048 |
91 | #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2) | |
92 | ||
93 | #define MAX_INST_SIZE 15 | |
94 | ||
80b7706e JR |
95 | static inline u32 svm_has(u32 feat) |
96 | { | |
97 | return svm_features & feat; | |
98 | } | |
99 | ||
6aa8b732 AK |
100 | static inline u8 pop_irq(struct kvm_vcpu *vcpu) |
101 | { | |
102 | int word_index = __ffs(vcpu->irq_summary); | |
103 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
104 | int irq = word_index * BITS_PER_LONG + bit_index; | |
105 | ||
106 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
107 | if (!vcpu->irq_pending[word_index]) | |
108 | clear_bit(word_index, &vcpu->irq_summary); | |
109 | return irq; | |
110 | } | |
111 | ||
112 | static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq) | |
113 | { | |
114 | set_bit(irq, vcpu->irq_pending); | |
115 | set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary); | |
116 | } | |
117 | ||
118 | static inline void clgi(void) | |
119 | { | |
120 | asm volatile (SVM_CLGI); | |
121 | } | |
122 | ||
123 | static inline void stgi(void) | |
124 | { | |
125 | asm volatile (SVM_STGI); | |
126 | } | |
127 | ||
128 | static inline void invlpga(unsigned long addr, u32 asid) | |
129 | { | |
130 | asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid)); | |
131 | } | |
132 | ||
133 | static inline unsigned long kvm_read_cr2(void) | |
134 | { | |
135 | unsigned long cr2; | |
136 | ||
137 | asm volatile ("mov %%cr2, %0" : "=r" (cr2)); | |
138 | return cr2; | |
139 | } | |
140 | ||
141 | static inline void kvm_write_cr2(unsigned long val) | |
142 | { | |
143 | asm volatile ("mov %0, %%cr2" :: "r" (val)); | |
144 | } | |
145 | ||
146 | static inline unsigned long read_dr6(void) | |
147 | { | |
148 | unsigned long dr6; | |
149 | ||
150 | asm volatile ("mov %%dr6, %0" : "=r" (dr6)); | |
151 | return dr6; | |
152 | } | |
153 | ||
154 | static inline void write_dr6(unsigned long val) | |
155 | { | |
156 | asm volatile ("mov %0, %%dr6" :: "r" (val)); | |
157 | } | |
158 | ||
159 | static inline unsigned long read_dr7(void) | |
160 | { | |
161 | unsigned long dr7; | |
162 | ||
163 | asm volatile ("mov %%dr7, %0" : "=r" (dr7)); | |
164 | return dr7; | |
165 | } | |
166 | ||
167 | static inline void write_dr7(unsigned long val) | |
168 | { | |
169 | asm volatile ("mov %0, %%dr7" :: "r" (val)); | |
170 | } | |
171 | ||
6aa8b732 AK |
172 | static inline void force_new_asid(struct kvm_vcpu *vcpu) |
173 | { | |
a2fa3e9f | 174 | to_svm(vcpu)->asid_generation--; |
6aa8b732 AK |
175 | } |
176 | ||
177 | static inline void flush_guest_tlb(struct kvm_vcpu *vcpu) | |
178 | { | |
179 | force_new_asid(vcpu); | |
180 | } | |
181 | ||
182 | static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer) | |
183 | { | |
2b5203ee CMAB |
184 | if (!(efer & EFER_LMA)) |
185 | efer &= ~EFER_LME; | |
6aa8b732 | 186 | |
a2fa3e9f | 187 | to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK; |
6aa8b732 AK |
188 | vcpu->shadow_efer = efer; |
189 | } | |
190 | ||
298101da AK |
191 | static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
192 | bool has_error_code, u32 error_code) | |
193 | { | |
194 | struct vcpu_svm *svm = to_svm(vcpu); | |
195 | ||
196 | svm->vmcb->control.event_inj = nr | |
197 | | SVM_EVTINJ_VALID | |
198 | | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0) | |
199 | | SVM_EVTINJ_TYPE_EXEPT; | |
200 | svm->vmcb->control.event_inj_err = error_code; | |
201 | } | |
202 | ||
203 | static bool svm_exception_injected(struct kvm_vcpu *vcpu) | |
204 | { | |
205 | struct vcpu_svm *svm = to_svm(vcpu); | |
206 | ||
207 | return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID); | |
208 | } | |
209 | ||
6aa8b732 AK |
210 | static void inject_ud(struct kvm_vcpu *vcpu) |
211 | { | |
a2fa3e9f | 212 | to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID | |
6aa8b732 AK |
213 | SVM_EVTINJ_TYPE_EXEPT | |
214 | UD_VECTOR; | |
215 | } | |
216 | ||
6aa8b732 AK |
217 | static int is_external_interrupt(u32 info) |
218 | { | |
219 | info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID; | |
220 | return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR); | |
221 | } | |
222 | ||
223 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
224 | { | |
a2fa3e9f GH |
225 | struct vcpu_svm *svm = to_svm(vcpu); |
226 | ||
227 | if (!svm->next_rip) { | |
6aa8b732 AK |
228 | printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__); |
229 | return; | |
230 | } | |
d77c26fc | 231 | if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) |
6aa8b732 AK |
232 | printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n", |
233 | __FUNCTION__, | |
a2fa3e9f GH |
234 | svm->vmcb->save.rip, |
235 | svm->next_rip); | |
6aa8b732 | 236 | |
a2fa3e9f GH |
237 | vcpu->rip = svm->vmcb->save.rip = svm->next_rip; |
238 | svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK; | |
c1150d8c DL |
239 | |
240 | vcpu->interrupt_window_open = 1; | |
6aa8b732 AK |
241 | } |
242 | ||
243 | static int has_svm(void) | |
244 | { | |
245 | uint32_t eax, ebx, ecx, edx; | |
246 | ||
1e885461 | 247 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { |
6aa8b732 AK |
248 | printk(KERN_INFO "has_svm: not amd\n"); |
249 | return 0; | |
250 | } | |
251 | ||
252 | cpuid(0x80000000, &eax, &ebx, &ecx, &edx); | |
253 | if (eax < SVM_CPUID_FUNC) { | |
254 | printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n"); | |
255 | return 0; | |
256 | } | |
257 | ||
258 | cpuid(0x80000001, &eax, &ebx, &ecx, &edx); | |
259 | if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) { | |
260 | printk(KERN_DEBUG "has_svm: svm not available\n"); | |
261 | return 0; | |
262 | } | |
263 | return 1; | |
264 | } | |
265 | ||
266 | static void svm_hardware_disable(void *garbage) | |
267 | { | |
268 | struct svm_cpu_data *svm_data | |
269 | = per_cpu(svm_data, raw_smp_processor_id()); | |
270 | ||
271 | if (svm_data) { | |
272 | uint64_t efer; | |
273 | ||
274 | wrmsrl(MSR_VM_HSAVE_PA, 0); | |
275 | rdmsrl(MSR_EFER, efer); | |
276 | wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK); | |
8b6d44c7 | 277 | per_cpu(svm_data, raw_smp_processor_id()) = NULL; |
6aa8b732 AK |
278 | __free_page(svm_data->save_area); |
279 | kfree(svm_data); | |
280 | } | |
281 | } | |
282 | ||
283 | static void svm_hardware_enable(void *garbage) | |
284 | { | |
285 | ||
286 | struct svm_cpu_data *svm_data; | |
287 | uint64_t efer; | |
05b3e0c2 | 288 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
289 | struct desc_ptr gdt_descr; |
290 | #else | |
6b68f01b | 291 | struct desc_ptr gdt_descr; |
6aa8b732 AK |
292 | #endif |
293 | struct desc_struct *gdt; | |
294 | int me = raw_smp_processor_id(); | |
295 | ||
296 | if (!has_svm()) { | |
297 | printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me); | |
298 | return; | |
299 | } | |
300 | svm_data = per_cpu(svm_data, me); | |
301 | ||
302 | if (!svm_data) { | |
303 | printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n", | |
304 | me); | |
305 | return; | |
306 | } | |
307 | ||
308 | svm_data->asid_generation = 1; | |
309 | svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1; | |
310 | svm_data->next_asid = svm_data->max_asid + 1; | |
80b7706e | 311 | svm_features = cpuid_edx(SVM_CPUID_FUNC); |
6aa8b732 | 312 | |
d77c26fc | 313 | asm volatile ("sgdt %0" : "=m"(gdt_descr)); |
6aa8b732 AK |
314 | gdt = (struct desc_struct *)gdt_descr.address; |
315 | svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS); | |
316 | ||
317 | rdmsrl(MSR_EFER, efer); | |
318 | wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK); | |
319 | ||
320 | wrmsrl(MSR_VM_HSAVE_PA, | |
321 | page_to_pfn(svm_data->save_area) << PAGE_SHIFT); | |
322 | } | |
323 | ||
324 | static int svm_cpu_init(int cpu) | |
325 | { | |
326 | struct svm_cpu_data *svm_data; | |
327 | int r; | |
328 | ||
329 | svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL); | |
330 | if (!svm_data) | |
331 | return -ENOMEM; | |
332 | svm_data->cpu = cpu; | |
333 | svm_data->save_area = alloc_page(GFP_KERNEL); | |
334 | r = -ENOMEM; | |
335 | if (!svm_data->save_area) | |
336 | goto err_1; | |
337 | ||
338 | per_cpu(svm_data, cpu) = svm_data; | |
339 | ||
340 | return 0; | |
341 | ||
342 | err_1: | |
343 | kfree(svm_data); | |
344 | return r; | |
345 | ||
346 | } | |
347 | ||
bfc733a7 RR |
348 | static void set_msr_interception(u32 *msrpm, unsigned msr, |
349 | int read, int write) | |
6aa8b732 AK |
350 | { |
351 | int i; | |
352 | ||
353 | for (i = 0; i < NUM_MSR_MAPS; i++) { | |
354 | if (msr >= msrpm_ranges[i] && | |
355 | msr < msrpm_ranges[i] + MSRS_IN_RANGE) { | |
356 | u32 msr_offset = (i * MSRS_IN_RANGE + msr - | |
357 | msrpm_ranges[i]) * 2; | |
358 | ||
359 | u32 *base = msrpm + (msr_offset / 32); | |
360 | u32 msr_shift = msr_offset % 32; | |
361 | u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1); | |
362 | *base = (*base & ~(0x3 << msr_shift)) | | |
363 | (mask << msr_shift); | |
bfc733a7 | 364 | return; |
6aa8b732 AK |
365 | } |
366 | } | |
bfc733a7 | 367 | BUG(); |
6aa8b732 AK |
368 | } |
369 | ||
370 | static __init int svm_hardware_setup(void) | |
371 | { | |
372 | int cpu; | |
373 | struct page *iopm_pages; | |
374 | struct page *msrpm_pages; | |
c8681339 | 375 | void *iopm_va, *msrpm_va; |
6aa8b732 AK |
376 | int r; |
377 | ||
6aa8b732 AK |
378 | iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER); |
379 | ||
380 | if (!iopm_pages) | |
381 | return -ENOMEM; | |
c8681339 AL |
382 | |
383 | iopm_va = page_address(iopm_pages); | |
384 | memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER)); | |
385 | clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */ | |
6aa8b732 AK |
386 | iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT; |
387 | ||
388 | ||
389 | msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER); | |
390 | ||
391 | r = -ENOMEM; | |
392 | if (!msrpm_pages) | |
393 | goto err_1; | |
394 | ||
395 | msrpm_va = page_address(msrpm_pages); | |
396 | memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER)); | |
397 | msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT; | |
398 | ||
05b3e0c2 | 399 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
400 | set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1); |
401 | set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1); | |
402 | set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1); | |
6aa8b732 AK |
403 | set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1); |
404 | set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1); | |
405 | set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1); | |
406 | #endif | |
0e859cac | 407 | set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1); |
6aa8b732 AK |
408 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1); |
409 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1); | |
410 | set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1); | |
411 | ||
412 | for_each_online_cpu(cpu) { | |
413 | r = svm_cpu_init(cpu); | |
414 | if (r) | |
415 | goto err_2; | |
416 | } | |
417 | return 0; | |
418 | ||
419 | err_2: | |
420 | __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER); | |
421 | msrpm_base = 0; | |
422 | err_1: | |
423 | __free_pages(iopm_pages, IOPM_ALLOC_ORDER); | |
424 | iopm_base = 0; | |
425 | return r; | |
426 | } | |
427 | ||
428 | static __exit void svm_hardware_unsetup(void) | |
429 | { | |
430 | __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER); | |
431 | __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER); | |
432 | iopm_base = msrpm_base = 0; | |
433 | } | |
434 | ||
435 | static void init_seg(struct vmcb_seg *seg) | |
436 | { | |
437 | seg->selector = 0; | |
438 | seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK | | |
439 | SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */ | |
440 | seg->limit = 0xffff; | |
441 | seg->base = 0; | |
442 | } | |
443 | ||
444 | static void init_sys_seg(struct vmcb_seg *seg, uint32_t type) | |
445 | { | |
446 | seg->selector = 0; | |
447 | seg->attrib = SVM_SELECTOR_P_MASK | type; | |
448 | seg->limit = 0xffff; | |
449 | seg->base = 0; | |
450 | } | |
451 | ||
6aa8b732 AK |
452 | static void init_vmcb(struct vmcb *vmcb) |
453 | { | |
454 | struct vmcb_control_area *control = &vmcb->control; | |
455 | struct vmcb_save_area *save = &vmcb->save; | |
6aa8b732 AK |
456 | |
457 | control->intercept_cr_read = INTERCEPT_CR0_MASK | | |
458 | INTERCEPT_CR3_MASK | | |
459 | INTERCEPT_CR4_MASK; | |
460 | ||
461 | control->intercept_cr_write = INTERCEPT_CR0_MASK | | |
462 | INTERCEPT_CR3_MASK | | |
463 | INTERCEPT_CR4_MASK; | |
464 | ||
465 | control->intercept_dr_read = INTERCEPT_DR0_MASK | | |
466 | INTERCEPT_DR1_MASK | | |
467 | INTERCEPT_DR2_MASK | | |
468 | INTERCEPT_DR3_MASK; | |
469 | ||
470 | control->intercept_dr_write = INTERCEPT_DR0_MASK | | |
471 | INTERCEPT_DR1_MASK | | |
472 | INTERCEPT_DR2_MASK | | |
473 | INTERCEPT_DR3_MASK | | |
474 | INTERCEPT_DR5_MASK | | |
475 | INTERCEPT_DR7_MASK; | |
476 | ||
7aa81cc0 AL |
477 | control->intercept_exceptions = (1 << PF_VECTOR) | |
478 | (1 << UD_VECTOR); | |
6aa8b732 AK |
479 | |
480 | ||
481 | control->intercept = (1ULL << INTERCEPT_INTR) | | |
482 | (1ULL << INTERCEPT_NMI) | | |
0152527b | 483 | (1ULL << INTERCEPT_SMI) | |
6aa8b732 AK |
484 | /* |
485 | * selective cr0 intercept bug? | |
486 | * 0: 0f 22 d8 mov %eax,%cr3 | |
487 | * 3: 0f 20 c0 mov %cr0,%eax | |
488 | * 6: 0d 00 00 00 80 or $0x80000000,%eax | |
489 | * b: 0f 22 c0 mov %eax,%cr0 | |
490 | * set cr3 ->interception | |
491 | * get cr0 ->interception | |
492 | * set cr0 -> no interception | |
493 | */ | |
494 | /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */ | |
495 | (1ULL << INTERCEPT_CPUID) | | |
cf5a94d1 | 496 | (1ULL << INTERCEPT_INVD) | |
6aa8b732 | 497 | (1ULL << INTERCEPT_HLT) | |
6aa8b732 AK |
498 | (1ULL << INTERCEPT_INVLPGA) | |
499 | (1ULL << INTERCEPT_IOIO_PROT) | | |
500 | (1ULL << INTERCEPT_MSR_PROT) | | |
501 | (1ULL << INTERCEPT_TASK_SWITCH) | | |
46fe4ddd | 502 | (1ULL << INTERCEPT_SHUTDOWN) | |
6aa8b732 AK |
503 | (1ULL << INTERCEPT_VMRUN) | |
504 | (1ULL << INTERCEPT_VMMCALL) | | |
505 | (1ULL << INTERCEPT_VMLOAD) | | |
506 | (1ULL << INTERCEPT_VMSAVE) | | |
507 | (1ULL << INTERCEPT_STGI) | | |
508 | (1ULL << INTERCEPT_CLGI) | | |
916ce236 | 509 | (1ULL << INTERCEPT_SKINIT) | |
cf5a94d1 | 510 | (1ULL << INTERCEPT_WBINVD) | |
916ce236 JR |
511 | (1ULL << INTERCEPT_MONITOR) | |
512 | (1ULL << INTERCEPT_MWAIT); | |
6aa8b732 AK |
513 | |
514 | control->iopm_base_pa = iopm_base; | |
515 | control->msrpm_base_pa = msrpm_base; | |
0cc5064d | 516 | control->tsc_offset = 0; |
6aa8b732 AK |
517 | control->int_ctl = V_INTR_MASKING_MASK; |
518 | ||
519 | init_seg(&save->es); | |
520 | init_seg(&save->ss); | |
521 | init_seg(&save->ds); | |
522 | init_seg(&save->fs); | |
523 | init_seg(&save->gs); | |
524 | ||
525 | save->cs.selector = 0xf000; | |
526 | /* Executable/Readable Code Segment */ | |
527 | save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK | | |
528 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK; | |
529 | save->cs.limit = 0xffff; | |
d92899a0 AK |
530 | /* |
531 | * cs.base should really be 0xffff0000, but vmx can't handle that, so | |
532 | * be consistent with it. | |
533 | * | |
534 | * Replace when we have real mode working for vmx. | |
535 | */ | |
536 | save->cs.base = 0xf0000; | |
6aa8b732 AK |
537 | |
538 | save->gdtr.limit = 0xffff; | |
539 | save->idtr.limit = 0xffff; | |
540 | ||
541 | init_sys_seg(&save->ldtr, SEG_TYPE_LDT); | |
542 | init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16); | |
543 | ||
544 | save->efer = MSR_EFER_SVME_MASK; | |
d77c26fc | 545 | save->dr6 = 0xffff0ff0; |
6aa8b732 AK |
546 | save->dr7 = 0x400; |
547 | save->rflags = 2; | |
548 | save->rip = 0x0000fff0; | |
549 | ||
550 | /* | |
551 | * cr0 val on cpu init should be 0x60000010, we enable cpu | |
552 | * cache by default. the orderly way is to enable cache in bios. | |
553 | */ | |
707d92fa | 554 | save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP; |
66aee91a | 555 | save->cr4 = X86_CR4_PAE; |
6aa8b732 AK |
556 | /* rdx = ?? */ |
557 | } | |
558 | ||
e00c8cf2 | 559 | static int svm_vcpu_reset(struct kvm_vcpu *vcpu) |
04d2cc77 AK |
560 | { |
561 | struct vcpu_svm *svm = to_svm(vcpu); | |
562 | ||
563 | init_vmcb(svm->vmcb); | |
70433389 AK |
564 | |
565 | if (vcpu->vcpu_id != 0) { | |
566 | svm->vmcb->save.rip = 0; | |
567 | svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12; | |
568 | svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8; | |
569 | } | |
e00c8cf2 AK |
570 | |
571 | return 0; | |
04d2cc77 AK |
572 | } |
573 | ||
fb3f0f51 | 574 | static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 575 | { |
a2fa3e9f | 576 | struct vcpu_svm *svm; |
6aa8b732 | 577 | struct page *page; |
fb3f0f51 | 578 | int err; |
6aa8b732 | 579 | |
c16f862d | 580 | svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
fb3f0f51 RR |
581 | if (!svm) { |
582 | err = -ENOMEM; | |
583 | goto out; | |
584 | } | |
585 | ||
586 | err = kvm_vcpu_init(&svm->vcpu, kvm, id); | |
587 | if (err) | |
588 | goto free_svm; | |
589 | ||
6aa8b732 | 590 | page = alloc_page(GFP_KERNEL); |
fb3f0f51 RR |
591 | if (!page) { |
592 | err = -ENOMEM; | |
593 | goto uninit; | |
594 | } | |
6aa8b732 | 595 | |
a2fa3e9f GH |
596 | svm->vmcb = page_address(page); |
597 | clear_page(svm->vmcb); | |
598 | svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT; | |
599 | svm->asid_generation = 0; | |
600 | memset(svm->db_regs, 0, sizeof(svm->db_regs)); | |
601 | init_vmcb(svm->vmcb); | |
602 | ||
fb3f0f51 RR |
603 | fx_init(&svm->vcpu); |
604 | svm->vcpu.fpu_active = 1; | |
605 | svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; | |
606 | if (svm->vcpu.vcpu_id == 0) | |
607 | svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP; | |
6aa8b732 | 608 | |
fb3f0f51 | 609 | return &svm->vcpu; |
36241b8c | 610 | |
fb3f0f51 RR |
611 | uninit: |
612 | kvm_vcpu_uninit(&svm->vcpu); | |
613 | free_svm: | |
a4770347 | 614 | kmem_cache_free(kvm_vcpu_cache, svm); |
fb3f0f51 RR |
615 | out: |
616 | return ERR_PTR(err); | |
6aa8b732 AK |
617 | } |
618 | ||
619 | static void svm_free_vcpu(struct kvm_vcpu *vcpu) | |
620 | { | |
a2fa3e9f GH |
621 | struct vcpu_svm *svm = to_svm(vcpu); |
622 | ||
fb3f0f51 RR |
623 | __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT)); |
624 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 625 | kmem_cache_free(kvm_vcpu_cache, svm); |
6aa8b732 AK |
626 | } |
627 | ||
15ad7146 | 628 | static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 629 | { |
a2fa3e9f | 630 | struct vcpu_svm *svm = to_svm(vcpu); |
15ad7146 | 631 | int i; |
0cc5064d | 632 | |
0cc5064d AK |
633 | if (unlikely(cpu != vcpu->cpu)) { |
634 | u64 tsc_this, delta; | |
635 | ||
636 | /* | |
637 | * Make sure that the guest sees a monotonically | |
638 | * increasing TSC. | |
639 | */ | |
640 | rdtscll(tsc_this); | |
641 | delta = vcpu->host_tsc - tsc_this; | |
a2fa3e9f | 642 | svm->vmcb->control.tsc_offset += delta; |
0cc5064d | 643 | vcpu->cpu = cpu; |
a3d7f85f | 644 | kvm_migrate_apic_timer(vcpu); |
0cc5064d | 645 | } |
94dfbdb3 AL |
646 | |
647 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) | |
a2fa3e9f | 648 | rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
6aa8b732 AK |
649 | } |
650 | ||
651 | static void svm_vcpu_put(struct kvm_vcpu *vcpu) | |
652 | { | |
a2fa3e9f | 653 | struct vcpu_svm *svm = to_svm(vcpu); |
94dfbdb3 AL |
654 | int i; |
655 | ||
e1beb1d3 | 656 | ++vcpu->stat.host_state_reload; |
94dfbdb3 | 657 | for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++) |
a2fa3e9f | 658 | wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); |
94dfbdb3 | 659 | |
0cc5064d | 660 | rdtscll(vcpu->host_tsc); |
6aa8b732 AK |
661 | } |
662 | ||
774c47f1 AK |
663 | static void svm_vcpu_decache(struct kvm_vcpu *vcpu) |
664 | { | |
665 | } | |
666 | ||
6aa8b732 AK |
667 | static void svm_cache_regs(struct kvm_vcpu *vcpu) |
668 | { | |
a2fa3e9f GH |
669 | struct vcpu_svm *svm = to_svm(vcpu); |
670 | ||
671 | vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax; | |
672 | vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp; | |
673 | vcpu->rip = svm->vmcb->save.rip; | |
6aa8b732 AK |
674 | } |
675 | ||
676 | static void svm_decache_regs(struct kvm_vcpu *vcpu) | |
677 | { | |
a2fa3e9f GH |
678 | struct vcpu_svm *svm = to_svm(vcpu); |
679 | svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX]; | |
680 | svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP]; | |
681 | svm->vmcb->save.rip = vcpu->rip; | |
6aa8b732 AK |
682 | } |
683 | ||
684 | static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu) | |
685 | { | |
a2fa3e9f | 686 | return to_svm(vcpu)->vmcb->save.rflags; |
6aa8b732 AK |
687 | } |
688 | ||
689 | static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
690 | { | |
a2fa3e9f | 691 | to_svm(vcpu)->vmcb->save.rflags = rflags; |
6aa8b732 AK |
692 | } |
693 | ||
694 | static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg) | |
695 | { | |
a2fa3e9f | 696 | struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save; |
6aa8b732 AK |
697 | |
698 | switch (seg) { | |
699 | case VCPU_SREG_CS: return &save->cs; | |
700 | case VCPU_SREG_DS: return &save->ds; | |
701 | case VCPU_SREG_ES: return &save->es; | |
702 | case VCPU_SREG_FS: return &save->fs; | |
703 | case VCPU_SREG_GS: return &save->gs; | |
704 | case VCPU_SREG_SS: return &save->ss; | |
705 | case VCPU_SREG_TR: return &save->tr; | |
706 | case VCPU_SREG_LDTR: return &save->ldtr; | |
707 | } | |
708 | BUG(); | |
8b6d44c7 | 709 | return NULL; |
6aa8b732 AK |
710 | } |
711 | ||
712 | static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg) | |
713 | { | |
714 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
715 | ||
716 | return s->base; | |
717 | } | |
718 | ||
719 | static void svm_get_segment(struct kvm_vcpu *vcpu, | |
720 | struct kvm_segment *var, int seg) | |
721 | { | |
722 | struct vmcb_seg *s = svm_seg(vcpu, seg); | |
723 | ||
724 | var->base = s->base; | |
725 | var->limit = s->limit; | |
726 | var->selector = s->selector; | |
727 | var->type = s->attrib & SVM_SELECTOR_TYPE_MASK; | |
728 | var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1; | |
729 | var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3; | |
730 | var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1; | |
731 | var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1; | |
732 | var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1; | |
733 | var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1; | |
734 | var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1; | |
735 | var->unusable = !var->present; | |
736 | } | |
737 | ||
6aa8b732 AK |
738 | static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) |
739 | { | |
a2fa3e9f GH |
740 | struct vcpu_svm *svm = to_svm(vcpu); |
741 | ||
742 | dt->limit = svm->vmcb->save.idtr.limit; | |
743 | dt->base = svm->vmcb->save.idtr.base; | |
6aa8b732 AK |
744 | } |
745 | ||
746 | static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
747 | { | |
a2fa3e9f GH |
748 | struct vcpu_svm *svm = to_svm(vcpu); |
749 | ||
750 | svm->vmcb->save.idtr.limit = dt->limit; | |
751 | svm->vmcb->save.idtr.base = dt->base ; | |
6aa8b732 AK |
752 | } |
753 | ||
754 | static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
755 | { | |
a2fa3e9f GH |
756 | struct vcpu_svm *svm = to_svm(vcpu); |
757 | ||
758 | dt->limit = svm->vmcb->save.gdtr.limit; | |
759 | dt->base = svm->vmcb->save.gdtr.base; | |
6aa8b732 AK |
760 | } |
761 | ||
762 | static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
763 | { | |
a2fa3e9f GH |
764 | struct vcpu_svm *svm = to_svm(vcpu); |
765 | ||
766 | svm->vmcb->save.gdtr.limit = dt->limit; | |
767 | svm->vmcb->save.gdtr.base = dt->base ; | |
6aa8b732 AK |
768 | } |
769 | ||
25c4c276 | 770 | static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 AK |
771 | { |
772 | } | |
773 | ||
6aa8b732 AK |
774 | static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
775 | { | |
a2fa3e9f GH |
776 | struct vcpu_svm *svm = to_svm(vcpu); |
777 | ||
05b3e0c2 | 778 | #ifdef CONFIG_X86_64 |
2b5203ee | 779 | if (vcpu->shadow_efer & EFER_LME) { |
707d92fa | 780 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) { |
2b5203ee CMAB |
781 | vcpu->shadow_efer |= EFER_LMA; |
782 | svm->vmcb->save.efer |= EFER_LMA | EFER_LME; | |
6aa8b732 AK |
783 | } |
784 | ||
d77c26fc | 785 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) { |
2b5203ee CMAB |
786 | vcpu->shadow_efer &= ~EFER_LMA; |
787 | svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME); | |
6aa8b732 AK |
788 | } |
789 | } | |
790 | #endif | |
707d92fa | 791 | if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) { |
a2fa3e9f | 792 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
7807fa6c AL |
793 | vcpu->fpu_active = 1; |
794 | } | |
795 | ||
6aa8b732 | 796 | vcpu->cr0 = cr0; |
707d92fa RR |
797 | cr0 |= X86_CR0_PG | X86_CR0_WP; |
798 | cr0 &= ~(X86_CR0_CD | X86_CR0_NW); | |
a2fa3e9f | 799 | svm->vmcb->save.cr0 = cr0; |
6aa8b732 AK |
800 | } |
801 | ||
802 | static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
803 | { | |
804 | vcpu->cr4 = cr4; | |
a2fa3e9f | 805 | to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE; |
6aa8b732 AK |
806 | } |
807 | ||
808 | static void svm_set_segment(struct kvm_vcpu *vcpu, | |
809 | struct kvm_segment *var, int seg) | |
810 | { | |
a2fa3e9f | 811 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
812 | struct vmcb_seg *s = svm_seg(vcpu, seg); |
813 | ||
814 | s->base = var->base; | |
815 | s->limit = var->limit; | |
816 | s->selector = var->selector; | |
817 | if (var->unusable) | |
818 | s->attrib = 0; | |
819 | else { | |
820 | s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK); | |
821 | s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT; | |
822 | s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT; | |
823 | s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT; | |
824 | s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT; | |
825 | s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT; | |
826 | s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT; | |
827 | s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT; | |
828 | } | |
829 | if (seg == VCPU_SREG_CS) | |
a2fa3e9f GH |
830 | svm->vmcb->save.cpl |
831 | = (svm->vmcb->save.cs.attrib | |
6aa8b732 AK |
832 | >> SVM_SELECTOR_DPL_SHIFT) & 3; |
833 | ||
834 | } | |
835 | ||
836 | /* FIXME: | |
837 | ||
a2fa3e9f GH |
838 | svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK; |
839 | svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK); | |
6aa8b732 AK |
840 | |
841 | */ | |
842 | ||
843 | static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
844 | { | |
845 | return -EOPNOTSUPP; | |
846 | } | |
847 | ||
2a8067f1 ED |
848 | static int svm_get_irq(struct kvm_vcpu *vcpu) |
849 | { | |
850 | struct vcpu_svm *svm = to_svm(vcpu); | |
851 | u32 exit_int_info = svm->vmcb->control.exit_int_info; | |
852 | ||
853 | if (is_external_interrupt(exit_int_info)) | |
854 | return exit_int_info & SVM_EVTINJ_VEC_MASK; | |
855 | return -1; | |
856 | } | |
857 | ||
6aa8b732 AK |
858 | static void load_host_msrs(struct kvm_vcpu *vcpu) |
859 | { | |
94dfbdb3 | 860 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 861 | wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 862 | #endif |
6aa8b732 AK |
863 | } |
864 | ||
865 | static void save_host_msrs(struct kvm_vcpu *vcpu) | |
866 | { | |
94dfbdb3 | 867 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 868 | rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); |
94dfbdb3 | 869 | #endif |
6aa8b732 AK |
870 | } |
871 | ||
e756fc62 | 872 | static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data) |
6aa8b732 AK |
873 | { |
874 | if (svm_data->next_asid > svm_data->max_asid) { | |
875 | ++svm_data->asid_generation; | |
876 | svm_data->next_asid = 1; | |
a2fa3e9f | 877 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID; |
6aa8b732 AK |
878 | } |
879 | ||
e756fc62 | 880 | svm->vcpu.cpu = svm_data->cpu; |
a2fa3e9f GH |
881 | svm->asid_generation = svm_data->asid_generation; |
882 | svm->vmcb->control.asid = svm_data->next_asid++; | |
6aa8b732 AK |
883 | } |
884 | ||
6aa8b732 AK |
885 | static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr) |
886 | { | |
a2fa3e9f | 887 | return to_svm(vcpu)->db_regs[dr]; |
6aa8b732 AK |
888 | } |
889 | ||
890 | static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value, | |
891 | int *exception) | |
892 | { | |
a2fa3e9f GH |
893 | struct vcpu_svm *svm = to_svm(vcpu); |
894 | ||
6aa8b732 AK |
895 | *exception = 0; |
896 | ||
a2fa3e9f GH |
897 | if (svm->vmcb->save.dr7 & DR7_GD_MASK) { |
898 | svm->vmcb->save.dr7 &= ~DR7_GD_MASK; | |
899 | svm->vmcb->save.dr6 |= DR6_BD_MASK; | |
6aa8b732 AK |
900 | *exception = DB_VECTOR; |
901 | return; | |
902 | } | |
903 | ||
904 | switch (dr) { | |
905 | case 0 ... 3: | |
a2fa3e9f | 906 | svm->db_regs[dr] = value; |
6aa8b732 AK |
907 | return; |
908 | case 4 ... 5: | |
66aee91a | 909 | if (vcpu->cr4 & X86_CR4_DE) { |
6aa8b732 AK |
910 | *exception = UD_VECTOR; |
911 | return; | |
912 | } | |
913 | case 7: { | |
914 | if (value & ~((1ULL << 32) - 1)) { | |
915 | *exception = GP_VECTOR; | |
916 | return; | |
917 | } | |
a2fa3e9f | 918 | svm->vmcb->save.dr7 = value; |
6aa8b732 AK |
919 | return; |
920 | } | |
921 | default: | |
922 | printk(KERN_DEBUG "%s: unexpected dr %u\n", | |
923 | __FUNCTION__, dr); | |
924 | *exception = UD_VECTOR; | |
925 | return; | |
926 | } | |
927 | } | |
928 | ||
e756fc62 | 929 | static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 930 | { |
a2fa3e9f | 931 | u32 exit_int_info = svm->vmcb->control.exit_int_info; |
e756fc62 | 932 | struct kvm *kvm = svm->vcpu.kvm; |
6aa8b732 AK |
933 | u64 fault_address; |
934 | u32 error_code; | |
6aa8b732 | 935 | |
85f455f7 ED |
936 | if (!irqchip_in_kernel(kvm) && |
937 | is_external_interrupt(exit_int_info)) | |
e756fc62 | 938 | push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK); |
6aa8b732 | 939 | |
a2fa3e9f GH |
940 | fault_address = svm->vmcb->control.exit_info_2; |
941 | error_code = svm->vmcb->control.exit_info_1; | |
3067714c | 942 | return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code); |
6aa8b732 AK |
943 | } |
944 | ||
7aa81cc0 AL |
945 | static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
946 | { | |
947 | int er; | |
948 | ||
3427318f | 949 | er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0); |
7aa81cc0 AL |
950 | if (er != EMULATE_DONE) |
951 | inject_ud(&svm->vcpu); | |
952 | ||
953 | return 1; | |
954 | } | |
955 | ||
e756fc62 | 956 | static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
7807fa6c | 957 | { |
a2fa3e9f | 958 | svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR); |
e756fc62 | 959 | if (!(svm->vcpu.cr0 & X86_CR0_TS)) |
a2fa3e9f | 960 | svm->vmcb->save.cr0 &= ~X86_CR0_TS; |
e756fc62 | 961 | svm->vcpu.fpu_active = 1; |
a2fa3e9f GH |
962 | |
963 | return 1; | |
7807fa6c AL |
964 | } |
965 | ||
e756fc62 | 966 | static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
46fe4ddd JR |
967 | { |
968 | /* | |
969 | * VMCB is undefined after a SHUTDOWN intercept | |
970 | * so reinitialize it. | |
971 | */ | |
a2fa3e9f GH |
972 | clear_page(svm->vmcb); |
973 | init_vmcb(svm->vmcb); | |
46fe4ddd JR |
974 | |
975 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
976 | return 0; | |
977 | } | |
978 | ||
e756fc62 | 979 | static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 980 | { |
d77c26fc | 981 | u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */ |
039576c0 AK |
982 | int size, down, in, string, rep; |
983 | unsigned port; | |
6aa8b732 | 984 | |
e756fc62 | 985 | ++svm->vcpu.stat.io_exits; |
6aa8b732 | 986 | |
a2fa3e9f | 987 | svm->next_rip = svm->vmcb->control.exit_info_2; |
6aa8b732 | 988 | |
e70669ab LV |
989 | string = (io_info & SVM_IOIO_STR_MASK) != 0; |
990 | ||
991 | if (string) { | |
3427318f LV |
992 | if (emulate_instruction(&svm->vcpu, |
993 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
994 | return 0; |
995 | return 1; | |
996 | } | |
997 | ||
039576c0 AK |
998 | in = (io_info & SVM_IOIO_TYPE_MASK) != 0; |
999 | port = io_info >> 16; | |
1000 | size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT; | |
039576c0 | 1001 | rep = (io_info & SVM_IOIO_REP_MASK) != 0; |
a2fa3e9f | 1002 | down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0; |
6aa8b732 | 1003 | |
3090dd73 | 1004 | return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
1005 | } |
1006 | ||
e756fc62 | 1007 | static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 AK |
1008 | { |
1009 | return 1; | |
1010 | } | |
1011 | ||
e756fc62 | 1012 | static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1013 | { |
a2fa3e9f | 1014 | svm->next_rip = svm->vmcb->save.rip + 1; |
e756fc62 RR |
1015 | skip_emulated_instruction(&svm->vcpu); |
1016 | return kvm_emulate_halt(&svm->vcpu); | |
6aa8b732 AK |
1017 | } |
1018 | ||
e756fc62 | 1019 | static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
02e235bc | 1020 | { |
a2fa3e9f | 1021 | svm->next_rip = svm->vmcb->save.rip + 3; |
e756fc62 | 1022 | skip_emulated_instruction(&svm->vcpu); |
7aa81cc0 AL |
1023 | kvm_emulate_hypercall(&svm->vcpu); |
1024 | return 1; | |
02e235bc AK |
1025 | } |
1026 | ||
e756fc62 RR |
1027 | static int invalid_op_interception(struct vcpu_svm *svm, |
1028 | struct kvm_run *kvm_run) | |
6aa8b732 | 1029 | { |
e756fc62 | 1030 | inject_ud(&svm->vcpu); |
6aa8b732 AK |
1031 | return 1; |
1032 | } | |
1033 | ||
e756fc62 RR |
1034 | static int task_switch_interception(struct vcpu_svm *svm, |
1035 | struct kvm_run *kvm_run) | |
6aa8b732 | 1036 | { |
f0242478 | 1037 | pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__); |
6aa8b732 AK |
1038 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
1039 | return 0; | |
1040 | } | |
1041 | ||
e756fc62 | 1042 | static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1043 | { |
a2fa3e9f | 1044 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1045 | kvm_emulate_cpuid(&svm->vcpu); |
06465c5a | 1046 | return 1; |
6aa8b732 AK |
1047 | } |
1048 | ||
e756fc62 RR |
1049 | static int emulate_on_interception(struct vcpu_svm *svm, |
1050 | struct kvm_run *kvm_run) | |
6aa8b732 | 1051 | { |
3427318f | 1052 | if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE) |
f0242478 | 1053 | pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__); |
6aa8b732 AK |
1054 | return 1; |
1055 | } | |
1056 | ||
1057 | static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data) | |
1058 | { | |
a2fa3e9f GH |
1059 | struct vcpu_svm *svm = to_svm(vcpu); |
1060 | ||
6aa8b732 | 1061 | switch (ecx) { |
6aa8b732 AK |
1062 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1063 | u64 tsc; | |
1064 | ||
1065 | rdtscll(tsc); | |
a2fa3e9f | 1066 | *data = svm->vmcb->control.tsc_offset + tsc; |
6aa8b732 AK |
1067 | break; |
1068 | } | |
0e859cac | 1069 | case MSR_K6_STAR: |
a2fa3e9f | 1070 | *data = svm->vmcb->save.star; |
6aa8b732 | 1071 | break; |
0e859cac | 1072 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1073 | case MSR_LSTAR: |
a2fa3e9f | 1074 | *data = svm->vmcb->save.lstar; |
6aa8b732 AK |
1075 | break; |
1076 | case MSR_CSTAR: | |
a2fa3e9f | 1077 | *data = svm->vmcb->save.cstar; |
6aa8b732 AK |
1078 | break; |
1079 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1080 | *data = svm->vmcb->save.kernel_gs_base; |
6aa8b732 AK |
1081 | break; |
1082 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1083 | *data = svm->vmcb->save.sfmask; |
6aa8b732 AK |
1084 | break; |
1085 | #endif | |
1086 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1087 | *data = svm->vmcb->save.sysenter_cs; |
6aa8b732 AK |
1088 | break; |
1089 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1090 | *data = svm->vmcb->save.sysenter_eip; |
6aa8b732 AK |
1091 | break; |
1092 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1093 | *data = svm->vmcb->save.sysenter_esp; |
6aa8b732 AK |
1094 | break; |
1095 | default: | |
3bab1f5d | 1096 | return kvm_get_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1097 | } |
1098 | return 0; | |
1099 | } | |
1100 | ||
e756fc62 | 1101 | static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1102 | { |
e756fc62 | 1103 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
1104 | u64 data; |
1105 | ||
e756fc62 | 1106 | if (svm_get_msr(&svm->vcpu, ecx, &data)) |
c1a5d4f9 | 1107 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1108 | else { |
a2fa3e9f | 1109 | svm->vmcb->save.rax = data & 0xffffffff; |
e756fc62 | 1110 | svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32; |
a2fa3e9f | 1111 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1112 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1113 | } |
1114 | return 1; | |
1115 | } | |
1116 | ||
1117 | static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data) | |
1118 | { | |
a2fa3e9f GH |
1119 | struct vcpu_svm *svm = to_svm(vcpu); |
1120 | ||
6aa8b732 | 1121 | switch (ecx) { |
6aa8b732 AK |
1122 | case MSR_IA32_TIME_STAMP_COUNTER: { |
1123 | u64 tsc; | |
1124 | ||
1125 | rdtscll(tsc); | |
a2fa3e9f | 1126 | svm->vmcb->control.tsc_offset = data - tsc; |
6aa8b732 AK |
1127 | break; |
1128 | } | |
0e859cac | 1129 | case MSR_K6_STAR: |
a2fa3e9f | 1130 | svm->vmcb->save.star = data; |
6aa8b732 | 1131 | break; |
49b14f24 | 1132 | #ifdef CONFIG_X86_64 |
6aa8b732 | 1133 | case MSR_LSTAR: |
a2fa3e9f | 1134 | svm->vmcb->save.lstar = data; |
6aa8b732 AK |
1135 | break; |
1136 | case MSR_CSTAR: | |
a2fa3e9f | 1137 | svm->vmcb->save.cstar = data; |
6aa8b732 AK |
1138 | break; |
1139 | case MSR_KERNEL_GS_BASE: | |
a2fa3e9f | 1140 | svm->vmcb->save.kernel_gs_base = data; |
6aa8b732 AK |
1141 | break; |
1142 | case MSR_SYSCALL_MASK: | |
a2fa3e9f | 1143 | svm->vmcb->save.sfmask = data; |
6aa8b732 AK |
1144 | break; |
1145 | #endif | |
1146 | case MSR_IA32_SYSENTER_CS: | |
a2fa3e9f | 1147 | svm->vmcb->save.sysenter_cs = data; |
6aa8b732 AK |
1148 | break; |
1149 | case MSR_IA32_SYSENTER_EIP: | |
a2fa3e9f | 1150 | svm->vmcb->save.sysenter_eip = data; |
6aa8b732 AK |
1151 | break; |
1152 | case MSR_IA32_SYSENTER_ESP: | |
a2fa3e9f | 1153 | svm->vmcb->save.sysenter_esp = data; |
6aa8b732 AK |
1154 | break; |
1155 | default: | |
3bab1f5d | 1156 | return kvm_set_msr_common(vcpu, ecx, data); |
6aa8b732 AK |
1157 | } |
1158 | return 0; | |
1159 | } | |
1160 | ||
e756fc62 | 1161 | static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1162 | { |
e756fc62 | 1163 | u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX]; |
a2fa3e9f | 1164 | u64 data = (svm->vmcb->save.rax & -1u) |
e756fc62 | 1165 | | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32); |
a2fa3e9f | 1166 | svm->next_rip = svm->vmcb->save.rip + 2; |
e756fc62 | 1167 | if (svm_set_msr(&svm->vcpu, ecx, data)) |
c1a5d4f9 | 1168 | kvm_inject_gp(&svm->vcpu, 0); |
6aa8b732 | 1169 | else |
e756fc62 | 1170 | skip_emulated_instruction(&svm->vcpu); |
6aa8b732 AK |
1171 | return 1; |
1172 | } | |
1173 | ||
e756fc62 | 1174 | static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run) |
6aa8b732 | 1175 | { |
e756fc62 RR |
1176 | if (svm->vmcb->control.exit_info_1) |
1177 | return wrmsr_interception(svm, kvm_run); | |
6aa8b732 | 1178 | else |
e756fc62 | 1179 | return rdmsr_interception(svm, kvm_run); |
6aa8b732 AK |
1180 | } |
1181 | ||
e756fc62 | 1182 | static int interrupt_window_interception(struct vcpu_svm *svm, |
c1150d8c DL |
1183 | struct kvm_run *kvm_run) |
1184 | { | |
85f455f7 ED |
1185 | svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR); |
1186 | svm->vmcb->control.int_ctl &= ~V_IRQ_MASK; | |
c1150d8c DL |
1187 | /* |
1188 | * If the user space waits to inject interrupts, exit as soon as | |
1189 | * possible | |
1190 | */ | |
1191 | if (kvm_run->request_interrupt_window && | |
e756fc62 RR |
1192 | !svm->vcpu.irq_summary) { |
1193 | ++svm->vcpu.stat.irq_window_exits; | |
c1150d8c DL |
1194 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1195 | return 0; | |
1196 | } | |
1197 | ||
1198 | return 1; | |
1199 | } | |
1200 | ||
e756fc62 | 1201 | static int (*svm_exit_handlers[])(struct vcpu_svm *svm, |
6aa8b732 AK |
1202 | struct kvm_run *kvm_run) = { |
1203 | [SVM_EXIT_READ_CR0] = emulate_on_interception, | |
1204 | [SVM_EXIT_READ_CR3] = emulate_on_interception, | |
1205 | [SVM_EXIT_READ_CR4] = emulate_on_interception, | |
1206 | /* for now: */ | |
1207 | [SVM_EXIT_WRITE_CR0] = emulate_on_interception, | |
1208 | [SVM_EXIT_WRITE_CR3] = emulate_on_interception, | |
1209 | [SVM_EXIT_WRITE_CR4] = emulate_on_interception, | |
1210 | [SVM_EXIT_READ_DR0] = emulate_on_interception, | |
1211 | [SVM_EXIT_READ_DR1] = emulate_on_interception, | |
1212 | [SVM_EXIT_READ_DR2] = emulate_on_interception, | |
1213 | [SVM_EXIT_READ_DR3] = emulate_on_interception, | |
1214 | [SVM_EXIT_WRITE_DR0] = emulate_on_interception, | |
1215 | [SVM_EXIT_WRITE_DR1] = emulate_on_interception, | |
1216 | [SVM_EXIT_WRITE_DR2] = emulate_on_interception, | |
1217 | [SVM_EXIT_WRITE_DR3] = emulate_on_interception, | |
1218 | [SVM_EXIT_WRITE_DR5] = emulate_on_interception, | |
1219 | [SVM_EXIT_WRITE_DR7] = emulate_on_interception, | |
7aa81cc0 | 1220 | [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception, |
6aa8b732 | 1221 | [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception, |
7807fa6c | 1222 | [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception, |
6aa8b732 AK |
1223 | [SVM_EXIT_INTR] = nop_on_interception, |
1224 | [SVM_EXIT_NMI] = nop_on_interception, | |
1225 | [SVM_EXIT_SMI] = nop_on_interception, | |
1226 | [SVM_EXIT_INIT] = nop_on_interception, | |
c1150d8c | 1227 | [SVM_EXIT_VINTR] = interrupt_window_interception, |
6aa8b732 AK |
1228 | /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */ |
1229 | [SVM_EXIT_CPUID] = cpuid_interception, | |
cf5a94d1 | 1230 | [SVM_EXIT_INVD] = emulate_on_interception, |
6aa8b732 AK |
1231 | [SVM_EXIT_HLT] = halt_interception, |
1232 | [SVM_EXIT_INVLPG] = emulate_on_interception, | |
1233 | [SVM_EXIT_INVLPGA] = invalid_op_interception, | |
1234 | [SVM_EXIT_IOIO] = io_interception, | |
1235 | [SVM_EXIT_MSR] = msr_interception, | |
1236 | [SVM_EXIT_TASK_SWITCH] = task_switch_interception, | |
46fe4ddd | 1237 | [SVM_EXIT_SHUTDOWN] = shutdown_interception, |
6aa8b732 | 1238 | [SVM_EXIT_VMRUN] = invalid_op_interception, |
02e235bc | 1239 | [SVM_EXIT_VMMCALL] = vmmcall_interception, |
6aa8b732 AK |
1240 | [SVM_EXIT_VMLOAD] = invalid_op_interception, |
1241 | [SVM_EXIT_VMSAVE] = invalid_op_interception, | |
1242 | [SVM_EXIT_STGI] = invalid_op_interception, | |
1243 | [SVM_EXIT_CLGI] = invalid_op_interception, | |
1244 | [SVM_EXIT_SKINIT] = invalid_op_interception, | |
cf5a94d1 | 1245 | [SVM_EXIT_WBINVD] = emulate_on_interception, |
916ce236 JR |
1246 | [SVM_EXIT_MONITOR] = invalid_op_interception, |
1247 | [SVM_EXIT_MWAIT] = invalid_op_interception, | |
6aa8b732 AK |
1248 | }; |
1249 | ||
1250 | ||
04d2cc77 | 1251 | static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) |
6aa8b732 | 1252 | { |
04d2cc77 | 1253 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1254 | u32 exit_code = svm->vmcb->control.exit_code; |
6aa8b732 | 1255 | |
04d2cc77 AK |
1256 | kvm_reput_irq(svm); |
1257 | ||
1258 | if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) { | |
1259 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
1260 | kvm_run->fail_entry.hardware_entry_failure_reason | |
1261 | = svm->vmcb->control.exit_code; | |
1262 | return 0; | |
1263 | } | |
1264 | ||
a2fa3e9f | 1265 | if (is_external_interrupt(svm->vmcb->control.exit_int_info) && |
6aa8b732 AK |
1266 | exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR) |
1267 | printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x " | |
1268 | "exit_code 0x%x\n", | |
a2fa3e9f | 1269 | __FUNCTION__, svm->vmcb->control.exit_int_info, |
6aa8b732 AK |
1270 | exit_code); |
1271 | ||
9d8f549d | 1272 | if (exit_code >= ARRAY_SIZE(svm_exit_handlers) |
56919c5c | 1273 | || !svm_exit_handlers[exit_code]) { |
6aa8b732 | 1274 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; |
364b625b | 1275 | kvm_run->hw.hardware_exit_reason = exit_code; |
6aa8b732 AK |
1276 | return 0; |
1277 | } | |
1278 | ||
e756fc62 | 1279 | return svm_exit_handlers[exit_code](svm, kvm_run); |
6aa8b732 AK |
1280 | } |
1281 | ||
1282 | static void reload_tss(struct kvm_vcpu *vcpu) | |
1283 | { | |
1284 | int cpu = raw_smp_processor_id(); | |
1285 | ||
1286 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
d77c26fc | 1287 | svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */ |
6aa8b732 AK |
1288 | load_TR_desc(); |
1289 | } | |
1290 | ||
e756fc62 | 1291 | static void pre_svm_run(struct vcpu_svm *svm) |
6aa8b732 AK |
1292 | { |
1293 | int cpu = raw_smp_processor_id(); | |
1294 | ||
1295 | struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu); | |
1296 | ||
a2fa3e9f | 1297 | svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING; |
e756fc62 | 1298 | if (svm->vcpu.cpu != cpu || |
a2fa3e9f | 1299 | svm->asid_generation != svm_data->asid_generation) |
e756fc62 | 1300 | new_asid(svm, svm_data); |
6aa8b732 AK |
1301 | } |
1302 | ||
1303 | ||
85f455f7 | 1304 | static inline void svm_inject_irq(struct vcpu_svm *svm, int irq) |
6aa8b732 AK |
1305 | { |
1306 | struct vmcb_control_area *control; | |
1307 | ||
e756fc62 | 1308 | control = &svm->vmcb->control; |
85f455f7 | 1309 | control->int_vector = irq; |
6aa8b732 AK |
1310 | control->int_ctl &= ~V_INTR_PRIO_MASK; |
1311 | control->int_ctl |= V_IRQ_MASK | | |
1312 | ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT); | |
1313 | } | |
1314 | ||
2a8067f1 ED |
1315 | static void svm_set_irq(struct kvm_vcpu *vcpu, int irq) |
1316 | { | |
1317 | struct vcpu_svm *svm = to_svm(vcpu); | |
1318 | ||
1319 | svm_inject_irq(svm, irq); | |
1320 | } | |
1321 | ||
04d2cc77 | 1322 | static void svm_intr_assist(struct kvm_vcpu *vcpu) |
6aa8b732 | 1323 | { |
04d2cc77 | 1324 | struct vcpu_svm *svm = to_svm(vcpu); |
85f455f7 ED |
1325 | struct vmcb *vmcb = svm->vmcb; |
1326 | int intr_vector = -1; | |
1327 | ||
1328 | if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) && | |
1329 | ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) { | |
1330 | intr_vector = vmcb->control.exit_int_info & | |
1331 | SVM_EVTINJ_VEC_MASK; | |
1332 | vmcb->control.exit_int_info = 0; | |
1333 | svm_inject_irq(svm, intr_vector); | |
1334 | return; | |
1335 | } | |
1336 | ||
1337 | if (vmcb->control.int_ctl & V_IRQ_MASK) | |
1338 | return; | |
1339 | ||
1b9778da | 1340 | if (!kvm_cpu_has_interrupt(vcpu)) |
85f455f7 ED |
1341 | return; |
1342 | ||
1343 | if (!(vmcb->save.rflags & X86_EFLAGS_IF) || | |
1344 | (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) || | |
1345 | (vmcb->control.event_inj & SVM_EVTINJ_VALID)) { | |
1346 | /* unable to deliver irq, set pending irq */ | |
1347 | vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR); | |
1348 | svm_inject_irq(svm, 0x0); | |
1349 | return; | |
1350 | } | |
1351 | /* Okay, we can deliver the interrupt: grab it and update PIC state. */ | |
1b9778da | 1352 | intr_vector = kvm_cpu_get_interrupt(vcpu); |
85f455f7 | 1353 | svm_inject_irq(svm, intr_vector); |
1b9778da | 1354 | kvm_timer_intr_post(vcpu, intr_vector); |
85f455f7 ED |
1355 | } |
1356 | ||
1357 | static void kvm_reput_irq(struct vcpu_svm *svm) | |
1358 | { | |
e756fc62 | 1359 | struct vmcb_control_area *control = &svm->vmcb->control; |
6aa8b732 | 1360 | |
7017fc3d ED |
1361 | if ((control->int_ctl & V_IRQ_MASK) |
1362 | && !irqchip_in_kernel(svm->vcpu.kvm)) { | |
6aa8b732 | 1363 | control->int_ctl &= ~V_IRQ_MASK; |
e756fc62 | 1364 | push_irq(&svm->vcpu, control->int_vector); |
6aa8b732 | 1365 | } |
c1150d8c | 1366 | |
e756fc62 | 1367 | svm->vcpu.interrupt_window_open = |
c1150d8c DL |
1368 | !(control->int_state & SVM_INTERRUPT_SHADOW_MASK); |
1369 | } | |
1370 | ||
85f455f7 ED |
1371 | static void svm_do_inject_vector(struct vcpu_svm *svm) |
1372 | { | |
1373 | struct kvm_vcpu *vcpu = &svm->vcpu; | |
1374 | int word_index = __ffs(vcpu->irq_summary); | |
1375 | int bit_index = __ffs(vcpu->irq_pending[word_index]); | |
1376 | int irq = word_index * BITS_PER_LONG + bit_index; | |
1377 | ||
1378 | clear_bit(bit_index, &vcpu->irq_pending[word_index]); | |
1379 | if (!vcpu->irq_pending[word_index]) | |
1380 | clear_bit(word_index, &vcpu->irq_summary); | |
1381 | svm_inject_irq(svm, irq); | |
1382 | } | |
1383 | ||
04d2cc77 | 1384 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, |
c1150d8c DL |
1385 | struct kvm_run *kvm_run) |
1386 | { | |
04d2cc77 | 1387 | struct vcpu_svm *svm = to_svm(vcpu); |
a2fa3e9f | 1388 | struct vmcb_control_area *control = &svm->vmcb->control; |
c1150d8c | 1389 | |
e756fc62 | 1390 | svm->vcpu.interrupt_window_open = |
c1150d8c | 1391 | (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) && |
a2fa3e9f | 1392 | (svm->vmcb->save.rflags & X86_EFLAGS_IF)); |
c1150d8c | 1393 | |
e756fc62 | 1394 | if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary) |
c1150d8c DL |
1395 | /* |
1396 | * If interrupts enabled, and not blocked by sti or mov ss. Good. | |
1397 | */ | |
85f455f7 | 1398 | svm_do_inject_vector(svm); |
c1150d8c DL |
1399 | |
1400 | /* | |
1401 | * Interrupts blocked. Wait for unblock. | |
1402 | */ | |
e756fc62 | 1403 | if (!svm->vcpu.interrupt_window_open && |
d77c26fc | 1404 | (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) |
c1150d8c | 1405 | control->intercept |= 1ULL << INTERCEPT_VINTR; |
d77c26fc | 1406 | else |
c1150d8c DL |
1407 | control->intercept &= ~(1ULL << INTERCEPT_VINTR); |
1408 | } | |
1409 | ||
cbc94022 IE |
1410 | static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr) |
1411 | { | |
1412 | return 0; | |
1413 | } | |
1414 | ||
6aa8b732 AK |
1415 | static void save_db_regs(unsigned long *db_regs) |
1416 | { | |
5aff458e AK |
1417 | asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0])); |
1418 | asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1])); | |
1419 | asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2])); | |
1420 | asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3])); | |
6aa8b732 AK |
1421 | } |
1422 | ||
1423 | static void load_db_regs(unsigned long *db_regs) | |
1424 | { | |
5aff458e AK |
1425 | asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0])); |
1426 | asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1])); | |
1427 | asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2])); | |
1428 | asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3])); | |
6aa8b732 AK |
1429 | } |
1430 | ||
d9e368d6 AK |
1431 | static void svm_flush_tlb(struct kvm_vcpu *vcpu) |
1432 | { | |
1433 | force_new_asid(vcpu); | |
1434 | } | |
1435 | ||
04d2cc77 AK |
1436 | static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu) |
1437 | { | |
1438 | } | |
1439 | ||
1440 | static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
6aa8b732 | 1441 | { |
a2fa3e9f | 1442 | struct vcpu_svm *svm = to_svm(vcpu); |
6aa8b732 AK |
1443 | u16 fs_selector; |
1444 | u16 gs_selector; | |
1445 | u16 ldt_selector; | |
d9e368d6 | 1446 | |
e756fc62 | 1447 | pre_svm_run(svm); |
6aa8b732 AK |
1448 | |
1449 | save_host_msrs(vcpu); | |
1450 | fs_selector = read_fs(); | |
1451 | gs_selector = read_gs(); | |
1452 | ldt_selector = read_ldt(); | |
a2fa3e9f GH |
1453 | svm->host_cr2 = kvm_read_cr2(); |
1454 | svm->host_dr6 = read_dr6(); | |
1455 | svm->host_dr7 = read_dr7(); | |
1456 | svm->vmcb->save.cr2 = vcpu->cr2; | |
6aa8b732 | 1457 | |
a2fa3e9f | 1458 | if (svm->vmcb->save.dr7 & 0xff) { |
6aa8b732 | 1459 | write_dr7(0); |
a2fa3e9f GH |
1460 | save_db_regs(svm->host_db_regs); |
1461 | load_db_regs(svm->db_regs); | |
6aa8b732 | 1462 | } |
36241b8c | 1463 | |
04d2cc77 AK |
1464 | clgi(); |
1465 | ||
1466 | local_irq_enable(); | |
36241b8c | 1467 | |
6aa8b732 | 1468 | asm volatile ( |
05b3e0c2 | 1469 | #ifdef CONFIG_X86_64 |
54a08c04 | 1470 | "push %%rbp; \n\t" |
6aa8b732 | 1471 | #else |
fe7935d4 | 1472 | "push %%ebp; \n\t" |
6aa8b732 AK |
1473 | #endif |
1474 | ||
05b3e0c2 | 1475 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1476 | "mov %c[rbx](%[svm]), %%rbx \n\t" |
1477 | "mov %c[rcx](%[svm]), %%rcx \n\t" | |
1478 | "mov %c[rdx](%[svm]), %%rdx \n\t" | |
1479 | "mov %c[rsi](%[svm]), %%rsi \n\t" | |
1480 | "mov %c[rdi](%[svm]), %%rdi \n\t" | |
1481 | "mov %c[rbp](%[svm]), %%rbp \n\t" | |
1482 | "mov %c[r8](%[svm]), %%r8 \n\t" | |
1483 | "mov %c[r9](%[svm]), %%r9 \n\t" | |
1484 | "mov %c[r10](%[svm]), %%r10 \n\t" | |
1485 | "mov %c[r11](%[svm]), %%r11 \n\t" | |
1486 | "mov %c[r12](%[svm]), %%r12 \n\t" | |
1487 | "mov %c[r13](%[svm]), %%r13 \n\t" | |
1488 | "mov %c[r14](%[svm]), %%r14 \n\t" | |
1489 | "mov %c[r15](%[svm]), %%r15 \n\t" | |
6aa8b732 | 1490 | #else |
fb3f0f51 RR |
1491 | "mov %c[rbx](%[svm]), %%ebx \n\t" |
1492 | "mov %c[rcx](%[svm]), %%ecx \n\t" | |
1493 | "mov %c[rdx](%[svm]), %%edx \n\t" | |
1494 | "mov %c[rsi](%[svm]), %%esi \n\t" | |
1495 | "mov %c[rdi](%[svm]), %%edi \n\t" | |
1496 | "mov %c[rbp](%[svm]), %%ebp \n\t" | |
6aa8b732 AK |
1497 | #endif |
1498 | ||
05b3e0c2 | 1499 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1500 | /* Enter guest mode */ |
1501 | "push %%rax \n\t" | |
fb3f0f51 | 1502 | "mov %c[vmcb](%[svm]), %%rax \n\t" |
6aa8b732 AK |
1503 | SVM_VMLOAD "\n\t" |
1504 | SVM_VMRUN "\n\t" | |
1505 | SVM_VMSAVE "\n\t" | |
1506 | "pop %%rax \n\t" | |
1507 | #else | |
1508 | /* Enter guest mode */ | |
1509 | "push %%eax \n\t" | |
fb3f0f51 | 1510 | "mov %c[vmcb](%[svm]), %%eax \n\t" |
6aa8b732 AK |
1511 | SVM_VMLOAD "\n\t" |
1512 | SVM_VMRUN "\n\t" | |
1513 | SVM_VMSAVE "\n\t" | |
1514 | "pop %%eax \n\t" | |
1515 | #endif | |
1516 | ||
1517 | /* Save guest registers, load host registers */ | |
05b3e0c2 | 1518 | #ifdef CONFIG_X86_64 |
fb3f0f51 RR |
1519 | "mov %%rbx, %c[rbx](%[svm]) \n\t" |
1520 | "mov %%rcx, %c[rcx](%[svm]) \n\t" | |
1521 | "mov %%rdx, %c[rdx](%[svm]) \n\t" | |
1522 | "mov %%rsi, %c[rsi](%[svm]) \n\t" | |
1523 | "mov %%rdi, %c[rdi](%[svm]) \n\t" | |
1524 | "mov %%rbp, %c[rbp](%[svm]) \n\t" | |
1525 | "mov %%r8, %c[r8](%[svm]) \n\t" | |
1526 | "mov %%r9, %c[r9](%[svm]) \n\t" | |
1527 | "mov %%r10, %c[r10](%[svm]) \n\t" | |
1528 | "mov %%r11, %c[r11](%[svm]) \n\t" | |
1529 | "mov %%r12, %c[r12](%[svm]) \n\t" | |
1530 | "mov %%r13, %c[r13](%[svm]) \n\t" | |
1531 | "mov %%r14, %c[r14](%[svm]) \n\t" | |
1532 | "mov %%r15, %c[r15](%[svm]) \n\t" | |
6aa8b732 | 1533 | |
54a08c04 | 1534 | "pop %%rbp; \n\t" |
6aa8b732 | 1535 | #else |
fb3f0f51 RR |
1536 | "mov %%ebx, %c[rbx](%[svm]) \n\t" |
1537 | "mov %%ecx, %c[rcx](%[svm]) \n\t" | |
1538 | "mov %%edx, %c[rdx](%[svm]) \n\t" | |
1539 | "mov %%esi, %c[rsi](%[svm]) \n\t" | |
1540 | "mov %%edi, %c[rdi](%[svm]) \n\t" | |
1541 | "mov %%ebp, %c[rbp](%[svm]) \n\t" | |
6aa8b732 | 1542 | |
fe7935d4 | 1543 | "pop %%ebp; \n\t" |
6aa8b732 AK |
1544 | #endif |
1545 | : | |
fb3f0f51 | 1546 | : [svm]"a"(svm), |
6aa8b732 | 1547 | [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)), |
d77c26fc MD |
1548 | [rbx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBX])), |
1549 | [rcx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RCX])), | |
1550 | [rdx]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDX])), | |
1551 | [rsi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RSI])), | |
1552 | [rdi]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RDI])), | |
1553 | [rbp]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_RBP])) | |
05b3e0c2 | 1554 | #ifdef CONFIG_X86_64 |
d77c26fc MD |
1555 | , [r8]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R8])), |
1556 | [r9]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R9])), | |
1557 | [r10]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R10])), | |
1558 | [r11]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R11])), | |
1559 | [r12]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R12])), | |
1560 | [r13]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R13])), | |
1561 | [r14]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R14])), | |
1562 | [r15]"i"(offsetof(struct vcpu_svm, vcpu.regs[VCPU_REGS_R15])) | |
6aa8b732 | 1563 | #endif |
54a08c04 LV |
1564 | : "cc", "memory" |
1565 | #ifdef CONFIG_X86_64 | |
1566 | , "rbx", "rcx", "rdx", "rsi", "rdi" | |
1567 | , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15" | |
fe7935d4 LV |
1568 | #else |
1569 | , "ebx", "ecx", "edx" , "esi", "edi" | |
54a08c04 LV |
1570 | #endif |
1571 | ); | |
6aa8b732 | 1572 | |
a2fa3e9f GH |
1573 | if ((svm->vmcb->save.dr7 & 0xff)) |
1574 | load_db_regs(svm->host_db_regs); | |
6aa8b732 | 1575 | |
a2fa3e9f | 1576 | vcpu->cr2 = svm->vmcb->save.cr2; |
6aa8b732 | 1577 | |
a2fa3e9f GH |
1578 | write_dr6(svm->host_dr6); |
1579 | write_dr7(svm->host_dr7); | |
1580 | kvm_write_cr2(svm->host_cr2); | |
6aa8b732 AK |
1581 | |
1582 | load_fs(fs_selector); | |
1583 | load_gs(gs_selector); | |
1584 | load_ldt(ldt_selector); | |
1585 | load_host_msrs(vcpu); | |
1586 | ||
1587 | reload_tss(vcpu); | |
1588 | ||
56ba47dd AK |
1589 | local_irq_disable(); |
1590 | ||
1591 | stgi(); | |
1592 | ||
a2fa3e9f | 1593 | svm->next_rip = 0; |
6aa8b732 AK |
1594 | } |
1595 | ||
6aa8b732 AK |
1596 | static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root) |
1597 | { | |
a2fa3e9f GH |
1598 | struct vcpu_svm *svm = to_svm(vcpu); |
1599 | ||
1600 | svm->vmcb->save.cr3 = root; | |
6aa8b732 | 1601 | force_new_asid(vcpu); |
7807fa6c AL |
1602 | |
1603 | if (vcpu->fpu_active) { | |
a2fa3e9f GH |
1604 | svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR); |
1605 | svm->vmcb->save.cr0 |= X86_CR0_TS; | |
7807fa6c AL |
1606 | vcpu->fpu_active = 0; |
1607 | } | |
6aa8b732 AK |
1608 | } |
1609 | ||
6aa8b732 AK |
1610 | static int is_disabled(void) |
1611 | { | |
6031a61c JR |
1612 | u64 vm_cr; |
1613 | ||
1614 | rdmsrl(MSR_VM_CR, vm_cr); | |
1615 | if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE)) | |
1616 | return 1; | |
1617 | ||
6aa8b732 AK |
1618 | return 0; |
1619 | } | |
1620 | ||
102d8325 IM |
1621 | static void |
1622 | svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
1623 | { | |
1624 | /* | |
1625 | * Patch in the VMMCALL instruction: | |
1626 | */ | |
1627 | hypercall[0] = 0x0f; | |
1628 | hypercall[1] = 0x01; | |
1629 | hypercall[2] = 0xd9; | |
102d8325 IM |
1630 | } |
1631 | ||
002c7f7c YS |
1632 | static void svm_check_processor_compat(void *rtn) |
1633 | { | |
1634 | *(int *)rtn = 0; | |
1635 | } | |
1636 | ||
cbdd1bea | 1637 | static struct kvm_x86_ops svm_x86_ops = { |
6aa8b732 AK |
1638 | .cpu_has_kvm_support = has_svm, |
1639 | .disabled_by_bios = is_disabled, | |
1640 | .hardware_setup = svm_hardware_setup, | |
1641 | .hardware_unsetup = svm_hardware_unsetup, | |
002c7f7c | 1642 | .check_processor_compatibility = svm_check_processor_compat, |
6aa8b732 AK |
1643 | .hardware_enable = svm_hardware_enable, |
1644 | .hardware_disable = svm_hardware_disable, | |
1645 | ||
1646 | .vcpu_create = svm_create_vcpu, | |
1647 | .vcpu_free = svm_free_vcpu, | |
04d2cc77 | 1648 | .vcpu_reset = svm_vcpu_reset, |
6aa8b732 | 1649 | |
04d2cc77 | 1650 | .prepare_guest_switch = svm_prepare_guest_switch, |
6aa8b732 AK |
1651 | .vcpu_load = svm_vcpu_load, |
1652 | .vcpu_put = svm_vcpu_put, | |
774c47f1 | 1653 | .vcpu_decache = svm_vcpu_decache, |
6aa8b732 AK |
1654 | |
1655 | .set_guest_debug = svm_guest_debug, | |
1656 | .get_msr = svm_get_msr, | |
1657 | .set_msr = svm_set_msr, | |
1658 | .get_segment_base = svm_get_segment_base, | |
1659 | .get_segment = svm_get_segment, | |
1660 | .set_segment = svm_set_segment, | |
1747fb71 | 1661 | .get_cs_db_l_bits = kvm_get_cs_db_l_bits, |
25c4c276 | 1662 | .decache_cr4_guest_bits = svm_decache_cr4_guest_bits, |
6aa8b732 | 1663 | .set_cr0 = svm_set_cr0, |
6aa8b732 AK |
1664 | .set_cr3 = svm_set_cr3, |
1665 | .set_cr4 = svm_set_cr4, | |
1666 | .set_efer = svm_set_efer, | |
1667 | .get_idt = svm_get_idt, | |
1668 | .set_idt = svm_set_idt, | |
1669 | .get_gdt = svm_get_gdt, | |
1670 | .set_gdt = svm_set_gdt, | |
1671 | .get_dr = svm_get_dr, | |
1672 | .set_dr = svm_set_dr, | |
1673 | .cache_regs = svm_cache_regs, | |
1674 | .decache_regs = svm_decache_regs, | |
1675 | .get_rflags = svm_get_rflags, | |
1676 | .set_rflags = svm_set_rflags, | |
1677 | ||
6aa8b732 | 1678 | .tlb_flush = svm_flush_tlb, |
6aa8b732 | 1679 | |
6aa8b732 | 1680 | .run = svm_vcpu_run, |
04d2cc77 | 1681 | .handle_exit = handle_exit, |
6aa8b732 | 1682 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 1683 | .patch_hypercall = svm_patch_hypercall, |
2a8067f1 ED |
1684 | .get_irq = svm_get_irq, |
1685 | .set_irq = svm_set_irq, | |
298101da AK |
1686 | .queue_exception = svm_queue_exception, |
1687 | .exception_injected = svm_exception_injected, | |
04d2cc77 AK |
1688 | .inject_pending_irq = svm_intr_assist, |
1689 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
1690 | |
1691 | .set_tss_addr = svm_set_tss_addr, | |
6aa8b732 AK |
1692 | }; |
1693 | ||
1694 | static int __init svm_init(void) | |
1695 | { | |
cb498ea2 | 1696 | return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm), |
c16f862d | 1697 | THIS_MODULE); |
6aa8b732 AK |
1698 | } |
1699 | ||
1700 | static void __exit svm_exit(void) | |
1701 | { | |
cb498ea2 | 1702 | kvm_exit(); |
6aa8b732 AK |
1703 | } |
1704 | ||
1705 | module_init(svm_init) | |
1706 | module_exit(svm_exit) |