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KVM: Remove redundant alloc_vmcs_cpu declaration
[mirror_ubuntu-bionic-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
e7d5d76c 19#include "x86_emulate.h"
6aa8b732 20#include "vmx.h"
e495606d
AK		 21#include "segment_descriptor.h"
22
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
07031e14 27#include <linux/profile.h>
e8edc6e0 28#include <linux/sched.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
a2fa3e9f
GH		 36struct vmcs {
37 u32 revision_id;
38 u32 abort;
39 char data[0];
40};
41
42struct vcpu_vmx {
fb3f0f51 43 struct kvm_vcpu vcpu;
a2fa3e9f
GH		 44 int launched;
45 struct kvm_msr_entry *guest_msrs;
46 struct kvm_msr_entry *host_msrs;
47 int nmsrs;
48 int save_nmsrs;
49 int msr_offset_efer;
50#ifdef CONFIG_X86_64
51 int msr_offset_kernel_gs_base;
52#endif
53 struct vmcs *vmcs;
54 struct {
55 int loaded;
56 u16 fs_sel, gs_sel, ldt_sel;
57 int fs_gs_ldt_reload_needed;
58 }host_state;
59
60};
61
62static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
63{
fb3f0f51 64 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 65}
66
75880a01
AK		 67static int init_rmode_tss(struct kvm *kvm);
68
6aa8b732
AK		 69static DEFINE_PER_CPU(struct vmcs *, vmxarea);
70static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
71
fdef3ad1
HQ		 72static struct page *vmx_io_bitmap_a;
73static struct page *vmx_io_bitmap_b;
74
2cc51560 75#define EFER_SAVE_RESTORE_BITS ((u64)EFER_SCE)
6aa8b732 76
1c3d14fe 77static struct vmcs_config {
6aa8b732
AK		 78 int size;
79 int order;
80 u32 revision_id;
1c3d14fe
YS		 81 u32 pin_based_exec_ctrl;
82 u32 cpu_based_exec_ctrl;
83 u32 vmexit_ctrl;
84 u32 vmentry_ctrl;
85} vmcs_config;
6aa8b732
AK		 86
87#define VMX_SEGMENT_FIELD(seg) \
88 [VCPU_SREG_##seg] = { \
89 .selector = GUEST_##seg##_SELECTOR, \
90 .base = GUEST_##seg##_BASE, \
91 .limit = GUEST_##seg##_LIMIT, \
92 .ar_bytes = GUEST_##seg##_AR_BYTES, \
93 }
94
95static struct kvm_vmx_segment_field {
96 unsigned selector;
97 unsigned base;
98 unsigned limit;
99 unsigned ar_bytes;
100} kvm_vmx_segment_fields[] = {
101 VMX_SEGMENT_FIELD(CS),
102 VMX_SEGMENT_FIELD(DS),
103 VMX_SEGMENT_FIELD(ES),
104 VMX_SEGMENT_FIELD(FS),
105 VMX_SEGMENT_FIELD(GS),
106 VMX_SEGMENT_FIELD(SS),
107 VMX_SEGMENT_FIELD(TR),
108 VMX_SEGMENT_FIELD(LDTR),
109};
110
4d56c8a7
AK		 111/*
112 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
113 * away by decrementing the array size.
114 */
6aa8b732 115static const u32 vmx_msr_index[] = {
05b3e0c2 116#ifdef CONFIG_X86_64
6aa8b732
AK		 117 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
118#endif
119 MSR_EFER, MSR_K6_STAR,
120};
9d8f549d 121#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 122
a2fa3e9f
GH		 123static void load_msrs(struct kvm_msr_entry *e, int n)
124{
125 int i;
126
127 for (i = 0; i < n; ++i)
128 wrmsrl(e[i].index, e[i].data);
129}
130
131static void save_msrs(struct kvm_msr_entry *e, int n)
132{
133 int i;
134
135 for (i = 0; i < n; ++i)
136 rdmsrl(e[i].index, e[i].data);
137}
138
139static inline u64 msr_efer_save_restore_bits(struct kvm_msr_entry msr)
2cc51560
ED		 140{
141 return (u64)msr.data & EFER_SAVE_RESTORE_BITS;
142}
143
8b9cf98c 144static inline int msr_efer_need_save_restore(struct vcpu_vmx *vmx)
2cc51560 145{
a2fa3e9f
GH		 146 int efer_offset = vmx->msr_offset_efer;
147 return msr_efer_save_restore_bits(vmx->host_msrs[efer_offset]) !=
148 msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560
ED		 149}
150
6aa8b732
AK		 151static inline int is_page_fault(u32 intr_info)
152{
153 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
154 INTR_INFO_VALID_MASK)) ==
155 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
156}
157
2ab455cc
AL		 158static inline int is_no_device(u32 intr_info)
159{
160 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
161 INTR_INFO_VALID_MASK)) ==
162 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
163}
164
6aa8b732
AK		 165static inline int is_external_interrupt(u32 intr_info)
166{
167 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
168 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
169}
170
8b9cf98c 171static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 172{
173 int i;
174
a2fa3e9f
GH		 175 for (i = 0; i < vmx->nmsrs; ++i)
176 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 177 return i;
178 return -1;
179}
180
8b9cf98c 181static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 182{
183 int i;
184
8b9cf98c 185 i = __find_msr_index(vmx, msr);
a75beee6 186 if (i >= 0)
a2fa3e9f 187 return &vmx->guest_msrs[i];
8b6d44c7 188 return NULL;
7725f0ba
AK		 189}
190
6aa8b732
AK		 191static void vmcs_clear(struct vmcs *vmcs)
192{
193 u64 phys_addr = __pa(vmcs);
194 u8 error;
195
196 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
197 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
198 : "cc", "memory");
199 if (error)
200 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
201 vmcs, phys_addr);
202}
203
204static void __vcpu_clear(void *arg)
205{
8b9cf98c 206 struct vcpu_vmx *vmx = arg;
d3b2c338 207 int cpu = raw_smp_processor_id();
6aa8b732 208
8b9cf98c 209 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 210 vmcs_clear(vmx->vmcs);
211 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 212 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 213 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 214}
215
8b9cf98c 216static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 217{
8b9cf98c
RR		 218 if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1)
219 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear,
220 vmx, 0, 1);
8d0be2b3 221 else
8b9cf98c
RR		 222 __vcpu_clear(vmx);
223 vmx->launched = 0;
8d0be2b3
AK		 224}
225
6aa8b732
AK		 226static unsigned long vmcs_readl(unsigned long field)
227{
228 unsigned long value;
229
230 asm volatile (ASM_VMX_VMREAD_RDX_RAX
231 : "=a"(value) : "d"(field) : "cc");
232 return value;
233}
234
235static u16 vmcs_read16(unsigned long field)
236{
237 return vmcs_readl(field);
238}
239
240static u32 vmcs_read32(unsigned long field)
241{
242 return vmcs_readl(field);
243}
244
245static u64 vmcs_read64(unsigned long field)
246{
05b3e0c2 247#ifdef CONFIG_X86_64
6aa8b732
AK		 248 return vmcs_readl(field);
249#else
250 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
251#endif
252}
253
e52de1b8
AK		 254static noinline void vmwrite_error(unsigned long field, unsigned long value)
255{
256 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
257 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
258 dump_stack();
259}
260
6aa8b732
AK		 261static void vmcs_writel(unsigned long field, unsigned long value)
262{
263 u8 error;
264
265 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
266 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 267 if (unlikely(error))
268 vmwrite_error(field, value);
6aa8b732
AK		 269}
270
271static void vmcs_write16(unsigned long field, u16 value)
272{
273 vmcs_writel(field, value);
274}
275
276static void vmcs_write32(unsigned long field, u32 value)
277{
278 vmcs_writel(field, value);
279}
280
281static void vmcs_write64(unsigned long field, u64 value)
282{
05b3e0c2 283#ifdef CONFIG_X86_64
6aa8b732
AK		 284 vmcs_writel(field, value);
285#else
286 vmcs_writel(field, value);
287 asm volatile ("");
288 vmcs_writel(field+1, value >> 32);
289#endif
290}
291
2ab455cc
AL		 292static void vmcs_clear_bits(unsigned long field, u32 mask)
293{
294 vmcs_writel(field, vmcs_readl(field) & ~mask);
295}
296
297static void vmcs_set_bits(unsigned long field, u32 mask)
298{
299 vmcs_writel(field, vmcs_readl(field) | mask);
300}
301
abd3f2d6
AK		 302static void update_exception_bitmap(struct kvm_vcpu *vcpu)
303{
304 u32 eb;
305
306 eb = 1u << PF_VECTOR;
307 if (!vcpu->fpu_active)
308 eb |= 1u << NM_VECTOR;
309 if (vcpu->guest_debug.enabled)
310 eb |= 1u << 1;
311 if (vcpu->rmode.active)
312 eb = ~0;
313 vmcs_write32(EXCEPTION_BITMAP, eb);
314}
315
33ed6329
AK		 316static void reload_tss(void)
317{
318#ifndef CONFIG_X86_64
319
320 /*
321 * VT restores TR but not its size. Useless.
322 */
323 struct descriptor_table gdt;
324 struct segment_descriptor *descs;
325
326 get_gdt(&gdt);
327 descs = (void *)gdt.base;
328 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
329 load_TR_desc();
330#endif
331}
332
8b9cf98c 333static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560
ED		 334{
335 u64 trans_efer;
a2fa3e9f 336 int efer_offset = vmx->msr_offset_efer;
2cc51560 337
a2fa3e9f 338 trans_efer = vmx->host_msrs[efer_offset].data;
2cc51560 339 trans_efer &= ~EFER_SAVE_RESTORE_BITS;
a2fa3e9f 340 trans_efer |= msr_efer_save_restore_bits(vmx->guest_msrs[efer_offset]);
2cc51560 341 wrmsrl(MSR_EFER, trans_efer);
8b9cf98c 342 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 343}
344
8b9cf98c 345static void vmx_save_host_state(struct vcpu_vmx *vmx)
33ed6329 346{
a2fa3e9f 347 if (vmx->host_state.loaded)
33ed6329
AK		 348 return;
349
a2fa3e9f 350 vmx->host_state.loaded = 1;
33ed6329
AK		 351 /*
352 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
353 * allow segment selectors with cpl > 0 or ti == 1.
354 */
a2fa3e9f
GH		 355 vmx->host_state.ldt_sel = read_ldt();
356 vmx->host_state.fs_gs_ldt_reload_needed = vmx->host_state.ldt_sel;
357 vmx->host_state.fs_sel = read_fs();
358 if (!(vmx->host_state.fs_sel & 7))
359 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
33ed6329
AK		 360 else {
361 vmcs_write16(HOST_FS_SELECTOR, 0);
a2fa3e9f 362 vmx->host_state.fs_gs_ldt_reload_needed = 1;
33ed6329 363 }
a2fa3e9f
GH		 364 vmx->host_state.gs_sel = read_gs();
365 if (!(vmx->host_state.gs_sel & 7))
366 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 367 else {
368 vmcs_write16(HOST_GS_SELECTOR, 0);
a2fa3e9f 369 vmx->host_state.fs_gs_ldt_reload_needed = 1;
33ed6329
AK		 370 }
371
372#ifdef CONFIG_X86_64
373 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
374 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
375#else
a2fa3e9f
GH		 376 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
377 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 378#endif
707c0874
AK		 379
380#ifdef CONFIG_X86_64
8b9cf98c 381 if (is_long_mode(&vmx->vcpu)) {
a2fa3e9f
GH		 382 save_msrs(vmx->host_msrs +
383 vmx->msr_offset_kernel_gs_base, 1);
707c0874
AK		 384 }
385#endif
a2fa3e9f 386 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
8b9cf98c
RR		 387 if (msr_efer_need_save_restore(vmx))
388 load_transition_efer(vmx);
33ed6329
AK		 389}
390
8b9cf98c 391static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 392{
15ad7146 393 unsigned long flags;
33ed6329 394
a2fa3e9f 395 if (!vmx->host_state.loaded)
33ed6329
AK		 396 return;
397
a2fa3e9f
GH		 398 vmx->host_state.loaded = 0;
399 if (vmx->host_state.fs_gs_ldt_reload_needed) {
400 load_ldt(vmx->host_state.ldt_sel);
401 load_fs(vmx->host_state.fs_sel);
33ed6329
AK		 402 /*
403 * If we have to reload gs, we must take care to
404 * preserve our gs base.
405 */
15ad7146 406 local_irq_save(flags);
a2fa3e9f 407 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 408#ifdef CONFIG_X86_64
409 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
410#endif
15ad7146 411 local_irq_restore(flags);
33ed6329
AK		 412
413 reload_tss();
414 }
a2fa3e9f
GH		 415 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
416 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
8b9cf98c 417 if (msr_efer_need_save_restore(vmx))
a2fa3e9f 418 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
33ed6329
AK		 419}
420
6aa8b732
AK		 421/*
422 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
423 * vcpu mutex is already taken.
424 */
15ad7146 425static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 426{
a2fa3e9f
GH		 427 struct vcpu_vmx *vmx = to_vmx(vcpu);
428 u64 phys_addr = __pa(vmx->vmcs);
7700270e 429 u64 tsc_this, delta;
6aa8b732 430
8d0be2b3 431 if (vcpu->cpu != cpu)
8b9cf98c 432 vcpu_clear(vmx);
6aa8b732 433
a2fa3e9f 434 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 435 u8 error;
436
a2fa3e9f 437 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 438 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
439 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
440 : "cc");
441 if (error)
442 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 443 vmx->vmcs, phys_addr);
6aa8b732
AK		 444 }
445
446 if (vcpu->cpu != cpu) {
447 struct descriptor_table dt;
448 unsigned long sysenter_esp;
449
450 vcpu->cpu = cpu;
451 /*
452 * Linux uses per-cpu TSS and GDT, so set these when switching
453 * processors.
454 */
455 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
456 get_gdt(&dt);
457 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
458
459 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
460 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 461
462 /*
463 * Make sure the time stamp counter is monotonous.
464 */
465 rdtscll(tsc_this);
466 delta = vcpu->host_tsc - tsc_this;
467 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 468 }
6aa8b732
AK		 469}
470
471static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
472{
8b9cf98c 473 vmx_load_host_state(to_vmx(vcpu));
7702fd1f 474 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 475}
476
5fd86fcf
AK		 477static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
478{
479 if (vcpu->fpu_active)
480 return;
481 vcpu->fpu_active = 1;
707d92fa
RR		 482 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
483 if (vcpu->cr0 & X86_CR0_TS)
484 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 485 update_exception_bitmap(vcpu);
486}
487
488static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
489{
490 if (!vcpu->fpu_active)
491 return;
492 vcpu->fpu_active = 0;
707d92fa 493 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 494 update_exception_bitmap(vcpu);
495}
496
774c47f1
AK		 497static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
498{
8b9cf98c 499 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 500}
501
6aa8b732
AK		 502static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
503{
504 return vmcs_readl(GUEST_RFLAGS);
505}
506
507static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
508{
509 vmcs_writel(GUEST_RFLAGS, rflags);
510}
511
512static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
513{
514 unsigned long rip;
515 u32 interruptibility;
516
517 rip = vmcs_readl(GUEST_RIP);
518 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
519 vmcs_writel(GUEST_RIP, rip);
520
521 /*
522 * We emulated an instruction, so temporary interrupt blocking
523 * should be removed, if set.
524 */
525 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
526 if (interruptibility & 3)
527 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
528 interruptibility & ~3);
c1150d8c 529 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 530}
531
532static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
533{
534 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
535 vmcs_readl(GUEST_RIP));
536 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
537 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
538 GP_VECTOR |
539 INTR_TYPE_EXCEPTION |
540 INTR_INFO_DELIEVER_CODE_MASK |
541 INTR_INFO_VALID_MASK);
542}
543
a75beee6
ED		 544/*
545 * Swap MSR entry in host/guest MSR entry array.
546 */
8b9cf98c 547static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 548{
a2fa3e9f
GH		 549 struct kvm_msr_entry tmp;
550
551 tmp = vmx->guest_msrs[to];
552 vmx->guest_msrs[to] = vmx->guest_msrs[from];
553 vmx->guest_msrs[from] = tmp;
554 tmp = vmx->host_msrs[to];
555 vmx->host_msrs[to] = vmx->host_msrs[from];
556 vmx->host_msrs[from] = tmp;
a75beee6
ED		 557}
558
e38aea3e
AK		 559/*
560 * Set up the vmcs to automatically save and restore system
561 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
562 * mode, as fiddling with msrs is very expensive.
563 */
8b9cf98c 564static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 565{
2cc51560 566 int save_nmsrs;
e38aea3e 567
a75beee6
ED		 568 save_nmsrs = 0;
569#ifdef CONFIG_X86_64
8b9cf98c 570 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 571 int index;
572
8b9cf98c 573 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 574 if (index >= 0)
8b9cf98c
RR		 575 move_msr_up(vmx, index, save_nmsrs++);
576 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 577 if (index >= 0)
8b9cf98c
RR		 578 move_msr_up(vmx, index, save_nmsrs++);
579 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 580 if (index >= 0)
8b9cf98c
RR		 581 move_msr_up(vmx, index, save_nmsrs++);
582 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 583 if (index >= 0)
8b9cf98c 584 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 585 /*
586 * MSR_K6_STAR is only needed on long mode guests, and only
587 * if efer.sce is enabled.
588 */
8b9cf98c
RR		 589 index = __find_msr_index(vmx, MSR_K6_STAR);
590 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
591 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 592 }
593#endif
a2fa3e9f 594 vmx->save_nmsrs = save_nmsrs;
e38aea3e 595
4d56c8a7 596#ifdef CONFIG_X86_64
a2fa3e9f 597 vmx->msr_offset_kernel_gs_base =
8b9cf98c 598 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 599#endif
8b9cf98c 600 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 601}
602
6aa8b732
AK		 603/*
604 * reads and returns guest's timestamp counter "register"
605 * guest_tsc = host_tsc + tsc_offset -- 21.3
606 */
607static u64 guest_read_tsc(void)
608{
609 u64 host_tsc, tsc_offset;
610
611 rdtscll(host_tsc);
612 tsc_offset = vmcs_read64(TSC_OFFSET);
613 return host_tsc + tsc_offset;
614}
615
616/*
617 * writes 'guest_tsc' into guest's timestamp counter "register"
618 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
619 */
620static void guest_write_tsc(u64 guest_tsc)
621{
622 u64 host_tsc;
623
624 rdtscll(host_tsc);
625 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
626}
627
6aa8b732
AK		 628/*
629 * Reads an msr value (of 'msr_index') into 'pdata'.
630 * Returns 0 on success, non-0 otherwise.
631 * Assumes vcpu_load() was already called.
632 */
633static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
634{
635 u64 data;
a2fa3e9f 636 struct kvm_msr_entry *msr;
6aa8b732
AK		 637
638 if (!pdata) {
639 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
640 return -EINVAL;
641 }
642
643 switch (msr_index) {
05b3e0c2 644#ifdef CONFIG_X86_64
6aa8b732
AK		 645 case MSR_FS_BASE:
646 data = vmcs_readl(GUEST_FS_BASE);
647 break;
648 case MSR_GS_BASE:
649 data = vmcs_readl(GUEST_GS_BASE);
650 break;
651 case MSR_EFER:
3bab1f5d 652 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 653#endif
654 case MSR_IA32_TIME_STAMP_COUNTER:
655 data = guest_read_tsc();
656 break;
657 case MSR_IA32_SYSENTER_CS:
658 data = vmcs_read32(GUEST_SYSENTER_CS);
659 break;
660 case MSR_IA32_SYSENTER_EIP:
f5b42c33 661 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 662 break;
663 case MSR_IA32_SYSENTER_ESP:
f5b42c33 664 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 665 break;
6aa8b732 666 default:
8b9cf98c 667 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 668 if (msr) {
669 data = msr->data;
670 break;
6aa8b732 671 }
3bab1f5d 672 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 673 }
674
675 *pdata = data;
676 return 0;
677}
678
679/*
680 * Writes msr value into into the appropriate "register".
681 * Returns 0 on success, non-0 otherwise.
682 * Assumes vcpu_load() was already called.
683 */
684static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
685{
a2fa3e9f
GH		 686 struct vcpu_vmx *vmx = to_vmx(vcpu);
687 struct kvm_msr_entry *msr;
2cc51560
ED		 688 int ret = 0;
689
6aa8b732 690 switch (msr_index) {
05b3e0c2 691#ifdef CONFIG_X86_64
3bab1f5d 692 case MSR_EFER:
2cc51560 693 ret = kvm_set_msr_common(vcpu, msr_index, data);
a2fa3e9f 694 if (vmx->host_state.loaded)
8b9cf98c 695 load_transition_efer(vmx);
2cc51560 696 break;
6aa8b732
AK		 697 case MSR_FS_BASE:
698 vmcs_writel(GUEST_FS_BASE, data);
699 break;
700 case MSR_GS_BASE:
701 vmcs_writel(GUEST_GS_BASE, data);
702 break;
703#endif
704 case MSR_IA32_SYSENTER_CS:
705 vmcs_write32(GUEST_SYSENTER_CS, data);
706 break;
707 case MSR_IA32_SYSENTER_EIP:
f5b42c33 708 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 709 break;
710 case MSR_IA32_SYSENTER_ESP:
f5b42c33 711 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 712 break;
d27d4aca 713 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 714 guest_write_tsc(data);
715 break;
6aa8b732 716 default:
8b9cf98c 717 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 718 if (msr) {
719 msr->data = data;
a2fa3e9f
GH		 720 if (vmx->host_state.loaded)
721 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 722 break;
6aa8b732 723 }
2cc51560 724 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 725 }
726
2cc51560 727 return ret;
6aa8b732
AK		 728}
729
730/*
731 * Sync the rsp and rip registers into the vcpu structure. This allows
732 * registers to be accessed by indexing vcpu->regs.
733 */
734static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
735{
736 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
737 vcpu->rip = vmcs_readl(GUEST_RIP);
738}
739
740/*
741 * Syncs rsp and rip back into the vmcs. Should be called after possible
742 * modification.
743 */
744static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
745{
746 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
747 vmcs_writel(GUEST_RIP, vcpu->rip);
748}
749
750static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
751{
752 unsigned long dr7 = 0x400;
6aa8b732
AK		 753 int old_singlestep;
754
6aa8b732
AK		 755 old_singlestep = vcpu->guest_debug.singlestep;
756
757 vcpu->guest_debug.enabled = dbg->enabled;
758 if (vcpu->guest_debug.enabled) {
759 int i;
760
761 dr7 |= 0x200; /* exact */
762 for (i = 0; i < 4; ++i) {
763 if (!dbg->breakpoints[i].enabled)
764 continue;
765 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
766 dr7 |= 2 << (i*2); /* global enable */
767 dr7 |= 0 << (i*4+16); /* execution breakpoint */
768 }
769
6aa8b732 770 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 771 } else
6aa8b732 772 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 773
774 if (old_singlestep && !vcpu->guest_debug.singlestep) {
775 unsigned long flags;
776
777 flags = vmcs_readl(GUEST_RFLAGS);
778 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
779 vmcs_writel(GUEST_RFLAGS, flags);
780 }
781
abd3f2d6 782 update_exception_bitmap(vcpu);
6aa8b732
AK		 783 vmcs_writel(GUEST_DR7, dr7);
784
785 return 0;
786}
787
788static __init int cpu_has_kvm_support(void)
789{
790 unsigned long ecx = cpuid_ecx(1);
791 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
792}
793
794static __init int vmx_disabled_by_bios(void)
795{
796 u64 msr;
797
798 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 799 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
800 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
801 == MSR_IA32_FEATURE_CONTROL_LOCKED;
802 /* locked but not enabled */
6aa8b732
AK		 803}
804
774c47f1 805static void hardware_enable(void *garbage)
6aa8b732
AK		 806{
807 int cpu = raw_smp_processor_id();
808 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
809 u64 old;
810
811 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 812 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
813 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
814 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
815 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 816 /* enable and lock */
62b3ffb8
YS		 817 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
818 MSR_IA32_FEATURE_CONTROL_LOCKED |
819 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 820 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 821 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
822 : "memory", "cc");
823}
824
825static void hardware_disable(void *garbage)
826{
827 asm volatile (ASM_VMX_VMXOFF : : : "cc");
828}
829
1c3d14fe
YS		 830static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
831 u32 msr, u32* result)
832{
833 u32 vmx_msr_low, vmx_msr_high;
834 u32 ctl = ctl_min | ctl_opt;
835
836 rdmsr(msr, vmx_msr_low, vmx_msr_high);
837
838 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
839 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
840
841 /* Ensure minimum (required) set of control bits are supported. */
842 if (ctl_min & ~ctl)
002c7f7c 843 return -EIO;
1c3d14fe
YS		 844
845 *result = ctl;
846 return 0;
847}
848
002c7f7c 849static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 850{
851 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 852 u32 min, opt;
853 u32 _pin_based_exec_control = 0;
854 u32 _cpu_based_exec_control = 0;
855 u32 _vmexit_control = 0;
856 u32 _vmentry_control = 0;
857
858 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
859 opt = 0;
860 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
861 &_pin_based_exec_control) < 0)
002c7f7c 862 return -EIO;
1c3d14fe
YS		 863
864 min = CPU_BASED_HLT_EXITING |
865#ifdef CONFIG_X86_64
866 CPU_BASED_CR8_LOAD_EXITING |
867 CPU_BASED_CR8_STORE_EXITING |
868#endif
869 CPU_BASED_USE_IO_BITMAPS |
870 CPU_BASED_MOV_DR_EXITING |
871 CPU_BASED_USE_TSC_OFFSETING;
872 opt = 0;
873 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
874 &_cpu_based_exec_control) < 0)
002c7f7c 875 return -EIO;
1c3d14fe
YS		 876
877 min = 0;
878#ifdef CONFIG_X86_64
879 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
880#endif
881 opt = 0;
882 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
883 &_vmexit_control) < 0)
002c7f7c 884 return -EIO;
1c3d14fe
YS		 885
886 min = opt = 0;
887 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
888 &_vmentry_control) < 0)
002c7f7c 889 return -EIO;
6aa8b732 890
c68876fd 891 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 892
893 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
894 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 895 return -EIO;
1c3d14fe
YS		 896
897#ifdef CONFIG_X86_64
898 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
899 if (vmx_msr_high & (1u<<16))
002c7f7c 900 return -EIO;
1c3d14fe
YS		 901#endif
902
903 /* Require Write-Back (WB) memory type for VMCS accesses. */
904 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 905 return -EIO;
1c3d14fe 906
002c7f7c
YS		 907 vmcs_conf->size = vmx_msr_high & 0x1fff;
908 vmcs_conf->order = get_order(vmcs_config.size);
909 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 910
002c7f7c
YS		 911 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
912 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
913 vmcs_conf->vmexit_ctrl = _vmexit_control;
914 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 915
916 return 0;
c68876fd 917}
6aa8b732
AK		 918
919static struct vmcs *alloc_vmcs_cpu(int cpu)
920{
921 int node = cpu_to_node(cpu);
922 struct page *pages;
923 struct vmcs *vmcs;
924
1c3d14fe 925 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 926 if (!pages)
927 return NULL;
928 vmcs = page_address(pages);
1c3d14fe
YS		 929 memset(vmcs, 0, vmcs_config.size);
930 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 931 return vmcs;
932}
933
934static struct vmcs *alloc_vmcs(void)
935{
d3b2c338 936 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 937}
938
939static void free_vmcs(struct vmcs *vmcs)
940{
1c3d14fe 941 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 942}
943
39959588 944static void free_kvm_area(void)
6aa8b732
AK		 945{
946 int cpu;
947
948 for_each_online_cpu(cpu)
949 free_vmcs(per_cpu(vmxarea, cpu));
950}
951
6aa8b732
AK		 952static __init int alloc_kvm_area(void)
953{
954 int cpu;
955
956 for_each_online_cpu(cpu) {
957 struct vmcs *vmcs;
958
959 vmcs = alloc_vmcs_cpu(cpu);
960 if (!vmcs) {
961 free_kvm_area();
962 return -ENOMEM;
963 }
964
965 per_cpu(vmxarea, cpu) = vmcs;
966 }
967 return 0;
968}
969
970static __init int hardware_setup(void)
971{
002c7f7c
YS		 972 if (setup_vmcs_config(&vmcs_config) < 0)
973 return -EIO;
6aa8b732
AK		 974 return alloc_kvm_area();
975}
976
977static __exit void hardware_unsetup(void)
978{
979 free_kvm_area();
980}
981
6aa8b732
AK		 982static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
983{
984 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
985
6af11b9e 986 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 987 vmcs_write16(sf->selector, save->selector);
988 vmcs_writel(sf->base, save->base);
989 vmcs_write32(sf->limit, save->limit);
990 vmcs_write32(sf->ar_bytes, save->ar);
991 } else {
992 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
993 << AR_DPL_SHIFT;
994 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
995 }
996}
997
998static void enter_pmode(struct kvm_vcpu *vcpu)
999{
1000 unsigned long flags;
1001
1002 vcpu->rmode.active = 0;
1003
1004 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1005 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1006 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1007
1008 flags = vmcs_readl(GUEST_RFLAGS);
1009 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
1010 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1011 vmcs_writel(GUEST_RFLAGS, flags);
1012
66aee91a
RR		 1013 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1014 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1015
1016 update_exception_bitmap(vcpu);
1017
1018 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1019 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1020 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1021 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1022
1023 vmcs_write16(GUEST_SS_SELECTOR, 0);
1024 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1025
1026 vmcs_write16(GUEST_CS_SELECTOR,
1027 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1028 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1029}
1030
1031static int rmode_tss_base(struct kvm* kvm)
1032{
1033 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1034 return base_gfn << PAGE_SHIFT;
1035}
1036
1037static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1038{
1039 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1040
1041 save->selector = vmcs_read16(sf->selector);
1042 save->base = vmcs_readl(sf->base);
1043 save->limit = vmcs_read32(sf->limit);
1044 save->ar = vmcs_read32(sf->ar_bytes);
1045 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1046 vmcs_write32(sf->limit, 0xffff);
1047 vmcs_write32(sf->ar_bytes, 0xf3);
1048}
1049
1050static void enter_rmode(struct kvm_vcpu *vcpu)
1051{
1052 unsigned long flags;
1053
1054 vcpu->rmode.active = 1;
1055
1056 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1057 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1058
1059 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1060 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1061
1062 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1063 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1064
1065 flags = vmcs_readl(GUEST_RFLAGS);
1066 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
1067
1068 flags |= IOPL_MASK | X86_EFLAGS_VM;
1069
1070 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1071 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1072 update_exception_bitmap(vcpu);
1073
1074 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1075 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1076 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1077
1078 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1079 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1080 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1081 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1082 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1083
1084 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1085 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1086 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1087 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01
AK		 1088
1089 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1090}
1091
05b3e0c2 1092#ifdef CONFIG_X86_64
6aa8b732
AK		 1093
1094static void enter_lmode(struct kvm_vcpu *vcpu)
1095{
1096 u32 guest_tr_ar;
1097
1098 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1099 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1100 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1101 __FUNCTION__);
1102 vmcs_write32(GUEST_TR_AR_BYTES,
1103 (guest_tr_ar & ~AR_TYPE_MASK)
1104 | AR_TYPE_BUSY_64_TSS);
1105 }
1106
1107 vcpu->shadow_efer |= EFER_LMA;
1108
8b9cf98c 1109 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1110 vmcs_write32(VM_ENTRY_CONTROLS,
1111 vmcs_read32(VM_ENTRY_CONTROLS)
1112 | VM_ENTRY_CONTROLS_IA32E_MASK);
1113}
1114
1115static void exit_lmode(struct kvm_vcpu *vcpu)
1116{
1117 vcpu->shadow_efer &= ~EFER_LMA;
1118
1119 vmcs_write32(VM_ENTRY_CONTROLS,
1120 vmcs_read32(VM_ENTRY_CONTROLS)
1121 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
1122}
1123
1124#endif
1125
25c4c276 1126static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1127{
399badf3
AK		 1128 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1129 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1130}
1131
6aa8b732
AK		 1132static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1133{
5fd86fcf
AK		 1134 vmx_fpu_deactivate(vcpu);
1135
707d92fa 1136 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1137 enter_pmode(vcpu);
1138
707d92fa 1139 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1140 enter_rmode(vcpu);
1141
05b3e0c2 1142#ifdef CONFIG_X86_64
6aa8b732 1143 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1144 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1145 enter_lmode(vcpu);
707d92fa 1146 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1147 exit_lmode(vcpu);
1148 }
1149#endif
1150
1151 vmcs_writel(CR0_READ_SHADOW, cr0);
1152 vmcs_writel(GUEST_CR0,
1153 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1154 vcpu->cr0 = cr0;
5fd86fcf 1155
707d92fa 1156 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1157 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1158}
1159
6aa8b732
AK		 1160static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1161{
1162 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1163 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1164 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1165}
1166
1167static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1168{
1169 vmcs_writel(CR4_READ_SHADOW, cr4);
1170 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1171 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1172 vcpu->cr4 = cr4;
1173}
1174
05b3e0c2 1175#ifdef CONFIG_X86_64
6aa8b732
AK		 1176
1177static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1178{
8b9cf98c
RR		 1179 struct vcpu_vmx *vmx = to_vmx(vcpu);
1180 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1181
1182 vcpu->shadow_efer = efer;
1183 if (efer & EFER_LMA) {
1184 vmcs_write32(VM_ENTRY_CONTROLS,
1185 vmcs_read32(VM_ENTRY_CONTROLS) |
1186 VM_ENTRY_CONTROLS_IA32E_MASK);
1187 msr->data = efer;
1188
1189 } else {
1190 vmcs_write32(VM_ENTRY_CONTROLS,
1191 vmcs_read32(VM_ENTRY_CONTROLS) &
1192 ~VM_ENTRY_CONTROLS_IA32E_MASK);
1193
1194 msr->data = efer & ~EFER_LME;
1195 }
8b9cf98c 1196 setup_msrs(vmx);
6aa8b732
AK		 1197}
1198
1199#endif
1200
1201static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1202{
1203 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1204
1205 return vmcs_readl(sf->base);
1206}
1207
1208static void vmx_get_segment(struct kvm_vcpu *vcpu,
1209 struct kvm_segment *var, int seg)
1210{
1211 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1212 u32 ar;
1213
1214 var->base = vmcs_readl(sf->base);
1215 var->limit = vmcs_read32(sf->limit);
1216 var->selector = vmcs_read16(sf->selector);
1217 ar = vmcs_read32(sf->ar_bytes);
1218 if (ar & AR_UNUSABLE_MASK)
1219 ar = 0;
1220 var->type = ar & 15;
1221 var->s = (ar >> 4) & 1;
1222 var->dpl = (ar >> 5) & 3;
1223 var->present = (ar >> 7) & 1;
1224 var->avl = (ar >> 12) & 1;
1225 var->l = (ar >> 13) & 1;
1226 var->db = (ar >> 14) & 1;
1227 var->g = (ar >> 15) & 1;
1228 var->unusable = (ar >> 16) & 1;
1229}
1230
653e3108 1231static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1232{
6aa8b732
AK		 1233 u32 ar;
1234
653e3108 1235 if (var->unusable)
6aa8b732
AK		 1236 ar = 1 << 16;
1237 else {
1238 ar = var->type & 15;
1239 ar |= (var->s & 1) << 4;
1240 ar |= (var->dpl & 3) << 5;
1241 ar |= (var->present & 1) << 7;
1242 ar |= (var->avl & 1) << 12;
1243 ar |= (var->l & 1) << 13;
1244 ar |= (var->db & 1) << 14;
1245 ar |= (var->g & 1) << 15;
1246 }
f7fbf1fd
UL		 1247 if (ar == 0) /* a 0 value means unusable */
1248 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1249
1250 return ar;
1251}
1252
1253static void vmx_set_segment(struct kvm_vcpu *vcpu,
1254 struct kvm_segment *var, int seg)
1255{
1256 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1257 u32 ar;
1258
1259 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1260 vcpu->rmode.tr.selector = var->selector;
1261 vcpu->rmode.tr.base = var->base;
1262 vcpu->rmode.tr.limit = var->limit;
1263 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1264 return;
1265 }
1266 vmcs_writel(sf->base, var->base);
1267 vmcs_write32(sf->limit, var->limit);
1268 vmcs_write16(sf->selector, var->selector);
1269 if (vcpu->rmode.active && var->s) {
1270 /*
1271 * Hack real-mode segments into vm86 compatibility.
1272 */
1273 if (var->base == 0xffff0000 && var->selector == 0xf000)
1274 vmcs_writel(sf->base, 0xf0000);
1275 ar = 0xf3;
1276 } else
1277 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1278 vmcs_write32(sf->ar_bytes, ar);
1279}
1280
6aa8b732
AK		 1281static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1282{
1283 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1284
1285 *db = (ar >> 14) & 1;
1286 *l = (ar >> 13) & 1;
1287}
1288
1289static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1290{
1291 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1292 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1293}
1294
1295static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1296{
1297 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1298 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1299}
1300
1301static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1302{
1303 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1304 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1305}
1306
1307static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1308{
1309 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1310 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1311}
1312
1313static int init_rmode_tss(struct kvm* kvm)
1314{
1315 struct page *p1, *p2, *p3;
1316 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1317 char *page;
1318
954bbbc2
AK		 1319 p1 = gfn_to_page(kvm, fn++);
1320 p2 = gfn_to_page(kvm, fn++);
1321 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1322
1323 if (!p1 || !p2 || !p3) {
1324 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1325 return 0;
1326 }
1327
1328 page = kmap_atomic(p1, KM_USER0);
a3870c47 1329 clear_page(page);
6aa8b732
AK		 1330 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1331 kunmap_atomic(page, KM_USER0);
1332
1333 page = kmap_atomic(p2, KM_USER0);
a3870c47 1334 clear_page(page);
6aa8b732
AK		 1335 kunmap_atomic(page, KM_USER0);
1336
1337 page = kmap_atomic(p3, KM_USER0);
a3870c47 1338 clear_page(page);
6aa8b732
AK		 1339 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1340 kunmap_atomic(page, KM_USER0);
1341
1342 return 1;
1343}
1344
6aa8b732
AK		 1345static void seg_setup(int seg)
1346{
1347 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1348
1349 vmcs_write16(sf->selector, 0);
1350 vmcs_writel(sf->base, 0);
1351 vmcs_write32(sf->limit, 0xffff);
1352 vmcs_write32(sf->ar_bytes, 0x93);
1353}
1354
1355/*
1356 * Sets up the vmcs for emulated real mode.
1357 */
8b9cf98c 1358static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1359{
1360 u32 host_sysenter_cs;
1361 u32 junk;
1362 unsigned long a;
1363 struct descriptor_table dt;
1364 int i;
1365 int ret = 0;
cd2276a7 1366 unsigned long kvm_vmx_return;
6aa8b732 1367
8b9cf98c 1368 if (!init_rmode_tss(vmx->vcpu.kvm)) {
6aa8b732
AK		 1369 ret = -ENOMEM;
1370 goto out;
1371 }
1372
8b9cf98c
RR		 1373 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1374 vmx->vcpu.cr8 = 0;
1375 vmx->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1376 if (vmx->vcpu.vcpu_id == 0)
1377 vmx->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
6aa8b732 1378
8b9cf98c 1379 fx_init(&vmx->vcpu);
6aa8b732
AK		 1380
1381 /*
1382 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1383 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1384 */
1385 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1386 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1387 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1388 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1389
1390 seg_setup(VCPU_SREG_DS);
1391 seg_setup(VCPU_SREG_ES);
1392 seg_setup(VCPU_SREG_FS);
1393 seg_setup(VCPU_SREG_GS);
1394 seg_setup(VCPU_SREG_SS);
1395
1396 vmcs_write16(GUEST_TR_SELECTOR, 0);
1397 vmcs_writel(GUEST_TR_BASE, 0);
1398 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1399 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1400
1401 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1402 vmcs_writel(GUEST_LDTR_BASE, 0);
1403 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1404 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1405
1406 vmcs_write32(GUEST_SYSENTER_CS, 0);
1407 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1408 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1409
1410 vmcs_writel(GUEST_RFLAGS, 0x02);
1411 vmcs_writel(GUEST_RIP, 0xfff0);
1412 vmcs_writel(GUEST_RSP, 0);
1413
6aa8b732
AK		 1414 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1415 vmcs_writel(GUEST_DR7, 0x400);
1416
1417 vmcs_writel(GUEST_GDTR_BASE, 0);
1418 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1419
1420 vmcs_writel(GUEST_IDTR_BASE, 0);
1421 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1422
1423 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1424 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1425 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1426
1427 /* I/O */
fdef3ad1
HQ		 1428 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1429 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1430
1431 guest_write_tsc(0);
1432
1433 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1434
1435 /* Special registers */
1436 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1437
1438 /* Control */
1c3d14fe
YS		 1439 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1440 vmcs_config.pin_based_exec_ctrl);
1441 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1442 vmcs_config.cpu_based_exec_ctrl);
6aa8b732 1443
6aa8b732
AK		 1444 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1445 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1446 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1447
1448 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1449 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1450 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1451
1452 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1453 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1454 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1455 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1456 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1457 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1458#ifdef CONFIG_X86_64
6aa8b732
AK		 1459 rdmsrl(MSR_FS_BASE, a);
1460 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1461 rdmsrl(MSR_GS_BASE, a);
1462 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1463#else
1464 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1465 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1466#endif
1467
1468 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1469
1470 get_idt(&dt);
1471 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1472
cd2276a7
AK		 1473 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1474 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1475 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1476 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1477 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1478
1479 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1480 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1481 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1482 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1483 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1484 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1485
6aa8b732
AK		 1486 for (i = 0; i < NR_VMX_MSR; ++i) {
1487 u32 index = vmx_msr_index[i];
1488 u32 data_low, data_high;
1489 u64 data;
a2fa3e9f 1490 int j = vmx->nmsrs;
6aa8b732
AK		 1491
1492 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1493 continue;
432bd6cb
AK		 1494 if (wrmsr_safe(index, data_low, data_high) < 0)
1495 continue;
6aa8b732 1496 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1497 vmx->host_msrs[j].index = index;
1498 vmx->host_msrs[j].reserved = 0;
1499 vmx->host_msrs[j].data = data;
1500 vmx->guest_msrs[j] = vmx->host_msrs[j];
1501 ++vmx->nmsrs;
6aa8b732 1502 }
6aa8b732 1503
8b9cf98c 1504 setup_msrs(vmx);
e38aea3e 1505
1c3d14fe 1506 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1507
1508 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1509 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1510
6aa8b732
AK		 1511 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1512
3b99ab24 1513#ifdef CONFIG_X86_64
6aa8b732
AK		 1514 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1515 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1516#endif
6aa8b732 1517
25c4c276 1518 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1519 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1520
8b9cf98c
RR		 1521 vmx->vcpu.cr0 = 0x60000010;
1522 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1523 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1524#ifdef CONFIG_X86_64
8b9cf98c 1525 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1526#endif
8b9cf98c
RR		 1527 vmx_fpu_activate(&vmx->vcpu);
1528 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1529
1530 return 0;
1531
6aa8b732
AK		 1532out:
1533 return ret;
1534}
1535
1536static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1537{
1538 u16 ent[2];
1539 u16 cs;
1540 u16 ip;
1541 unsigned long flags;
1542 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1543 u16 sp = vmcs_readl(GUEST_RSP);
1544 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1545
3964994b 1546 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1547 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1548 __FUNCTION__,
1549 vmcs_readl(GUEST_RSP),
1550 vmcs_readl(GUEST_SS_BASE),
1551 vmcs_read32(GUEST_SS_LIMIT));
1552 return;
1553 }
1554
e7d5d76c
LV		 1555 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1556 X86EMUL_CONTINUE) {
6aa8b732
AK		 1557 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1558 return;
1559 }
1560
1561 flags = vmcs_readl(GUEST_RFLAGS);
1562 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1563 ip = vmcs_readl(GUEST_RIP);
1564
1565
e7d5d76c
LV		 1566 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1567 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1568 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
6aa8b732
AK		 1569 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1570 return;
1571 }
1572
1573 vmcs_writel(GUEST_RFLAGS, flags &
1574 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1575 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1576 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1577 vmcs_writel(GUEST_RIP, ent[0]);
1578 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1579}
1580
1581static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1582{
1583 int word_index = __ffs(vcpu->irq_summary);
1584 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1585 int irq = word_index * BITS_PER_LONG + bit_index;
1586
1587 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1588 if (!vcpu->irq_pending[word_index])
1589 clear_bit(word_index, &vcpu->irq_summary);
1590
1591 if (vcpu->rmode.active) {
1592 inject_rmode_irq(vcpu, irq);
1593 return;
1594 }
1595 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1596 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1597}
1598
c1150d8c
DL		 1599
1600static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1601 struct kvm_run *kvm_run)
6aa8b732 1602{
c1150d8c
DL		 1603 u32 cpu_based_vm_exec_control;
1604
1605 vcpu->interrupt_window_open =
1606 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1607 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1608
1609 if (vcpu->interrupt_window_open &&
1610 vcpu->irq_summary &&
1611 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1612 /*
c1150d8c 1613 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1614 */
1615 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1616
1617 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1618 if (!vcpu->interrupt_window_open &&
1619 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1620 /*
1621 * Interrupts blocked. Wait for unblock.
1622 */
c1150d8c
DL		 1623 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1624 else
1625 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1626 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1627}
1628
1629static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1630{
1631 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1632
1633 set_debugreg(dbg->bp[0], 0);
1634 set_debugreg(dbg->bp[1], 1);
1635 set_debugreg(dbg->bp[2], 2);
1636 set_debugreg(dbg->bp[3], 3);
1637
1638 if (dbg->singlestep) {
1639 unsigned long flags;
1640
1641 flags = vmcs_readl(GUEST_RFLAGS);
1642 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1643 vmcs_writel(GUEST_RFLAGS, flags);
1644 }
1645}
1646
1647static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1648 int vec, u32 err_code)
1649{
1650 if (!vcpu->rmode.active)
1651 return 0;
1652
b3f37707
NK		 1653 /*
1654 * Instruction with address size override prefix opcode 0x67
1655 * Cause the #SS fault with 0 error code in VM86 mode.
1656 */
1657 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
6aa8b732
AK		 1658 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1659 return 1;
1660 return 0;
1661}
1662
1663static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1664{
1665 u32 intr_info, error_code;
1666 unsigned long cr2, rip;
1667 u32 vect_info;
1668 enum emulation_result er;
e2dec939 1669 int r;
6aa8b732
AK		 1670
1671 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1672 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1673
1674 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1675 !is_page_fault(intr_info)) {
1676 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1677 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1678 }
1679
1680 if (is_external_interrupt(vect_info)) {
1681 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1682 set_bit(irq, vcpu->irq_pending);
1683 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1684 }
1685
1686 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1687 asm ("int $2");
1688 return 1;
1689 }
2ab455cc
AL		 1690
1691 if (is_no_device(intr_info)) {
5fd86fcf 1692 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1693 return 1;
1694 }
1695
6aa8b732
AK		 1696 error_code = 0;
1697 rip = vmcs_readl(GUEST_RIP);
1698 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1699 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1700 if (is_page_fault(intr_info)) {
1701 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1702
11ec2804 1703 mutex_lock(&vcpu->kvm->lock);
e2dec939
AK		 1704 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1705 if (r < 0) {
11ec2804 1706 mutex_unlock(&vcpu->kvm->lock);
e2dec939
AK		 1707 return r;
1708 }
1709 if (!r) {
11ec2804 1710 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1711 return 1;
1712 }
1713
1714 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
11ec2804 1715 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1716
1717 switch (er) {
1718 case EMULATE_DONE:
1719 return 1;
1720 case EMULATE_DO_MMIO:
1165f5fe 1721 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1722 return 0;
1723 case EMULATE_FAIL:
1724 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1725 break;
1726 default:
1727 BUG();
1728 }
1729 }
1730
1731 if (vcpu->rmode.active &&
1732 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1733 error_code)) {
1734 if (vcpu->halt_request) {
1735 vcpu->halt_request = 0;
1736 return kvm_emulate_halt(vcpu);
1737 }
6aa8b732 1738 return 1;
72d6e5a0 1739 }
6aa8b732
AK		 1740
1741 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1742 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1743 return 0;
1744 }
1745 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1746 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1747 kvm_run->ex.error_code = error_code;
1748 return 0;
1749}
1750
1751static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1752 struct kvm_run *kvm_run)
1753{
1165f5fe 1754 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1755 return 1;
1756}
1757
988ad74f
AK		 1758static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1759{
1760 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1761 return 0;
1762}
6aa8b732 1763
039576c0 1764static int get_io_count(struct kvm_vcpu *vcpu, unsigned long *count)
6aa8b732
AK		 1765{
1766 u64 inst;
1767 gva_t rip;
1768 int countr_size;
e7d5d76c 1769 int i;
6aa8b732
AK		 1770
1771 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1772 countr_size = 2;
1773 } else {
1774 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1775
1776 countr_size = (cs_ar & AR_L_MASK) ? 8:
1777 (cs_ar & AR_DB_MASK) ? 4: 2;
1778 }
1779
1780 rip = vmcs_readl(GUEST_RIP);
1781 if (countr_size != 8)
1782 rip += vmcs_readl(GUEST_CS_BASE);
1783
e7d5d76c
LV		 1784 if (emulator_read_std(rip, &inst, sizeof(inst), vcpu) !=
1785 X86EMUL_CONTINUE)
1786 return 0;
6aa8b732 1787
e7d5d76c 1788 for (i = 0; i < sizeof(inst); i++) {
6aa8b732
AK		 1789 switch (((u8*)&inst)[i]) {
1790 case 0xf0:
1791 case 0xf2:
1792 case 0xf3:
1793 case 0x2e:
1794 case 0x36:
1795 case 0x3e:
1796 case 0x26:
1797 case 0x64:
1798 case 0x65:
1799 case 0x66:
1800 break;
1801 case 0x67:
1802 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1803 default:
1804 goto done;
1805 }
1806 }
1807 return 0;
1808done:
1809 countr_size *= 8;
1810 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
039576c0 1811 //printk("cx: %lx\n", vcpu->regs[VCPU_REGS_RCX]);
6aa8b732
AK		 1812 return 1;
1813}
1814
1815static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1816{
1817 u64 exit_qualification;
039576c0
AK		 1818 int size, down, in, string, rep;
1819 unsigned port;
1820 unsigned long count;
1821 gva_t address;
6aa8b732 1822
1165f5fe 1823 ++vcpu->stat.io_exits;
6aa8b732 1824 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
039576c0
AK		 1825 in = (exit_qualification & 8) != 0;
1826 size = (exit_qualification & 7) + 1;
1827 string = (exit_qualification & 16) != 0;
1828 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1829 count = 1;
1830 rep = (exit_qualification & 32) != 0;
1831 port = exit_qualification >> 16;
1832 address = 0;
1833 if (string) {
1834 if (rep && !get_io_count(vcpu, &count))
6aa8b732 1835 return 1;
039576c0
AK		 1836 address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1837 }
1838 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1839 address, rep, port);
6aa8b732
AK		 1840}
1841
102d8325
IM		 1842static void
1843vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1844{
1845 /*
1846 * Patch in the VMCALL instruction:
1847 */
1848 hypercall[0] = 0x0f;
1849 hypercall[1] = 0x01;
1850 hypercall[2] = 0xc1;
1851 hypercall[3] = 0xc3;
1852}
1853
6aa8b732
AK		 1854static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1855{
1856 u64 exit_qualification;
1857 int cr;
1858 int reg;
1859
1860 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1861 cr = exit_qualification & 15;
1862 reg = (exit_qualification >> 8) & 15;
1863 switch ((exit_qualification >> 4) & 3) {
1864 case 0: /* mov to cr */
1865 switch (cr) {
1866 case 0:
1867 vcpu_load_rsp_rip(vcpu);
1868 set_cr0(vcpu, vcpu->regs[reg]);
1869 skip_emulated_instruction(vcpu);
1870 return 1;
1871 case 3:
1872 vcpu_load_rsp_rip(vcpu);
1873 set_cr3(vcpu, vcpu->regs[reg]);
1874 skip_emulated_instruction(vcpu);
1875 return 1;
1876 case 4:
1877 vcpu_load_rsp_rip(vcpu);
1878 set_cr4(vcpu, vcpu->regs[reg]);
1879 skip_emulated_instruction(vcpu);
1880 return 1;
1881 case 8:
1882 vcpu_load_rsp_rip(vcpu);
1883 set_cr8(vcpu, vcpu->regs[reg]);
1884 skip_emulated_instruction(vcpu);
1885 return 1;
1886 };
1887 break;
25c4c276
AL		 1888 case 2: /* clts */
1889 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1890 vmx_fpu_deactivate(vcpu);
707d92fa 1891 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1892 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1893 vmx_fpu_activate(vcpu);
25c4c276
AL		 1894 skip_emulated_instruction(vcpu);
1895 return 1;
6aa8b732
AK		 1896 case 1: /*mov from cr*/
1897 switch (cr) {
1898 case 3:
1899 vcpu_load_rsp_rip(vcpu);
1900 vcpu->regs[reg] = vcpu->cr3;
1901 vcpu_put_rsp_rip(vcpu);
1902 skip_emulated_instruction(vcpu);
1903 return 1;
1904 case 8:
6aa8b732
AK		 1905 vcpu_load_rsp_rip(vcpu);
1906 vcpu->regs[reg] = vcpu->cr8;
1907 vcpu_put_rsp_rip(vcpu);
1908 skip_emulated_instruction(vcpu);
1909 return 1;
1910 }
1911 break;
1912 case 3: /* lmsw */
1913 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1914
1915 skip_emulated_instruction(vcpu);
1916 return 1;
1917 default:
1918 break;
1919 }
1920 kvm_run->exit_reason = 0;
1921 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1922 (int)(exit_qualification >> 4) & 3, cr);
1923 return 0;
1924}
1925
1926static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1927{
1928 u64 exit_qualification;
1929 unsigned long val;
1930 int dr, reg;
1931
1932 /*
1933 * FIXME: this code assumes the host is debugging the guest.
1934 * need to deal with guest debugging itself too.
1935 */
1936 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1937 dr = exit_qualification & 7;
1938 reg = (exit_qualification >> 8) & 15;
1939 vcpu_load_rsp_rip(vcpu);
1940 if (exit_qualification & 16) {
1941 /* mov from dr */
1942 switch (dr) {
1943 case 6:
1944 val = 0xffff0ff0;
1945 break;
1946 case 7:
1947 val = 0x400;
1948 break;
1949 default:
1950 val = 0;
1951 }
1952 vcpu->regs[reg] = val;
1953 } else {
1954 /* mov to dr */
1955 }
1956 vcpu_put_rsp_rip(vcpu);
1957 skip_emulated_instruction(vcpu);
1958 return 1;
1959}
1960
1961static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1962{
06465c5a
AK		 1963 kvm_emulate_cpuid(vcpu);
1964 return 1;
6aa8b732
AK		 1965}
1966
1967static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1968{
1969 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1970 u64 data;
1971
1972 if (vmx_get_msr(vcpu, ecx, &data)) {
1973 vmx_inject_gp(vcpu, 0);
1974 return 1;
1975 }
1976
1977 /* FIXME: handling of bits 32:63 of rax, rdx */
1978 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1979 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1980 skip_emulated_instruction(vcpu);
1981 return 1;
1982}
1983
1984static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1985{
1986 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1987 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1988 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1989
1990 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1991 vmx_inject_gp(vcpu, 0);
1992 return 1;
1993 }
1994
1995 skip_emulated_instruction(vcpu);
1996 return 1;
1997}
1998
c1150d8c
DL		 1999static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2000 struct kvm_run *kvm_run)
2001{
2002 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
2003 kvm_run->cr8 = vcpu->cr8;
2004 kvm_run->apic_base = vcpu->apic_base;
2005 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
2006 vcpu->irq_summary == 0);
2007}
2008
6aa8b732
AK		 2009static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2010 struct kvm_run *kvm_run)
2011{
c1150d8c
DL		 2012 /*
2013 * If the user space waits to inject interrupts, exit as soon as
2014 * possible
2015 */
2016 if (kvm_run->request_interrupt_window &&
022a9308 2017 !vcpu->irq_summary) {
c1150d8c 2018 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2019 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2020 return 0;
2021 }
6aa8b732
AK		 2022 return 1;
2023}
2024
2025static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2026{
2027 skip_emulated_instruction(vcpu);
d3bef15f 2028 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2029}
2030
c21415e8
IM		 2031static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2032{
510043da 2033 skip_emulated_instruction(vcpu);
270fd9b9 2034 return kvm_hypercall(vcpu, kvm_run);
c21415e8
IM		 2035}
2036
6aa8b732
AK		 2037/*
2038 * The exit handlers return 1 if the exit was handled fully and guest execution
2039 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2040 * to be done to userspace and return 0.
2041 */
2042static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2043 struct kvm_run *kvm_run) = {
2044 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2045 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2046 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2047 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2048 [EXIT_REASON_CR_ACCESS] = handle_cr,
2049 [EXIT_REASON_DR_ACCESS] = handle_dr,
2050 [EXIT_REASON_CPUID] = handle_cpuid,
2051 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2052 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2053 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2054 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2055 [EXIT_REASON_VMCALL] = handle_vmcall,
6aa8b732
AK		 2056};
2057
2058static const int kvm_vmx_max_exit_handlers =
50a3485c 2059 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2060
2061/*
2062 * The guest has exited. See if we can fix it or if we need userspace
2063 * assistance.
2064 */
2065static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2066{
2067 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2068 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2069
2070 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2071 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2072 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2073 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2074 if (exit_reason < kvm_vmx_max_exit_handlers
2075 && kvm_vmx_exit_handlers[exit_reason])
2076 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2077 else {
2078 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2079 kvm_run->hw.hardware_exit_reason = exit_reason;
2080 }
2081 return 0;
2082}
2083
c1150d8c
DL		 2084/*
2085 * Check if userspace requested an interrupt window, and that the
2086 * interrupt window is open.
2087 *
2088 * No need to exit to userspace if we already have an interrupt queued.
2089 */
2090static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2091 struct kvm_run *kvm_run)
2092{
2093 return (!vcpu->irq_summary &&
2094 kvm_run->request_interrupt_window &&
2095 vcpu->interrupt_window_open &&
2096 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
2097}
2098
d9e368d6
AK		 2099static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2100{
d9e368d6
AK		 2101}
2102
6aa8b732
AK		 2103static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2104{
a2fa3e9f 2105 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2106 u8 fail;
e2dec939 2107 int r;
6aa8b732 2108
e6adf283 2109preempted:
6aa8b732
AK		 2110 if (vcpu->guest_debug.enabled)
2111 kvm_guest_debug_pre(vcpu);
2112
e6adf283 2113again:
9ae0448f
SL		 2114 r = kvm_mmu_reload(vcpu);
2115 if (unlikely(r))
2116 goto out;
2117
15ad7146
AK		 2118 preempt_disable();
2119
ff1dc794
GH		 2120 if (!vcpu->mmio_read_completed)
2121 do_interrupt_requests(vcpu, kvm_run);
2122
8b9cf98c 2123 vmx_save_host_state(vmx);
e6adf283
AK		 2124 kvm_load_guest_fpu(vcpu);
2125
2126 /*
2127 * Loading guest fpu may have cleared host cr0.ts
2128 */
2129 vmcs_writel(HOST_CR0, read_cr0());
2130
d9e368d6
AK		 2131 local_irq_disable();
2132
2133 vcpu->guest_mode = 1;
2134 if (vcpu->requests)
2135 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
2136 vmx_flush_tlb(vcpu);
2137
6aa8b732
AK		 2138 asm (
2139 /* Store host registers */
05b3e0c2 2140#ifdef CONFIG_X86_64
6aa8b732
AK		 2141 "push %%rax; push %%rbx; push %%rdx;"
2142 "push %%rsi; push %%rdi; push %%rbp;"
2143 "push %%r8; push %%r9; push %%r10; push %%r11;"
2144 "push %%r12; push %%r13; push %%r14; push %%r15;"
2145 "push %%rcx \n\t"
2146 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2147#else
2148 "pusha; push %%ecx \n\t"
2149 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2150#endif
2151 /* Check if vmlaunch of vmresume is needed */
2152 "cmp $0, %1 \n\t"
2153 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2154#ifdef CONFIG_X86_64
6aa8b732
AK		 2155 "mov %c[cr2](%3), %%rax \n\t"
2156 "mov %%rax, %%cr2 \n\t"
2157 "mov %c[rax](%3), %%rax \n\t"
2158 "mov %c[rbx](%3), %%rbx \n\t"
2159 "mov %c[rdx](%3), %%rdx \n\t"
2160 "mov %c[rsi](%3), %%rsi \n\t"
2161 "mov %c[rdi](%3), %%rdi \n\t"
2162 "mov %c[rbp](%3), %%rbp \n\t"
2163 "mov %c[r8](%3), %%r8 \n\t"
2164 "mov %c[r9](%3), %%r9 \n\t"
2165 "mov %c[r10](%3), %%r10 \n\t"
2166 "mov %c[r11](%3), %%r11 \n\t"
2167 "mov %c[r12](%3), %%r12 \n\t"
2168 "mov %c[r13](%3), %%r13 \n\t"
2169 "mov %c[r14](%3), %%r14 \n\t"
2170 "mov %c[r15](%3), %%r15 \n\t"
2171 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2172#else
2173 "mov %c[cr2](%3), %%eax \n\t"
2174 "mov %%eax, %%cr2 \n\t"
2175 "mov %c[rax](%3), %%eax \n\t"
2176 "mov %c[rbx](%3), %%ebx \n\t"
2177 "mov %c[rdx](%3), %%edx \n\t"
2178 "mov %c[rsi](%3), %%esi \n\t"
2179 "mov %c[rdi](%3), %%edi \n\t"
2180 "mov %c[rbp](%3), %%ebp \n\t"
2181 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2182#endif
2183 /* Enter guest mode */
cd2276a7 2184 "jne .Llaunched \n\t"
6aa8b732 2185 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2186 "jmp .Lkvm_vmx_return \n\t"
2187 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2188 ".Lkvm_vmx_return: "
6aa8b732 2189 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2190#ifdef CONFIG_X86_64
96958231 2191 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2192 "mov %%rax, %c[rax](%3) \n\t"
2193 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2194 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2195 "mov %%rdx, %c[rdx](%3) \n\t"
2196 "mov %%rsi, %c[rsi](%3) \n\t"
2197 "mov %%rdi, %c[rdi](%3) \n\t"
2198 "mov %%rbp, %c[rbp](%3) \n\t"
2199 "mov %%r8, %c[r8](%3) \n\t"
2200 "mov %%r9, %c[r9](%3) \n\t"
2201 "mov %%r10, %c[r10](%3) \n\t"
2202 "mov %%r11, %c[r11](%3) \n\t"
2203 "mov %%r12, %c[r12](%3) \n\t"
2204 "mov %%r13, %c[r13](%3) \n\t"
2205 "mov %%r14, %c[r14](%3) \n\t"
2206 "mov %%r15, %c[r15](%3) \n\t"
2207 "mov %%cr2, %%rax \n\t"
2208 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2209 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2210
2211 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2212 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2213 "pop %%rbp; pop %%rdi; pop %%rsi;"
2214 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2215#else
96958231 2216 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2217 "mov %%eax, %c[rax](%3) \n\t"
2218 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2219 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2220 "mov %%edx, %c[rdx](%3) \n\t"
2221 "mov %%esi, %c[rsi](%3) \n\t"
2222 "mov %%edi, %c[rdi](%3) \n\t"
2223 "mov %%ebp, %c[rbp](%3) \n\t"
2224 "mov %%cr2, %%eax \n\t"
2225 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2226 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2227
2228 "pop %%ecx; popa \n\t"
2229#endif
2230 "setbe %0 \n\t"
e0015489 2231 : "=q" (fail)
a2fa3e9f 2232 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
6aa8b732
AK		 2233 "c"(vcpu),
2234 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2235 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2236 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2237 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2238 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2239 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2240 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2241#ifdef CONFIG_X86_64
6aa8b732
AK		 2242 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2243 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2244 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2245 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2246 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2247 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2248 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2249 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2250#endif
2251 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2252 : "cc", "memory" );
2253
d9e368d6
AK		 2254 vcpu->guest_mode = 0;
2255 local_irq_enable();
2256
1165f5fe 2257 ++vcpu->stat.exits;
6aa8b732 2258
c1150d8c 2259 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2260
6aa8b732 2261 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146
AK		 2262 vmx->launched = 1;
2263
2264 preempt_enable();
6aa8b732 2265
05e0c8c3 2266 if (unlikely(fail)) {
8eb7d334
AK		 2267 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2268 kvm_run->fail_entry.hardware_entry_failure_reason
2269 = vmcs_read32(VM_INSTRUCTION_ERROR);
e2dec939 2270 r = 0;
05e0c8c3
AK		 2271 goto out;
2272 }
2273 /*
2274 * Profile KVM exit RIPs:
2275 */
2276 if (unlikely(prof_on == KVM_PROFILING))
2277 profile_hit(KVM_PROFILING, (void *)vmcs_readl(GUEST_RIP));
2278
05e0c8c3
AK		 2279 r = kvm_handle_exit(kvm_run, vcpu);
2280 if (r > 0) {
2281 /* Give scheduler a change to reschedule. */
2282 if (signal_pending(current)) {
2283 r = -EINTR;
2284 kvm_run->exit_reason = KVM_EXIT_INTR;
2285 ++vcpu->stat.signal_exits;
2286 goto out;
2287 }
2288
2289 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
2290 r = -EINTR;
2291 kvm_run->exit_reason = KVM_EXIT_INTR;
2292 ++vcpu->stat.request_irq_exits;
2293 goto out;
2294 }
2295 if (!need_resched()) {
2296 ++vcpu->stat.light_exits;
2297 goto again;
6aa8b732
AK		 2298 }
2299 }
c1150d8c 2300
e6adf283 2301out:
e6adf283
AK		 2302 if (r > 0) {
2303 kvm_resched(vcpu);
2304 goto preempted;
2305 }
2306
c1150d8c 2307 post_kvm_run_save(vcpu, kvm_run);
e2dec939 2308 return r;
6aa8b732
AK		 2309}
2310
6aa8b732
AK		 2311static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2312 unsigned long addr,
2313 u32 err_code)
2314{
2315 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2316
1165f5fe 2317 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2318
2319 if (is_page_fault(vect_info)) {
2320 printk(KERN_DEBUG "inject_page_fault: "
2321 "double fault 0x%lx @ 0x%lx\n",
2322 addr, vmcs_readl(GUEST_RIP));
2323 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2324 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2325 DF_VECTOR |
2326 INTR_TYPE_EXCEPTION |
2327 INTR_INFO_DELIEVER_CODE_MASK |
2328 INTR_INFO_VALID_MASK);
2329 return;
2330 }
2331 vcpu->cr2 = addr;
2332 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2333 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2334 PF_VECTOR |
2335 INTR_TYPE_EXCEPTION |
2336 INTR_INFO_DELIEVER_CODE_MASK |
2337 INTR_INFO_VALID_MASK);
2338
2339}
2340
2341static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2342{
a2fa3e9f
GH		 2343 struct vcpu_vmx *vmx = to_vmx(vcpu);
2344
2345 if (vmx->vmcs) {
8b9cf98c 2346 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2347 free_vmcs(vmx->vmcs);
2348 vmx->vmcs = NULL;
6aa8b732
AK		 2349 }
2350}
2351
2352static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2353{
fb3f0f51
RR		 2354 struct vcpu_vmx *vmx = to_vmx(vcpu);
2355
6aa8b732 2356 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2357 kfree(vmx->host_msrs);
2358 kfree(vmx->guest_msrs);
2359 kvm_vcpu_uninit(vcpu);
2360 kfree(vmx);
6aa8b732
AK		 2361}
2362
fb3f0f51 2363static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2364{
fb3f0f51 2365 int err;
c16f862d 2366 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2367 int cpu;
6aa8b732 2368
a2fa3e9f 2369 if (!vmx)
fb3f0f51
RR		 2370 return ERR_PTR(-ENOMEM);
2371
2372 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2373 if (err)
2374 goto free_vcpu;
965b58a5 2375
a2fa3e9f 2376 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2377 if (!vmx->guest_msrs) {
2378 err = -ENOMEM;
2379 goto uninit_vcpu;
2380 }
965b58a5 2381
a2fa3e9f
GH		 2382 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2383 if (!vmx->host_msrs)
fb3f0f51 2384 goto free_guest_msrs;
965b58a5 2385
a2fa3e9f
GH		 2386 vmx->vmcs = alloc_vmcs();
2387 if (!vmx->vmcs)
fb3f0f51 2388 goto free_msrs;
a2fa3e9f
GH		 2389
2390 vmcs_clear(vmx->vmcs);
2391
15ad7146
AK		 2392 cpu = get_cpu();
2393 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2394 err = vmx_vcpu_setup(vmx);
fb3f0f51 2395 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2396 put_cpu();
fb3f0f51
RR		 2397 if (err)
2398 goto free_vmcs;
2399
2400 return &vmx->vcpu;
2401
2402free_vmcs:
2403 free_vmcs(vmx->vmcs);
2404free_msrs:
2405 kfree(vmx->host_msrs);
2406free_guest_msrs:
2407 kfree(vmx->guest_msrs);
2408uninit_vcpu:
2409 kvm_vcpu_uninit(&vmx->vcpu);
2410free_vcpu:
a2fa3e9f 2411 kfree(vmx);
fb3f0f51 2412 return ERR_PTR(err);
6aa8b732
AK		 2413}
2414
002c7f7c
YS		 2415static void __init vmx_check_processor_compat(void *rtn)
2416{
2417 struct vmcs_config vmcs_conf;
2418
2419 *(int *)rtn = 0;
2420 if (setup_vmcs_config(&vmcs_conf) < 0)
2421 *(int *)rtn = -EIO;
2422 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2423 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2424 smp_processor_id());
2425 *(int *)rtn = -EIO;
2426 }
2427}
2428
6aa8b732
AK		 2429static struct kvm_arch_ops vmx_arch_ops = {
2430 .cpu_has_kvm_support = cpu_has_kvm_support,
2431 .disabled_by_bios = vmx_disabled_by_bios,
2432 .hardware_setup = hardware_setup,
2433 .hardware_unsetup = hardware_unsetup,
002c7f7c 2434 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2435 .hardware_enable = hardware_enable,
2436 .hardware_disable = hardware_disable,
2437
2438 .vcpu_create = vmx_create_vcpu,
2439 .vcpu_free = vmx_free_vcpu,
2440
2441 .vcpu_load = vmx_vcpu_load,
2442 .vcpu_put = vmx_vcpu_put,
774c47f1 2443 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2444
2445 .set_guest_debug = set_guest_debug,
2446 .get_msr = vmx_get_msr,
2447 .set_msr = vmx_set_msr,
2448 .get_segment_base = vmx_get_segment_base,
2449 .get_segment = vmx_get_segment,
2450 .set_segment = vmx_set_segment,
6aa8b732 2451 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2452 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2453 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2454 .set_cr3 = vmx_set_cr3,
2455 .set_cr4 = vmx_set_cr4,
05b3e0c2 2456#ifdef CONFIG_X86_64
6aa8b732
AK		 2457 .set_efer = vmx_set_efer,
2458#endif
2459 .get_idt = vmx_get_idt,
2460 .set_idt = vmx_set_idt,
2461 .get_gdt = vmx_get_gdt,
2462 .set_gdt = vmx_set_gdt,
2463 .cache_regs = vcpu_load_rsp_rip,
2464 .decache_regs = vcpu_put_rsp_rip,
2465 .get_rflags = vmx_get_rflags,
2466 .set_rflags = vmx_set_rflags,
2467
2468 .tlb_flush = vmx_flush_tlb,
2469 .inject_page_fault = vmx_inject_page_fault,
2470
2471 .inject_gp = vmx_inject_gp,
2472
2473 .run = vmx_vcpu_run,
2474 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2475 .patch_hypercall = vmx_patch_hypercall,
6aa8b732
AK		 2476};
2477
2478static int __init vmx_init(void)
2479{
fdef3ad1
HQ		 2480 void *iova;
2481 int r;
2482
2483 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2484 if (!vmx_io_bitmap_a)
2485 return -ENOMEM;
2486
2487 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2488 if (!vmx_io_bitmap_b) {
2489 r = -ENOMEM;
2490 goto out;
2491 }
2492
2493 /*
2494 * Allow direct access to the PC debug port (it is often used for I/O
2495 * delays, but the vmexits simply slow things down).
2496 */
2497 iova = kmap(vmx_io_bitmap_a);
2498 memset(iova, 0xff, PAGE_SIZE);
2499 clear_bit(0x80, iova);
cd0536d7 2500 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2501
2502 iova = kmap(vmx_io_bitmap_b);
2503 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2504 kunmap(vmx_io_bitmap_b);
fdef3ad1 2505
c16f862d 2506 r = kvm_init_arch(&vmx_arch_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2507 if (r)
2508 goto out1;
2509
2510 return 0;
2511
2512out1:
2513 __free_page(vmx_io_bitmap_b);
2514out:
2515 __free_page(vmx_io_bitmap_a);
2516 return r;
6aa8b732
AK		 2517}
2518
2519static void __exit vmx_exit(void)
2520{
fdef3ad1
HQ		 2521 __free_page(vmx_io_bitmap_b);
2522 __free_page(vmx_io_bitmap_a);
2523
6aa8b732
AK		 2524 kvm_exit_arch();
2525}
2526
2527module_init(vmx_init)
2528module_exit(vmx_exit)
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