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KVM: VMX: Further reduce efer reloads
[mirror_ubuntu-bionic-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
e7d5d76c 19#include "x86_emulate.h"
85f455f7 20#include "irq.h"
6aa8b732 21#include "vmx.h"
e495606d
AK		 22#include "segment_descriptor.h"
23
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
e495606d 29
6aa8b732 30#include <asm/io.h>
3b3be0d1 31#include <asm/desc.h>
6aa8b732 32
6aa8b732
AK		 33MODULE_AUTHOR("Qumranet");
34MODULE_LICENSE("GPL");
35
a2fa3e9f
GH		 36struct vmcs {
37 u32 revision_id;
38 u32 abort;
39 char data[0];
40};
41
42struct vcpu_vmx {
fb3f0f51 43 struct kvm_vcpu vcpu;
a2fa3e9f 44 int launched;
29bd8a78 45 u8 fail;
a2fa3e9f
GH		 46 struct kvm_msr_entry *guest_msrs;
47 struct kvm_msr_entry *host_msrs;
48 int nmsrs;
49 int save_nmsrs;
50 int msr_offset_efer;
51#ifdef CONFIG_X86_64
52 int msr_offset_kernel_gs_base;
53#endif
54 struct vmcs *vmcs;
55 struct {
56 int loaded;
57 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 58 int gs_ldt_reload_needed;
59 int fs_reload_needed;
51c6cf66 60 int guest_efer_loaded;
a2fa3e9f
GH		 61 }host_state;
62
63};
64
65static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
66{
fb3f0f51 67 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 68}
69
75880a01
AK		 70static int init_rmode_tss(struct kvm *kvm);
71
6aa8b732
AK		 72static DEFINE_PER_CPU(struct vmcs *, vmxarea);
73static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
74
fdef3ad1
HQ		 75static struct page *vmx_io_bitmap_a;
76static struct page *vmx_io_bitmap_b;
77
1c3d14fe 78static struct vmcs_config {
6aa8b732
AK		 79 int size;
80 int order;
81 u32 revision_id;
1c3d14fe
YS		 82 u32 pin_based_exec_ctrl;
83 u32 cpu_based_exec_ctrl;
84 u32 vmexit_ctrl;
85 u32 vmentry_ctrl;
86} vmcs_config;
6aa8b732
AK		 87
88#define VMX_SEGMENT_FIELD(seg) \
89 [VCPU_SREG_##seg] = { \
90 .selector = GUEST_##seg##_SELECTOR, \
91 .base = GUEST_##seg##_BASE, \
92 .limit = GUEST_##seg##_LIMIT, \
93 .ar_bytes = GUEST_##seg##_AR_BYTES, \
94 }
95
96static struct kvm_vmx_segment_field {
97 unsigned selector;
98 unsigned base;
99 unsigned limit;
100 unsigned ar_bytes;
101} kvm_vmx_segment_fields[] = {
102 VMX_SEGMENT_FIELD(CS),
103 VMX_SEGMENT_FIELD(DS),
104 VMX_SEGMENT_FIELD(ES),
105 VMX_SEGMENT_FIELD(FS),
106 VMX_SEGMENT_FIELD(GS),
107 VMX_SEGMENT_FIELD(SS),
108 VMX_SEGMENT_FIELD(TR),
109 VMX_SEGMENT_FIELD(LDTR),
110};
111
4d56c8a7
AK		 112/*
113 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
114 * away by decrementing the array size.
115 */
6aa8b732 116static const u32 vmx_msr_index[] = {
05b3e0c2 117#ifdef CONFIG_X86_64
6aa8b732
AK		 118 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
119#endif
120 MSR_EFER, MSR_K6_STAR,
121};
9d8f549d 122#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 123
a2fa3e9f
GH		 124static void load_msrs(struct kvm_msr_entry *e, int n)
125{
126 int i;
127
128 for (i = 0; i < n; ++i)
129 wrmsrl(e[i].index, e[i].data);
130}
131
132static void save_msrs(struct kvm_msr_entry *e, int n)
133{
134 int i;
135
136 for (i = 0; i < n; ++i)
137 rdmsrl(e[i].index, e[i].data);
138}
139
6aa8b732
AK		 140static inline int is_page_fault(u32 intr_info)
141{
142 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
143 INTR_INFO_VALID_MASK)) ==
144 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
145}
146
2ab455cc
AL		 147static inline int is_no_device(u32 intr_info)
148{
149 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
150 INTR_INFO_VALID_MASK)) ==
151 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
152}
153
7aa81cc0
AL		 154static inline int is_invalid_opcode(u32 intr_info)
155{
156 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
157 INTR_INFO_VALID_MASK)) ==
158 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
159}
160
6aa8b732
AK		 161static inline int is_external_interrupt(u32 intr_info)
162{
163 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
164 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
165}
166
6e5d865c
YS		 167static inline int cpu_has_vmx_tpr_shadow(void)
168{
169 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
170}
171
172static inline int vm_need_tpr_shadow(struct kvm *kvm)
173{
174 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
175}
176
8b9cf98c 177static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 178{
179 int i;
180
a2fa3e9f
GH		 181 for (i = 0; i < vmx->nmsrs; ++i)
182 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 183 return i;
184 return -1;
185}
186
8b9cf98c 187static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 188{
189 int i;
190
8b9cf98c 191 i = __find_msr_index(vmx, msr);
a75beee6 192 if (i >= 0)
a2fa3e9f 193 return &vmx->guest_msrs[i];
8b6d44c7 194 return NULL;
7725f0ba
AK		 195}
196
6aa8b732
AK		 197static void vmcs_clear(struct vmcs *vmcs)
198{
199 u64 phys_addr = __pa(vmcs);
200 u8 error;
201
202 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
203 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
204 : "cc", "memory");
205 if (error)
206 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
207 vmcs, phys_addr);
208}
209
210static void __vcpu_clear(void *arg)
211{
8b9cf98c 212 struct vcpu_vmx *vmx = arg;
d3b2c338 213 int cpu = raw_smp_processor_id();
6aa8b732 214
8b9cf98c 215 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 216 vmcs_clear(vmx->vmcs);
217 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 218 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 219 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 220}
221
8b9cf98c 222static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 223{
8b9cf98c
RR		 224 if (vmx->vcpu.cpu != raw_smp_processor_id() && vmx->vcpu.cpu != -1)
225 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear,
226 vmx, 0, 1);
8d0be2b3 227 else
8b9cf98c
RR		 228 __vcpu_clear(vmx);
229 vmx->launched = 0;
8d0be2b3
AK		 230}
231
6aa8b732
AK		 232static unsigned long vmcs_readl(unsigned long field)
233{
234 unsigned long value;
235
236 asm volatile (ASM_VMX_VMREAD_RDX_RAX
237 : "=a"(value) : "d"(field) : "cc");
238 return value;
239}
240
241static u16 vmcs_read16(unsigned long field)
242{
243 return vmcs_readl(field);
244}
245
246static u32 vmcs_read32(unsigned long field)
247{
248 return vmcs_readl(field);
249}
250
251static u64 vmcs_read64(unsigned long field)
252{
05b3e0c2 253#ifdef CONFIG_X86_64
6aa8b732
AK		 254 return vmcs_readl(field);
255#else
256 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
257#endif
258}
259
e52de1b8
AK		 260static noinline void vmwrite_error(unsigned long field, unsigned long value)
261{
262 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
263 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
264 dump_stack();
265}
266
6aa8b732
AK		 267static void vmcs_writel(unsigned long field, unsigned long value)
268{
269 u8 error;
270
271 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
272 : "=q"(error) : "a"(value), "d"(field) : "cc" );
e52de1b8
AK		 273 if (unlikely(error))
274 vmwrite_error(field, value);
6aa8b732
AK		 275}
276
277static void vmcs_write16(unsigned long field, u16 value)
278{
279 vmcs_writel(field, value);
280}
281
282static void vmcs_write32(unsigned long field, u32 value)
283{
284 vmcs_writel(field, value);
285}
286
287static void vmcs_write64(unsigned long field, u64 value)
288{
05b3e0c2 289#ifdef CONFIG_X86_64
6aa8b732
AK		 290 vmcs_writel(field, value);
291#else
292 vmcs_writel(field, value);
293 asm volatile ("");
294 vmcs_writel(field+1, value >> 32);
295#endif
296}
297
2ab455cc
AL		 298static void vmcs_clear_bits(unsigned long field, u32 mask)
299{
300 vmcs_writel(field, vmcs_readl(field) & ~mask);
301}
302
303static void vmcs_set_bits(unsigned long field, u32 mask)
304{
305 vmcs_writel(field, vmcs_readl(field) | mask);
306}
307
abd3f2d6
AK		 308static void update_exception_bitmap(struct kvm_vcpu *vcpu)
309{
310 u32 eb;
311
7aa81cc0 312 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 313 if (!vcpu->fpu_active)
314 eb |= 1u << NM_VECTOR;
315 if (vcpu->guest_debug.enabled)
316 eb |= 1u << 1;
317 if (vcpu->rmode.active)
318 eb = ~0;
319 vmcs_write32(EXCEPTION_BITMAP, eb);
320}
321
33ed6329
AK		 322static void reload_tss(void)
323{
324#ifndef CONFIG_X86_64
325
326 /*
327 * VT restores TR but not its size. Useless.
328 */
329 struct descriptor_table gdt;
330 struct segment_descriptor *descs;
331
332 get_gdt(&gdt);
333 descs = (void *)gdt.base;
334 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
335 load_TR_desc();
336#endif
337}
338
8b9cf98c 339static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 340{
a2fa3e9f 341 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 342 u64 host_efer = vmx->host_msrs[efer_offset].data;
343 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
344 u64 ignore_bits;
345
346 if (efer_offset < 0)
347 return;
348 /*
349 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
350 * outside long mode
351 */
352 ignore_bits = EFER_NX | EFER_SCE;
353#ifdef CONFIG_X86_64
354 ignore_bits |= EFER_LMA | EFER_LME;
355 /* SCE is meaningful only in long mode on Intel */
356 if (guest_efer & EFER_LMA)
357 ignore_bits &= ~(u64)EFER_SCE;
358#endif
359 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
360 return;
2cc51560 361
51c6cf66
AK		 362 vmx->host_state.guest_efer_loaded = 1;
363 guest_efer &= ~ignore_bits;
364 guest_efer |= host_efer & ignore_bits;
365 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 366 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 367}
368
51c6cf66
AK		 369static void reload_host_efer(struct vcpu_vmx *vmx)
370{
371 if (vmx->host_state.guest_efer_loaded) {
372 vmx->host_state.guest_efer_loaded = 0;
373 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
374 }
375}
376
04d2cc77 377static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 378{
04d2cc77
AK		 379 struct vcpu_vmx *vmx = to_vmx(vcpu);
380
a2fa3e9f 381 if (vmx->host_state.loaded)
33ed6329
AK		 382 return;
383
a2fa3e9f 384 vmx->host_state.loaded = 1;
33ed6329
AK		 385 /*
386 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
387 * allow segment selectors with cpl > 0 or ti == 1.
388 */
a2fa3e9f 389 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 390 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 391 vmx->host_state.fs_sel = read_fs();
152d3f2f 392 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 393 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 394 vmx->host_state.fs_reload_needed = 0;
395 } else {
33ed6329 396 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 397 vmx->host_state.fs_reload_needed = 1;
33ed6329 398 }
a2fa3e9f
GH		 399 vmx->host_state.gs_sel = read_gs();
400 if (!(vmx->host_state.gs_sel & 7))
401 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 402 else {
403 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 404 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 405 }
406
407#ifdef CONFIG_X86_64
408 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
409 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
410#else
a2fa3e9f
GH		 411 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
412 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 413#endif
707c0874
AK		 414
415#ifdef CONFIG_X86_64
8b9cf98c 416 if (is_long_mode(&vmx->vcpu)) {
a2fa3e9f
GH		 417 save_msrs(vmx->host_msrs +
418 vmx->msr_offset_kernel_gs_base, 1);
707c0874
AK		 419 }
420#endif
a2fa3e9f 421 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 422 load_transition_efer(vmx);
33ed6329
AK		 423}
424
8b9cf98c 425static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 426{
15ad7146 427 unsigned long flags;
33ed6329 428
a2fa3e9f 429 if (!vmx->host_state.loaded)
33ed6329
AK		 430 return;
431
a2fa3e9f 432 vmx->host_state.loaded = 0;
152d3f2f 433 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 434 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 435 if (vmx->host_state.gs_ldt_reload_needed) {
436 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 437 /*
438 * If we have to reload gs, we must take care to
439 * preserve our gs base.
440 */
15ad7146 441 local_irq_save(flags);
a2fa3e9f 442 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 443#ifdef CONFIG_X86_64
444 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
445#endif
15ad7146 446 local_irq_restore(flags);
33ed6329 447 }
152d3f2f 448 reload_tss();
a2fa3e9f
GH		 449 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
450 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 451 reload_host_efer(vmx);
33ed6329
AK		 452}
453
6aa8b732
AK		 454/*
455 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
456 * vcpu mutex is already taken.
457 */
15ad7146 458static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 459{
a2fa3e9f
GH		 460 struct vcpu_vmx *vmx = to_vmx(vcpu);
461 u64 phys_addr = __pa(vmx->vmcs);
7700270e 462 u64 tsc_this, delta;
6aa8b732 463
a3d7f85f 464 if (vcpu->cpu != cpu) {
8b9cf98c 465 vcpu_clear(vmx);
a3d7f85f
ED		 466 kvm_migrate_apic_timer(vcpu);
467 }
6aa8b732 468
a2fa3e9f 469 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 470 u8 error;
471
a2fa3e9f 472 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 473 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
474 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
475 : "cc");
476 if (error)
477 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 478 vmx->vmcs, phys_addr);
6aa8b732
AK		 479 }
480
481 if (vcpu->cpu != cpu) {
482 struct descriptor_table dt;
483 unsigned long sysenter_esp;
484
485 vcpu->cpu = cpu;
486 /*
487 * Linux uses per-cpu TSS and GDT, so set these when switching
488 * processors.
489 */
490 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
491 get_gdt(&dt);
492 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
493
494 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
495 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 496
497 /*
498 * Make sure the time stamp counter is monotonous.
499 */
500 rdtscll(tsc_this);
501 delta = vcpu->host_tsc - tsc_this;
502 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 503 }
6aa8b732
AK		 504}
505
506static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
507{
8b9cf98c 508 vmx_load_host_state(to_vmx(vcpu));
7702fd1f 509 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 510}
511
5fd86fcf
AK		 512static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
513{
514 if (vcpu->fpu_active)
515 return;
516 vcpu->fpu_active = 1;
707d92fa
RR		 517 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
518 if (vcpu->cr0 & X86_CR0_TS)
519 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 520 update_exception_bitmap(vcpu);
521}
522
523static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
524{
525 if (!vcpu->fpu_active)
526 return;
527 vcpu->fpu_active = 0;
707d92fa 528 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 529 update_exception_bitmap(vcpu);
530}
531
774c47f1
AK		 532static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
533{
8b9cf98c 534 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 535}
536
6aa8b732
AK		 537static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
538{
539 return vmcs_readl(GUEST_RFLAGS);
540}
541
542static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
543{
78f78268 544 if (vcpu->rmode.active)
053de044 545 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 546 vmcs_writel(GUEST_RFLAGS, rflags);
547}
548
549static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
550{
551 unsigned long rip;
552 u32 interruptibility;
553
554 rip = vmcs_readl(GUEST_RIP);
555 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
556 vmcs_writel(GUEST_RIP, rip);
557
558 /*
559 * We emulated an instruction, so temporary interrupt blocking
560 * should be removed, if set.
561 */
562 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
563 if (interruptibility & 3)
564 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
565 interruptibility & ~3);
c1150d8c 566 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 567}
568
569static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
570{
571 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
572 vmcs_readl(GUEST_RIP));
573 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
574 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
575 GP_VECTOR |
576 INTR_TYPE_EXCEPTION |
577 INTR_INFO_DELIEVER_CODE_MASK |
578 INTR_INFO_VALID_MASK);
579}
580
7aa81cc0
AL		 581static void vmx_inject_ud(struct kvm_vcpu *vcpu)
582{
583 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
584 UD_VECTOR |
585 INTR_TYPE_EXCEPTION |
586 INTR_INFO_VALID_MASK);
587}
588
a75beee6
ED		 589/*
590 * Swap MSR entry in host/guest MSR entry array.
591 */
54e11fa1 592#ifdef CONFIG_X86_64
8b9cf98c 593static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 594{
a2fa3e9f
GH		 595 struct kvm_msr_entry tmp;
596
597 tmp = vmx->guest_msrs[to];
598 vmx->guest_msrs[to] = vmx->guest_msrs[from];
599 vmx->guest_msrs[from] = tmp;
600 tmp = vmx->host_msrs[to];
601 vmx->host_msrs[to] = vmx->host_msrs[from];
602 vmx->host_msrs[from] = tmp;
a75beee6 603}
54e11fa1 604#endif
a75beee6 605
e38aea3e
AK		 606/*
607 * Set up the vmcs to automatically save and restore system
608 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
609 * mode, as fiddling with msrs is very expensive.
610 */
8b9cf98c 611static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 612{
2cc51560 613 int save_nmsrs;
e38aea3e 614
a75beee6
ED		 615 save_nmsrs = 0;
616#ifdef CONFIG_X86_64
8b9cf98c 617 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 618 int index;
619
8b9cf98c 620 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 621 if (index >= 0)
8b9cf98c
RR		 622 move_msr_up(vmx, index, save_nmsrs++);
623 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 624 if (index >= 0)
8b9cf98c
RR		 625 move_msr_up(vmx, index, save_nmsrs++);
626 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 627 if (index >= 0)
8b9cf98c
RR		 628 move_msr_up(vmx, index, save_nmsrs++);
629 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 630 if (index >= 0)
8b9cf98c 631 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 632 /*
633 * MSR_K6_STAR is only needed on long mode guests, and only
634 * if efer.sce is enabled.
635 */
8b9cf98c
RR		 636 index = __find_msr_index(vmx, MSR_K6_STAR);
637 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
638 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 639 }
640#endif
a2fa3e9f 641 vmx->save_nmsrs = save_nmsrs;
e38aea3e 642
4d56c8a7 643#ifdef CONFIG_X86_64
a2fa3e9f 644 vmx->msr_offset_kernel_gs_base =
8b9cf98c 645 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 646#endif
8b9cf98c 647 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 648}
649
6aa8b732
AK		 650/*
651 * reads and returns guest's timestamp counter "register"
652 * guest_tsc = host_tsc + tsc_offset -- 21.3
653 */
654static u64 guest_read_tsc(void)
655{
656 u64 host_tsc, tsc_offset;
657
658 rdtscll(host_tsc);
659 tsc_offset = vmcs_read64(TSC_OFFSET);
660 return host_tsc + tsc_offset;
661}
662
663/*
664 * writes 'guest_tsc' into guest's timestamp counter "register"
665 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
666 */
667static void guest_write_tsc(u64 guest_tsc)
668{
669 u64 host_tsc;
670
671 rdtscll(host_tsc);
672 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
673}
674
6aa8b732
AK		 675/*
676 * Reads an msr value (of 'msr_index') into 'pdata'.
677 * Returns 0 on success, non-0 otherwise.
678 * Assumes vcpu_load() was already called.
679 */
680static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
681{
682 u64 data;
a2fa3e9f 683 struct kvm_msr_entry *msr;
6aa8b732
AK		 684
685 if (!pdata) {
686 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
687 return -EINVAL;
688 }
689
690 switch (msr_index) {
05b3e0c2 691#ifdef CONFIG_X86_64
6aa8b732
AK		 692 case MSR_FS_BASE:
693 data = vmcs_readl(GUEST_FS_BASE);
694 break;
695 case MSR_GS_BASE:
696 data = vmcs_readl(GUEST_GS_BASE);
697 break;
698 case MSR_EFER:
3bab1f5d 699 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 700#endif
701 case MSR_IA32_TIME_STAMP_COUNTER:
702 data = guest_read_tsc();
703 break;
704 case MSR_IA32_SYSENTER_CS:
705 data = vmcs_read32(GUEST_SYSENTER_CS);
706 break;
707 case MSR_IA32_SYSENTER_EIP:
f5b42c33 708 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 709 break;
710 case MSR_IA32_SYSENTER_ESP:
f5b42c33 711 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 712 break;
6aa8b732 713 default:
8b9cf98c 714 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 715 if (msr) {
716 data = msr->data;
717 break;
6aa8b732 718 }
3bab1f5d 719 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 720 }
721
722 *pdata = data;
723 return 0;
724}
725
726/*
727 * Writes msr value into into the appropriate "register".
728 * Returns 0 on success, non-0 otherwise.
729 * Assumes vcpu_load() was already called.
730 */
731static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
732{
a2fa3e9f
GH		 733 struct vcpu_vmx *vmx = to_vmx(vcpu);
734 struct kvm_msr_entry *msr;
2cc51560
ED		 735 int ret = 0;
736
6aa8b732 737 switch (msr_index) {
05b3e0c2 738#ifdef CONFIG_X86_64
3bab1f5d 739 case MSR_EFER:
2cc51560 740 ret = kvm_set_msr_common(vcpu, msr_index, data);
51c6cf66
AK		 741 if (vmx->host_state.loaded) {
742 reload_host_efer(vmx);
8b9cf98c 743 load_transition_efer(vmx);
51c6cf66 744 }
2cc51560 745 break;
6aa8b732
AK		 746 case MSR_FS_BASE:
747 vmcs_writel(GUEST_FS_BASE, data);
748 break;
749 case MSR_GS_BASE:
750 vmcs_writel(GUEST_GS_BASE, data);
751 break;
752#endif
753 case MSR_IA32_SYSENTER_CS:
754 vmcs_write32(GUEST_SYSENTER_CS, data);
755 break;
756 case MSR_IA32_SYSENTER_EIP:
f5b42c33 757 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 758 break;
759 case MSR_IA32_SYSENTER_ESP:
f5b42c33 760 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 761 break;
d27d4aca 762 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 763 guest_write_tsc(data);
764 break;
6aa8b732 765 default:
8b9cf98c 766 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 767 if (msr) {
768 msr->data = data;
a2fa3e9f
GH		 769 if (vmx->host_state.loaded)
770 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 771 break;
6aa8b732 772 }
2cc51560 773 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 774 }
775
2cc51560 776 return ret;
6aa8b732
AK		 777}
778
779/*
780 * Sync the rsp and rip registers into the vcpu structure. This allows
781 * registers to be accessed by indexing vcpu->regs.
782 */
783static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
784{
785 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
786 vcpu->rip = vmcs_readl(GUEST_RIP);
787}
788
789/*
790 * Syncs rsp and rip back into the vmcs. Should be called after possible
791 * modification.
792 */
793static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
794{
795 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
796 vmcs_writel(GUEST_RIP, vcpu->rip);
797}
798
799static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
800{
801 unsigned long dr7 = 0x400;
6aa8b732
AK		 802 int old_singlestep;
803
6aa8b732
AK		 804 old_singlestep = vcpu->guest_debug.singlestep;
805
806 vcpu->guest_debug.enabled = dbg->enabled;
807 if (vcpu->guest_debug.enabled) {
808 int i;
809
810 dr7 |= 0x200; /* exact */
811 for (i = 0; i < 4; ++i) {
812 if (!dbg->breakpoints[i].enabled)
813 continue;
814 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
815 dr7 |= 2 << (i*2); /* global enable */
816 dr7 |= 0 << (i*4+16); /* execution breakpoint */
817 }
818
6aa8b732 819 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 820 } else
6aa8b732 821 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 822
823 if (old_singlestep && !vcpu->guest_debug.singlestep) {
824 unsigned long flags;
825
826 flags = vmcs_readl(GUEST_RFLAGS);
827 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
828 vmcs_writel(GUEST_RFLAGS, flags);
829 }
830
abd3f2d6 831 update_exception_bitmap(vcpu);
6aa8b732
AK		 832 vmcs_writel(GUEST_DR7, dr7);
833
834 return 0;
835}
836
2a8067f1
ED		 837static int vmx_get_irq(struct kvm_vcpu *vcpu)
838{
839 u32 idtv_info_field;
840
841 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
842 if (idtv_info_field & INTR_INFO_VALID_MASK) {
843 if (is_external_interrupt(idtv_info_field))
844 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
845 else
846 printk("pending exception: not handled yet\n");
847 }
848 return -1;
849}
850
6aa8b732
AK		 851static __init int cpu_has_kvm_support(void)
852{
853 unsigned long ecx = cpuid_ecx(1);
854 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
855}
856
857static __init int vmx_disabled_by_bios(void)
858{
859 u64 msr;
860
861 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 862 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
863 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
864 == MSR_IA32_FEATURE_CONTROL_LOCKED;
865 /* locked but not enabled */
6aa8b732
AK		 866}
867
774c47f1 868static void hardware_enable(void *garbage)
6aa8b732
AK		 869{
870 int cpu = raw_smp_processor_id();
871 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
872 u64 old;
873
874 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 875 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
876 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
877 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
878 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 879 /* enable and lock */
62b3ffb8
YS		 880 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
881 MSR_IA32_FEATURE_CONTROL_LOCKED |
882 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 883 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 884 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
885 : "memory", "cc");
886}
887
888static void hardware_disable(void *garbage)
889{
890 asm volatile (ASM_VMX_VMXOFF : : : "cc");
891}
892
1c3d14fe
YS		 893static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
894 u32 msr, u32* result)
895{
896 u32 vmx_msr_low, vmx_msr_high;
897 u32 ctl = ctl_min | ctl_opt;
898
899 rdmsr(msr, vmx_msr_low, vmx_msr_high);
900
901 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
902 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
903
904 /* Ensure minimum (required) set of control bits are supported. */
905 if (ctl_min & ~ctl)
002c7f7c 906 return -EIO;
1c3d14fe
YS		 907
908 *result = ctl;
909 return 0;
910}
911
002c7f7c 912static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 913{
914 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 915 u32 min, opt;
916 u32 _pin_based_exec_control = 0;
917 u32 _cpu_based_exec_control = 0;
918 u32 _vmexit_control = 0;
919 u32 _vmentry_control = 0;
920
921 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
922 opt = 0;
923 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
924 &_pin_based_exec_control) < 0)
002c7f7c 925 return -EIO;
1c3d14fe
YS		 926
927 min = CPU_BASED_HLT_EXITING |
928#ifdef CONFIG_X86_64
929 CPU_BASED_CR8_LOAD_EXITING |
930 CPU_BASED_CR8_STORE_EXITING |
931#endif
932 CPU_BASED_USE_IO_BITMAPS |
933 CPU_BASED_MOV_DR_EXITING |
934 CPU_BASED_USE_TSC_OFFSETING;
6e5d865c
YS		 935#ifdef CONFIG_X86_64
936 opt = CPU_BASED_TPR_SHADOW;
937#else
1c3d14fe 938 opt = 0;
6e5d865c 939#endif
1c3d14fe
YS		 940 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
941 &_cpu_based_exec_control) < 0)
002c7f7c 942 return -EIO;
6e5d865c
YS		 943#ifdef CONFIG_X86_64
944 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
945 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
946 ~CPU_BASED_CR8_STORE_EXITING;
947#endif
1c3d14fe
YS		 948
949 min = 0;
950#ifdef CONFIG_X86_64
951 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
952#endif
953 opt = 0;
954 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
955 &_vmexit_control) < 0)
002c7f7c 956 return -EIO;
1c3d14fe
YS		 957
958 min = opt = 0;
959 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
960 &_vmentry_control) < 0)
002c7f7c 961 return -EIO;
6aa8b732 962
c68876fd 963 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 964
965 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
966 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 967 return -EIO;
1c3d14fe
YS		 968
969#ifdef CONFIG_X86_64
970 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
971 if (vmx_msr_high & (1u<<16))
002c7f7c 972 return -EIO;
1c3d14fe
YS		 973#endif
974
975 /* Require Write-Back (WB) memory type for VMCS accesses. */
976 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 977 return -EIO;
1c3d14fe 978
002c7f7c
YS		 979 vmcs_conf->size = vmx_msr_high & 0x1fff;
980 vmcs_conf->order = get_order(vmcs_config.size);
981 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 982
002c7f7c
YS		 983 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
984 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
985 vmcs_conf->vmexit_ctrl = _vmexit_control;
986 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 987
988 return 0;
c68876fd 989}
6aa8b732
AK		 990
991static struct vmcs *alloc_vmcs_cpu(int cpu)
992{
993 int node = cpu_to_node(cpu);
994 struct page *pages;
995 struct vmcs *vmcs;
996
1c3d14fe 997 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 998 if (!pages)
999 return NULL;
1000 vmcs = page_address(pages);
1c3d14fe
YS		 1001 memset(vmcs, 0, vmcs_config.size);
1002 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1003 return vmcs;
1004}
1005
1006static struct vmcs *alloc_vmcs(void)
1007{
d3b2c338 1008 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1009}
1010
1011static void free_vmcs(struct vmcs *vmcs)
1012{
1c3d14fe 1013 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1014}
1015
39959588 1016static void free_kvm_area(void)
6aa8b732
AK		 1017{
1018 int cpu;
1019
1020 for_each_online_cpu(cpu)
1021 free_vmcs(per_cpu(vmxarea, cpu));
1022}
1023
6aa8b732
AK		 1024static __init int alloc_kvm_area(void)
1025{
1026 int cpu;
1027
1028 for_each_online_cpu(cpu) {
1029 struct vmcs *vmcs;
1030
1031 vmcs = alloc_vmcs_cpu(cpu);
1032 if (!vmcs) {
1033 free_kvm_area();
1034 return -ENOMEM;
1035 }
1036
1037 per_cpu(vmxarea, cpu) = vmcs;
1038 }
1039 return 0;
1040}
1041
1042static __init int hardware_setup(void)
1043{
002c7f7c
YS		 1044 if (setup_vmcs_config(&vmcs_config) < 0)
1045 return -EIO;
6aa8b732
AK		 1046 return alloc_kvm_area();
1047}
1048
1049static __exit void hardware_unsetup(void)
1050{
1051 free_kvm_area();
1052}
1053
6aa8b732
AK		 1054static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1055{
1056 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1057
6af11b9e 1058 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1059 vmcs_write16(sf->selector, save->selector);
1060 vmcs_writel(sf->base, save->base);
1061 vmcs_write32(sf->limit, save->limit);
1062 vmcs_write32(sf->ar_bytes, save->ar);
1063 } else {
1064 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1065 << AR_DPL_SHIFT;
1066 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1067 }
1068}
1069
1070static void enter_pmode(struct kvm_vcpu *vcpu)
1071{
1072 unsigned long flags;
1073
1074 vcpu->rmode.active = 0;
1075
1076 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1077 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1078 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1079
1080 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1081 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
6aa8b732
AK		 1082 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1083 vmcs_writel(GUEST_RFLAGS, flags);
1084
66aee91a
RR		 1085 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1086 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1087
1088 update_exception_bitmap(vcpu);
1089
1090 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1091 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1092 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1093 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1094
1095 vmcs_write16(GUEST_SS_SELECTOR, 0);
1096 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1097
1098 vmcs_write16(GUEST_CS_SELECTOR,
1099 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1100 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1101}
1102
33f5fa16 1103static gva_t rmode_tss_base(struct kvm* kvm)
6aa8b732
AK		 1104{
1105 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1106 return base_gfn << PAGE_SHIFT;
1107}
1108
1109static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1110{
1111 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1112
1113 save->selector = vmcs_read16(sf->selector);
1114 save->base = vmcs_readl(sf->base);
1115 save->limit = vmcs_read32(sf->limit);
1116 save->ar = vmcs_read32(sf->ar_bytes);
1117 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1118 vmcs_write32(sf->limit, 0xffff);
1119 vmcs_write32(sf->ar_bytes, 0xf3);
1120}
1121
1122static void enter_rmode(struct kvm_vcpu *vcpu)
1123{
1124 unsigned long flags;
1125
1126 vcpu->rmode.active = 1;
1127
1128 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1129 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1130
1131 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1132 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1133
1134 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1135 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1136
1137 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1138 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1139
053de044 1140 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1141
1142 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1143 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1144 update_exception_bitmap(vcpu);
1145
1146 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1147 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1148 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1149
1150 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1151 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1152 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1153 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1154 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1155
1156 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1157 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1158 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1159 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01 1160
8668a3c4 1161 kvm_mmu_reset_context(vcpu);
75880a01 1162 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1163}
1164
05b3e0c2 1165#ifdef CONFIG_X86_64
6aa8b732
AK		 1166
1167static void enter_lmode(struct kvm_vcpu *vcpu)
1168{
1169 u32 guest_tr_ar;
1170
1171 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1172 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1173 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1174 __FUNCTION__);
1175 vmcs_write32(GUEST_TR_AR_BYTES,
1176 (guest_tr_ar & ~AR_TYPE_MASK)
1177 | AR_TYPE_BUSY_64_TSS);
1178 }
1179
1180 vcpu->shadow_efer |= EFER_LMA;
1181
8b9cf98c 1182 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1183 vmcs_write32(VM_ENTRY_CONTROLS,
1184 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1185 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1186}
1187
1188static void exit_lmode(struct kvm_vcpu *vcpu)
1189{
1190 vcpu->shadow_efer &= ~EFER_LMA;
1191
1192 vmcs_write32(VM_ENTRY_CONTROLS,
1193 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1194 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1195}
1196
1197#endif
1198
25c4c276 1199static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1200{
399badf3
AK		 1201 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1202 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1203}
1204
6aa8b732
AK		 1205static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1206{
5fd86fcf
AK		 1207 vmx_fpu_deactivate(vcpu);
1208
707d92fa 1209 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1210 enter_pmode(vcpu);
1211
707d92fa 1212 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1213 enter_rmode(vcpu);
1214
05b3e0c2 1215#ifdef CONFIG_X86_64
6aa8b732 1216 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1217 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1218 enter_lmode(vcpu);
707d92fa 1219 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1220 exit_lmode(vcpu);
1221 }
1222#endif
1223
1224 vmcs_writel(CR0_READ_SHADOW, cr0);
1225 vmcs_writel(GUEST_CR0,
1226 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1227 vcpu->cr0 = cr0;
5fd86fcf 1228
707d92fa 1229 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1230 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1231}
1232
6aa8b732
AK		 1233static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1234{
1235 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1236 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1237 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1238}
1239
1240static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1241{
1242 vmcs_writel(CR4_READ_SHADOW, cr4);
1243 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1244 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1245 vcpu->cr4 = cr4;
1246}
1247
05b3e0c2 1248#ifdef CONFIG_X86_64
6aa8b732
AK		 1249
1250static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1251{
8b9cf98c
RR		 1252 struct vcpu_vmx *vmx = to_vmx(vcpu);
1253 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1254
1255 vcpu->shadow_efer = efer;
1256 if (efer & EFER_LMA) {
1257 vmcs_write32(VM_ENTRY_CONTROLS,
1258 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1259 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1260 msr->data = efer;
1261
1262 } else {
1263 vmcs_write32(VM_ENTRY_CONTROLS,
1264 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1265 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1266
1267 msr->data = efer & ~EFER_LME;
1268 }
8b9cf98c 1269 setup_msrs(vmx);
6aa8b732
AK		 1270}
1271
1272#endif
1273
1274static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1275{
1276 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1277
1278 return vmcs_readl(sf->base);
1279}
1280
1281static void vmx_get_segment(struct kvm_vcpu *vcpu,
1282 struct kvm_segment *var, int seg)
1283{
1284 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1285 u32 ar;
1286
1287 var->base = vmcs_readl(sf->base);
1288 var->limit = vmcs_read32(sf->limit);
1289 var->selector = vmcs_read16(sf->selector);
1290 ar = vmcs_read32(sf->ar_bytes);
1291 if (ar & AR_UNUSABLE_MASK)
1292 ar = 0;
1293 var->type = ar & 15;
1294 var->s = (ar >> 4) & 1;
1295 var->dpl = (ar >> 5) & 3;
1296 var->present = (ar >> 7) & 1;
1297 var->avl = (ar >> 12) & 1;
1298 var->l = (ar >> 13) & 1;
1299 var->db = (ar >> 14) & 1;
1300 var->g = (ar >> 15) & 1;
1301 var->unusable = (ar >> 16) & 1;
1302}
1303
653e3108 1304static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1305{
6aa8b732
AK		 1306 u32 ar;
1307
653e3108 1308 if (var->unusable)
6aa8b732
AK		 1309 ar = 1 << 16;
1310 else {
1311 ar = var->type & 15;
1312 ar |= (var->s & 1) << 4;
1313 ar |= (var->dpl & 3) << 5;
1314 ar |= (var->present & 1) << 7;
1315 ar |= (var->avl & 1) << 12;
1316 ar |= (var->l & 1) << 13;
1317 ar |= (var->db & 1) << 14;
1318 ar |= (var->g & 1) << 15;
1319 }
f7fbf1fd
UL		 1320 if (ar == 0) /* a 0 value means unusable */
1321 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1322
1323 return ar;
1324}
1325
1326static void vmx_set_segment(struct kvm_vcpu *vcpu,
1327 struct kvm_segment *var, int seg)
1328{
1329 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1330 u32 ar;
1331
1332 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1333 vcpu->rmode.tr.selector = var->selector;
1334 vcpu->rmode.tr.base = var->base;
1335 vcpu->rmode.tr.limit = var->limit;
1336 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1337 return;
1338 }
1339 vmcs_writel(sf->base, var->base);
1340 vmcs_write32(sf->limit, var->limit);
1341 vmcs_write16(sf->selector, var->selector);
1342 if (vcpu->rmode.active && var->s) {
1343 /*
1344 * Hack real-mode segments into vm86 compatibility.
1345 */
1346 if (var->base == 0xffff0000 && var->selector == 0xf000)
1347 vmcs_writel(sf->base, 0xf0000);
1348 ar = 0xf3;
1349 } else
1350 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1351 vmcs_write32(sf->ar_bytes, ar);
1352}
1353
6aa8b732
AK		 1354static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1355{
1356 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1357
1358 *db = (ar >> 14) & 1;
1359 *l = (ar >> 13) & 1;
1360}
1361
1362static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1363{
1364 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1365 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1366}
1367
1368static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1369{
1370 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1371 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1372}
1373
1374static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1375{
1376 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1377 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1378}
1379
1380static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1381{
1382 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1383 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1384}
1385
1386static int init_rmode_tss(struct kvm* kvm)
1387{
1388 struct page *p1, *p2, *p3;
1389 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1390 char *page;
1391
954bbbc2
AK		 1392 p1 = gfn_to_page(kvm, fn++);
1393 p2 = gfn_to_page(kvm, fn++);
1394 p3 = gfn_to_page(kvm, fn);
6aa8b732
AK		 1395
1396 if (!p1 || !p2 || !p3) {
1397 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
1398 return 0;
1399 }
1400
1401 page = kmap_atomic(p1, KM_USER0);
a3870c47 1402 clear_page(page);
6aa8b732
AK		 1403 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1404 kunmap_atomic(page, KM_USER0);
1405
1406 page = kmap_atomic(p2, KM_USER0);
a3870c47 1407 clear_page(page);
6aa8b732
AK		 1408 kunmap_atomic(page, KM_USER0);
1409
1410 page = kmap_atomic(p3, KM_USER0);
a3870c47 1411 clear_page(page);
6aa8b732
AK		 1412 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
1413 kunmap_atomic(page, KM_USER0);
1414
1415 return 1;
1416}
1417
6aa8b732
AK		 1418static void seg_setup(int seg)
1419{
1420 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1421
1422 vmcs_write16(sf->selector, 0);
1423 vmcs_writel(sf->base, 0);
1424 vmcs_write32(sf->limit, 0xffff);
1425 vmcs_write32(sf->ar_bytes, 0x93);
1426}
1427
1428/*
1429 * Sets up the vmcs for emulated real mode.
1430 */
8b9cf98c 1431static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1432{
1433 u32 host_sysenter_cs;
1434 u32 junk;
1435 unsigned long a;
1436 struct descriptor_table dt;
1437 int i;
1438 int ret = 0;
cd2276a7 1439 unsigned long kvm_vmx_return;
7017fc3d 1440 u64 msr;
6e5d865c 1441 u32 exec_control;
6aa8b732 1442
8b9cf98c 1443 if (!init_rmode_tss(vmx->vcpu.kvm)) {
6aa8b732
AK		 1444 ret = -ENOMEM;
1445 goto out;
1446 }
1447
c5ec1534
HQ		 1448 vmx->vcpu.rmode.active = 0;
1449
8b9cf98c 1450 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
7017fc3d
ED		 1451 set_cr8(&vmx->vcpu, 0);
1452 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
8b9cf98c 1453 if (vmx->vcpu.vcpu_id == 0)
7017fc3d
ED		 1454 msr |= MSR_IA32_APICBASE_BSP;
1455 kvm_set_apic_base(&vmx->vcpu, msr);
6aa8b732 1456
8b9cf98c 1457 fx_init(&vmx->vcpu);
6aa8b732
AK		 1458
1459 /*
1460 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1461 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1462 */
c5ec1534
HQ		 1463 if (vmx->vcpu.vcpu_id == 0) {
1464 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1465 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1466 } else {
1467 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1468 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1469 }
6aa8b732
AK		 1470 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1471 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1472
1473 seg_setup(VCPU_SREG_DS);
1474 seg_setup(VCPU_SREG_ES);
1475 seg_setup(VCPU_SREG_FS);
1476 seg_setup(VCPU_SREG_GS);
1477 seg_setup(VCPU_SREG_SS);
1478
1479 vmcs_write16(GUEST_TR_SELECTOR, 0);
1480 vmcs_writel(GUEST_TR_BASE, 0);
1481 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1482 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1483
1484 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1485 vmcs_writel(GUEST_LDTR_BASE, 0);
1486 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1487 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1488
1489 vmcs_write32(GUEST_SYSENTER_CS, 0);
1490 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1491 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1492
1493 vmcs_writel(GUEST_RFLAGS, 0x02);
c5ec1534
HQ		 1494 if (vmx->vcpu.vcpu_id == 0)
1495 vmcs_writel(GUEST_RIP, 0xfff0);
1496 else
1497 vmcs_writel(GUEST_RIP, 0);
6aa8b732
AK		 1498 vmcs_writel(GUEST_RSP, 0);
1499
6aa8b732
AK		 1500 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1501 vmcs_writel(GUEST_DR7, 0x400);
1502
1503 vmcs_writel(GUEST_GDTR_BASE, 0);
1504 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1505
1506 vmcs_writel(GUEST_IDTR_BASE, 0);
1507 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1508
1509 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1510 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1511 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1512
1513 /* I/O */
fdef3ad1
HQ		 1514 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1515 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732
AK		 1516
1517 guest_write_tsc(0);
1518
1519 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1520
1521 /* Special registers */
1522 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1523
1524 /* Control */
1c3d14fe
YS		 1525 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1526 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1527
1528 exec_control = vmcs_config.cpu_based_exec_ctrl;
1529 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1530 exec_control &= ~CPU_BASED_TPR_SHADOW;
1531#ifdef CONFIG_X86_64
1532 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1533 CPU_BASED_CR8_LOAD_EXITING;
1534#endif
1535 }
1536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1537
6aa8b732
AK		 1538 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1539 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1540 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1541
1542 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1543 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1544 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1545
1546 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1547 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1548 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1549 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1550 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1551 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1552#ifdef CONFIG_X86_64
6aa8b732
AK		 1553 rdmsrl(MSR_FS_BASE, a);
1554 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1555 rdmsrl(MSR_GS_BASE, a);
1556 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1557#else
1558 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1559 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1560#endif
1561
1562 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1563
1564 get_idt(&dt);
1565 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1566
cd2276a7
AK		 1567 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1568 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1569 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1570 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1571 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1572
1573 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1574 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1575 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1576 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1577 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1578 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1579
6aa8b732
AK		 1580 for (i = 0; i < NR_VMX_MSR; ++i) {
1581 u32 index = vmx_msr_index[i];
1582 u32 data_low, data_high;
1583 u64 data;
a2fa3e9f 1584 int j = vmx->nmsrs;
6aa8b732
AK		 1585
1586 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1587 continue;
432bd6cb
AK		 1588 if (wrmsr_safe(index, data_low, data_high) < 0)
1589 continue;
6aa8b732 1590 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1591 vmx->host_msrs[j].index = index;
1592 vmx->host_msrs[j].reserved = 0;
1593 vmx->host_msrs[j].data = data;
1594 vmx->guest_msrs[j] = vmx->host_msrs[j];
1595 ++vmx->nmsrs;
6aa8b732 1596 }
6aa8b732 1597
8b9cf98c 1598 setup_msrs(vmx);
e38aea3e 1599
1c3d14fe 1600 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1601
1602 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1603 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1604
6aa8b732
AK		 1605 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1606
3b99ab24 1607#ifdef CONFIG_X86_64
6e5d865c
YS		 1608 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1609 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1610 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1611 page_to_phys(vmx->vcpu.apic->regs_page));
1612 vmcs_write32(TPR_THRESHOLD, 0);
3b99ab24 1613#endif
6aa8b732 1614
25c4c276 1615 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
6aa8b732
AK		 1616 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1617
8b9cf98c
RR		 1618 vmx->vcpu.cr0 = 0x60000010;
1619 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1620 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1621#ifdef CONFIG_X86_64
8b9cf98c 1622 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1623#endif
8b9cf98c
RR		 1624 vmx_fpu_activate(&vmx->vcpu);
1625 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1626
1627 return 0;
1628
6aa8b732
AK		 1629out:
1630 return ret;
1631}
1632
04d2cc77
AK		 1633static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1634{
1635 struct vcpu_vmx *vmx = to_vmx(vcpu);
1636
1637 vmx_vcpu_setup(vmx);
1638}
1639
6aa8b732
AK		 1640static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1641{
1642 u16 ent[2];
1643 u16 cs;
1644 u16 ip;
1645 unsigned long flags;
1646 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1647 u16 sp = vmcs_readl(GUEST_RSP);
1648 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1649
3964994b 1650 if (sp > ss_limit || sp < 6 ) {
6aa8b732
AK		 1651 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1652 __FUNCTION__,
1653 vmcs_readl(GUEST_RSP),
1654 vmcs_readl(GUEST_SS_BASE),
1655 vmcs_read32(GUEST_SS_LIMIT));
1656 return;
1657 }
1658
e7d5d76c
LV		 1659 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1660 X86EMUL_CONTINUE) {
6aa8b732
AK		 1661 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1662 return;
1663 }
1664
1665 flags = vmcs_readl(GUEST_RFLAGS);
1666 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1667 ip = vmcs_readl(GUEST_RIP);
1668
1669
e7d5d76c
LV		 1670 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1671 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1672 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
6aa8b732
AK		 1673 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1674 return;
1675 }
1676
1677 vmcs_writel(GUEST_RFLAGS, flags &
1678 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1679 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1680 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1681 vmcs_writel(GUEST_RIP, ent[0]);
1682 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1683}
1684
85f455f7
ED		 1685static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1686{
1687 if (vcpu->rmode.active) {
1688 inject_rmode_irq(vcpu, irq);
1689 return;
1690 }
1691 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1692 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1693}
1694
6aa8b732
AK		 1695static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1696{
1697 int word_index = __ffs(vcpu->irq_summary);
1698 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1699 int irq = word_index * BITS_PER_LONG + bit_index;
1700
1701 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1702 if (!vcpu->irq_pending[word_index])
1703 clear_bit(word_index, &vcpu->irq_summary);
85f455f7 1704 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1705}
1706
c1150d8c
DL		 1707
1708static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1709 struct kvm_run *kvm_run)
6aa8b732 1710{
c1150d8c
DL		 1711 u32 cpu_based_vm_exec_control;
1712
1713 vcpu->interrupt_window_open =
1714 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1715 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1716
1717 if (vcpu->interrupt_window_open &&
1718 vcpu->irq_summary &&
1719 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1720 /*
c1150d8c 1721 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1722 */
1723 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1724
1725 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1726 if (!vcpu->interrupt_window_open &&
1727 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1728 /*
1729 * Interrupts blocked. Wait for unblock.
1730 */
c1150d8c
DL		 1731 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1732 else
1733 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1734 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1735}
1736
1737static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1738{
1739 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1740
1741 set_debugreg(dbg->bp[0], 0);
1742 set_debugreg(dbg->bp[1], 1);
1743 set_debugreg(dbg->bp[2], 2);
1744 set_debugreg(dbg->bp[3], 3);
1745
1746 if (dbg->singlestep) {
1747 unsigned long flags;
1748
1749 flags = vmcs_readl(GUEST_RFLAGS);
1750 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1751 vmcs_writel(GUEST_RFLAGS, flags);
1752 }
1753}
1754
1755static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1756 int vec, u32 err_code)
1757{
1758 if (!vcpu->rmode.active)
1759 return 0;
1760
b3f37707
NK		 1761 /*
1762 * Instruction with address size override prefix opcode 0x67
1763 * Cause the #SS fault with 0 error code in VM86 mode.
1764 */
1765 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 1766 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 1767 return 1;
1768 return 0;
1769}
1770
1771static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1772{
1773 u32 intr_info, error_code;
1774 unsigned long cr2, rip;
1775 u32 vect_info;
1776 enum emulation_result er;
e2dec939 1777 int r;
6aa8b732
AK		 1778
1779 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1780 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1781
1782 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1783 !is_page_fault(intr_info)) {
1784 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1785 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1786 }
1787
85f455f7 1788 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732
AK		 1789 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1790 set_bit(irq, vcpu->irq_pending);
1791 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1792 }
1793
1b6269db
AK		 1794 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1795 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1796
1797 if (is_no_device(intr_info)) {
5fd86fcf 1798 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1799 return 1;
1800 }
1801
7aa81cc0 1802 if (is_invalid_opcode(intr_info)) {
3427318f 1803 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
7aa81cc0
AL		 1804 if (er != EMULATE_DONE)
1805 vmx_inject_ud(vcpu);
1806
1807 return 1;
1808 }
1809
6aa8b732
AK		 1810 error_code = 0;
1811 rip = vmcs_readl(GUEST_RIP);
1812 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1813 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1814 if (is_page_fault(intr_info)) {
1815 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1816
11ec2804 1817 mutex_lock(&vcpu->kvm->lock);
e2dec939
AK		 1818 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1819 if (r < 0) {
11ec2804 1820 mutex_unlock(&vcpu->kvm->lock);
e2dec939
AK		 1821 return r;
1822 }
1823 if (!r) {
11ec2804 1824 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1825 return 1;
1826 }
1827
3427318f 1828 er = emulate_instruction(vcpu, kvm_run, cr2, error_code, 0);
11ec2804 1829 mutex_unlock(&vcpu->kvm->lock);
6aa8b732
AK		 1830
1831 switch (er) {
1832 case EMULATE_DONE:
1833 return 1;
1834 case EMULATE_DO_MMIO:
1165f5fe 1835 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 1836 return 0;
1837 case EMULATE_FAIL:
054b1369 1838 kvm_report_emulation_failure(vcpu, "pagetable");
6aa8b732
AK		 1839 break;
1840 default:
1841 BUG();
1842 }
1843 }
1844
1845 if (vcpu->rmode.active &&
1846 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1847 error_code)) {
1848 if (vcpu->halt_request) {
1849 vcpu->halt_request = 0;
1850 return kvm_emulate_halt(vcpu);
1851 }
6aa8b732 1852 return 1;
72d6e5a0 1853 }
6aa8b732
AK		 1854
1855 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1856 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1857 return 0;
1858 }
1859 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1860 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1861 kvm_run->ex.error_code = error_code;
1862 return 0;
1863}
1864
1865static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1866 struct kvm_run *kvm_run)
1867{
1165f5fe 1868 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1869 return 1;
1870}
1871
988ad74f
AK		 1872static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1873{
1874 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1875 return 0;
1876}
6aa8b732 1877
6aa8b732
AK		 1878static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1879{
bfdaab09 1880 unsigned long exit_qualification;
039576c0
AK		 1881 int size, down, in, string, rep;
1882 unsigned port;
6aa8b732 1883
1165f5fe 1884 ++vcpu->stat.io_exits;
bfdaab09 1885 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1886 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1887
1888 if (string) {
3427318f
LV		 1889 if (emulate_instruction(vcpu,
1890 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1891 return 0;
1892 return 1;
1893 }
1894
1895 size = (exit_qualification & 7) + 1;
1896 in = (exit_qualification & 8) != 0;
039576c0 1897 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1898 rep = (exit_qualification & 32) != 0;
1899 port = exit_qualification >> 16;
e70669ab 1900
3090dd73 1901 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1902}
1903
102d8325
IM		 1904static void
1905vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1906{
1907 /*
1908 * Patch in the VMCALL instruction:
1909 */
1910 hypercall[0] = 0x0f;
1911 hypercall[1] = 0x01;
1912 hypercall[2] = 0xc1;
102d8325
IM		 1913}
1914
6aa8b732
AK		 1915static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1916{
bfdaab09 1917 unsigned long exit_qualification;
6aa8b732
AK		 1918 int cr;
1919 int reg;
1920
bfdaab09 1921 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1922 cr = exit_qualification & 15;
1923 reg = (exit_qualification >> 8) & 15;
1924 switch ((exit_qualification >> 4) & 3) {
1925 case 0: /* mov to cr */
1926 switch (cr) {
1927 case 0:
1928 vcpu_load_rsp_rip(vcpu);
1929 set_cr0(vcpu, vcpu->regs[reg]);
1930 skip_emulated_instruction(vcpu);
1931 return 1;
1932 case 3:
1933 vcpu_load_rsp_rip(vcpu);
1934 set_cr3(vcpu, vcpu->regs[reg]);
1935 skip_emulated_instruction(vcpu);
1936 return 1;
1937 case 4:
1938 vcpu_load_rsp_rip(vcpu);
1939 set_cr4(vcpu, vcpu->regs[reg]);
1940 skip_emulated_instruction(vcpu);
1941 return 1;
1942 case 8:
1943 vcpu_load_rsp_rip(vcpu);
1944 set_cr8(vcpu, vcpu->regs[reg]);
1945 skip_emulated_instruction(vcpu);
253abdee
YS		 1946 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1947 return 0;
6aa8b732
AK		 1948 };
1949 break;
25c4c276
AL		 1950 case 2: /* clts */
1951 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1952 vmx_fpu_deactivate(vcpu);
707d92fa 1953 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1954 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1955 vmx_fpu_activate(vcpu);
25c4c276
AL		 1956 skip_emulated_instruction(vcpu);
1957 return 1;
6aa8b732
AK		 1958 case 1: /*mov from cr*/
1959 switch (cr) {
1960 case 3:
1961 vcpu_load_rsp_rip(vcpu);
1962 vcpu->regs[reg] = vcpu->cr3;
1963 vcpu_put_rsp_rip(vcpu);
1964 skip_emulated_instruction(vcpu);
1965 return 1;
1966 case 8:
6aa8b732 1967 vcpu_load_rsp_rip(vcpu);
7017fc3d 1968 vcpu->regs[reg] = get_cr8(vcpu);
6aa8b732
AK		 1969 vcpu_put_rsp_rip(vcpu);
1970 skip_emulated_instruction(vcpu);
1971 return 1;
1972 }
1973 break;
1974 case 3: /* lmsw */
1975 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1976
1977 skip_emulated_instruction(vcpu);
1978 return 1;
1979 default:
1980 break;
1981 }
1982 kvm_run->exit_reason = 0;
f0242478 1983 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 1984 (int)(exit_qualification >> 4) & 3, cr);
1985 return 0;
1986}
1987
1988static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1989{
bfdaab09 1990 unsigned long exit_qualification;
6aa8b732
AK		 1991 unsigned long val;
1992 int dr, reg;
1993
1994 /*
1995 * FIXME: this code assumes the host is debugging the guest.
1996 * need to deal with guest debugging itself too.
1997 */
bfdaab09 1998 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1999 dr = exit_qualification & 7;
2000 reg = (exit_qualification >> 8) & 15;
2001 vcpu_load_rsp_rip(vcpu);
2002 if (exit_qualification & 16) {
2003 /* mov from dr */
2004 switch (dr) {
2005 case 6:
2006 val = 0xffff0ff0;
2007 break;
2008 case 7:
2009 val = 0x400;
2010 break;
2011 default:
2012 val = 0;
2013 }
2014 vcpu->regs[reg] = val;
2015 } else {
2016 /* mov to dr */
2017 }
2018 vcpu_put_rsp_rip(vcpu);
2019 skip_emulated_instruction(vcpu);
2020 return 1;
2021}
2022
2023static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2024{
06465c5a
AK		 2025 kvm_emulate_cpuid(vcpu);
2026 return 1;
6aa8b732
AK		 2027}
2028
2029static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2030{
2031 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2032 u64 data;
2033
2034 if (vmx_get_msr(vcpu, ecx, &data)) {
2035 vmx_inject_gp(vcpu, 0);
2036 return 1;
2037 }
2038
2039 /* FIXME: handling of bits 32:63 of rax, rdx */
2040 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2041 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2042 skip_emulated_instruction(vcpu);
2043 return 1;
2044}
2045
2046static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2047{
2048 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2049 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2050 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2051
2052 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2053 vmx_inject_gp(vcpu, 0);
2054 return 1;
2055 }
2056
2057 skip_emulated_instruction(vcpu);
2058 return 1;
2059}
2060
6e5d865c
YS		 2061static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2062 struct kvm_run *kvm_run)
2063{
2064 return 1;
2065}
2066
6aa8b732
AK		 2067static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2068 struct kvm_run *kvm_run)
2069{
85f455f7
ED		 2070 u32 cpu_based_vm_exec_control;
2071
2072 /* clear pending irq */
2073 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2074 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2075 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2076 /*
2077 * If the user space waits to inject interrupts, exit as soon as
2078 * possible
2079 */
2080 if (kvm_run->request_interrupt_window &&
022a9308 2081 !vcpu->irq_summary) {
c1150d8c 2082 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2083 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2084 return 0;
2085 }
6aa8b732
AK		 2086 return 1;
2087}
2088
2089static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2090{
2091 skip_emulated_instruction(vcpu);
d3bef15f 2092 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2093}
2094
c21415e8
IM		 2095static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2096{
510043da 2097 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2098 kvm_emulate_hypercall(vcpu);
2099 return 1;
c21415e8
IM		 2100}
2101
6aa8b732
AK		 2102/*
2103 * The exit handlers return 1 if the exit was handled fully and guest execution
2104 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2105 * to be done to userspace and return 0.
2106 */
2107static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2108 struct kvm_run *kvm_run) = {
2109 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2110 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2111 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2112 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2113 [EXIT_REASON_CR_ACCESS] = handle_cr,
2114 [EXIT_REASON_DR_ACCESS] = handle_dr,
2115 [EXIT_REASON_CPUID] = handle_cpuid,
2116 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2117 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2118 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2119 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2120 [EXIT_REASON_VMCALL] = handle_vmcall,
6e5d865c 2121 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold
6aa8b732
AK		 2122};
2123
2124static const int kvm_vmx_max_exit_handlers =
50a3485c 2125 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2126
2127/*
2128 * The guest has exited. See if we can fix it or if we need userspace
2129 * assistance.
2130 */
2131static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2132{
2133 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2134 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78
AK		 2135 struct vcpu_vmx *vmx = to_vmx(vcpu);
2136
2137 if (unlikely(vmx->fail)) {
2138 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2139 kvm_run->fail_entry.hardware_entry_failure_reason
2140 = vmcs_read32(VM_INSTRUCTION_ERROR);
2141 return 0;
2142 }
6aa8b732
AK		 2143
2144 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2145 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2146 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2147 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2148 if (exit_reason < kvm_vmx_max_exit_handlers
2149 && kvm_vmx_exit_handlers[exit_reason])
2150 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2151 else {
2152 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2153 kvm_run->hw.hardware_exit_reason = exit_reason;
2154 }
2155 return 0;
2156}
2157
d9e368d6
AK		 2158static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2159{
d9e368d6
AK		 2160}
2161
6e5d865c
YS		 2162static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2163{
2164 int max_irr, tpr;
2165
2166 if (!vm_need_tpr_shadow(vcpu->kvm))
2167 return;
2168
2169 if (!kvm_lapic_enabled(vcpu) ||
2170 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2171 vmcs_write32(TPR_THRESHOLD, 0);
2172 return;
2173 }
2174
2175 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2176 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2177}
2178
85f455f7
ED		 2179static void enable_irq_window(struct kvm_vcpu *vcpu)
2180{
2181 u32 cpu_based_vm_exec_control;
2182
2183 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2184 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2185 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2186}
2187
2188static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2189{
2190 u32 idtv_info_field, intr_info_field;
2191 int has_ext_irq, interrupt_window_open;
1b9778da 2192 int vector;
85f455f7 2193
1b9778da 2194 kvm_inject_pending_timer_irqs(vcpu);
6e5d865c
YS		 2195 update_tpr_threshold(vcpu);
2196
85f455f7
ED		 2197 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2198 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2199 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2200 if (intr_info_field & INTR_INFO_VALID_MASK) {
2201 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2202 /* TODO: fault when IDT_Vectoring */
2203 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2204 }
2205 if (has_ext_irq)
2206 enable_irq_window(vcpu);
2207 return;
2208 }
2209 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2210 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2211 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2212 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2213
2214 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2215 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2216 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2217 if (unlikely(has_ext_irq))
2218 enable_irq_window(vcpu);
2219 return;
2220 }
2221 if (!has_ext_irq)
2222 return;
2223 interrupt_window_open =
2224 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2225 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2226 if (interrupt_window_open) {
2227 vector = kvm_cpu_get_interrupt(vcpu);
2228 vmx_inject_irq(vcpu, vector);
2229 kvm_timer_intr_post(vcpu, vector);
2230 } else
85f455f7
ED		 2231 enable_irq_window(vcpu);
2232}
2233
04d2cc77 2234static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2235{
a2fa3e9f 2236 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2237 u32 intr_info;
e6adf283
AK		 2238
2239 /*
2240 * Loading guest fpu may have cleared host cr0.ts
2241 */
2242 vmcs_writel(HOST_CR0, read_cr0());
2243
6aa8b732
AK		 2244 asm (
2245 /* Store host registers */
05b3e0c2 2246#ifdef CONFIG_X86_64
6aa8b732
AK		 2247 "push %%rax; push %%rbx; push %%rdx;"
2248 "push %%rsi; push %%rdi; push %%rbp;"
2249 "push %%r8; push %%r9; push %%r10; push %%r11;"
2250 "push %%r12; push %%r13; push %%r14; push %%r15;"
2251 "push %%rcx \n\t"
2252 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2253#else
2254 "pusha; push %%ecx \n\t"
2255 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2256#endif
2257 /* Check if vmlaunch of vmresume is needed */
2258 "cmp $0, %1 \n\t"
2259 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2260#ifdef CONFIG_X86_64
6aa8b732
AK		 2261 "mov %c[cr2](%3), %%rax \n\t"
2262 "mov %%rax, %%cr2 \n\t"
2263 "mov %c[rax](%3), %%rax \n\t"
2264 "mov %c[rbx](%3), %%rbx \n\t"
2265 "mov %c[rdx](%3), %%rdx \n\t"
2266 "mov %c[rsi](%3), %%rsi \n\t"
2267 "mov %c[rdi](%3), %%rdi \n\t"
2268 "mov %c[rbp](%3), %%rbp \n\t"
2269 "mov %c[r8](%3), %%r8 \n\t"
2270 "mov %c[r9](%3), %%r9 \n\t"
2271 "mov %c[r10](%3), %%r10 \n\t"
2272 "mov %c[r11](%3), %%r11 \n\t"
2273 "mov %c[r12](%3), %%r12 \n\t"
2274 "mov %c[r13](%3), %%r13 \n\t"
2275 "mov %c[r14](%3), %%r14 \n\t"
2276 "mov %c[r15](%3), %%r15 \n\t"
2277 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2278#else
2279 "mov %c[cr2](%3), %%eax \n\t"
2280 "mov %%eax, %%cr2 \n\t"
2281 "mov %c[rax](%3), %%eax \n\t"
2282 "mov %c[rbx](%3), %%ebx \n\t"
2283 "mov %c[rdx](%3), %%edx \n\t"
2284 "mov %c[rsi](%3), %%esi \n\t"
2285 "mov %c[rdi](%3), %%edi \n\t"
2286 "mov %c[rbp](%3), %%ebp \n\t"
2287 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2288#endif
2289 /* Enter guest mode */
cd2276a7 2290 "jne .Llaunched \n\t"
6aa8b732 2291 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2292 "jmp .Lkvm_vmx_return \n\t"
2293 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2294 ".Lkvm_vmx_return: "
6aa8b732 2295 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2296#ifdef CONFIG_X86_64
96958231 2297 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2298 "mov %%rax, %c[rax](%3) \n\t"
2299 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2300 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2301 "mov %%rdx, %c[rdx](%3) \n\t"
2302 "mov %%rsi, %c[rsi](%3) \n\t"
2303 "mov %%rdi, %c[rdi](%3) \n\t"
2304 "mov %%rbp, %c[rbp](%3) \n\t"
2305 "mov %%r8, %c[r8](%3) \n\t"
2306 "mov %%r9, %c[r9](%3) \n\t"
2307 "mov %%r10, %c[r10](%3) \n\t"
2308 "mov %%r11, %c[r11](%3) \n\t"
2309 "mov %%r12, %c[r12](%3) \n\t"
2310 "mov %%r13, %c[r13](%3) \n\t"
2311 "mov %%r14, %c[r14](%3) \n\t"
2312 "mov %%r15, %c[r15](%3) \n\t"
2313 "mov %%cr2, %%rax \n\t"
2314 "mov %%rax, %c[cr2](%3) \n\t"
96958231 2315 "mov (%%rsp), %3 \n\t"
6aa8b732
AK		 2316
2317 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2318 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2319 "pop %%rbp; pop %%rdi; pop %%rsi;"
2320 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2321#else
96958231 2322 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2323 "mov %%eax, %c[rax](%3) \n\t"
2324 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2325 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2326 "mov %%edx, %c[rdx](%3) \n\t"
2327 "mov %%esi, %c[rsi](%3) \n\t"
2328 "mov %%edi, %c[rdi](%3) \n\t"
2329 "mov %%ebp, %c[rbp](%3) \n\t"
2330 "mov %%cr2, %%eax \n\t"
2331 "mov %%eax, %c[cr2](%3) \n\t"
96958231 2332 "mov (%%esp), %3 \n\t"
6aa8b732
AK		 2333
2334 "pop %%ecx; popa \n\t"
2335#endif
2336 "setbe %0 \n\t"
29bd8a78 2337 : "=q" (vmx->fail)
a2fa3e9f 2338 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
6aa8b732
AK		 2339 "c"(vcpu),
2340 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2341 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2342 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2343 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2344 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2345 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2346 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2347#ifdef CONFIG_X86_64
6aa8b732
AK		 2348 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2349 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2350 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2351 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2352 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2353 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2354 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2355 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2356#endif
2357 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2358 : "cc", "memory" );
2359
c1150d8c 2360 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2361
6aa8b732 2362 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2363 vmx->launched = 1;
1b6269db
AK		 2364
2365 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2366
2367 /* We need to handle NMIs before interrupts are enabled */
2368 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2369 asm("int $2");
6aa8b732
AK		 2370}
2371
6aa8b732
AK		 2372static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2373 unsigned long addr,
2374 u32 err_code)
2375{
2376 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2377
1165f5fe 2378 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2379
2380 if (is_page_fault(vect_info)) {
2381 printk(KERN_DEBUG "inject_page_fault: "
2382 "double fault 0x%lx @ 0x%lx\n",
2383 addr, vmcs_readl(GUEST_RIP));
2384 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2385 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2386 DF_VECTOR |
2387 INTR_TYPE_EXCEPTION |
2388 INTR_INFO_DELIEVER_CODE_MASK |
2389 INTR_INFO_VALID_MASK);
2390 return;
2391 }
2392 vcpu->cr2 = addr;
2393 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2394 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2395 PF_VECTOR |
2396 INTR_TYPE_EXCEPTION |
2397 INTR_INFO_DELIEVER_CODE_MASK |
2398 INTR_INFO_VALID_MASK);
2399
2400}
2401
2402static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2403{
a2fa3e9f
GH		 2404 struct vcpu_vmx *vmx = to_vmx(vcpu);
2405
2406 if (vmx->vmcs) {
8b9cf98c 2407 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2408 free_vmcs(vmx->vmcs);
2409 vmx->vmcs = NULL;
6aa8b732
AK		 2410 }
2411}
2412
2413static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2414{
fb3f0f51
RR		 2415 struct vcpu_vmx *vmx = to_vmx(vcpu);
2416
6aa8b732 2417 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2418 kfree(vmx->host_msrs);
2419 kfree(vmx->guest_msrs);
2420 kvm_vcpu_uninit(vcpu);
a4770347 2421 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2422}
2423
fb3f0f51 2424static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2425{
fb3f0f51 2426 int err;
c16f862d 2427 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2428 int cpu;
6aa8b732 2429
a2fa3e9f 2430 if (!vmx)
fb3f0f51
RR		 2431 return ERR_PTR(-ENOMEM);
2432
2433 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2434 if (err)
2435 goto free_vcpu;
965b58a5 2436
97222cc8
ED		 2437 if (irqchip_in_kernel(kvm)) {
2438 err = kvm_create_lapic(&vmx->vcpu);
2439 if (err < 0)
2440 goto free_vcpu;
2441 }
2442
a2fa3e9f 2443 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2444 if (!vmx->guest_msrs) {
2445 err = -ENOMEM;
2446 goto uninit_vcpu;
2447 }
965b58a5 2448
a2fa3e9f
GH		 2449 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2450 if (!vmx->host_msrs)
fb3f0f51 2451 goto free_guest_msrs;
965b58a5 2452
a2fa3e9f
GH		 2453 vmx->vmcs = alloc_vmcs();
2454 if (!vmx->vmcs)
fb3f0f51 2455 goto free_msrs;
a2fa3e9f
GH		 2456
2457 vmcs_clear(vmx->vmcs);
2458
15ad7146
AK		 2459 cpu = get_cpu();
2460 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2461 err = vmx_vcpu_setup(vmx);
fb3f0f51 2462 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2463 put_cpu();
fb3f0f51
RR		 2464 if (err)
2465 goto free_vmcs;
2466
2467 return &vmx->vcpu;
2468
2469free_vmcs:
2470 free_vmcs(vmx->vmcs);
2471free_msrs:
2472 kfree(vmx->host_msrs);
2473free_guest_msrs:
2474 kfree(vmx->guest_msrs);
2475uninit_vcpu:
2476 kvm_vcpu_uninit(&vmx->vcpu);
2477free_vcpu:
a4770347 2478 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2479 return ERR_PTR(err);
6aa8b732
AK		 2480}
2481
002c7f7c
YS		 2482static void __init vmx_check_processor_compat(void *rtn)
2483{
2484 struct vmcs_config vmcs_conf;
2485
2486 *(int *)rtn = 0;
2487 if (setup_vmcs_config(&vmcs_conf) < 0)
2488 *(int *)rtn = -EIO;
2489 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2490 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2491 smp_processor_id());
2492 *(int *)rtn = -EIO;
2493 }
2494}
2495
cbdd1bea 2496static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2497 .cpu_has_kvm_support = cpu_has_kvm_support,
2498 .disabled_by_bios = vmx_disabled_by_bios,
2499 .hardware_setup = hardware_setup,
2500 .hardware_unsetup = hardware_unsetup,
002c7f7c 2501 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2502 .hardware_enable = hardware_enable,
2503 .hardware_disable = hardware_disable,
2504
2505 .vcpu_create = vmx_create_vcpu,
2506 .vcpu_free = vmx_free_vcpu,
04d2cc77 2507 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2508
04d2cc77 2509 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2510 .vcpu_load = vmx_vcpu_load,
2511 .vcpu_put = vmx_vcpu_put,
774c47f1 2512 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2513
2514 .set_guest_debug = set_guest_debug,
04d2cc77 2515 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2516 .get_msr = vmx_get_msr,
2517 .set_msr = vmx_set_msr,
2518 .get_segment_base = vmx_get_segment_base,
2519 .get_segment = vmx_get_segment,
2520 .set_segment = vmx_set_segment,
6aa8b732 2521 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2522 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2523 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2524 .set_cr3 = vmx_set_cr3,
2525 .set_cr4 = vmx_set_cr4,
05b3e0c2 2526#ifdef CONFIG_X86_64
6aa8b732
AK		 2527 .set_efer = vmx_set_efer,
2528#endif
2529 .get_idt = vmx_get_idt,
2530 .set_idt = vmx_set_idt,
2531 .get_gdt = vmx_get_gdt,
2532 .set_gdt = vmx_set_gdt,
2533 .cache_regs = vcpu_load_rsp_rip,
2534 .decache_regs = vcpu_put_rsp_rip,
2535 .get_rflags = vmx_get_rflags,
2536 .set_rflags = vmx_set_rflags,
2537
2538 .tlb_flush = vmx_flush_tlb,
2539 .inject_page_fault = vmx_inject_page_fault,
2540
2541 .inject_gp = vmx_inject_gp,
2542
2543 .run = vmx_vcpu_run,
04d2cc77 2544 .handle_exit = kvm_handle_exit,
6aa8b732 2545 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2546 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2547 .get_irq = vmx_get_irq,
2548 .set_irq = vmx_inject_irq,
04d2cc77
AK		 2549 .inject_pending_irq = vmx_intr_assist,
2550 .inject_pending_vectors = do_interrupt_requests,
6aa8b732
AK		 2551};
2552
2553static int __init vmx_init(void)
2554{
fdef3ad1
HQ		 2555 void *iova;
2556 int r;
2557
2558 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2559 if (!vmx_io_bitmap_a)
2560 return -ENOMEM;
2561
2562 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2563 if (!vmx_io_bitmap_b) {
2564 r = -ENOMEM;
2565 goto out;
2566 }
2567
2568 /*
2569 * Allow direct access to the PC debug port (it is often used for I/O
2570 * delays, but the vmexits simply slow things down).
2571 */
2572 iova = kmap(vmx_io_bitmap_a);
2573 memset(iova, 0xff, PAGE_SIZE);
2574 clear_bit(0x80, iova);
cd0536d7 2575 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2576
2577 iova = kmap(vmx_io_bitmap_b);
2578 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2579 kunmap(vmx_io_bitmap_b);
fdef3ad1 2580
cbdd1bea 2581 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2582 if (r)
2583 goto out1;
2584
2585 return 0;
2586
2587out1:
2588 __free_page(vmx_io_bitmap_b);
2589out:
2590 __free_page(vmx_io_bitmap_a);
2591 return r;
6aa8b732
AK		 2592}
2593
2594static void __exit vmx_exit(void)
2595{
fdef3ad1
HQ		 2596 __free_page(vmx_io_bitmap_b);
2597 __free_page(vmx_io_bitmap_a);
2598
cbdd1bea 2599 kvm_exit_x86();
6aa8b732
AK		 2600}
2601
2602module_init(vmx_init)
2603module_exit(vmx_exit)
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