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[PATCH] KVM: Implement a few system configuration msrs
[mirror_ubuntu-bionic-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
20#include "kvm_vmx.h"
21#include <linux/module.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <asm/io.h>
3b3be0d1 25#include <asm/desc.h>
6aa8b732
AK		 26
27#include "segment_descriptor.h"
28
29#define MSR_IA32_FEATURE_CONTROL 0x03a
30
31MODULE_AUTHOR("Qumranet");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
36
05b3e0c2 37#ifdef CONFIG_X86_64
6aa8b732
AK		 38#define HOST_IS_64 1
39#else
40#define HOST_IS_64 0
41#endif
42
43static struct vmcs_descriptor {
44 int size;
45 int order;
46 u32 revision_id;
47} vmcs_descriptor;
48
49#define VMX_SEGMENT_FIELD(seg) \
50 [VCPU_SREG_##seg] = { \
51 .selector = GUEST_##seg##_SELECTOR, \
52 .base = GUEST_##seg##_BASE, \
53 .limit = GUEST_##seg##_LIMIT, \
54 .ar_bytes = GUEST_##seg##_AR_BYTES, \
55 }
56
57static struct kvm_vmx_segment_field {
58 unsigned selector;
59 unsigned base;
60 unsigned limit;
61 unsigned ar_bytes;
62} kvm_vmx_segment_fields[] = {
63 VMX_SEGMENT_FIELD(CS),
64 VMX_SEGMENT_FIELD(DS),
65 VMX_SEGMENT_FIELD(ES),
66 VMX_SEGMENT_FIELD(FS),
67 VMX_SEGMENT_FIELD(GS),
68 VMX_SEGMENT_FIELD(SS),
69 VMX_SEGMENT_FIELD(TR),
70 VMX_SEGMENT_FIELD(LDTR),
71};
72
73static const u32 vmx_msr_index[] = {
05b3e0c2 74#ifdef CONFIG_X86_64
6aa8b732
AK		 75 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
76#endif
77 MSR_EFER, MSR_K6_STAR,
78};
79#define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
80
6aa8b732
AK		 81static inline int is_page_fault(u32 intr_info)
82{
83 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
84 INTR_INFO_VALID_MASK)) ==
85 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
86}
87
88static inline int is_external_interrupt(u32 intr_info)
89{
90 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
91 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
92}
93
7725f0ba
AK		 94static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
95{
96 int i;
97
98 for (i = 0; i < vcpu->nmsrs; ++i)
99 if (vcpu->guest_msrs[i].index == msr)
100 return &vcpu->guest_msrs[i];
101 return 0;
102}
103
6aa8b732
AK		 104static void vmcs_clear(struct vmcs *vmcs)
105{
106 u64 phys_addr = __pa(vmcs);
107 u8 error;
108
109 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
110 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
111 : "cc", "memory");
112 if (error)
113 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
114 vmcs, phys_addr);
115}
116
117static void __vcpu_clear(void *arg)
118{
119 struct kvm_vcpu *vcpu = arg;
120 int cpu = smp_processor_id();
121
122 if (vcpu->cpu == cpu)
123 vmcs_clear(vcpu->vmcs);
124 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
125 per_cpu(current_vmcs, cpu) = NULL;
126}
127
128static unsigned long vmcs_readl(unsigned long field)
129{
130 unsigned long value;
131
132 asm volatile (ASM_VMX_VMREAD_RDX_RAX
133 : "=a"(value) : "d"(field) : "cc");
134 return value;
135}
136
137static u16 vmcs_read16(unsigned long field)
138{
139 return vmcs_readl(field);
140}
141
142static u32 vmcs_read32(unsigned long field)
143{
144 return vmcs_readl(field);
145}
146
147static u64 vmcs_read64(unsigned long field)
148{
05b3e0c2 149#ifdef CONFIG_X86_64
6aa8b732
AK		 150 return vmcs_readl(field);
151#else
152 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
153#endif
154}
155
156static void vmcs_writel(unsigned long field, unsigned long value)
157{
158 u8 error;
159
160 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
161 : "=q"(error) : "a"(value), "d"(field) : "cc" );
162 if (error)
163 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
164 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
165}
166
167static void vmcs_write16(unsigned long field, u16 value)
168{
169 vmcs_writel(field, value);
170}
171
172static void vmcs_write32(unsigned long field, u32 value)
173{
174 vmcs_writel(field, value);
175}
176
177static void vmcs_write64(unsigned long field, u64 value)
178{
05b3e0c2 179#ifdef CONFIG_X86_64
6aa8b732
AK		 180 vmcs_writel(field, value);
181#else
182 vmcs_writel(field, value);
183 asm volatile ("");
184 vmcs_writel(field+1, value >> 32);
185#endif
186}
187
188/*
189 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
190 * vcpu mutex is already taken.
191 */
192static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
193{
194 u64 phys_addr = __pa(vcpu->vmcs);
195 int cpu;
196
197 cpu = get_cpu();
198
199 if (vcpu->cpu != cpu) {
200 smp_call_function(__vcpu_clear, vcpu, 0, 1);
201 vcpu->launched = 0;
202 }
203
204 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
205 u8 error;
206
207 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
208 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
209 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
210 : "cc");
211 if (error)
212 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
213 vcpu->vmcs, phys_addr);
214 }
215
216 if (vcpu->cpu != cpu) {
217 struct descriptor_table dt;
218 unsigned long sysenter_esp;
219
220 vcpu->cpu = cpu;
221 /*
222 * Linux uses per-cpu TSS and GDT, so set these when switching
223 * processors.
224 */
225 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
226 get_gdt(&dt);
227 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
228
229 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
230 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
231 }
232 return vcpu;
233}
234
235static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
236{
237 put_cpu();
238}
239
240static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
241{
242 return vmcs_readl(GUEST_RFLAGS);
243}
244
245static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
246{
247 vmcs_writel(GUEST_RFLAGS, rflags);
248}
249
250static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
251{
252 unsigned long rip;
253 u32 interruptibility;
254
255 rip = vmcs_readl(GUEST_RIP);
256 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
257 vmcs_writel(GUEST_RIP, rip);
258
259 /*
260 * We emulated an instruction, so temporary interrupt blocking
261 * should be removed, if set.
262 */
263 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
264 if (interruptibility & 3)
265 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
266 interruptibility & ~3);
267}
268
269static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
270{
271 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
272 vmcs_readl(GUEST_RIP));
273 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
274 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
275 GP_VECTOR |
276 INTR_TYPE_EXCEPTION |
277 INTR_INFO_DELIEVER_CODE_MASK |
278 INTR_INFO_VALID_MASK);
279}
280
281/*
282 * reads and returns guest's timestamp counter "register"
283 * guest_tsc = host_tsc + tsc_offset -- 21.3
284 */
285static u64 guest_read_tsc(void)
286{
287 u64 host_tsc, tsc_offset;
288
289 rdtscll(host_tsc);
290 tsc_offset = vmcs_read64(TSC_OFFSET);
291 return host_tsc + tsc_offset;
292}
293
294/*
295 * writes 'guest_tsc' into guest's timestamp counter "register"
296 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
297 */
298static void guest_write_tsc(u64 guest_tsc)
299{
300 u64 host_tsc;
301
302 rdtscll(host_tsc);
303 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
304}
305
306static void reload_tss(void)
307{
05b3e0c2 308#ifndef CONFIG_X86_64
6aa8b732
AK		 309
310 /*
311 * VT restores TR but not its size. Useless.
312 */
313 struct descriptor_table gdt;
314 struct segment_descriptor *descs;
315
316 get_gdt(&gdt);
317 descs = (void *)gdt.base;
318 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
319 load_TR_desc();
320#endif
321}
322
323/*
324 * Reads an msr value (of 'msr_index') into 'pdata'.
325 * Returns 0 on success, non-0 otherwise.
326 * Assumes vcpu_load() was already called.
327 */
328static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
329{
330 u64 data;
331 struct vmx_msr_entry *msr;
332
333 if (!pdata) {
334 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
335 return -EINVAL;
336 }
337
338 switch (msr_index) {
05b3e0c2 339#ifdef CONFIG_X86_64
6aa8b732
AK		 340 case MSR_FS_BASE:
341 data = vmcs_readl(GUEST_FS_BASE);
342 break;
343 case MSR_GS_BASE:
344 data = vmcs_readl(GUEST_GS_BASE);
345 break;
346 case MSR_EFER:
347 data = vcpu->shadow_efer;
348 break;
349#endif
350 case MSR_IA32_TIME_STAMP_COUNTER:
351 data = guest_read_tsc();
352 break;
353 case MSR_IA32_SYSENTER_CS:
354 data = vmcs_read32(GUEST_SYSENTER_CS);
355 break;
356 case MSR_IA32_SYSENTER_EIP:
357 data = vmcs_read32(GUEST_SYSENTER_EIP);
358 break;
359 case MSR_IA32_SYSENTER_ESP:
360 data = vmcs_read32(GUEST_SYSENTER_ESP);
361 break;
671d6564
AK		 362 case 0xc0010010: /* SYSCFG */
363 case 0xc0010015: /* HWCR */
364 case MSR_IA32_PLATFORM_ID:
0f8e3d36
MR		 365 case MSR_IA32_P5_MC_ADDR:
366 case MSR_IA32_P5_MC_TYPE:
6aa8b732
AK		 367 case MSR_IA32_MC0_CTL:
368 case MSR_IA32_MCG_STATUS:
369 case MSR_IA32_MCG_CAP:
370 case MSR_IA32_MC0_MISC:
371 case MSR_IA32_MC0_MISC+4:
372 case MSR_IA32_MC0_MISC+8:
373 case MSR_IA32_MC0_MISC+12:
374 case MSR_IA32_MC0_MISC+16:
375 case MSR_IA32_UCODE_REV:
376 /* MTRR registers */
377 case 0xfe:
378 case 0x200 ... 0x2ff:
379 data = 0;
380 break;
381 case MSR_IA32_APICBASE:
382 data = vcpu->apic_base;
383 break;
384 default:
385 msr = find_msr_entry(vcpu, msr_index);
386 if (!msr) {
387 printk(KERN_ERR "kvm: unhandled rdmsr: %x\n", msr_index);
388 return 1;
389 }
390 data = msr->data;
391 break;
392 }
393
394 *pdata = data;
395 return 0;
396}
397
398/*
399 * Writes msr value into into the appropriate "register".
400 * Returns 0 on success, non-0 otherwise.
401 * Assumes vcpu_load() was already called.
402 */
403static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
404{
405 struct vmx_msr_entry *msr;
406 switch (msr_index) {
05b3e0c2 407#ifdef CONFIG_X86_64
6aa8b732
AK		 408 case MSR_FS_BASE:
409 vmcs_writel(GUEST_FS_BASE, data);
410 break;
411 case MSR_GS_BASE:
412 vmcs_writel(GUEST_GS_BASE, data);
413 break;
414#endif
415 case MSR_IA32_SYSENTER_CS:
416 vmcs_write32(GUEST_SYSENTER_CS, data);
417 break;
418 case MSR_IA32_SYSENTER_EIP:
419 vmcs_write32(GUEST_SYSENTER_EIP, data);
420 break;
421 case MSR_IA32_SYSENTER_ESP:
422 vmcs_write32(GUEST_SYSENTER_ESP, data);
423 break;
424#ifdef __x86_64
425 case MSR_EFER:
426 set_efer(vcpu, data);
427 break;
428 case MSR_IA32_MC0_STATUS:
429 printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n"
430 , __FUNCTION__, data);
431 break;
432#endif
433 case MSR_IA32_TIME_STAMP_COUNTER: {
434 guest_write_tsc(data);
435 break;
436 }
437 case MSR_IA32_UCODE_REV:
438 case MSR_IA32_UCODE_WRITE:
439 case 0x200 ... 0x2ff: /* MTRRs */
440 break;
441 case MSR_IA32_APICBASE:
442 vcpu->apic_base = data;
443 break;
444 default:
445 msr = find_msr_entry(vcpu, msr_index);
446 if (!msr) {
447 printk(KERN_ERR "kvm: unhandled wrmsr: 0x%x\n", msr_index);
448 return 1;
449 }
450 msr->data = data;
451 break;
452 }
453
454 return 0;
455}
456
457/*
458 * Sync the rsp and rip registers into the vcpu structure. This allows
459 * registers to be accessed by indexing vcpu->regs.
460 */
461static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
462{
463 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
464 vcpu->rip = vmcs_readl(GUEST_RIP);
465}
466
467/*
468 * Syncs rsp and rip back into the vmcs. Should be called after possible
469 * modification.
470 */
471static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
472{
473 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
474 vmcs_writel(GUEST_RIP, vcpu->rip);
475}
476
477static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
478{
479 unsigned long dr7 = 0x400;
480 u32 exception_bitmap;
481 int old_singlestep;
482
483 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
484 old_singlestep = vcpu->guest_debug.singlestep;
485
486 vcpu->guest_debug.enabled = dbg->enabled;
487 if (vcpu->guest_debug.enabled) {
488 int i;
489
490 dr7 |= 0x200; /* exact */
491 for (i = 0; i < 4; ++i) {
492 if (!dbg->breakpoints[i].enabled)
493 continue;
494 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
495 dr7 |= 2 << (i*2); /* global enable */
496 dr7 |= 0 << (i*4+16); /* execution breakpoint */
497 }
498
499 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
500
501 vcpu->guest_debug.singlestep = dbg->singlestep;
502 } else {
503 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
504 vcpu->guest_debug.singlestep = 0;
505 }
506
507 if (old_singlestep && !vcpu->guest_debug.singlestep) {
508 unsigned long flags;
509
510 flags = vmcs_readl(GUEST_RFLAGS);
511 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
512 vmcs_writel(GUEST_RFLAGS, flags);
513 }
514
515 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
516 vmcs_writel(GUEST_DR7, dr7);
517
518 return 0;
519}
520
521static __init int cpu_has_kvm_support(void)
522{
523 unsigned long ecx = cpuid_ecx(1);
524 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
525}
526
527static __init int vmx_disabled_by_bios(void)
528{
529 u64 msr;
530
531 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
532 return (msr & 5) == 1; /* locked but not enabled */
533}
534
535static __init void hardware_enable(void *garbage)
536{
537 int cpu = raw_smp_processor_id();
538 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
539 u64 old;
540
541 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
bfdc0c28 542 if ((old & 5) != 5)
6aa8b732
AK		 543 /* enable and lock */
544 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
545 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
546 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
547 : "memory", "cc");
548}
549
550static void hardware_disable(void *garbage)
551{
552 asm volatile (ASM_VMX_VMXOFF : : : "cc");
553}
554
555static __init void setup_vmcs_descriptor(void)
556{
557 u32 vmx_msr_low, vmx_msr_high;
558
559 rdmsr(MSR_IA32_VMX_BASIC_MSR, vmx_msr_low, vmx_msr_high);
560 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
561 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
562 vmcs_descriptor.revision_id = vmx_msr_low;
563};
564
565static struct vmcs *alloc_vmcs_cpu(int cpu)
566{
567 int node = cpu_to_node(cpu);
568 struct page *pages;
569 struct vmcs *vmcs;
570
571 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
572 if (!pages)
573 return NULL;
574 vmcs = page_address(pages);
575 memset(vmcs, 0, vmcs_descriptor.size);
576 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
577 return vmcs;
578}
579
580static struct vmcs *alloc_vmcs(void)
581{
582 return alloc_vmcs_cpu(smp_processor_id());
583}
584
585static void free_vmcs(struct vmcs *vmcs)
586{
587 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
588}
589
590static __exit void free_kvm_area(void)
591{
592 int cpu;
593
594 for_each_online_cpu(cpu)
595 free_vmcs(per_cpu(vmxarea, cpu));
596}
597
598extern struct vmcs *alloc_vmcs_cpu(int cpu);
599
600static __init int alloc_kvm_area(void)
601{
602 int cpu;
603
604 for_each_online_cpu(cpu) {
605 struct vmcs *vmcs;
606
607 vmcs = alloc_vmcs_cpu(cpu);
608 if (!vmcs) {
609 free_kvm_area();
610 return -ENOMEM;
611 }
612
613 per_cpu(vmxarea, cpu) = vmcs;
614 }
615 return 0;
616}
617
618static __init int hardware_setup(void)
619{
620 setup_vmcs_descriptor();
621 return alloc_kvm_area();
622}
623
624static __exit void hardware_unsetup(void)
625{
626 free_kvm_area();
627}
628
629static void update_exception_bitmap(struct kvm_vcpu *vcpu)
630{
631 if (vcpu->rmode.active)
632 vmcs_write32(EXCEPTION_BITMAP, ~0);
633 else
634 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
635}
636
637static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
638{
639 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
640
641 if (vmcs_readl(sf->base) == save->base) {
642 vmcs_write16(sf->selector, save->selector);
643 vmcs_writel(sf->base, save->base);
644 vmcs_write32(sf->limit, save->limit);
645 vmcs_write32(sf->ar_bytes, save->ar);
646 } else {
647 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
648 << AR_DPL_SHIFT;
649 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
650 }
651}
652
653static void enter_pmode(struct kvm_vcpu *vcpu)
654{
655 unsigned long flags;
656
657 vcpu->rmode.active = 0;
658
659 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
660 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
661 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
662
663 flags = vmcs_readl(GUEST_RFLAGS);
664 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
665 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
666 vmcs_writel(GUEST_RFLAGS, flags);
667
668 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
669 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
670
671 update_exception_bitmap(vcpu);
672
673 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
674 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
675 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
676 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
677
678 vmcs_write16(GUEST_SS_SELECTOR, 0);
679 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
680
681 vmcs_write16(GUEST_CS_SELECTOR,
682 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
683 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
684}
685
686static int rmode_tss_base(struct kvm* kvm)
687{
688 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
689 return base_gfn << PAGE_SHIFT;
690}
691
692static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
693{
694 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
695
696 save->selector = vmcs_read16(sf->selector);
697 save->base = vmcs_readl(sf->base);
698 save->limit = vmcs_read32(sf->limit);
699 save->ar = vmcs_read32(sf->ar_bytes);
700 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
701 vmcs_write32(sf->limit, 0xffff);
702 vmcs_write32(sf->ar_bytes, 0xf3);
703}
704
705static void enter_rmode(struct kvm_vcpu *vcpu)
706{
707 unsigned long flags;
708
709 vcpu->rmode.active = 1;
710
711 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
712 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
713
714 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
715 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
716
717 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
718 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
719
720 flags = vmcs_readl(GUEST_RFLAGS);
721 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
722
723 flags |= IOPL_MASK | X86_EFLAGS_VM;
724
725 vmcs_writel(GUEST_RFLAGS, flags);
726 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
727 update_exception_bitmap(vcpu);
728
729 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
730 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
731 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
732
733 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 734 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
6aa8b732
AK		 735 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
736
737 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
738 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
739 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
740 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
741}
742
05b3e0c2 743#ifdef CONFIG_X86_64
6aa8b732
AK		 744
745static void enter_lmode(struct kvm_vcpu *vcpu)
746{
747 u32 guest_tr_ar;
748
749 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
750 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
751 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
752 __FUNCTION__);
753 vmcs_write32(GUEST_TR_AR_BYTES,
754 (guest_tr_ar & ~AR_TYPE_MASK)
755 | AR_TYPE_BUSY_64_TSS);
756 }
757
758 vcpu->shadow_efer |= EFER_LMA;
759
760 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
761 vmcs_write32(VM_ENTRY_CONTROLS,
762 vmcs_read32(VM_ENTRY_CONTROLS)
763 | VM_ENTRY_CONTROLS_IA32E_MASK);
764}
765
766static void exit_lmode(struct kvm_vcpu *vcpu)
767{
768 vcpu->shadow_efer &= ~EFER_LMA;
769
770 vmcs_write32(VM_ENTRY_CONTROLS,
771 vmcs_read32(VM_ENTRY_CONTROLS)
772 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
773}
774
775#endif
776
777static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
778{
779 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
780 enter_pmode(vcpu);
781
782 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
783 enter_rmode(vcpu);
784
05b3e0c2 785#ifdef CONFIG_X86_64
6aa8b732
AK		 786 if (vcpu->shadow_efer & EFER_LME) {
787 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
788 enter_lmode(vcpu);
789 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
790 exit_lmode(vcpu);
791 }
792#endif
793
794 vmcs_writel(CR0_READ_SHADOW, cr0);
795 vmcs_writel(GUEST_CR0,
796 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
797 vcpu->cr0 = cr0;
798}
799
800/*
801 * Used when restoring the VM to avoid corrupting segment registers
802 */
803static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
804{
805 vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
806 update_exception_bitmap(vcpu);
807 vmcs_writel(CR0_READ_SHADOW, cr0);
808 vmcs_writel(GUEST_CR0,
809 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
810 vcpu->cr0 = cr0;
811}
812
813static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
814{
815 vmcs_writel(GUEST_CR3, cr3);
816}
817
818static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
819{
820 vmcs_writel(CR4_READ_SHADOW, cr4);
821 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
822 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
823 vcpu->cr4 = cr4;
824}
825
05b3e0c2 826#ifdef CONFIG_X86_64
6aa8b732
AK		 827
828static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
829{
830 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
831
832 vcpu->shadow_efer = efer;
833 if (efer & EFER_LMA) {
834 vmcs_write32(VM_ENTRY_CONTROLS,
835 vmcs_read32(VM_ENTRY_CONTROLS) |
836 VM_ENTRY_CONTROLS_IA32E_MASK);
837 msr->data = efer;
838
839 } else {
840 vmcs_write32(VM_ENTRY_CONTROLS,
841 vmcs_read32(VM_ENTRY_CONTROLS) &
842 ~VM_ENTRY_CONTROLS_IA32E_MASK);
843
844 msr->data = efer & ~EFER_LME;
845 }
846}
847
848#endif
849
850static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
851{
852 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
853
854 return vmcs_readl(sf->base);
855}
856
857static void vmx_get_segment(struct kvm_vcpu *vcpu,
858 struct kvm_segment *var, int seg)
859{
860 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
861 u32 ar;
862
863 var->base = vmcs_readl(sf->base);
864 var->limit = vmcs_read32(sf->limit);
865 var->selector = vmcs_read16(sf->selector);
866 ar = vmcs_read32(sf->ar_bytes);
867 if (ar & AR_UNUSABLE_MASK)
868 ar = 0;
869 var->type = ar & 15;
870 var->s = (ar >> 4) & 1;
871 var->dpl = (ar >> 5) & 3;
872 var->present = (ar >> 7) & 1;
873 var->avl = (ar >> 12) & 1;
874 var->l = (ar >> 13) & 1;
875 var->db = (ar >> 14) & 1;
876 var->g = (ar >> 15) & 1;
877 var->unusable = (ar >> 16) & 1;
878}
879
880static void vmx_set_segment(struct kvm_vcpu *vcpu,
881 struct kvm_segment *var, int seg)
882{
883 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
884 u32 ar;
885
886 vmcs_writel(sf->base, var->base);
887 vmcs_write32(sf->limit, var->limit);
888 vmcs_write16(sf->selector, var->selector);
889 if (var->unusable)
890 ar = 1 << 16;
891 else {
892 ar = var->type & 15;
893 ar |= (var->s & 1) << 4;
894 ar |= (var->dpl & 3) << 5;
895 ar |= (var->present & 1) << 7;
896 ar |= (var->avl & 1) << 12;
897 ar |= (var->l & 1) << 13;
898 ar |= (var->db & 1) << 14;
899 ar |= (var->g & 1) << 15;
900 }
f7fbf1fd
UL		 901 if (ar == 0) /* a 0 value means unusable */
902 ar = AR_UNUSABLE_MASK;
6aa8b732
AK		 903 vmcs_write32(sf->ar_bytes, ar);
904}
905
6aa8b732
AK		 906static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
907{
908 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
909
910 *db = (ar >> 14) & 1;
911 *l = (ar >> 13) & 1;
912}
913
914static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
915{
916 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
917 dt->base = vmcs_readl(GUEST_IDTR_BASE);
918}
919
920static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
921{
922 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
923 vmcs_writel(GUEST_IDTR_BASE, dt->base);
924}
925
926static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
927{
928 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
929 dt->base = vmcs_readl(GUEST_GDTR_BASE);
930}
931
932static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
933{
934 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
935 vmcs_writel(GUEST_GDTR_BASE, dt->base);
936}
937
938static int init_rmode_tss(struct kvm* kvm)
939{
940 struct page *p1, *p2, *p3;
941 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
942 char *page;
943
944 p1 = _gfn_to_page(kvm, fn++);
945 p2 = _gfn_to_page(kvm, fn++);
946 p3 = _gfn_to_page(kvm, fn);
947
948 if (!p1 || !p2 || !p3) {
949 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
950 return 0;
951 }
952
953 page = kmap_atomic(p1, KM_USER0);
954 memset(page, 0, PAGE_SIZE);
955 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
956 kunmap_atomic(page, KM_USER0);
957
958 page = kmap_atomic(p2, KM_USER0);
959 memset(page, 0, PAGE_SIZE);
960 kunmap_atomic(page, KM_USER0);
961
962 page = kmap_atomic(p3, KM_USER0);
963 memset(page, 0, PAGE_SIZE);
964 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
965 kunmap_atomic(page, KM_USER0);
966
967 return 1;
968}
969
970static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
971{
972 u32 msr_high, msr_low;
973
974 rdmsr(msr, msr_low, msr_high);
975
976 val &= msr_high;
977 val |= msr_low;
978 vmcs_write32(vmcs_field, val);
979}
980
981static void seg_setup(int seg)
982{
983 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
984
985 vmcs_write16(sf->selector, 0);
986 vmcs_writel(sf->base, 0);
987 vmcs_write32(sf->limit, 0xffff);
988 vmcs_write32(sf->ar_bytes, 0x93);
989}
990
991/*
992 * Sets up the vmcs for emulated real mode.
993 */
994static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
995{
996 u32 host_sysenter_cs;
997 u32 junk;
998 unsigned long a;
999 struct descriptor_table dt;
1000 int i;
1001 int ret = 0;
1002 int nr_good_msrs;
1003 extern asmlinkage void kvm_vmx_return(void);
1004
1005 if (!init_rmode_tss(vcpu->kvm)) {
1006 ret = -ENOMEM;
1007 goto out;
1008 }
1009
1010 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1011 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1012 vcpu->cr8 = 0;
1013 vcpu->apic_base = 0xfee00000 |
1014 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1015 MSR_IA32_APICBASE_ENABLE;
1016
1017 fx_init(vcpu);
1018
1019 /*
1020 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1021 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1022 */
1023 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1024 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1025 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1026 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1027
1028 seg_setup(VCPU_SREG_DS);
1029 seg_setup(VCPU_SREG_ES);
1030 seg_setup(VCPU_SREG_FS);
1031 seg_setup(VCPU_SREG_GS);
1032 seg_setup(VCPU_SREG_SS);
1033
1034 vmcs_write16(GUEST_TR_SELECTOR, 0);
1035 vmcs_writel(GUEST_TR_BASE, 0);
1036 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1037 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1038
1039 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1040 vmcs_writel(GUEST_LDTR_BASE, 0);
1041 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1042 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1043
1044 vmcs_write32(GUEST_SYSENTER_CS, 0);
1045 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1046 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1047
1048 vmcs_writel(GUEST_RFLAGS, 0x02);
1049 vmcs_writel(GUEST_RIP, 0xfff0);
1050 vmcs_writel(GUEST_RSP, 0);
1051
1052 vmcs_writel(GUEST_CR3, 0);
1053
1054 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1055 vmcs_writel(GUEST_DR7, 0x400);
1056
1057 vmcs_writel(GUEST_GDTR_BASE, 0);
1058 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1059
1060 vmcs_writel(GUEST_IDTR_BASE, 0);
1061 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1062
1063 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1064 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1065 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1066
1067 /* I/O */
1068 vmcs_write64(IO_BITMAP_A, 0);
1069 vmcs_write64(IO_BITMAP_B, 0);
1070
1071 guest_write_tsc(0);
1072
1073 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1074
1075 /* Special registers */
1076 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1077
1078 /* Control */
1079 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS_MSR,
1080 PIN_BASED_VM_EXEC_CONTROL,
1081 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1082 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1083 );
1084 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS_MSR,
1085 CPU_BASED_VM_EXEC_CONTROL,
1086 CPU_BASED_HLT_EXITING /* 20.6.2 */
1087 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1088 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1089 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1090 | CPU_BASED_INVDPG_EXITING
1091 | CPU_BASED_MOV_DR_EXITING
1092 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1093 );
1094
1095 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1096 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1097 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1098 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1099
1100 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1101 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1102 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1103
1104 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1105 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1106 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1107 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1108 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1109 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1110#ifdef CONFIG_X86_64
6aa8b732
AK		 1111 rdmsrl(MSR_FS_BASE, a);
1112 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1113 rdmsrl(MSR_GS_BASE, a);
1114 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1115#else
1116 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1117 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1118#endif
1119
1120 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1121
1122 get_idt(&dt);
1123 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1124
1125
1126 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1127
1128 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1129 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1130 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1131 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1132 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1133 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1134
1135 ret = -ENOMEM;
1136 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1137 if (!vcpu->guest_msrs)
1138 goto out;
1139 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1140 if (!vcpu->host_msrs)
1141 goto out_free_guest_msrs;
1142
1143 for (i = 0; i < NR_VMX_MSR; ++i) {
1144 u32 index = vmx_msr_index[i];
1145 u32 data_low, data_high;
1146 u64 data;
1147 int j = vcpu->nmsrs;
1148
1149 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1150 continue;
1151 data = data_low | ((u64)data_high << 32);
1152 vcpu->host_msrs[j].index = index;
1153 vcpu->host_msrs[j].reserved = 0;
1154 vcpu->host_msrs[j].data = data;
1155 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1156 ++vcpu->nmsrs;
1157 }
1158 printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1159
1160 nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1161 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1162 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1163 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1164 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1165 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1166 virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
1167 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS_MSR, VM_EXIT_CONTROLS,
1168 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1169 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1170 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1171 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1172
1173
1174 /* 22.2.1, 20.8.1 */
1175 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS_MSR,
1176 VM_ENTRY_CONTROLS, 0);
1177 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1178
3b99ab24 1179#ifdef CONFIG_X86_64
6aa8b732
AK		 1180 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1181 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1182#endif
6aa8b732
AK		 1183
1184 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1185 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1186
1187 vcpu->cr0 = 0x60000010;
1188 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1189 vmx_set_cr4(vcpu, 0);
05b3e0c2 1190#ifdef CONFIG_X86_64
6aa8b732
AK		 1191 vmx_set_efer(vcpu, 0);
1192#endif
1193
1194 return 0;
1195
1196out_free_guest_msrs:
1197 kfree(vcpu->guest_msrs);
1198out:
1199 return ret;
1200}
1201
1202static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1203{
1204 u16 ent[2];
1205 u16 cs;
1206 u16 ip;
1207 unsigned long flags;
1208 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1209 u16 sp = vmcs_readl(GUEST_RSP);
1210 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1211
1212 if (sp > ss_limit || sp - 6 > sp) {
1213 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1214 __FUNCTION__,
1215 vmcs_readl(GUEST_RSP),
1216 vmcs_readl(GUEST_SS_BASE),
1217 vmcs_read32(GUEST_SS_LIMIT));
1218 return;
1219 }
1220
1221 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1222 sizeof(ent)) {
1223 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1224 return;
1225 }
1226
1227 flags = vmcs_readl(GUEST_RFLAGS);
1228 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1229 ip = vmcs_readl(GUEST_RIP);
1230
1231
1232 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1233 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1234 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1235 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1236 return;
1237 }
1238
1239 vmcs_writel(GUEST_RFLAGS, flags &
1240 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1241 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1242 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1243 vmcs_writel(GUEST_RIP, ent[0]);
1244 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1245}
1246
1247static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1248{
1249 int word_index = __ffs(vcpu->irq_summary);
1250 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1251 int irq = word_index * BITS_PER_LONG + bit_index;
1252
1253 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1254 if (!vcpu->irq_pending[word_index])
1255 clear_bit(word_index, &vcpu->irq_summary);
1256
1257 if (vcpu->rmode.active) {
1258 inject_rmode_irq(vcpu, irq);
1259 return;
1260 }
1261 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1262 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1263}
1264
1265static void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
1266{
1267 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)
1268 && (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0)
1269 /*
1270 * Interrupts enabled, and not blocked by sti or mov ss. Good.
1271 */
1272 kvm_do_inject_irq(vcpu);
1273 else
1274 /*
1275 * Interrupts blocked. Wait for unblock.
1276 */
1277 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1278 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1279 | CPU_BASED_VIRTUAL_INTR_PENDING);
1280}
1281
1282static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1283{
1284 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1285
1286 set_debugreg(dbg->bp[0], 0);
1287 set_debugreg(dbg->bp[1], 1);
1288 set_debugreg(dbg->bp[2], 2);
1289 set_debugreg(dbg->bp[3], 3);
1290
1291 if (dbg->singlestep) {
1292 unsigned long flags;
1293
1294 flags = vmcs_readl(GUEST_RFLAGS);
1295 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1296 vmcs_writel(GUEST_RFLAGS, flags);
1297 }
1298}
1299
1300static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1301 int vec, u32 err_code)
1302{
1303 if (!vcpu->rmode.active)
1304 return 0;
1305
1306 if (vec == GP_VECTOR && err_code == 0)
1307 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1308 return 1;
1309 return 0;
1310}
1311
1312static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1313{
1314 u32 intr_info, error_code;
1315 unsigned long cr2, rip;
1316 u32 vect_info;
1317 enum emulation_result er;
1318
1319 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1320 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1321
1322 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1323 !is_page_fault(intr_info)) {
1324 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1325 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1326 }
1327
1328 if (is_external_interrupt(vect_info)) {
1329 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1330 set_bit(irq, vcpu->irq_pending);
1331 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1332 }
1333
1334 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1335 asm ("int $2");
1336 return 1;
1337 }
1338 error_code = 0;
1339 rip = vmcs_readl(GUEST_RIP);
1340 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1341 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1342 if (is_page_fault(intr_info)) {
1343 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1344
1345 spin_lock(&vcpu->kvm->lock);
1346 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1347 spin_unlock(&vcpu->kvm->lock);
1348 return 1;
1349 }
1350
1351 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1352 spin_unlock(&vcpu->kvm->lock);
1353
1354 switch (er) {
1355 case EMULATE_DONE:
1356 return 1;
1357 case EMULATE_DO_MMIO:
1358 ++kvm_stat.mmio_exits;
1359 kvm_run->exit_reason = KVM_EXIT_MMIO;
1360 return 0;
1361 case EMULATE_FAIL:
1362 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1363 break;
1364 default:
1365 BUG();
1366 }
1367 }
1368
1369 if (vcpu->rmode.active &&
1370 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1371 error_code))
1372 return 1;
1373
1374 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1375 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1376 return 0;
1377 }
1378 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1379 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1380 kvm_run->ex.error_code = error_code;
1381 return 0;
1382}
1383
1384static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1385 struct kvm_run *kvm_run)
1386{
1387 ++kvm_stat.irq_exits;
1388 return 1;
1389}
1390
1391
1392static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1393{
1394 u64 inst;
1395 gva_t rip;
1396 int countr_size;
1397 int i, n;
1398
1399 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1400 countr_size = 2;
1401 } else {
1402 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1403
1404 countr_size = (cs_ar & AR_L_MASK) ? 8:
1405 (cs_ar & AR_DB_MASK) ? 4: 2;
1406 }
1407
1408 rip = vmcs_readl(GUEST_RIP);
1409 if (countr_size != 8)
1410 rip += vmcs_readl(GUEST_CS_BASE);
1411
1412 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1413
1414 for (i = 0; i < n; i++) {
1415 switch (((u8*)&inst)[i]) {
1416 case 0xf0:
1417 case 0xf2:
1418 case 0xf3:
1419 case 0x2e:
1420 case 0x36:
1421 case 0x3e:
1422 case 0x26:
1423 case 0x64:
1424 case 0x65:
1425 case 0x66:
1426 break;
1427 case 0x67:
1428 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1429 default:
1430 goto done;
1431 }
1432 }
1433 return 0;
1434done:
1435 countr_size *= 8;
1436 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1437 return 1;
1438}
1439
1440static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1441{
1442 u64 exit_qualification;
1443
1444 ++kvm_stat.io_exits;
1445 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1446 kvm_run->exit_reason = KVM_EXIT_IO;
1447 if (exit_qualification & 8)
1448 kvm_run->io.direction = KVM_EXIT_IO_IN;
1449 else
1450 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1451 kvm_run->io.size = (exit_qualification & 7) + 1;
1452 kvm_run->io.string = (exit_qualification & 16) != 0;
1453 kvm_run->io.string_down
1454 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1455 kvm_run->io.rep = (exit_qualification & 32) != 0;
1456 kvm_run->io.port = exit_qualification >> 16;
1457 if (kvm_run->io.string) {
1458 if (!get_io_count(vcpu, &kvm_run->io.count))
1459 return 1;
1460 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1461 } else
1462 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1463 return 0;
1464}
1465
1466static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1467{
1468 u64 address = vmcs_read64(EXIT_QUALIFICATION);
1469 int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1470 spin_lock(&vcpu->kvm->lock);
1471 vcpu->mmu.inval_page(vcpu, address);
1472 spin_unlock(&vcpu->kvm->lock);
1473 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1474 return 1;
1475}
1476
1477static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1478{
1479 u64 exit_qualification;
1480 int cr;
1481 int reg;
1482
1483 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1484 cr = exit_qualification & 15;
1485 reg = (exit_qualification >> 8) & 15;
1486 switch ((exit_qualification >> 4) & 3) {
1487 case 0: /* mov to cr */
1488 switch (cr) {
1489 case 0:
1490 vcpu_load_rsp_rip(vcpu);
1491 set_cr0(vcpu, vcpu->regs[reg]);
1492 skip_emulated_instruction(vcpu);
1493 return 1;
1494 case 3:
1495 vcpu_load_rsp_rip(vcpu);
1496 set_cr3(vcpu, vcpu->regs[reg]);
1497 skip_emulated_instruction(vcpu);
1498 return 1;
1499 case 4:
1500 vcpu_load_rsp_rip(vcpu);
1501 set_cr4(vcpu, vcpu->regs[reg]);
1502 skip_emulated_instruction(vcpu);
1503 return 1;
1504 case 8:
1505 vcpu_load_rsp_rip(vcpu);
1506 set_cr8(vcpu, vcpu->regs[reg]);
1507 skip_emulated_instruction(vcpu);
1508 return 1;
1509 };
1510 break;
1511 case 1: /*mov from cr*/
1512 switch (cr) {
1513 case 3:
1514 vcpu_load_rsp_rip(vcpu);
1515 vcpu->regs[reg] = vcpu->cr3;
1516 vcpu_put_rsp_rip(vcpu);
1517 skip_emulated_instruction(vcpu);
1518 return 1;
1519 case 8:
1520 printk(KERN_DEBUG "handle_cr: read CR8 "
1521 "cpu erratum AA15\n");
1522 vcpu_load_rsp_rip(vcpu);
1523 vcpu->regs[reg] = vcpu->cr8;
1524 vcpu_put_rsp_rip(vcpu);
1525 skip_emulated_instruction(vcpu);
1526 return 1;
1527 }
1528 break;
1529 case 3: /* lmsw */
1530 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1531
1532 skip_emulated_instruction(vcpu);
1533 return 1;
1534 default:
1535 break;
1536 }
1537 kvm_run->exit_reason = 0;
1538 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1539 (int)(exit_qualification >> 4) & 3, cr);
1540 return 0;
1541}
1542
1543static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1544{
1545 u64 exit_qualification;
1546 unsigned long val;
1547 int dr, reg;
1548
1549 /*
1550 * FIXME: this code assumes the host is debugging the guest.
1551 * need to deal with guest debugging itself too.
1552 */
1553 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1554 dr = exit_qualification & 7;
1555 reg = (exit_qualification >> 8) & 15;
1556 vcpu_load_rsp_rip(vcpu);
1557 if (exit_qualification & 16) {
1558 /* mov from dr */
1559 switch (dr) {
1560 case 6:
1561 val = 0xffff0ff0;
1562 break;
1563 case 7:
1564 val = 0x400;
1565 break;
1566 default:
1567 val = 0;
1568 }
1569 vcpu->regs[reg] = val;
1570 } else {
1571 /* mov to dr */
1572 }
1573 vcpu_put_rsp_rip(vcpu);
1574 skip_emulated_instruction(vcpu);
1575 return 1;
1576}
1577
1578static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1579{
1580 kvm_run->exit_reason = KVM_EXIT_CPUID;
1581 return 0;
1582}
1583
1584static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1585{
1586 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1587 u64 data;
1588
1589 if (vmx_get_msr(vcpu, ecx, &data)) {
1590 vmx_inject_gp(vcpu, 0);
1591 return 1;
1592 }
1593
1594 /* FIXME: handling of bits 32:63 of rax, rdx */
1595 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1596 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1597 skip_emulated_instruction(vcpu);
1598 return 1;
1599}
1600
1601static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1602{
1603 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1604 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1605 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1606
1607 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1608 vmx_inject_gp(vcpu, 0);
1609 return 1;
1610 }
1611
1612 skip_emulated_instruction(vcpu);
1613 return 1;
1614}
1615
1616static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1617 struct kvm_run *kvm_run)
1618{
1619 /* Turn off interrupt window reporting. */
1620 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1621 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1622 & ~CPU_BASED_VIRTUAL_INTR_PENDING);
1623 return 1;
1624}
1625
1626static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1627{
1628 skip_emulated_instruction(vcpu);
1629 if (vcpu->irq_summary && (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF))
1630 return 1;
1631
1632 kvm_run->exit_reason = KVM_EXIT_HLT;
1633 return 0;
1634}
1635
1636/*
1637 * The exit handlers return 1 if the exit was handled fully and guest execution
1638 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1639 * to be done to userspace and return 0.
1640 */
1641static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1642 struct kvm_run *kvm_run) = {
1643 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1644 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1645 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1646 [EXIT_REASON_INVLPG] = handle_invlpg,
1647 [EXIT_REASON_CR_ACCESS] = handle_cr,
1648 [EXIT_REASON_DR_ACCESS] = handle_dr,
1649 [EXIT_REASON_CPUID] = handle_cpuid,
1650 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1651 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1652 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1653 [EXIT_REASON_HLT] = handle_halt,
1654};
1655
1656static const int kvm_vmx_max_exit_handlers =
1657 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1658
1659/*
1660 * The guest has exited. See if we can fix it or if we need userspace
1661 * assistance.
1662 */
1663static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1664{
1665 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1666 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1667
1668 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1669 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1670 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1671 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1672 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1673 if (exit_reason < kvm_vmx_max_exit_handlers
1674 && kvm_vmx_exit_handlers[exit_reason])
1675 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1676 else {
1677 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1678 kvm_run->hw.hardware_exit_reason = exit_reason;
1679 }
1680 return 0;
1681}
1682
1683static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1684{
1685 u8 fail;
1686 u16 fs_sel, gs_sel, ldt_sel;
1687 int fs_gs_ldt_reload_needed;
1688
1689again:
1690 /*
1691 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1692 * allow segment selectors with cpl > 0 or ti == 1.
1693 */
1694 fs_sel = read_fs();
1695 gs_sel = read_gs();
1696 ldt_sel = read_ldt();
1697 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1698 if (!fs_gs_ldt_reload_needed) {
1699 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1700 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1701 } else {
1702 vmcs_write16(HOST_FS_SELECTOR, 0);
1703 vmcs_write16(HOST_GS_SELECTOR, 0);
1704 }
1705
05b3e0c2 1706#ifdef CONFIG_X86_64
6aa8b732
AK		 1707 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1708 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1709#else
1710 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1711 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1712#endif
1713
1714 if (vcpu->irq_summary &&
1715 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1716 kvm_try_inject_irq(vcpu);
1717
1718 if (vcpu->guest_debug.enabled)
1719 kvm_guest_debug_pre(vcpu);
1720
1721 fx_save(vcpu->host_fx_image);
1722 fx_restore(vcpu->guest_fx_image);
1723
1724 save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1725 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1726
1727 asm (
1728 /* Store host registers */
1729 "pushf \n\t"
05b3e0c2 1730#ifdef CONFIG_X86_64
6aa8b732
AK		 1731 "push %%rax; push %%rbx; push %%rdx;"
1732 "push %%rsi; push %%rdi; push %%rbp;"
1733 "push %%r8; push %%r9; push %%r10; push %%r11;"
1734 "push %%r12; push %%r13; push %%r14; push %%r15;"
1735 "push %%rcx \n\t"
1736 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1737#else
1738 "pusha; push %%ecx \n\t"
1739 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1740#endif
1741 /* Check if vmlaunch of vmresume is needed */
1742 "cmp $0, %1 \n\t"
1743 /* Load guest registers. Don't clobber flags. */
05b3e0c2 1744#ifdef CONFIG_X86_64
6aa8b732
AK		 1745 "mov %c[cr2](%3), %%rax \n\t"
1746 "mov %%rax, %%cr2 \n\t"
1747 "mov %c[rax](%3), %%rax \n\t"
1748 "mov %c[rbx](%3), %%rbx \n\t"
1749 "mov %c[rdx](%3), %%rdx \n\t"
1750 "mov %c[rsi](%3), %%rsi \n\t"
1751 "mov %c[rdi](%3), %%rdi \n\t"
1752 "mov %c[rbp](%3), %%rbp \n\t"
1753 "mov %c[r8](%3), %%r8 \n\t"
1754 "mov %c[r9](%3), %%r9 \n\t"
1755 "mov %c[r10](%3), %%r10 \n\t"
1756 "mov %c[r11](%3), %%r11 \n\t"
1757 "mov %c[r12](%3), %%r12 \n\t"
1758 "mov %c[r13](%3), %%r13 \n\t"
1759 "mov %c[r14](%3), %%r14 \n\t"
1760 "mov %c[r15](%3), %%r15 \n\t"
1761 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1762#else
1763 "mov %c[cr2](%3), %%eax \n\t"
1764 "mov %%eax, %%cr2 \n\t"
1765 "mov %c[rax](%3), %%eax \n\t"
1766 "mov %c[rbx](%3), %%ebx \n\t"
1767 "mov %c[rdx](%3), %%edx \n\t"
1768 "mov %c[rsi](%3), %%esi \n\t"
1769 "mov %c[rdi](%3), %%edi \n\t"
1770 "mov %c[rbp](%3), %%ebp \n\t"
1771 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1772#endif
1773 /* Enter guest mode */
1774 "jne launched \n\t"
1775 ASM_VMX_VMLAUNCH "\n\t"
1776 "jmp kvm_vmx_return \n\t"
1777 "launched: " ASM_VMX_VMRESUME "\n\t"
1778 ".globl kvm_vmx_return \n\t"
1779 "kvm_vmx_return: "
1780 /* Save guest registers, load host registers, keep flags */
05b3e0c2 1781#ifdef CONFIG_X86_64
6aa8b732
AK		 1782 "xchg %3, 0(%%rsp) \n\t"
1783 "mov %%rax, %c[rax](%3) \n\t"
1784 "mov %%rbx, %c[rbx](%3) \n\t"
1785 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1786 "mov %%rdx, %c[rdx](%3) \n\t"
1787 "mov %%rsi, %c[rsi](%3) \n\t"
1788 "mov %%rdi, %c[rdi](%3) \n\t"
1789 "mov %%rbp, %c[rbp](%3) \n\t"
1790 "mov %%r8, %c[r8](%3) \n\t"
1791 "mov %%r9, %c[r9](%3) \n\t"
1792 "mov %%r10, %c[r10](%3) \n\t"
1793 "mov %%r11, %c[r11](%3) \n\t"
1794 "mov %%r12, %c[r12](%3) \n\t"
1795 "mov %%r13, %c[r13](%3) \n\t"
1796 "mov %%r14, %c[r14](%3) \n\t"
1797 "mov %%r15, %c[r15](%3) \n\t"
1798 "mov %%cr2, %%rax \n\t"
1799 "mov %%rax, %c[cr2](%3) \n\t"
1800 "mov 0(%%rsp), %3 \n\t"
1801
1802 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1803 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1804 "pop %%rbp; pop %%rdi; pop %%rsi;"
1805 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1806#else
1807 "xchg %3, 0(%%esp) \n\t"
1808 "mov %%eax, %c[rax](%3) \n\t"
1809 "mov %%ebx, %c[rbx](%3) \n\t"
1810 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1811 "mov %%edx, %c[rdx](%3) \n\t"
1812 "mov %%esi, %c[rsi](%3) \n\t"
1813 "mov %%edi, %c[rdi](%3) \n\t"
1814 "mov %%ebp, %c[rbp](%3) \n\t"
1815 "mov %%cr2, %%eax \n\t"
1816 "mov %%eax, %c[cr2](%3) \n\t"
1817 "mov 0(%%esp), %3 \n\t"
1818
1819 "pop %%ecx; popa \n\t"
1820#endif
1821 "setbe %0 \n\t"
1822 "popf \n\t"
1823 : "=g" (fail)
1824 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1825 "c"(vcpu),
1826 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1827 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1828 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1829 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1830 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1831 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1832 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 1833#ifdef CONFIG_X86_64
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AK		 1834 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1835 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1836 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1837 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1838 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1839 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1840 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1841 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1842#endif
1843 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1844 : "cc", "memory" );
1845
1846 ++kvm_stat.exits;
1847
1848 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1849 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1850
1851 fx_save(vcpu->guest_fx_image);
1852 fx_restore(vcpu->host_fx_image);
1853
05b3e0c2 1854#ifndef CONFIG_X86_64
6aa8b732
AK		 1855 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1856#endif
1857
1858 kvm_run->exit_type = 0;
1859 if (fail) {
1860 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1861 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1862 } else {
1863 if (fs_gs_ldt_reload_needed) {
1864 load_ldt(ldt_sel);
1865 load_fs(fs_sel);
1866 /*
1867 * If we have to reload gs, we must take care to
1868 * preserve our gs base.
1869 */
1870 local_irq_disable();
1871 load_gs(gs_sel);
05b3e0c2 1872#ifdef CONFIG_X86_64
6aa8b732
AK		 1873 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1874#endif
1875 local_irq_enable();
1876
1877 reload_tss();
1878 }
1879 vcpu->launched = 1;
1880 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1881 if (kvm_handle_exit(kvm_run, vcpu)) {
1882 /* Give scheduler a change to reschedule. */
1883 if (signal_pending(current)) {
1884 ++kvm_stat.signal_exits;
1885 return -EINTR;
1886 }
1887 kvm_resched(vcpu);
1888 goto again;
1889 }
1890 }
1891 return 0;
1892}
1893
1894static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1895{
1896 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1897}
1898
1899static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1900 unsigned long addr,
1901 u32 err_code)
1902{
1903 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1904
1905 ++kvm_stat.pf_guest;
1906
1907 if (is_page_fault(vect_info)) {
1908 printk(KERN_DEBUG "inject_page_fault: "
1909 "double fault 0x%lx @ 0x%lx\n",
1910 addr, vmcs_readl(GUEST_RIP));
1911 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1912 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1913 DF_VECTOR |
1914 INTR_TYPE_EXCEPTION |
1915 INTR_INFO_DELIEVER_CODE_MASK |
1916 INTR_INFO_VALID_MASK);
1917 return;
1918 }
1919 vcpu->cr2 = addr;
1920 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1921 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1922 PF_VECTOR |
1923 INTR_TYPE_EXCEPTION |
1924 INTR_INFO_DELIEVER_CODE_MASK |
1925 INTR_INFO_VALID_MASK);
1926
1927}
1928
1929static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1930{
1931 if (vcpu->vmcs) {
1932 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1933 free_vmcs(vcpu->vmcs);
1934 vcpu->vmcs = NULL;
1935 }
1936}
1937
1938static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1939{
1940 vmx_free_vmcs(vcpu);
1941}
1942
1943static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1944{
1945 struct vmcs *vmcs;
1946
1947 vmcs = alloc_vmcs();
1948 if (!vmcs)
1949 return -ENOMEM;
1950 vmcs_clear(vmcs);
1951 vcpu->vmcs = vmcs;
1952 vcpu->launched = 0;
1953 return 0;
1954}
1955
1956static struct kvm_arch_ops vmx_arch_ops = {
1957 .cpu_has_kvm_support = cpu_has_kvm_support,
1958 .disabled_by_bios = vmx_disabled_by_bios,
1959 .hardware_setup = hardware_setup,
1960 .hardware_unsetup = hardware_unsetup,
1961 .hardware_enable = hardware_enable,
1962 .hardware_disable = hardware_disable,
1963
1964 .vcpu_create = vmx_create_vcpu,
1965 .vcpu_free = vmx_free_vcpu,
1966
1967 .vcpu_load = vmx_vcpu_load,
1968 .vcpu_put = vmx_vcpu_put,
1969
1970 .set_guest_debug = set_guest_debug,
1971 .get_msr = vmx_get_msr,
1972 .set_msr = vmx_set_msr,
1973 .get_segment_base = vmx_get_segment_base,
1974 .get_segment = vmx_get_segment,
1975 .set_segment = vmx_set_segment,
6aa8b732
AK		 1976 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
1977 .set_cr0 = vmx_set_cr0,
1978 .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
1979 .set_cr3 = vmx_set_cr3,
1980 .set_cr4 = vmx_set_cr4,
05b3e0c2 1981#ifdef CONFIG_X86_64
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AK		 1982 .set_efer = vmx_set_efer,
1983#endif
1984 .get_idt = vmx_get_idt,
1985 .set_idt = vmx_set_idt,
1986 .get_gdt = vmx_get_gdt,
1987 .set_gdt = vmx_set_gdt,
1988 .cache_regs = vcpu_load_rsp_rip,
1989 .decache_regs = vcpu_put_rsp_rip,
1990 .get_rflags = vmx_get_rflags,
1991 .set_rflags = vmx_set_rflags,
1992
1993 .tlb_flush = vmx_flush_tlb,
1994 .inject_page_fault = vmx_inject_page_fault,
1995
1996 .inject_gp = vmx_inject_gp,
1997
1998 .run = vmx_vcpu_run,
1999 .skip_emulated_instruction = skip_emulated_instruction,
2000 .vcpu_setup = vmx_vcpu_setup,
2001};
2002
2003static int __init vmx_init(void)
2004{
873a7c42 2005 return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
6aa8b732
AK		 2006}
2007
2008static void __exit vmx_exit(void)
2009{
2010 kvm_exit_arch();
2011}
2012
2013module_init(vmx_init)
2014module_exit(vmx_exit)
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