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[PATCH] Update the rtc-rs5c372 driver
[mirror_ubuntu-bionic-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
20#include "kvm_vmx.h"
21#include <linux/module.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <asm/io.h>
3b3be0d1 25#include <asm/desc.h>
6aa8b732
AK		 26
27#include "segment_descriptor.h"
28
6aa8b732
AK		 29
30MODULE_AUTHOR("Qumranet");
31MODULE_LICENSE("GPL");
32
33static DEFINE_PER_CPU(struct vmcs *, vmxarea);
34static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
35
05b3e0c2 36#ifdef CONFIG_X86_64
6aa8b732
AK		 37#define HOST_IS_64 1
38#else
39#define HOST_IS_64 0
40#endif
41
42static struct vmcs_descriptor {
43 int size;
44 int order;
45 u32 revision_id;
46} vmcs_descriptor;
47
48#define VMX_SEGMENT_FIELD(seg) \
49 [VCPU_SREG_##seg] = { \
50 .selector = GUEST_##seg##_SELECTOR, \
51 .base = GUEST_##seg##_BASE, \
52 .limit = GUEST_##seg##_LIMIT, \
53 .ar_bytes = GUEST_##seg##_AR_BYTES, \
54 }
55
56static struct kvm_vmx_segment_field {
57 unsigned selector;
58 unsigned base;
59 unsigned limit;
60 unsigned ar_bytes;
61} kvm_vmx_segment_fields[] = {
62 VMX_SEGMENT_FIELD(CS),
63 VMX_SEGMENT_FIELD(DS),
64 VMX_SEGMENT_FIELD(ES),
65 VMX_SEGMENT_FIELD(FS),
66 VMX_SEGMENT_FIELD(GS),
67 VMX_SEGMENT_FIELD(SS),
68 VMX_SEGMENT_FIELD(TR),
69 VMX_SEGMENT_FIELD(LDTR),
70};
71
72static const u32 vmx_msr_index[] = {
05b3e0c2 73#ifdef CONFIG_X86_64
6aa8b732
AK		 74 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
75#endif
76 MSR_EFER, MSR_K6_STAR,
77};
78#define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
79
6aa8b732
AK		 80static inline int is_page_fault(u32 intr_info)
81{
82 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
83 INTR_INFO_VALID_MASK)) ==
84 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
85}
86
87static inline int is_external_interrupt(u32 intr_info)
88{
89 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
90 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
91}
92
7725f0ba
AK		 93static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
94{
95 int i;
96
97 for (i = 0; i < vcpu->nmsrs; ++i)
98 if (vcpu->guest_msrs[i].index == msr)
99 return &vcpu->guest_msrs[i];
100 return 0;
101}
102
6aa8b732
AK		 103static void vmcs_clear(struct vmcs *vmcs)
104{
105 u64 phys_addr = __pa(vmcs);
106 u8 error;
107
108 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
109 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
110 : "cc", "memory");
111 if (error)
112 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
113 vmcs, phys_addr);
114}
115
116static void __vcpu_clear(void *arg)
117{
118 struct kvm_vcpu *vcpu = arg;
d3b2c338 119 int cpu = raw_smp_processor_id();
6aa8b732
AK		 120
121 if (vcpu->cpu == cpu)
122 vmcs_clear(vcpu->vmcs);
123 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
124 per_cpu(current_vmcs, cpu) = NULL;
125}
126
127static unsigned long vmcs_readl(unsigned long field)
128{
129 unsigned long value;
130
131 asm volatile (ASM_VMX_VMREAD_RDX_RAX
132 : "=a"(value) : "d"(field) : "cc");
133 return value;
134}
135
136static u16 vmcs_read16(unsigned long field)
137{
138 return vmcs_readl(field);
139}
140
141static u32 vmcs_read32(unsigned long field)
142{
143 return vmcs_readl(field);
144}
145
146static u64 vmcs_read64(unsigned long field)
147{
05b3e0c2 148#ifdef CONFIG_X86_64
6aa8b732
AK		 149 return vmcs_readl(field);
150#else
151 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
152#endif
153}
154
155static void vmcs_writel(unsigned long field, unsigned long value)
156{
157 u8 error;
158
159 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
160 : "=q"(error) : "a"(value), "d"(field) : "cc" );
161 if (error)
162 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
163 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
164}
165
166static void vmcs_write16(unsigned long field, u16 value)
167{
168 vmcs_writel(field, value);
169}
170
171static void vmcs_write32(unsigned long field, u32 value)
172{
173 vmcs_writel(field, value);
174}
175
176static void vmcs_write64(unsigned long field, u64 value)
177{
05b3e0c2 178#ifdef CONFIG_X86_64
6aa8b732
AK		 179 vmcs_writel(field, value);
180#else
181 vmcs_writel(field, value);
182 asm volatile ("");
183 vmcs_writel(field+1, value >> 32);
184#endif
185}
186
187/*
188 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
189 * vcpu mutex is already taken.
190 */
191static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
192{
193 u64 phys_addr = __pa(vcpu->vmcs);
194 int cpu;
195
196 cpu = get_cpu();
197
198 if (vcpu->cpu != cpu) {
199 smp_call_function(__vcpu_clear, vcpu, 0, 1);
200 vcpu->launched = 0;
201 }
202
203 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
204 u8 error;
205
206 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
207 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
208 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
209 : "cc");
210 if (error)
211 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
212 vcpu->vmcs, phys_addr);
213 }
214
215 if (vcpu->cpu != cpu) {
216 struct descriptor_table dt;
217 unsigned long sysenter_esp;
218
219 vcpu->cpu = cpu;
220 /*
221 * Linux uses per-cpu TSS and GDT, so set these when switching
222 * processors.
223 */
224 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
225 get_gdt(&dt);
226 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
227
228 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
229 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
230 }
231 return vcpu;
232}
233
234static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
235{
236 put_cpu();
237}
238
239static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
240{
241 return vmcs_readl(GUEST_RFLAGS);
242}
243
244static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
245{
246 vmcs_writel(GUEST_RFLAGS, rflags);
247}
248
249static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
250{
251 unsigned long rip;
252 u32 interruptibility;
253
254 rip = vmcs_readl(GUEST_RIP);
255 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
256 vmcs_writel(GUEST_RIP, rip);
257
258 /*
259 * We emulated an instruction, so temporary interrupt blocking
260 * should be removed, if set.
261 */
262 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
263 if (interruptibility & 3)
264 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
265 interruptibility & ~3);
c1150d8c 266 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 267}
268
269static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
270{
271 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
272 vmcs_readl(GUEST_RIP));
273 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
274 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
275 GP_VECTOR |
276 INTR_TYPE_EXCEPTION |
277 INTR_INFO_DELIEVER_CODE_MASK |
278 INTR_INFO_VALID_MASK);
279}
280
281/*
282 * reads and returns guest's timestamp counter "register"
283 * guest_tsc = host_tsc + tsc_offset -- 21.3
284 */
285static u64 guest_read_tsc(void)
286{
287 u64 host_tsc, tsc_offset;
288
289 rdtscll(host_tsc);
290 tsc_offset = vmcs_read64(TSC_OFFSET);
291 return host_tsc + tsc_offset;
292}
293
294/*
295 * writes 'guest_tsc' into guest's timestamp counter "register"
296 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
297 */
298static void guest_write_tsc(u64 guest_tsc)
299{
300 u64 host_tsc;
301
302 rdtscll(host_tsc);
303 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
304}
305
306static void reload_tss(void)
307{
05b3e0c2 308#ifndef CONFIG_X86_64
6aa8b732
AK		 309
310 /*
311 * VT restores TR but not its size. Useless.
312 */
313 struct descriptor_table gdt;
314 struct segment_descriptor *descs;
315
316 get_gdt(&gdt);
317 descs = (void *)gdt.base;
318 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
319 load_TR_desc();
320#endif
321}
322
323/*
324 * Reads an msr value (of 'msr_index') into 'pdata'.
325 * Returns 0 on success, non-0 otherwise.
326 * Assumes vcpu_load() was already called.
327 */
328static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
329{
330 u64 data;
331 struct vmx_msr_entry *msr;
332
333 if (!pdata) {
334 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
335 return -EINVAL;
336 }
337
338 switch (msr_index) {
05b3e0c2 339#ifdef CONFIG_X86_64
6aa8b732
AK		 340 case MSR_FS_BASE:
341 data = vmcs_readl(GUEST_FS_BASE);
342 break;
343 case MSR_GS_BASE:
344 data = vmcs_readl(GUEST_GS_BASE);
345 break;
346 case MSR_EFER:
3bab1f5d 347 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 348#endif
349 case MSR_IA32_TIME_STAMP_COUNTER:
350 data = guest_read_tsc();
351 break;
352 case MSR_IA32_SYSENTER_CS:
353 data = vmcs_read32(GUEST_SYSENTER_CS);
354 break;
355 case MSR_IA32_SYSENTER_EIP:
356 data = vmcs_read32(GUEST_SYSENTER_EIP);
357 break;
358 case MSR_IA32_SYSENTER_ESP:
359 data = vmcs_read32(GUEST_SYSENTER_ESP);
360 break;
6aa8b732
AK		 361 default:
362 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 363 if (msr) {
364 data = msr->data;
365 break;
6aa8b732 366 }
3bab1f5d 367 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 368 }
369
370 *pdata = data;
371 return 0;
372}
373
374/*
375 * Writes msr value into into the appropriate "register".
376 * Returns 0 on success, non-0 otherwise.
377 * Assumes vcpu_load() was already called.
378 */
379static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
380{
381 struct vmx_msr_entry *msr;
382 switch (msr_index) {
05b3e0c2 383#ifdef CONFIG_X86_64
3bab1f5d
AK		 384 case MSR_EFER:
385 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 386 case MSR_FS_BASE:
387 vmcs_writel(GUEST_FS_BASE, data);
388 break;
389 case MSR_GS_BASE:
390 vmcs_writel(GUEST_GS_BASE, data);
391 break;
392#endif
393 case MSR_IA32_SYSENTER_CS:
394 vmcs_write32(GUEST_SYSENTER_CS, data);
395 break;
396 case MSR_IA32_SYSENTER_EIP:
397 vmcs_write32(GUEST_SYSENTER_EIP, data);
398 break;
399 case MSR_IA32_SYSENTER_ESP:
400 vmcs_write32(GUEST_SYSENTER_ESP, data);
401 break;
6aa8b732
AK		 402 case MSR_IA32_TIME_STAMP_COUNTER: {
403 guest_write_tsc(data);
404 break;
405 }
6aa8b732
AK		 406 default:
407 msr = find_msr_entry(vcpu, msr_index);
3bab1f5d
AK		 408 if (msr) {
409 msr->data = data;
410 break;
6aa8b732 411 }
3bab1f5d 412 return kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 413 msr->data = data;
414 break;
415 }
416
417 return 0;
418}
419
420/*
421 * Sync the rsp and rip registers into the vcpu structure. This allows
422 * registers to be accessed by indexing vcpu->regs.
423 */
424static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
425{
426 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
427 vcpu->rip = vmcs_readl(GUEST_RIP);
428}
429
430/*
431 * Syncs rsp and rip back into the vmcs. Should be called after possible
432 * modification.
433 */
434static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
435{
436 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
437 vmcs_writel(GUEST_RIP, vcpu->rip);
438}
439
440static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
441{
442 unsigned long dr7 = 0x400;
443 u32 exception_bitmap;
444 int old_singlestep;
445
446 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
447 old_singlestep = vcpu->guest_debug.singlestep;
448
449 vcpu->guest_debug.enabled = dbg->enabled;
450 if (vcpu->guest_debug.enabled) {
451 int i;
452
453 dr7 |= 0x200; /* exact */
454 for (i = 0; i < 4; ++i) {
455 if (!dbg->breakpoints[i].enabled)
456 continue;
457 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
458 dr7 |= 2 << (i*2); /* global enable */
459 dr7 |= 0 << (i*4+16); /* execution breakpoint */
460 }
461
462 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
463
464 vcpu->guest_debug.singlestep = dbg->singlestep;
465 } else {
466 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
467 vcpu->guest_debug.singlestep = 0;
468 }
469
470 if (old_singlestep && !vcpu->guest_debug.singlestep) {
471 unsigned long flags;
472
473 flags = vmcs_readl(GUEST_RFLAGS);
474 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
475 vmcs_writel(GUEST_RFLAGS, flags);
476 }
477
478 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
479 vmcs_writel(GUEST_DR7, dr7);
480
481 return 0;
482}
483
484static __init int cpu_has_kvm_support(void)
485{
486 unsigned long ecx = cpuid_ecx(1);
487 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
488}
489
490static __init int vmx_disabled_by_bios(void)
491{
492 u64 msr;
493
494 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
495 return (msr & 5) == 1; /* locked but not enabled */
496}
497
498static __init void hardware_enable(void *garbage)
499{
500 int cpu = raw_smp_processor_id();
501 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
502 u64 old;
503
504 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
bfdc0c28 505 if ((old & 5) != 5)
6aa8b732
AK		 506 /* enable and lock */
507 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
508 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
509 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
510 : "memory", "cc");
511}
512
513static void hardware_disable(void *garbage)
514{
515 asm volatile (ASM_VMX_VMXOFF : : : "cc");
516}
517
518static __init void setup_vmcs_descriptor(void)
519{
520 u32 vmx_msr_low, vmx_msr_high;
521
c68876fd 522 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
6aa8b732
AK		 523 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
524 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
525 vmcs_descriptor.revision_id = vmx_msr_low;
c68876fd 526}
6aa8b732
AK		 527
528static struct vmcs *alloc_vmcs_cpu(int cpu)
529{
530 int node = cpu_to_node(cpu);
531 struct page *pages;
532 struct vmcs *vmcs;
533
534 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
535 if (!pages)
536 return NULL;
537 vmcs = page_address(pages);
538 memset(vmcs, 0, vmcs_descriptor.size);
539 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
540 return vmcs;
541}
542
543static struct vmcs *alloc_vmcs(void)
544{
d3b2c338 545 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 546}
547
548static void free_vmcs(struct vmcs *vmcs)
549{
550 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
551}
552
553static __exit void free_kvm_area(void)
554{
555 int cpu;
556
557 for_each_online_cpu(cpu)
558 free_vmcs(per_cpu(vmxarea, cpu));
559}
560
561extern struct vmcs *alloc_vmcs_cpu(int cpu);
562
563static __init int alloc_kvm_area(void)
564{
565 int cpu;
566
567 for_each_online_cpu(cpu) {
568 struct vmcs *vmcs;
569
570 vmcs = alloc_vmcs_cpu(cpu);
571 if (!vmcs) {
572 free_kvm_area();
573 return -ENOMEM;
574 }
575
576 per_cpu(vmxarea, cpu) = vmcs;
577 }
578 return 0;
579}
580
581static __init int hardware_setup(void)
582{
583 setup_vmcs_descriptor();
584 return alloc_kvm_area();
585}
586
587static __exit void hardware_unsetup(void)
588{
589 free_kvm_area();
590}
591
592static void update_exception_bitmap(struct kvm_vcpu *vcpu)
593{
594 if (vcpu->rmode.active)
595 vmcs_write32(EXCEPTION_BITMAP, ~0);
596 else
597 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
598}
599
600static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
601{
602 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
603
604 if (vmcs_readl(sf->base) == save->base) {
605 vmcs_write16(sf->selector, save->selector);
606 vmcs_writel(sf->base, save->base);
607 vmcs_write32(sf->limit, save->limit);
608 vmcs_write32(sf->ar_bytes, save->ar);
609 } else {
610 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
611 << AR_DPL_SHIFT;
612 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
613 }
614}
615
616static void enter_pmode(struct kvm_vcpu *vcpu)
617{
618 unsigned long flags;
619
620 vcpu->rmode.active = 0;
621
622 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
623 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
624 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
625
626 flags = vmcs_readl(GUEST_RFLAGS);
627 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
628 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
629 vmcs_writel(GUEST_RFLAGS, flags);
630
631 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
632 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
633
634 update_exception_bitmap(vcpu);
635
636 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
637 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
638 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
639 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
640
641 vmcs_write16(GUEST_SS_SELECTOR, 0);
642 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
643
644 vmcs_write16(GUEST_CS_SELECTOR,
645 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
646 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
647}
648
649static int rmode_tss_base(struct kvm* kvm)
650{
651 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
652 return base_gfn << PAGE_SHIFT;
653}
654
655static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
656{
657 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
658
659 save->selector = vmcs_read16(sf->selector);
660 save->base = vmcs_readl(sf->base);
661 save->limit = vmcs_read32(sf->limit);
662 save->ar = vmcs_read32(sf->ar_bytes);
663 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
664 vmcs_write32(sf->limit, 0xffff);
665 vmcs_write32(sf->ar_bytes, 0xf3);
666}
667
668static void enter_rmode(struct kvm_vcpu *vcpu)
669{
670 unsigned long flags;
671
672 vcpu->rmode.active = 1;
673
674 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
675 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
676
677 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
678 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
679
680 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
681 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
682
683 flags = vmcs_readl(GUEST_RFLAGS);
684 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
685
686 flags |= IOPL_MASK | X86_EFLAGS_VM;
687
688 vmcs_writel(GUEST_RFLAGS, flags);
689 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
690 update_exception_bitmap(vcpu);
691
692 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
693 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
694 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
695
696 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 697 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
6aa8b732
AK		 698 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
699
700 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
701 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
702 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
703 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
704}
705
05b3e0c2 706#ifdef CONFIG_X86_64
6aa8b732
AK		 707
708static void enter_lmode(struct kvm_vcpu *vcpu)
709{
710 u32 guest_tr_ar;
711
712 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
713 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
714 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
715 __FUNCTION__);
716 vmcs_write32(GUEST_TR_AR_BYTES,
717 (guest_tr_ar & ~AR_TYPE_MASK)
718 | AR_TYPE_BUSY_64_TSS);
719 }
720
721 vcpu->shadow_efer |= EFER_LMA;
722
723 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
724 vmcs_write32(VM_ENTRY_CONTROLS,
725 vmcs_read32(VM_ENTRY_CONTROLS)
726 | VM_ENTRY_CONTROLS_IA32E_MASK);
727}
728
729static void exit_lmode(struct kvm_vcpu *vcpu)
730{
731 vcpu->shadow_efer &= ~EFER_LMA;
732
733 vmcs_write32(VM_ENTRY_CONTROLS,
734 vmcs_read32(VM_ENTRY_CONTROLS)
735 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
736}
737
738#endif
739
740static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
741{
742 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
743 enter_pmode(vcpu);
744
745 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
746 enter_rmode(vcpu);
747
05b3e0c2 748#ifdef CONFIG_X86_64
6aa8b732
AK		 749 if (vcpu->shadow_efer & EFER_LME) {
750 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
751 enter_lmode(vcpu);
752 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
753 exit_lmode(vcpu);
754 }
755#endif
756
757 vmcs_writel(CR0_READ_SHADOW, cr0);
758 vmcs_writel(GUEST_CR0,
759 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
760 vcpu->cr0 = cr0;
761}
762
763/*
764 * Used when restoring the VM to avoid corrupting segment registers
765 */
766static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
767{
768 vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
769 update_exception_bitmap(vcpu);
770 vmcs_writel(CR0_READ_SHADOW, cr0);
771 vmcs_writel(GUEST_CR0,
772 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
773 vcpu->cr0 = cr0;
774}
775
776static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
777{
778 vmcs_writel(GUEST_CR3, cr3);
779}
780
781static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
782{
783 vmcs_writel(CR4_READ_SHADOW, cr4);
784 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
785 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
786 vcpu->cr4 = cr4;
787}
788
05b3e0c2 789#ifdef CONFIG_X86_64
6aa8b732
AK		 790
791static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
792{
793 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
794
795 vcpu->shadow_efer = efer;
796 if (efer & EFER_LMA) {
797 vmcs_write32(VM_ENTRY_CONTROLS,
798 vmcs_read32(VM_ENTRY_CONTROLS) |
799 VM_ENTRY_CONTROLS_IA32E_MASK);
800 msr->data = efer;
801
802 } else {
803 vmcs_write32(VM_ENTRY_CONTROLS,
804 vmcs_read32(VM_ENTRY_CONTROLS) &
805 ~VM_ENTRY_CONTROLS_IA32E_MASK);
806
807 msr->data = efer & ~EFER_LME;
808 }
809}
810
811#endif
812
813static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
814{
815 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
816
817 return vmcs_readl(sf->base);
818}
819
820static void vmx_get_segment(struct kvm_vcpu *vcpu,
821 struct kvm_segment *var, int seg)
822{
823 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
824 u32 ar;
825
826 var->base = vmcs_readl(sf->base);
827 var->limit = vmcs_read32(sf->limit);
828 var->selector = vmcs_read16(sf->selector);
829 ar = vmcs_read32(sf->ar_bytes);
830 if (ar & AR_UNUSABLE_MASK)
831 ar = 0;
832 var->type = ar & 15;
833 var->s = (ar >> 4) & 1;
834 var->dpl = (ar >> 5) & 3;
835 var->present = (ar >> 7) & 1;
836 var->avl = (ar >> 12) & 1;
837 var->l = (ar >> 13) & 1;
838 var->db = (ar >> 14) & 1;
839 var->g = (ar >> 15) & 1;
840 var->unusable = (ar >> 16) & 1;
841}
842
843static void vmx_set_segment(struct kvm_vcpu *vcpu,
844 struct kvm_segment *var, int seg)
845{
846 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
847 u32 ar;
848
849 vmcs_writel(sf->base, var->base);
850 vmcs_write32(sf->limit, var->limit);
851 vmcs_write16(sf->selector, var->selector);
852 if (var->unusable)
853 ar = 1 << 16;
854 else {
855 ar = var->type & 15;
856 ar |= (var->s & 1) << 4;
857 ar |= (var->dpl & 3) << 5;
858 ar |= (var->present & 1) << 7;
859 ar |= (var->avl & 1) << 12;
860 ar |= (var->l & 1) << 13;
861 ar |= (var->db & 1) << 14;
862 ar |= (var->g & 1) << 15;
863 }
f7fbf1fd
UL		 864 if (ar == 0) /* a 0 value means unusable */
865 ar = AR_UNUSABLE_MASK;
6aa8b732
AK		 866 vmcs_write32(sf->ar_bytes, ar);
867}
868
6aa8b732
AK		 869static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
870{
871 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
872
873 *db = (ar >> 14) & 1;
874 *l = (ar >> 13) & 1;
875}
876
877static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
878{
879 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
880 dt->base = vmcs_readl(GUEST_IDTR_BASE);
881}
882
883static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
884{
885 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
886 vmcs_writel(GUEST_IDTR_BASE, dt->base);
887}
888
889static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
890{
891 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
892 dt->base = vmcs_readl(GUEST_GDTR_BASE);
893}
894
895static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
896{
897 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
898 vmcs_writel(GUEST_GDTR_BASE, dt->base);
899}
900
901static int init_rmode_tss(struct kvm* kvm)
902{
903 struct page *p1, *p2, *p3;
904 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
905 char *page;
906
907 p1 = _gfn_to_page(kvm, fn++);
908 p2 = _gfn_to_page(kvm, fn++);
909 p3 = _gfn_to_page(kvm, fn);
910
911 if (!p1 || !p2 || !p3) {
912 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
913 return 0;
914 }
915
916 page = kmap_atomic(p1, KM_USER0);
917 memset(page, 0, PAGE_SIZE);
918 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
919 kunmap_atomic(page, KM_USER0);
920
921 page = kmap_atomic(p2, KM_USER0);
922 memset(page, 0, PAGE_SIZE);
923 kunmap_atomic(page, KM_USER0);
924
925 page = kmap_atomic(p3, KM_USER0);
926 memset(page, 0, PAGE_SIZE);
927 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
928 kunmap_atomic(page, KM_USER0);
929
930 return 1;
931}
932
933static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
934{
935 u32 msr_high, msr_low;
936
937 rdmsr(msr, msr_low, msr_high);
938
939 val &= msr_high;
940 val |= msr_low;
941 vmcs_write32(vmcs_field, val);
942}
943
944static void seg_setup(int seg)
945{
946 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
947
948 vmcs_write16(sf->selector, 0);
949 vmcs_writel(sf->base, 0);
950 vmcs_write32(sf->limit, 0xffff);
951 vmcs_write32(sf->ar_bytes, 0x93);
952}
953
954/*
955 * Sets up the vmcs for emulated real mode.
956 */
957static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
958{
959 u32 host_sysenter_cs;
960 u32 junk;
961 unsigned long a;
962 struct descriptor_table dt;
963 int i;
964 int ret = 0;
965 int nr_good_msrs;
966 extern asmlinkage void kvm_vmx_return(void);
967
968 if (!init_rmode_tss(vcpu->kvm)) {
969 ret = -ENOMEM;
970 goto out;
971 }
972
973 memset(vcpu->regs, 0, sizeof(vcpu->regs));
974 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
975 vcpu->cr8 = 0;
976 vcpu->apic_base = 0xfee00000 |
977 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
978 MSR_IA32_APICBASE_ENABLE;
979
980 fx_init(vcpu);
981
982 /*
983 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
984 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
985 */
986 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
987 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
988 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
989 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
990
991 seg_setup(VCPU_SREG_DS);
992 seg_setup(VCPU_SREG_ES);
993 seg_setup(VCPU_SREG_FS);
994 seg_setup(VCPU_SREG_GS);
995 seg_setup(VCPU_SREG_SS);
996
997 vmcs_write16(GUEST_TR_SELECTOR, 0);
998 vmcs_writel(GUEST_TR_BASE, 0);
999 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1000 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1001
1002 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1003 vmcs_writel(GUEST_LDTR_BASE, 0);
1004 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1005 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1006
1007 vmcs_write32(GUEST_SYSENTER_CS, 0);
1008 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1009 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1010
1011 vmcs_writel(GUEST_RFLAGS, 0x02);
1012 vmcs_writel(GUEST_RIP, 0xfff0);
1013 vmcs_writel(GUEST_RSP, 0);
1014
1015 vmcs_writel(GUEST_CR3, 0);
1016
1017 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1018 vmcs_writel(GUEST_DR7, 0x400);
1019
1020 vmcs_writel(GUEST_GDTR_BASE, 0);
1021 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1022
1023 vmcs_writel(GUEST_IDTR_BASE, 0);
1024 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1025
1026 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1027 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1028 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1029
1030 /* I/O */
1031 vmcs_write64(IO_BITMAP_A, 0);
1032 vmcs_write64(IO_BITMAP_B, 0);
1033
1034 guest_write_tsc(0);
1035
1036 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1037
1038 /* Special registers */
1039 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1040
1041 /* Control */
c68876fd 1042 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
6aa8b732
AK		 1043 PIN_BASED_VM_EXEC_CONTROL,
1044 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1045 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1046 );
c68876fd 1047 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
6aa8b732
AK		 1048 CPU_BASED_VM_EXEC_CONTROL,
1049 CPU_BASED_HLT_EXITING /* 20.6.2 */
1050 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1051 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1052 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1053 | CPU_BASED_INVDPG_EXITING
1054 | CPU_BASED_MOV_DR_EXITING
1055 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1056 );
1057
1058 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1059 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1060 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1061 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1062
1063 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1064 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1065 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1066
1067 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1068 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1069 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1070 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1071 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1072 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1073#ifdef CONFIG_X86_64
6aa8b732
AK		 1074 rdmsrl(MSR_FS_BASE, a);
1075 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1076 rdmsrl(MSR_GS_BASE, a);
1077 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1078#else
1079 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1080 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1081#endif
1082
1083 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1084
1085 get_idt(&dt);
1086 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1087
1088
1089 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1090
1091 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1092 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1093 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1094 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1095 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1096 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1097
6aa8b732
AK		 1098 for (i = 0; i < NR_VMX_MSR; ++i) {
1099 u32 index = vmx_msr_index[i];
1100 u32 data_low, data_high;
1101 u64 data;
1102 int j = vcpu->nmsrs;
1103
1104 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1105 continue;
1106 data = data_low | ((u64)data_high << 32);
1107 vcpu->host_msrs[j].index = index;
1108 vcpu->host_msrs[j].reserved = 0;
1109 vcpu->host_msrs[j].data = data;
1110 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1111 ++vcpu->nmsrs;
1112 }
1113 printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1114
1115 nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1116 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1117 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1118 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1119 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1120 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1121 virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
c68876fd 1122 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
6aa8b732
AK		 1123 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1124 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1125 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1126 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1127
1128
1129 /* 22.2.1, 20.8.1 */
c68876fd 1130 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
6aa8b732
AK		 1131 VM_ENTRY_CONTROLS, 0);
1132 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1133
3b99ab24 1134#ifdef CONFIG_X86_64
6aa8b732
AK		 1135 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1136 vmcs_writel(TPR_THRESHOLD, 0);
3b99ab24 1137#endif
6aa8b732
AK		 1138
1139 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1140 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1141
1142 vcpu->cr0 = 0x60000010;
1143 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1144 vmx_set_cr4(vcpu, 0);
05b3e0c2 1145#ifdef CONFIG_X86_64
6aa8b732
AK		 1146 vmx_set_efer(vcpu, 0);
1147#endif
1148
1149 return 0;
1150
6aa8b732
AK		 1151out:
1152 return ret;
1153}
1154
1155static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1156{
1157 u16 ent[2];
1158 u16 cs;
1159 u16 ip;
1160 unsigned long flags;
1161 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1162 u16 sp = vmcs_readl(GUEST_RSP);
1163 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1164
1165 if (sp > ss_limit || sp - 6 > sp) {
1166 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1167 __FUNCTION__,
1168 vmcs_readl(GUEST_RSP),
1169 vmcs_readl(GUEST_SS_BASE),
1170 vmcs_read32(GUEST_SS_LIMIT));
1171 return;
1172 }
1173
1174 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1175 sizeof(ent)) {
1176 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1177 return;
1178 }
1179
1180 flags = vmcs_readl(GUEST_RFLAGS);
1181 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1182 ip = vmcs_readl(GUEST_RIP);
1183
1184
1185 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1186 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1187 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1188 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1189 return;
1190 }
1191
1192 vmcs_writel(GUEST_RFLAGS, flags &
1193 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1194 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1195 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1196 vmcs_writel(GUEST_RIP, ent[0]);
1197 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1198}
1199
1200static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1201{
1202 int word_index = __ffs(vcpu->irq_summary);
1203 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1204 int irq = word_index * BITS_PER_LONG + bit_index;
1205
1206 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1207 if (!vcpu->irq_pending[word_index])
1208 clear_bit(word_index, &vcpu->irq_summary);
1209
1210 if (vcpu->rmode.active) {
1211 inject_rmode_irq(vcpu, irq);
1212 return;
1213 }
1214 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1215 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1216}
1217
c1150d8c
DL		 1218
1219static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1220 struct kvm_run *kvm_run)
6aa8b732 1221{
c1150d8c
DL		 1222 u32 cpu_based_vm_exec_control;
1223
1224 vcpu->interrupt_window_open =
1225 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1226 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1227
1228 if (vcpu->interrupt_window_open &&
1229 vcpu->irq_summary &&
1230 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1231 /*
c1150d8c 1232 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1233 */
1234 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1235
1236 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1237 if (!vcpu->interrupt_window_open &&
1238 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1239 /*
1240 * Interrupts blocked. Wait for unblock.
1241 */
c1150d8c
DL		 1242 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1243 else
1244 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1245 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1246}
1247
1248static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1249{
1250 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1251
1252 set_debugreg(dbg->bp[0], 0);
1253 set_debugreg(dbg->bp[1], 1);
1254 set_debugreg(dbg->bp[2], 2);
1255 set_debugreg(dbg->bp[3], 3);
1256
1257 if (dbg->singlestep) {
1258 unsigned long flags;
1259
1260 flags = vmcs_readl(GUEST_RFLAGS);
1261 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1262 vmcs_writel(GUEST_RFLAGS, flags);
1263 }
1264}
1265
1266static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1267 int vec, u32 err_code)
1268{
1269 if (!vcpu->rmode.active)
1270 return 0;
1271
1272 if (vec == GP_VECTOR && err_code == 0)
1273 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1274 return 1;
1275 return 0;
1276}
1277
1278static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1279{
1280 u32 intr_info, error_code;
1281 unsigned long cr2, rip;
1282 u32 vect_info;
1283 enum emulation_result er;
1284
1285 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1286 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1287
1288 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1289 !is_page_fault(intr_info)) {
1290 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1291 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1292 }
1293
1294 if (is_external_interrupt(vect_info)) {
1295 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1296 set_bit(irq, vcpu->irq_pending);
1297 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1298 }
1299
1300 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1301 asm ("int $2");
1302 return 1;
1303 }
1304 error_code = 0;
1305 rip = vmcs_readl(GUEST_RIP);
1306 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1307 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1308 if (is_page_fault(intr_info)) {
1309 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1310
1311 spin_lock(&vcpu->kvm->lock);
1312 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1313 spin_unlock(&vcpu->kvm->lock);
1314 return 1;
1315 }
1316
1317 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1318 spin_unlock(&vcpu->kvm->lock);
1319
1320 switch (er) {
1321 case EMULATE_DONE:
1322 return 1;
1323 case EMULATE_DO_MMIO:
1324 ++kvm_stat.mmio_exits;
1325 kvm_run->exit_reason = KVM_EXIT_MMIO;
1326 return 0;
1327 case EMULATE_FAIL:
1328 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1329 break;
1330 default:
1331 BUG();
1332 }
1333 }
1334
1335 if (vcpu->rmode.active &&
1336 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1337 error_code))
1338 return 1;
1339
1340 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1341 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1342 return 0;
1343 }
1344 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1345 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1346 kvm_run->ex.error_code = error_code;
1347 return 0;
1348}
1349
1350static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1351 struct kvm_run *kvm_run)
1352{
1353 ++kvm_stat.irq_exits;
1354 return 1;
1355}
1356
1357
1358static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1359{
1360 u64 inst;
1361 gva_t rip;
1362 int countr_size;
1363 int i, n;
1364
1365 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1366 countr_size = 2;
1367 } else {
1368 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1369
1370 countr_size = (cs_ar & AR_L_MASK) ? 8:
1371 (cs_ar & AR_DB_MASK) ? 4: 2;
1372 }
1373
1374 rip = vmcs_readl(GUEST_RIP);
1375 if (countr_size != 8)
1376 rip += vmcs_readl(GUEST_CS_BASE);
1377
1378 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1379
1380 for (i = 0; i < n; i++) {
1381 switch (((u8*)&inst)[i]) {
1382 case 0xf0:
1383 case 0xf2:
1384 case 0xf3:
1385 case 0x2e:
1386 case 0x36:
1387 case 0x3e:
1388 case 0x26:
1389 case 0x64:
1390 case 0x65:
1391 case 0x66:
1392 break;
1393 case 0x67:
1394 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1395 default:
1396 goto done;
1397 }
1398 }
1399 return 0;
1400done:
1401 countr_size *= 8;
1402 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1403 return 1;
1404}
1405
1406static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1407{
1408 u64 exit_qualification;
1409
1410 ++kvm_stat.io_exits;
1411 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1412 kvm_run->exit_reason = KVM_EXIT_IO;
1413 if (exit_qualification & 8)
1414 kvm_run->io.direction = KVM_EXIT_IO_IN;
1415 else
1416 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1417 kvm_run->io.size = (exit_qualification & 7) + 1;
1418 kvm_run->io.string = (exit_qualification & 16) != 0;
1419 kvm_run->io.string_down
1420 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1421 kvm_run->io.rep = (exit_qualification & 32) != 0;
1422 kvm_run->io.port = exit_qualification >> 16;
1423 if (kvm_run->io.string) {
1424 if (!get_io_count(vcpu, &kvm_run->io.count))
1425 return 1;
1426 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1427 } else
1428 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1429 return 0;
1430}
1431
1432static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1433{
1434 u64 address = vmcs_read64(EXIT_QUALIFICATION);
1435 int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1436 spin_lock(&vcpu->kvm->lock);
1437 vcpu->mmu.inval_page(vcpu, address);
1438 spin_unlock(&vcpu->kvm->lock);
1439 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1440 return 1;
1441}
1442
1443static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1444{
1445 u64 exit_qualification;
1446 int cr;
1447 int reg;
1448
1449 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1450 cr = exit_qualification & 15;
1451 reg = (exit_qualification >> 8) & 15;
1452 switch ((exit_qualification >> 4) & 3) {
1453 case 0: /* mov to cr */
1454 switch (cr) {
1455 case 0:
1456 vcpu_load_rsp_rip(vcpu);
1457 set_cr0(vcpu, vcpu->regs[reg]);
1458 skip_emulated_instruction(vcpu);
1459 return 1;
1460 case 3:
1461 vcpu_load_rsp_rip(vcpu);
1462 set_cr3(vcpu, vcpu->regs[reg]);
1463 skip_emulated_instruction(vcpu);
1464 return 1;
1465 case 4:
1466 vcpu_load_rsp_rip(vcpu);
1467 set_cr4(vcpu, vcpu->regs[reg]);
1468 skip_emulated_instruction(vcpu);
1469 return 1;
1470 case 8:
1471 vcpu_load_rsp_rip(vcpu);
1472 set_cr8(vcpu, vcpu->regs[reg]);
1473 skip_emulated_instruction(vcpu);
1474 return 1;
1475 };
1476 break;
1477 case 1: /*mov from cr*/
1478 switch (cr) {
1479 case 3:
1480 vcpu_load_rsp_rip(vcpu);
1481 vcpu->regs[reg] = vcpu->cr3;
1482 vcpu_put_rsp_rip(vcpu);
1483 skip_emulated_instruction(vcpu);
1484 return 1;
1485 case 8:
1486 printk(KERN_DEBUG "handle_cr: read CR8 "
1487 "cpu erratum AA15\n");
1488 vcpu_load_rsp_rip(vcpu);
1489 vcpu->regs[reg] = vcpu->cr8;
1490 vcpu_put_rsp_rip(vcpu);
1491 skip_emulated_instruction(vcpu);
1492 return 1;
1493 }
1494 break;
1495 case 3: /* lmsw */
1496 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1497
1498 skip_emulated_instruction(vcpu);
1499 return 1;
1500 default:
1501 break;
1502 }
1503 kvm_run->exit_reason = 0;
1504 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1505 (int)(exit_qualification >> 4) & 3, cr);
1506 return 0;
1507}
1508
1509static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1510{
1511 u64 exit_qualification;
1512 unsigned long val;
1513 int dr, reg;
1514
1515 /*
1516 * FIXME: this code assumes the host is debugging the guest.
1517 * need to deal with guest debugging itself too.
1518 */
1519 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1520 dr = exit_qualification & 7;
1521 reg = (exit_qualification >> 8) & 15;
1522 vcpu_load_rsp_rip(vcpu);
1523 if (exit_qualification & 16) {
1524 /* mov from dr */
1525 switch (dr) {
1526 case 6:
1527 val = 0xffff0ff0;
1528 break;
1529 case 7:
1530 val = 0x400;
1531 break;
1532 default:
1533 val = 0;
1534 }
1535 vcpu->regs[reg] = val;
1536 } else {
1537 /* mov to dr */
1538 }
1539 vcpu_put_rsp_rip(vcpu);
1540 skip_emulated_instruction(vcpu);
1541 return 1;
1542}
1543
1544static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1545{
1546 kvm_run->exit_reason = KVM_EXIT_CPUID;
1547 return 0;
1548}
1549
1550static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1551{
1552 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1553 u64 data;
1554
1555 if (vmx_get_msr(vcpu, ecx, &data)) {
1556 vmx_inject_gp(vcpu, 0);
1557 return 1;
1558 }
1559
1560 /* FIXME: handling of bits 32:63 of rax, rdx */
1561 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1562 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1563 skip_emulated_instruction(vcpu);
1564 return 1;
1565}
1566
1567static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1568{
1569 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1570 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1571 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1572
1573 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1574 vmx_inject_gp(vcpu, 0);
1575 return 1;
1576 }
1577
1578 skip_emulated_instruction(vcpu);
1579 return 1;
1580}
1581
c1150d8c
DL		 1582static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1583 struct kvm_run *kvm_run)
1584{
1585 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1586 kvm_run->cr8 = vcpu->cr8;
1587 kvm_run->apic_base = vcpu->apic_base;
1588 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1589 vcpu->irq_summary == 0);
1590}
1591
6aa8b732
AK		 1592static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1593 struct kvm_run *kvm_run)
1594{
c1150d8c
DL		 1595 /*
1596 * If the user space waits to inject interrupts, exit as soon as
1597 * possible
1598 */
1599 if (kvm_run->request_interrupt_window &&
1600 !vcpu->irq_summary &&
1601 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)) {
1602 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1603 ++kvm_stat.irq_window_exits;
1604 return 0;
1605 }
6aa8b732
AK		 1606 return 1;
1607}
1608
1609static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1610{
1611 skip_emulated_instruction(vcpu);
c1150d8c 1612 if (vcpu->irq_summary)
6aa8b732
AK		 1613 return 1;
1614
1615 kvm_run->exit_reason = KVM_EXIT_HLT;
c1150d8c 1616 ++kvm_stat.halt_exits;
6aa8b732
AK		 1617 return 0;
1618}
1619
1620/*
1621 * The exit handlers return 1 if the exit was handled fully and guest execution
1622 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1623 * to be done to userspace and return 0.
1624 */
1625static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1626 struct kvm_run *kvm_run) = {
1627 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1628 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1629 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1630 [EXIT_REASON_INVLPG] = handle_invlpg,
1631 [EXIT_REASON_CR_ACCESS] = handle_cr,
1632 [EXIT_REASON_DR_ACCESS] = handle_dr,
1633 [EXIT_REASON_CPUID] = handle_cpuid,
1634 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1635 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1636 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1637 [EXIT_REASON_HLT] = handle_halt,
1638};
1639
1640static const int kvm_vmx_max_exit_handlers =
1641 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1642
1643/*
1644 * The guest has exited. See if we can fix it or if we need userspace
1645 * assistance.
1646 */
1647static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1648{
1649 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1650 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1651
1652 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1653 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1654 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1655 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1656 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1657 if (exit_reason < kvm_vmx_max_exit_handlers
1658 && kvm_vmx_exit_handlers[exit_reason])
1659 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1660 else {
1661 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1662 kvm_run->hw.hardware_exit_reason = exit_reason;
1663 }
1664 return 0;
1665}
1666
c1150d8c
DL		 1667/*
1668 * Check if userspace requested an interrupt window, and that the
1669 * interrupt window is open.
1670 *
1671 * No need to exit to userspace if we already have an interrupt queued.
1672 */
1673static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1674 struct kvm_run *kvm_run)
1675{
1676 return (!vcpu->irq_summary &&
1677 kvm_run->request_interrupt_window &&
1678 vcpu->interrupt_window_open &&
1679 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1680}
1681
6aa8b732
AK		 1682static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1683{
1684 u8 fail;
1685 u16 fs_sel, gs_sel, ldt_sel;
1686 int fs_gs_ldt_reload_needed;
1687
1688again:
1689 /*
1690 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1691 * allow segment selectors with cpl > 0 or ti == 1.
1692 */
1693 fs_sel = read_fs();
1694 gs_sel = read_gs();
1695 ldt_sel = read_ldt();
1696 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1697 if (!fs_gs_ldt_reload_needed) {
1698 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1699 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1700 } else {
1701 vmcs_write16(HOST_FS_SELECTOR, 0);
1702 vmcs_write16(HOST_GS_SELECTOR, 0);
1703 }
1704
05b3e0c2 1705#ifdef CONFIG_X86_64
6aa8b732
AK		 1706 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1707 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1708#else
1709 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1710 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1711#endif
1712
c1150d8c 1713 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1714
1715 if (vcpu->guest_debug.enabled)
1716 kvm_guest_debug_pre(vcpu);
1717
1718 fx_save(vcpu->host_fx_image);
1719 fx_restore(vcpu->guest_fx_image);
1720
1721 save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1722 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1723
1724 asm (
1725 /* Store host registers */
1726 "pushf \n\t"
05b3e0c2 1727#ifdef CONFIG_X86_64
6aa8b732
AK		 1728 "push %%rax; push %%rbx; push %%rdx;"
1729 "push %%rsi; push %%rdi; push %%rbp;"
1730 "push %%r8; push %%r9; push %%r10; push %%r11;"
1731 "push %%r12; push %%r13; push %%r14; push %%r15;"
1732 "push %%rcx \n\t"
1733 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1734#else
1735 "pusha; push %%ecx \n\t"
1736 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1737#endif
1738 /* Check if vmlaunch of vmresume is needed */
1739 "cmp $0, %1 \n\t"
1740 /* Load guest registers. Don't clobber flags. */
05b3e0c2 1741#ifdef CONFIG_X86_64
6aa8b732
AK		 1742 "mov %c[cr2](%3), %%rax \n\t"
1743 "mov %%rax, %%cr2 \n\t"
1744 "mov %c[rax](%3), %%rax \n\t"
1745 "mov %c[rbx](%3), %%rbx \n\t"
1746 "mov %c[rdx](%3), %%rdx \n\t"
1747 "mov %c[rsi](%3), %%rsi \n\t"
1748 "mov %c[rdi](%3), %%rdi \n\t"
1749 "mov %c[rbp](%3), %%rbp \n\t"
1750 "mov %c[r8](%3), %%r8 \n\t"
1751 "mov %c[r9](%3), %%r9 \n\t"
1752 "mov %c[r10](%3), %%r10 \n\t"
1753 "mov %c[r11](%3), %%r11 \n\t"
1754 "mov %c[r12](%3), %%r12 \n\t"
1755 "mov %c[r13](%3), %%r13 \n\t"
1756 "mov %c[r14](%3), %%r14 \n\t"
1757 "mov %c[r15](%3), %%r15 \n\t"
1758 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1759#else
1760 "mov %c[cr2](%3), %%eax \n\t"
1761 "mov %%eax, %%cr2 \n\t"
1762 "mov %c[rax](%3), %%eax \n\t"
1763 "mov %c[rbx](%3), %%ebx \n\t"
1764 "mov %c[rdx](%3), %%edx \n\t"
1765 "mov %c[rsi](%3), %%esi \n\t"
1766 "mov %c[rdi](%3), %%edi \n\t"
1767 "mov %c[rbp](%3), %%ebp \n\t"
1768 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1769#endif
1770 /* Enter guest mode */
1771 "jne launched \n\t"
1772 ASM_VMX_VMLAUNCH "\n\t"
1773 "jmp kvm_vmx_return \n\t"
1774 "launched: " ASM_VMX_VMRESUME "\n\t"
1775 ".globl kvm_vmx_return \n\t"
1776 "kvm_vmx_return: "
1777 /* Save guest registers, load host registers, keep flags */
05b3e0c2 1778#ifdef CONFIG_X86_64
6aa8b732
AK		 1779 "xchg %3, 0(%%rsp) \n\t"
1780 "mov %%rax, %c[rax](%3) \n\t"
1781 "mov %%rbx, %c[rbx](%3) \n\t"
1782 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1783 "mov %%rdx, %c[rdx](%3) \n\t"
1784 "mov %%rsi, %c[rsi](%3) \n\t"
1785 "mov %%rdi, %c[rdi](%3) \n\t"
1786 "mov %%rbp, %c[rbp](%3) \n\t"
1787 "mov %%r8, %c[r8](%3) \n\t"
1788 "mov %%r9, %c[r9](%3) \n\t"
1789 "mov %%r10, %c[r10](%3) \n\t"
1790 "mov %%r11, %c[r11](%3) \n\t"
1791 "mov %%r12, %c[r12](%3) \n\t"
1792 "mov %%r13, %c[r13](%3) \n\t"
1793 "mov %%r14, %c[r14](%3) \n\t"
1794 "mov %%r15, %c[r15](%3) \n\t"
1795 "mov %%cr2, %%rax \n\t"
1796 "mov %%rax, %c[cr2](%3) \n\t"
1797 "mov 0(%%rsp), %3 \n\t"
1798
1799 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1800 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1801 "pop %%rbp; pop %%rdi; pop %%rsi;"
1802 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1803#else
1804 "xchg %3, 0(%%esp) \n\t"
1805 "mov %%eax, %c[rax](%3) \n\t"
1806 "mov %%ebx, %c[rbx](%3) \n\t"
1807 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1808 "mov %%edx, %c[rdx](%3) \n\t"
1809 "mov %%esi, %c[rsi](%3) \n\t"
1810 "mov %%edi, %c[rdi](%3) \n\t"
1811 "mov %%ebp, %c[rbp](%3) \n\t"
1812 "mov %%cr2, %%eax \n\t"
1813 "mov %%eax, %c[cr2](%3) \n\t"
1814 "mov 0(%%esp), %3 \n\t"
1815
1816 "pop %%ecx; popa \n\t"
1817#endif
1818 "setbe %0 \n\t"
1819 "popf \n\t"
1820 : "=g" (fail)
1821 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1822 "c"(vcpu),
1823 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1824 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1825 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1826 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1827 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1828 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1829 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 1830#ifdef CONFIG_X86_64
6aa8b732
AK		 1831 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1832 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1833 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1834 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1835 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1836 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1837 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1838 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1839#endif
1840 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1841 : "cc", "memory" );
1842
1843 ++kvm_stat.exits;
1844
1845 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1846 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1847
1848 fx_save(vcpu->guest_fx_image);
1849 fx_restore(vcpu->host_fx_image);
c1150d8c 1850 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 1851
05b3e0c2 1852#ifndef CONFIG_X86_64
6aa8b732
AK		 1853 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1854#endif
1855
1856 kvm_run->exit_type = 0;
1857 if (fail) {
1858 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1859 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1860 } else {
1861 if (fs_gs_ldt_reload_needed) {
1862 load_ldt(ldt_sel);
1863 load_fs(fs_sel);
1864 /*
1865 * If we have to reload gs, we must take care to
1866 * preserve our gs base.
1867 */
1868 local_irq_disable();
1869 load_gs(gs_sel);
05b3e0c2 1870#ifdef CONFIG_X86_64
6aa8b732
AK		 1871 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1872#endif
1873 local_irq_enable();
1874
1875 reload_tss();
1876 }
1877 vcpu->launched = 1;
1878 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1879 if (kvm_handle_exit(kvm_run, vcpu)) {
1880 /* Give scheduler a change to reschedule. */
1881 if (signal_pending(current)) {
1882 ++kvm_stat.signal_exits;
c1150d8c
DL		 1883 post_kvm_run_save(vcpu, kvm_run);
1884 return -EINTR;
1885 }
1886
1887 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1888 ++kvm_stat.request_irq_exits;
1889 post_kvm_run_save(vcpu, kvm_run);
6aa8b732
AK		 1890 return -EINTR;
1891 }
c1150d8c 1892
6aa8b732
AK		 1893 kvm_resched(vcpu);
1894 goto again;
1895 }
1896 }
c1150d8c
DL		 1897
1898 post_kvm_run_save(vcpu, kvm_run);
6aa8b732
AK		 1899 return 0;
1900}
1901
1902static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1903{
1904 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1905}
1906
1907static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1908 unsigned long addr,
1909 u32 err_code)
1910{
1911 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1912
1913 ++kvm_stat.pf_guest;
1914
1915 if (is_page_fault(vect_info)) {
1916 printk(KERN_DEBUG "inject_page_fault: "
1917 "double fault 0x%lx @ 0x%lx\n",
1918 addr, vmcs_readl(GUEST_RIP));
1919 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1920 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1921 DF_VECTOR |
1922 INTR_TYPE_EXCEPTION |
1923 INTR_INFO_DELIEVER_CODE_MASK |
1924 INTR_INFO_VALID_MASK);
1925 return;
1926 }
1927 vcpu->cr2 = addr;
1928 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1929 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1930 PF_VECTOR |
1931 INTR_TYPE_EXCEPTION |
1932 INTR_INFO_DELIEVER_CODE_MASK |
1933 INTR_INFO_VALID_MASK);
1934
1935}
1936
1937static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1938{
1939 if (vcpu->vmcs) {
1940 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1941 free_vmcs(vcpu->vmcs);
1942 vcpu->vmcs = NULL;
1943 }
1944}
1945
1946static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1947{
1948 vmx_free_vmcs(vcpu);
1949}
1950
1951static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1952{
1953 struct vmcs *vmcs;
1954
965b58a5
IM		 1955 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1956 if (!vcpu->guest_msrs)
1957 return -ENOMEM;
1958
1959 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1960 if (!vcpu->host_msrs)
1961 goto out_free_guest_msrs;
1962
6aa8b732
AK		 1963 vmcs = alloc_vmcs();
1964 if (!vmcs)
965b58a5
IM		 1965 goto out_free_msrs;
1966
6aa8b732
AK		 1967 vmcs_clear(vmcs);
1968 vcpu->vmcs = vmcs;
1969 vcpu->launched = 0;
965b58a5 1970
6aa8b732 1971 return 0;
965b58a5
IM		 1972
1973out_free_msrs:
1974 kfree(vcpu->host_msrs);
1975 vcpu->host_msrs = NULL;
1976
1977out_free_guest_msrs:
1978 kfree(vcpu->guest_msrs);
1979 vcpu->guest_msrs = NULL;
1980
1981 return -ENOMEM;
6aa8b732
AK		 1982}
1983
1984static struct kvm_arch_ops vmx_arch_ops = {
1985 .cpu_has_kvm_support = cpu_has_kvm_support,
1986 .disabled_by_bios = vmx_disabled_by_bios,
1987 .hardware_setup = hardware_setup,
1988 .hardware_unsetup = hardware_unsetup,
1989 .hardware_enable = hardware_enable,
1990 .hardware_disable = hardware_disable,
1991
1992 .vcpu_create = vmx_create_vcpu,
1993 .vcpu_free = vmx_free_vcpu,
1994
1995 .vcpu_load = vmx_vcpu_load,
1996 .vcpu_put = vmx_vcpu_put,
1997
1998 .set_guest_debug = set_guest_debug,
1999 .get_msr = vmx_get_msr,
2000 .set_msr = vmx_set_msr,
2001 .get_segment_base = vmx_get_segment_base,
2002 .get_segment = vmx_get_segment,
2003 .set_segment = vmx_set_segment,
6aa8b732
AK		 2004 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2005 .set_cr0 = vmx_set_cr0,
2006 .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
2007 .set_cr3 = vmx_set_cr3,
2008 .set_cr4 = vmx_set_cr4,
05b3e0c2 2009#ifdef CONFIG_X86_64
6aa8b732
AK		 2010 .set_efer = vmx_set_efer,
2011#endif
2012 .get_idt = vmx_get_idt,
2013 .set_idt = vmx_set_idt,
2014 .get_gdt = vmx_get_gdt,
2015 .set_gdt = vmx_set_gdt,
2016 .cache_regs = vcpu_load_rsp_rip,
2017 .decache_regs = vcpu_put_rsp_rip,
2018 .get_rflags = vmx_get_rflags,
2019 .set_rflags = vmx_set_rflags,
2020
2021 .tlb_flush = vmx_flush_tlb,
2022 .inject_page_fault = vmx_inject_page_fault,
2023
2024 .inject_gp = vmx_inject_gp,
2025
2026 .run = vmx_vcpu_run,
2027 .skip_emulated_instruction = skip_emulated_instruction,
2028 .vcpu_setup = vmx_vcpu_setup,
2029};
2030
2031static int __init vmx_init(void)
2032{
873a7c42 2033 return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
6aa8b732
AK		 2034}
2035
2036static void __exit vmx_exit(void)
2037{
2038 kvm_exit_arch();
2039}
2040
2041module_init(vmx_init)
2042module_exit(vmx_exit)
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