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1 | /****************************************************************************** |
2 | * x86_emulate.c | |
3 | * | |
4 | * Generic x86 (32-bit and 64-bit) instruction decoder and emulator. | |
5 | * | |
6 | * Copyright (c) 2005 Keir Fraser | |
7 | * | |
8 | * Linux coding style, mod r/m decoder, segment base fixes, real-mode | |
dcc0766b | 9 | * privileged instructions: |
6aa8b732 AK |
10 | * |
11 | * Copyright (C) 2006 Qumranet | |
12 | * | |
13 | * Avi Kivity <avi@qumranet.com> | |
14 | * Yaniv Kamay <yaniv@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4 | |
20 | */ | |
21 | ||
22 | #ifndef __KERNEL__ | |
23 | #include <stdio.h> | |
24 | #include <stdint.h> | |
25 | #include <public/xen.h> | |
d77c26fc | 26 | #define DPRINTF(_f, _a ...) printf(_f , ## _a) |
6aa8b732 AK |
27 | #else |
28 | #include "kvm.h" | |
29 | #define DPRINTF(x...) do {} while (0) | |
30 | #endif | |
31 | #include "x86_emulate.h" | |
32 | #include <linux/module.h> | |
33 | ||
34 | /* | |
35 | * Opcode effective-address decode tables. | |
36 | * Note that we only emulate instructions that have at least one memory | |
37 | * operand (excluding implicit stack references). We assume that stack | |
38 | * references and instruction fetches will never occur in special memory | |
39 | * areas that require emulation. So, for example, 'mov <imm>,<reg>' need | |
40 | * not be handled. | |
41 | */ | |
42 | ||
43 | /* Operand sizes: 8-bit operands or specified/overridden size. */ | |
44 | #define ByteOp (1<<0) /* 8-bit operands. */ | |
45 | /* Destination operand type. */ | |
46 | #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */ | |
47 | #define DstReg (2<<1) /* Register operand. */ | |
48 | #define DstMem (3<<1) /* Memory operand. */ | |
49 | #define DstMask (3<<1) | |
50 | /* Source operand type. */ | |
51 | #define SrcNone (0<<3) /* No source operand. */ | |
52 | #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */ | |
53 | #define SrcReg (1<<3) /* Register operand. */ | |
54 | #define SrcMem (2<<3) /* Memory operand. */ | |
55 | #define SrcMem16 (3<<3) /* Memory operand (16-bit). */ | |
56 | #define SrcMem32 (4<<3) /* Memory operand (32-bit). */ | |
57 | #define SrcImm (5<<3) /* Immediate operand. */ | |
58 | #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */ | |
59 | #define SrcMask (7<<3) | |
60 | /* Generic ModRM decode. */ | |
61 | #define ModRM (1<<6) | |
62 | /* Destination is only written; never read. */ | |
63 | #define Mov (1<<7) | |
038e51de | 64 | #define BitOp (1<<8) |
6aa8b732 AK |
65 | |
66 | static u8 opcode_table[256] = { | |
67 | /* 0x00 - 0x07 */ | |
68 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
69 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
70 | 0, 0, 0, 0, | |
71 | /* 0x08 - 0x0F */ | |
72 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
73 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
74 | 0, 0, 0, 0, | |
75 | /* 0x10 - 0x17 */ | |
76 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
77 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
78 | 0, 0, 0, 0, | |
79 | /* 0x18 - 0x1F */ | |
80 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
81 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
82 | 0, 0, 0, 0, | |
83 | /* 0x20 - 0x27 */ | |
84 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
85 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
19eb938e | 86 | SrcImmByte, SrcImm, 0, 0, |
6aa8b732 AK |
87 | /* 0x28 - 0x2F */ |
88 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
89 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
90 | 0, 0, 0, 0, | |
91 | /* 0x30 - 0x37 */ | |
92 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
93 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
94 | 0, 0, 0, 0, | |
95 | /* 0x38 - 0x3F */ | |
96 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
97 | ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM, | |
98 | 0, 0, 0, 0, | |
99 | /* 0x40 - 0x4F */ | |
100 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
7f0aaee0 | 101 | /* 0x50 - 0x57 */ |
7e778161 NK |
102 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
103 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
7f0aaee0 NK |
104 | /* 0x58 - 0x5F */ |
105 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
106 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
7d316911 | 107 | /* 0x60 - 0x67 */ |
6aa8b732 | 108 | 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ , |
7d316911 NK |
109 | 0, 0, 0, 0, |
110 | /* 0x68 - 0x6F */ | |
111 | 0, 0, ImplicitOps|Mov, 0, | |
e70669ab LV |
112 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */ |
113 | SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */ | |
55bebde4 NK |
114 | /* 0x70 - 0x77 */ |
115 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
116 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
117 | /* 0x78 - 0x7F */ | |
118 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
119 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 AK |
120 | /* 0x80 - 0x87 */ |
121 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM, | |
122 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, | |
123 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
124 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, | |
125 | /* 0x88 - 0x8F */ | |
126 | ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov, | |
127 | ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
7e0b54b1 | 128 | 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov, |
6aa8b732 | 129 | /* 0x90 - 0x9F */ |
535eabcf | 130 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0, |
6aa8b732 AK |
131 | /* 0xA0 - 0xA7 */ |
132 | ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov, | |
133 | ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov, | |
134 | ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, | |
135 | ByteOp | ImplicitOps, ImplicitOps, | |
136 | /* 0xA8 - 0xAF */ | |
137 | 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, | |
138 | ByteOp | ImplicitOps | Mov, ImplicitOps | Mov, | |
139 | ByteOp | ImplicitOps, ImplicitOps, | |
140 | /* 0xB0 - 0xBF */ | |
141 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
142 | /* 0xC0 - 0xC7 */ | |
d9413cd7 NK |
143 | ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM, |
144 | 0, ImplicitOps, 0, 0, | |
145 | ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov, | |
6aa8b732 AK |
146 | /* 0xC8 - 0xCF */ |
147 | 0, 0, 0, 0, 0, 0, 0, 0, | |
148 | /* 0xD0 - 0xD7 */ | |
149 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
150 | ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM, | |
151 | 0, 0, 0, 0, | |
152 | /* 0xD8 - 0xDF */ | |
153 | 0, 0, 0, 0, 0, 0, 0, 0, | |
098c937b NK |
154 | /* 0xE0 - 0xE7 */ |
155 | 0, 0, 0, 0, 0, 0, 0, 0, | |
156 | /* 0xE8 - 0xEF */ | |
f6eed391 | 157 | ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0, |
6aa8b732 AK |
158 | /* 0xF0 - 0xF7 */ |
159 | 0, 0, 0, 0, | |
72d6e5a0 AK |
160 | ImplicitOps, 0, |
161 | ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM, | |
6aa8b732 AK |
162 | /* 0xF8 - 0xFF */ |
163 | 0, 0, 0, 0, | |
164 | 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM | |
165 | }; | |
166 | ||
038e51de | 167 | static u16 twobyte_table[256] = { |
6aa8b732 AK |
168 | /* 0x00 - 0x0F */ |
169 | 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0, | |
651a3e29 | 170 | ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0, |
6aa8b732 AK |
171 | /* 0x10 - 0x1F */ |
172 | 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0, | |
173 | /* 0x20 - 0x2F */ | |
174 | ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0, | |
175 | 0, 0, 0, 0, 0, 0, 0, 0, | |
176 | /* 0x30 - 0x3F */ | |
35f3f286 | 177 | ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
6aa8b732 AK |
178 | /* 0x40 - 0x47 */ |
179 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
180 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
181 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
182 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
183 | /* 0x48 - 0x4F */ | |
184 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
185 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
186 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
187 | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov, | |
188 | /* 0x50 - 0x5F */ | |
189 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
190 | /* 0x60 - 0x6F */ | |
191 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
192 | /* 0x70 - 0x7F */ | |
193 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
194 | /* 0x80 - 0x8F */ | |
bbe9abbd NK |
195 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, |
196 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
197 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
198 | ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, | |
6aa8b732 AK |
199 | /* 0x90 - 0x9F */ |
200 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
201 | /* 0xA0 - 0xA7 */ | |
038e51de | 202 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 | 203 | /* 0xA8 - 0xAF */ |
038e51de | 204 | 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0, |
6aa8b732 AK |
205 | /* 0xB0 - 0xB7 */ |
206 | ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0, | |
038e51de | 207 | DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
208 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
209 | DstReg | SrcMem16 | ModRM | Mov, | |
210 | /* 0xB8 - 0xBF */ | |
038e51de | 211 | 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp, |
6aa8b732 AK |
212 | 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov, |
213 | DstReg | SrcMem16 | ModRM | Mov, | |
214 | /* 0xC0 - 0xCF */ | |
a012e65a SY |
215 | 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM, |
216 | 0, 0, 0, 0, 0, 0, 0, 0, | |
6aa8b732 AK |
217 | /* 0xD0 - 0xDF */ |
218 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
219 | /* 0xE0 - 0xEF */ | |
220 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
221 | /* 0xF0 - 0xFF */ | |
222 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 | |
223 | }; | |
224 | ||
6aa8b732 AK |
225 | /* EFLAGS bit definitions. */ |
226 | #define EFLG_OF (1<<11) | |
227 | #define EFLG_DF (1<<10) | |
228 | #define EFLG_SF (1<<7) | |
229 | #define EFLG_ZF (1<<6) | |
230 | #define EFLG_AF (1<<4) | |
231 | #define EFLG_PF (1<<2) | |
232 | #define EFLG_CF (1<<0) | |
233 | ||
234 | /* | |
235 | * Instruction emulation: | |
236 | * Most instructions are emulated directly via a fragment of inline assembly | |
237 | * code. This allows us to save/restore EFLAGS and thus very easily pick up | |
238 | * any modified flags. | |
239 | */ | |
240 | ||
05b3e0c2 | 241 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
242 | #define _LO32 "k" /* force 32-bit operand */ |
243 | #define _STK "%%rsp" /* stack pointer */ | |
244 | #elif defined(__i386__) | |
245 | #define _LO32 "" /* force 32-bit operand */ | |
246 | #define _STK "%%esp" /* stack pointer */ | |
247 | #endif | |
248 | ||
249 | /* | |
250 | * These EFLAGS bits are restored from saved value during emulation, and | |
251 | * any changes are written back to the saved value after emulation. | |
252 | */ | |
253 | #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF) | |
254 | ||
255 | /* Before executing instruction: restore necessary bits in EFLAGS. */ | |
256 | #define _PRE_EFLAGS(_sav, _msk, _tmp) \ | |
257 | /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \ | |
258 | "push %"_sav"; " \ | |
259 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
260 | "andl %"_LO32 _tmp",("_STK"); " \ | |
261 | "pushf; " \ | |
262 | "notl %"_LO32 _tmp"; " \ | |
263 | "andl %"_LO32 _tmp",("_STK"); " \ | |
264 | "pop %"_tmp"; " \ | |
265 | "orl %"_LO32 _tmp",("_STK"); " \ | |
266 | "popf; " \ | |
267 | /* _sav &= ~msk; */ \ | |
268 | "movl %"_msk",%"_LO32 _tmp"; " \ | |
269 | "notl %"_LO32 _tmp"; " \ | |
270 | "andl %"_LO32 _tmp",%"_sav"; " | |
271 | ||
272 | /* After executing instruction: write-back necessary bits in EFLAGS. */ | |
273 | #define _POST_EFLAGS(_sav, _msk, _tmp) \ | |
274 | /* _sav |= EFLAGS & _msk; */ \ | |
275 | "pushf; " \ | |
276 | "pop %"_tmp"; " \ | |
277 | "andl %"_msk",%"_LO32 _tmp"; " \ | |
278 | "orl %"_LO32 _tmp",%"_sav"; " | |
279 | ||
280 | /* Raw emulation: instruction has two explicit operands. */ | |
281 | #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
282 | do { \ | |
283 | unsigned long _tmp; \ | |
284 | \ | |
285 | switch ((_dst).bytes) { \ | |
286 | case 2: \ | |
287 | __asm__ __volatile__ ( \ | |
d77c26fc | 288 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 289 | _op"w %"_wx"3,%1; " \ |
d77c26fc | 290 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
291 | : "=m" (_eflags), "=m" ((_dst).val), \ |
292 | "=&r" (_tmp) \ | |
d77c26fc | 293 | : _wy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
294 | break; \ |
295 | case 4: \ | |
296 | __asm__ __volatile__ ( \ | |
d77c26fc | 297 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 298 | _op"l %"_lx"3,%1; " \ |
d77c26fc | 299 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
300 | : "=m" (_eflags), "=m" ((_dst).val), \ |
301 | "=&r" (_tmp) \ | |
d77c26fc | 302 | : _ly ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
303 | break; \ |
304 | case 8: \ | |
305 | __emulate_2op_8byte(_op, _src, _dst, \ | |
306 | _eflags, _qx, _qy); \ | |
307 | break; \ | |
308 | } \ | |
309 | } while (0) | |
310 | ||
311 | #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \ | |
312 | do { \ | |
313 | unsigned long _tmp; \ | |
d77c26fc | 314 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
315 | case 1: \ |
316 | __asm__ __volatile__ ( \ | |
d77c26fc | 317 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 318 | _op"b %"_bx"3,%1; " \ |
d77c26fc | 319 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 AK |
320 | : "=m" (_eflags), "=m" ((_dst).val), \ |
321 | "=&r" (_tmp) \ | |
d77c26fc | 322 | : _by ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
323 | break; \ |
324 | default: \ | |
325 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
326 | _wx, _wy, _lx, _ly, _qx, _qy); \ | |
327 | break; \ | |
328 | } \ | |
329 | } while (0) | |
330 | ||
331 | /* Source operand is byte-sized and may be restricted to just %cl. */ | |
332 | #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \ | |
333 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
334 | "b", "c", "b", "c", "b", "c", "b", "c") | |
335 | ||
336 | /* Source operand is byte, word, long or quad sized. */ | |
337 | #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \ | |
338 | __emulate_2op(_op, _src, _dst, _eflags, \ | |
339 | "b", "q", "w", "r", _LO32, "r", "", "r") | |
340 | ||
341 | /* Source operand is word, long or quad sized. */ | |
342 | #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \ | |
343 | __emulate_2op_nobyte(_op, _src, _dst, _eflags, \ | |
344 | "w", "r", _LO32, "r", "", "r") | |
345 | ||
346 | /* Instruction has only one explicit operand (no source operand). */ | |
347 | #define emulate_1op(_op, _dst, _eflags) \ | |
348 | do { \ | |
349 | unsigned long _tmp; \ | |
350 | \ | |
d77c26fc | 351 | switch ((_dst).bytes) { \ |
6aa8b732 AK |
352 | case 1: \ |
353 | __asm__ __volatile__ ( \ | |
d77c26fc | 354 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 355 | _op"b %1; " \ |
d77c26fc | 356 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
357 | : "=m" (_eflags), "=m" ((_dst).val), \ |
358 | "=&r" (_tmp) \ | |
d77c26fc | 359 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
360 | break; \ |
361 | case 2: \ | |
362 | __asm__ __volatile__ ( \ | |
d77c26fc | 363 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 364 | _op"w %1; " \ |
d77c26fc | 365 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
366 | : "=m" (_eflags), "=m" ((_dst).val), \ |
367 | "=&r" (_tmp) \ | |
d77c26fc | 368 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
369 | break; \ |
370 | case 4: \ | |
371 | __asm__ __volatile__ ( \ | |
d77c26fc | 372 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 373 | _op"l %1; " \ |
d77c26fc | 374 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 AK |
375 | : "=m" (_eflags), "=m" ((_dst).val), \ |
376 | "=&r" (_tmp) \ | |
d77c26fc | 377 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
378 | break; \ |
379 | case 8: \ | |
380 | __emulate_1op_8byte(_op, _dst, _eflags); \ | |
381 | break; \ | |
382 | } \ | |
383 | } while (0) | |
384 | ||
385 | /* Emulate an instruction with quadword operands (x86/64 only). */ | |
05b3e0c2 | 386 | #if defined(CONFIG_X86_64) |
6aa8b732 AK |
387 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \ |
388 | do { \ | |
389 | __asm__ __volatile__ ( \ | |
d77c26fc | 390 | _PRE_EFLAGS("0", "4", "2") \ |
6aa8b732 | 391 | _op"q %"_qx"3,%1; " \ |
d77c26fc | 392 | _POST_EFLAGS("0", "4", "2") \ |
6aa8b732 | 393 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 394 | : _qy ((_src).val), "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
395 | } while (0) |
396 | ||
397 | #define __emulate_1op_8byte(_op, _dst, _eflags) \ | |
398 | do { \ | |
399 | __asm__ __volatile__ ( \ | |
d77c26fc | 400 | _PRE_EFLAGS("0", "3", "2") \ |
6aa8b732 | 401 | _op"q %1; " \ |
d77c26fc | 402 | _POST_EFLAGS("0", "3", "2") \ |
6aa8b732 | 403 | : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \ |
d77c26fc | 404 | : "i" (EFLAGS_MASK)); \ |
6aa8b732 AK |
405 | } while (0) |
406 | ||
407 | #elif defined(__i386__) | |
408 | #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) | |
409 | #define __emulate_1op_8byte(_op, _dst, _eflags) | |
410 | #endif /* __i386__ */ | |
411 | ||
412 | /* Fetch next part of the instruction being emulated. */ | |
413 | #define insn_fetch(_type, _size, _eip) \ | |
414 | ({ unsigned long _x; \ | |
415 | rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \ | |
d77c26fc MD |
416 | (_size), ctxt->vcpu); \ |
417 | if (rc != 0) \ | |
6aa8b732 AK |
418 | goto done; \ |
419 | (_eip) += (_size); \ | |
420 | (_type)_x; \ | |
421 | }) | |
422 | ||
423 | /* Access/update address held in a register, based on addressing mode. */ | |
e70669ab | 424 | #define address_mask(reg) \ |
e4e03ded LV |
425 | ((c->ad_bytes == sizeof(unsigned long)) ? \ |
426 | (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1))) | |
6aa8b732 | 427 | #define register_address(base, reg) \ |
e70669ab | 428 | ((base) + address_mask(reg)) |
6aa8b732 AK |
429 | #define register_address_increment(reg, inc) \ |
430 | do { \ | |
431 | /* signed type ensures sign extension to long */ \ | |
432 | int _inc = (inc); \ | |
e4e03ded | 433 | if (c->ad_bytes == sizeof(unsigned long)) \ |
6aa8b732 AK |
434 | (reg) += _inc; \ |
435 | else \ | |
e4e03ded LV |
436 | (reg) = ((reg) & \ |
437 | ~((1UL << (c->ad_bytes << 3)) - 1)) | \ | |
438 | (((reg) + _inc) & \ | |
439 | ((1UL << (c->ad_bytes << 3)) - 1)); \ | |
6aa8b732 AK |
440 | } while (0) |
441 | ||
098c937b NK |
442 | #define JMP_REL(rel) \ |
443 | do { \ | |
e4e03ded | 444 | register_address_increment(c->eip, rel); \ |
098c937b NK |
445 | } while (0) |
446 | ||
1e3c5cb0 RR |
447 | /* |
448 | * Given the 'reg' portion of a ModRM byte, and a register block, return a | |
449 | * pointer into the block that addresses the relevant register. | |
450 | * @highbyte_regs specifies whether to decode AH,CH,DH,BH. | |
451 | */ | |
452 | static void *decode_register(u8 modrm_reg, unsigned long *regs, | |
453 | int highbyte_regs) | |
6aa8b732 AK |
454 | { |
455 | void *p; | |
456 | ||
457 | p = ®s[modrm_reg]; | |
458 | if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8) | |
459 | p = (unsigned char *)®s[modrm_reg & 3] + 1; | |
460 | return p; | |
461 | } | |
462 | ||
463 | static int read_descriptor(struct x86_emulate_ctxt *ctxt, | |
464 | struct x86_emulate_ops *ops, | |
465 | void *ptr, | |
466 | u16 *size, unsigned long *address, int op_bytes) | |
467 | { | |
468 | int rc; | |
469 | ||
470 | if (op_bytes == 2) | |
471 | op_bytes = 3; | |
472 | *address = 0; | |
cebff02b LV |
473 | rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2, |
474 | ctxt->vcpu); | |
6aa8b732 AK |
475 | if (rc) |
476 | return rc; | |
cebff02b LV |
477 | rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes, |
478 | ctxt->vcpu); | |
6aa8b732 AK |
479 | return rc; |
480 | } | |
481 | ||
bbe9abbd NK |
482 | static int test_cc(unsigned int condition, unsigned int flags) |
483 | { | |
484 | int rc = 0; | |
485 | ||
486 | switch ((condition & 15) >> 1) { | |
487 | case 0: /* o */ | |
488 | rc |= (flags & EFLG_OF); | |
489 | break; | |
490 | case 1: /* b/c/nae */ | |
491 | rc |= (flags & EFLG_CF); | |
492 | break; | |
493 | case 2: /* z/e */ | |
494 | rc |= (flags & EFLG_ZF); | |
495 | break; | |
496 | case 3: /* be/na */ | |
497 | rc |= (flags & (EFLG_CF|EFLG_ZF)); | |
498 | break; | |
499 | case 4: /* s */ | |
500 | rc |= (flags & EFLG_SF); | |
501 | break; | |
502 | case 5: /* p/pe */ | |
503 | rc |= (flags & EFLG_PF); | |
504 | break; | |
505 | case 7: /* le/ng */ | |
506 | rc |= (flags & EFLG_ZF); | |
507 | /* fall through */ | |
508 | case 6: /* l/nge */ | |
509 | rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF)); | |
510 | break; | |
511 | } | |
512 | ||
513 | /* Odd condition identifiers (lsb == 1) have inverted sense. */ | |
514 | return (!!rc ^ (condition & 1)); | |
515 | } | |
516 | ||
6aa8b732 | 517 | int |
8b4caf66 | 518 | x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
6aa8b732 | 519 | { |
e4e03ded LV |
520 | struct decode_cache *c = &ctxt->decode; |
521 | u8 sib, rex_prefix = 0; | |
6aa8b732 | 522 | int rc = 0; |
6aa8b732 | 523 | int mode = ctxt->mode; |
e4e03ded | 524 | int index_reg = 0, base_reg = 0, scale, rip_relative = 0; |
6aa8b732 AK |
525 | |
526 | /* Shadow copy of register state. Committed on successful emulation. */ | |
6aa8b732 | 527 | |
e4e03ded LV |
528 | memset(c, 0, sizeof(struct decode_cache)); |
529 | c->eip = ctxt->vcpu->rip; | |
530 | memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs); | |
6aa8b732 AK |
531 | |
532 | switch (mode) { | |
533 | case X86EMUL_MODE_REAL: | |
534 | case X86EMUL_MODE_PROT16: | |
e4e03ded | 535 | c->op_bytes = c->ad_bytes = 2; |
6aa8b732 AK |
536 | break; |
537 | case X86EMUL_MODE_PROT32: | |
e4e03ded | 538 | c->op_bytes = c->ad_bytes = 4; |
6aa8b732 | 539 | break; |
05b3e0c2 | 540 | #ifdef CONFIG_X86_64 |
6aa8b732 | 541 | case X86EMUL_MODE_PROT64: |
e4e03ded LV |
542 | c->op_bytes = 4; |
543 | c->ad_bytes = 8; | |
6aa8b732 AK |
544 | break; |
545 | #endif | |
546 | default: | |
547 | return -1; | |
548 | } | |
549 | ||
550 | /* Legacy prefixes. */ | |
b4c6abfe | 551 | for (;;) { |
e4e03ded | 552 | switch (c->b = insn_fetch(u8, 1, c->eip)) { |
6aa8b732 | 553 | case 0x66: /* operand-size override */ |
e4e03ded | 554 | c->op_bytes ^= 6; /* switch between 2/4 bytes */ |
6aa8b732 AK |
555 | break; |
556 | case 0x67: /* address-size override */ | |
557 | if (mode == X86EMUL_MODE_PROT64) | |
e4e03ded LV |
558 | /* switch between 4/8 bytes */ |
559 | c->ad_bytes ^= 12; | |
6aa8b732 | 560 | else |
e4e03ded LV |
561 | /* switch between 2/4 bytes */ |
562 | c->ad_bytes ^= 6; | |
6aa8b732 AK |
563 | break; |
564 | case 0x2e: /* CS override */ | |
e4e03ded | 565 | c->override_base = &ctxt->cs_base; |
6aa8b732 AK |
566 | break; |
567 | case 0x3e: /* DS override */ | |
e4e03ded | 568 | c->override_base = &ctxt->ds_base; |
6aa8b732 AK |
569 | break; |
570 | case 0x26: /* ES override */ | |
e4e03ded | 571 | c->override_base = &ctxt->es_base; |
6aa8b732 AK |
572 | break; |
573 | case 0x64: /* FS override */ | |
e4e03ded | 574 | c->override_base = &ctxt->fs_base; |
6aa8b732 AK |
575 | break; |
576 | case 0x65: /* GS override */ | |
e4e03ded | 577 | c->override_base = &ctxt->gs_base; |
6aa8b732 AK |
578 | break; |
579 | case 0x36: /* SS override */ | |
e4e03ded | 580 | c->override_base = &ctxt->ss_base; |
6aa8b732 | 581 | break; |
b4c6abfe LV |
582 | case 0x40 ... 0x4f: /* REX */ |
583 | if (mode != X86EMUL_MODE_PROT64) | |
584 | goto done_prefixes; | |
585 | rex_prefix = c->b; | |
586 | continue; | |
6aa8b732 | 587 | case 0xf0: /* LOCK */ |
e4e03ded | 588 | c->lock_prefix = 1; |
6aa8b732 | 589 | break; |
ae6200ba | 590 | case 0xf2: /* REPNE/REPNZ */ |
6aa8b732 | 591 | case 0xf3: /* REP/REPE/REPZ */ |
e4e03ded | 592 | c->rep_prefix = 1; |
6aa8b732 | 593 | break; |
6aa8b732 AK |
594 | default: |
595 | goto done_prefixes; | |
596 | } | |
b4c6abfe LV |
597 | |
598 | /* Any legacy prefix after a REX prefix nullifies its effect. */ | |
599 | ||
600 | rex_prefix = 0; | |
6aa8b732 AK |
601 | } |
602 | ||
603 | done_prefixes: | |
604 | ||
605 | /* REX prefix. */ | |
b4c6abfe LV |
606 | if (rex_prefix) { |
607 | if (rex_prefix & 8) | |
e4e03ded | 608 | c->op_bytes = 8; /* REX.W */ |
b4c6abfe LV |
609 | c->modrm_reg = (rex_prefix & 4) << 1; /* REX.R */ |
610 | index_reg = (rex_prefix & 2) << 2; /* REX.X */ | |
611 | c->modrm_rm = base_reg = (rex_prefix & 1) << 3; /* REG.B */ | |
6aa8b732 AK |
612 | } |
613 | ||
614 | /* Opcode byte(s). */ | |
e4e03ded LV |
615 | c->d = opcode_table[c->b]; |
616 | if (c->d == 0) { | |
6aa8b732 | 617 | /* Two-byte opcode? */ |
e4e03ded LV |
618 | if (c->b == 0x0f) { |
619 | c->twobyte = 1; | |
620 | c->b = insn_fetch(u8, 1, c->eip); | |
621 | c->d = twobyte_table[c->b]; | |
6aa8b732 AK |
622 | } |
623 | ||
624 | /* Unrecognised? */ | |
8b4caf66 LV |
625 | if (c->d == 0) { |
626 | DPRINTF("Cannot emulate %02x\n", c->b); | |
627 | return -1; | |
628 | } | |
6aa8b732 AK |
629 | } |
630 | ||
631 | /* ModRM and SIB bytes. */ | |
e4e03ded LV |
632 | if (c->d & ModRM) { |
633 | c->modrm = insn_fetch(u8, 1, c->eip); | |
634 | c->modrm_mod |= (c->modrm & 0xc0) >> 6; | |
635 | c->modrm_reg |= (c->modrm & 0x38) >> 3; | |
636 | c->modrm_rm |= (c->modrm & 0x07); | |
637 | c->modrm_ea = 0; | |
638 | c->use_modrm_ea = 1; | |
639 | ||
640 | if (c->modrm_mod == 3) { | |
641 | c->modrm_val = *(unsigned long *) | |
642 | decode_register(c->modrm_rm, c->regs, c->d & ByteOp); | |
6aa8b732 AK |
643 | goto modrm_done; |
644 | } | |
645 | ||
e4e03ded LV |
646 | if (c->ad_bytes == 2) { |
647 | unsigned bx = c->regs[VCPU_REGS_RBX]; | |
648 | unsigned bp = c->regs[VCPU_REGS_RBP]; | |
649 | unsigned si = c->regs[VCPU_REGS_RSI]; | |
650 | unsigned di = c->regs[VCPU_REGS_RDI]; | |
6aa8b732 AK |
651 | |
652 | /* 16-bit ModR/M decode. */ | |
e4e03ded | 653 | switch (c->modrm_mod) { |
6aa8b732 | 654 | case 0: |
e4e03ded LV |
655 | if (c->modrm_rm == 6) |
656 | c->modrm_ea += | |
657 | insn_fetch(u16, 2, c->eip); | |
6aa8b732 AK |
658 | break; |
659 | case 1: | |
e4e03ded | 660 | c->modrm_ea += insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
661 | break; |
662 | case 2: | |
e4e03ded | 663 | c->modrm_ea += insn_fetch(u16, 2, c->eip); |
6aa8b732 AK |
664 | break; |
665 | } | |
e4e03ded | 666 | switch (c->modrm_rm) { |
6aa8b732 | 667 | case 0: |
e4e03ded | 668 | c->modrm_ea += bx + si; |
6aa8b732 AK |
669 | break; |
670 | case 1: | |
e4e03ded | 671 | c->modrm_ea += bx + di; |
6aa8b732 AK |
672 | break; |
673 | case 2: | |
e4e03ded | 674 | c->modrm_ea += bp + si; |
6aa8b732 AK |
675 | break; |
676 | case 3: | |
e4e03ded | 677 | c->modrm_ea += bp + di; |
6aa8b732 AK |
678 | break; |
679 | case 4: | |
e4e03ded | 680 | c->modrm_ea += si; |
6aa8b732 AK |
681 | break; |
682 | case 5: | |
e4e03ded | 683 | c->modrm_ea += di; |
6aa8b732 AK |
684 | break; |
685 | case 6: | |
e4e03ded LV |
686 | if (c->modrm_mod != 0) |
687 | c->modrm_ea += bp; | |
6aa8b732 AK |
688 | break; |
689 | case 7: | |
e4e03ded | 690 | c->modrm_ea += bx; |
6aa8b732 AK |
691 | break; |
692 | } | |
e4e03ded LV |
693 | if (c->modrm_rm == 2 || c->modrm_rm == 3 || |
694 | (c->modrm_rm == 6 && c->modrm_mod != 0)) | |
695 | if (!c->override_base) | |
696 | c->override_base = &ctxt->ss_base; | |
697 | c->modrm_ea = (u16)c->modrm_ea; | |
6aa8b732 AK |
698 | } else { |
699 | /* 32/64-bit ModR/M decode. */ | |
e4e03ded | 700 | switch (c->modrm_rm) { |
6aa8b732 AK |
701 | case 4: |
702 | case 12: | |
e4e03ded | 703 | sib = insn_fetch(u8, 1, c->eip); |
6aa8b732 AK |
704 | index_reg |= (sib >> 3) & 7; |
705 | base_reg |= sib & 7; | |
706 | scale = sib >> 6; | |
707 | ||
708 | switch (base_reg) { | |
709 | case 5: | |
e4e03ded LV |
710 | if (c->modrm_mod != 0) |
711 | c->modrm_ea += | |
712 | c->regs[base_reg]; | |
6aa8b732 | 713 | else |
e4e03ded LV |
714 | c->modrm_ea += |
715 | insn_fetch(s32, 4, c->eip); | |
6aa8b732 AK |
716 | break; |
717 | default: | |
e4e03ded | 718 | c->modrm_ea += c->regs[base_reg]; |
6aa8b732 AK |
719 | } |
720 | switch (index_reg) { | |
721 | case 4: | |
722 | break; | |
723 | default: | |
e4e03ded LV |
724 | c->modrm_ea += |
725 | c->regs[index_reg] << scale; | |
6aa8b732 AK |
726 | |
727 | } | |
728 | break; | |
729 | case 5: | |
e4e03ded LV |
730 | if (c->modrm_mod != 0) |
731 | c->modrm_ea += c->regs[c->modrm_rm]; | |
6aa8b732 AK |
732 | else if (mode == X86EMUL_MODE_PROT64) |
733 | rip_relative = 1; | |
734 | break; | |
735 | default: | |
e4e03ded | 736 | c->modrm_ea += c->regs[c->modrm_rm]; |
6aa8b732 AK |
737 | break; |
738 | } | |
e4e03ded | 739 | switch (c->modrm_mod) { |
6aa8b732 | 740 | case 0: |
e4e03ded LV |
741 | if (c->modrm_rm == 5) |
742 | c->modrm_ea += | |
743 | insn_fetch(s32, 4, c->eip); | |
6aa8b732 AK |
744 | break; |
745 | case 1: | |
e4e03ded | 746 | c->modrm_ea += insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
747 | break; |
748 | case 2: | |
e4e03ded | 749 | c->modrm_ea += insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
750 | break; |
751 | } | |
752 | } | |
e4e03ded LV |
753 | if (!c->override_base) |
754 | c->override_base = &ctxt->ds_base; | |
6aa8b732 | 755 | if (mode == X86EMUL_MODE_PROT64 && |
e4e03ded LV |
756 | c->override_base != &ctxt->fs_base && |
757 | c->override_base != &ctxt->gs_base) | |
758 | c->override_base = NULL; | |
6aa8b732 | 759 | |
e4e03ded LV |
760 | if (c->override_base) |
761 | c->modrm_ea += *c->override_base; | |
6aa8b732 AK |
762 | |
763 | if (rip_relative) { | |
e4e03ded LV |
764 | c->modrm_ea += c->eip; |
765 | switch (c->d & SrcMask) { | |
6aa8b732 | 766 | case SrcImmByte: |
e4e03ded | 767 | c->modrm_ea += 1; |
6aa8b732 AK |
768 | break; |
769 | case SrcImm: | |
e4e03ded LV |
770 | if (c->d & ByteOp) |
771 | c->modrm_ea += 1; | |
6aa8b732 | 772 | else |
e4e03ded LV |
773 | if (c->op_bytes == 8) |
774 | c->modrm_ea += 4; | |
6aa8b732 | 775 | else |
e4e03ded | 776 | c->modrm_ea += c->op_bytes; |
6aa8b732 AK |
777 | } |
778 | } | |
e4e03ded LV |
779 | if (c->ad_bytes != 8) |
780 | c->modrm_ea = (u32)c->modrm_ea; | |
d77c26fc | 781 | modrm_done: |
6aa8b732 AK |
782 | ; |
783 | } | |
784 | ||
6aa8b732 AK |
785 | /* |
786 | * Decode and fetch the source operand: register, memory | |
787 | * or immediate. | |
788 | */ | |
e4e03ded | 789 | switch (c->d & SrcMask) { |
6aa8b732 AK |
790 | case SrcNone: |
791 | break; | |
792 | case SrcReg: | |
e4e03ded LV |
793 | c->src.type = OP_REG; |
794 | if (c->d & ByteOp) { | |
795 | c->src.ptr = | |
796 | decode_register(c->modrm_reg, c->regs, | |
6aa8b732 | 797 | (rex_prefix == 0)); |
e4e03ded LV |
798 | c->src.val = c->src.orig_val = *(u8 *)c->src.ptr; |
799 | c->src.bytes = 1; | |
6aa8b732 | 800 | } else { |
e4e03ded LV |
801 | c->src.ptr = |
802 | decode_register(c->modrm_reg, c->regs, 0); | |
803 | switch ((c->src.bytes = c->op_bytes)) { | |
6aa8b732 | 804 | case 2: |
e4e03ded LV |
805 | c->src.val = c->src.orig_val = |
806 | *(u16 *) c->src.ptr; | |
6aa8b732 AK |
807 | break; |
808 | case 4: | |
e4e03ded LV |
809 | c->src.val = c->src.orig_val = |
810 | *(u32 *) c->src.ptr; | |
6aa8b732 AK |
811 | break; |
812 | case 8: | |
e4e03ded LV |
813 | c->src.val = c->src.orig_val = |
814 | *(u64 *) c->src.ptr; | |
6aa8b732 AK |
815 | break; |
816 | } | |
817 | } | |
818 | break; | |
819 | case SrcMem16: | |
e4e03ded | 820 | c->src.bytes = 2; |
6aa8b732 AK |
821 | goto srcmem_common; |
822 | case SrcMem32: | |
e4e03ded | 823 | c->src.bytes = 4; |
6aa8b732 AK |
824 | goto srcmem_common; |
825 | case SrcMem: | |
e4e03ded LV |
826 | c->src.bytes = (c->d & ByteOp) ? 1 : |
827 | c->op_bytes; | |
b85b9ee9 | 828 | /* Don't fetch the address for invlpg: it could be unmapped. */ |
d77c26fc | 829 | if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7) |
b85b9ee9 | 830 | break; |
d77c26fc | 831 | srcmem_common: |
4e62417b AJ |
832 | /* |
833 | * For instructions with a ModR/M byte, switch to register | |
834 | * access if Mod = 3. | |
835 | */ | |
e4e03ded LV |
836 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
837 | c->src.type = OP_REG; | |
4e62417b AJ |
838 | break; |
839 | } | |
e4e03ded | 840 | c->src.type = OP_MEM; |
6aa8b732 AK |
841 | break; |
842 | case SrcImm: | |
e4e03ded LV |
843 | c->src.type = OP_IMM; |
844 | c->src.ptr = (unsigned long *)c->eip; | |
845 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
846 | if (c->src.bytes == 8) | |
847 | c->src.bytes = 4; | |
6aa8b732 | 848 | /* NB. Immediates are sign-extended as necessary. */ |
e4e03ded | 849 | switch (c->src.bytes) { |
6aa8b732 | 850 | case 1: |
e4e03ded | 851 | c->src.val = insn_fetch(s8, 1, c->eip); |
6aa8b732 AK |
852 | break; |
853 | case 2: | |
e4e03ded | 854 | c->src.val = insn_fetch(s16, 2, c->eip); |
6aa8b732 AK |
855 | break; |
856 | case 4: | |
e4e03ded | 857 | c->src.val = insn_fetch(s32, 4, c->eip); |
6aa8b732 AK |
858 | break; |
859 | } | |
860 | break; | |
861 | case SrcImmByte: | |
e4e03ded LV |
862 | c->src.type = OP_IMM; |
863 | c->src.ptr = (unsigned long *)c->eip; | |
864 | c->src.bytes = 1; | |
865 | c->src.val = insn_fetch(s8, 1, c->eip); | |
6aa8b732 AK |
866 | break; |
867 | } | |
868 | ||
038e51de | 869 | /* Decode and fetch the destination operand: register or memory. */ |
e4e03ded | 870 | switch (c->d & DstMask) { |
038e51de AK |
871 | case ImplicitOps: |
872 | /* Special instructions do their own operand decoding. */ | |
8b4caf66 | 873 | return 0; |
038e51de | 874 | case DstReg: |
e4e03ded LV |
875 | c->dst.type = OP_REG; |
876 | if ((c->d & ByteOp) | |
877 | && !(c->twobyte && | |
878 | (c->b == 0xb6 || c->b == 0xb7))) { | |
879 | c->dst.ptr = | |
880 | decode_register(c->modrm_reg, c->regs, | |
038e51de | 881 | (rex_prefix == 0)); |
e4e03ded LV |
882 | c->dst.val = *(u8 *) c->dst.ptr; |
883 | c->dst.bytes = 1; | |
038e51de | 884 | } else { |
e4e03ded LV |
885 | c->dst.ptr = |
886 | decode_register(c->modrm_reg, c->regs, 0); | |
887 | switch ((c->dst.bytes = c->op_bytes)) { | |
038e51de | 888 | case 2: |
e4e03ded | 889 | c->dst.val = *(u16 *)c->dst.ptr; |
038e51de AK |
890 | break; |
891 | case 4: | |
e4e03ded | 892 | c->dst.val = *(u32 *)c->dst.ptr; |
038e51de AK |
893 | break; |
894 | case 8: | |
e4e03ded | 895 | c->dst.val = *(u64 *)c->dst.ptr; |
038e51de AK |
896 | break; |
897 | } | |
898 | } | |
899 | break; | |
900 | case DstMem: | |
e4e03ded LV |
901 | if ((c->d & ModRM) && c->modrm_mod == 3) { |
902 | c->dst.type = OP_REG; | |
4e62417b AJ |
903 | break; |
904 | } | |
8b4caf66 LV |
905 | c->dst.type = OP_MEM; |
906 | break; | |
907 | } | |
908 | ||
909 | done: | |
910 | return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0; | |
911 | } | |
912 | ||
8cdbd2c9 LV |
913 | static inline void emulate_push(struct x86_emulate_ctxt *ctxt) |
914 | { | |
915 | struct decode_cache *c = &ctxt->decode; | |
916 | ||
917 | c->dst.type = OP_MEM; | |
918 | c->dst.bytes = c->op_bytes; | |
919 | c->dst.val = c->src.val; | |
920 | register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes); | |
921 | c->dst.ptr = (void *) register_address(ctxt->ss_base, | |
922 | c->regs[VCPU_REGS_RSP]); | |
923 | } | |
924 | ||
925 | static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt, | |
926 | struct x86_emulate_ops *ops) | |
927 | { | |
928 | struct decode_cache *c = &ctxt->decode; | |
929 | int rc; | |
930 | ||
931 | /* 64-bit mode: POP always pops a 64-bit operand. */ | |
932 | ||
933 | if (ctxt->mode == X86EMUL_MODE_PROT64) | |
934 | c->dst.bytes = 8; | |
935 | ||
936 | rc = ops->read_std(register_address(ctxt->ss_base, | |
937 | c->regs[VCPU_REGS_RSP]), | |
938 | &c->dst.val, c->dst.bytes, ctxt->vcpu); | |
939 | if (rc != 0) | |
940 | return rc; | |
941 | ||
942 | register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes); | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
05f086f8 | 947 | static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt) |
8cdbd2c9 | 948 | { |
05f086f8 | 949 | struct decode_cache *c = &ctxt->decode; |
8cdbd2c9 LV |
950 | switch (c->modrm_reg) { |
951 | case 0: /* rol */ | |
05f086f8 | 952 | emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
953 | break; |
954 | case 1: /* ror */ | |
05f086f8 | 955 | emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
956 | break; |
957 | case 2: /* rcl */ | |
05f086f8 | 958 | emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
959 | break; |
960 | case 3: /* rcr */ | |
05f086f8 | 961 | emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
962 | break; |
963 | case 4: /* sal/shl */ | |
964 | case 6: /* sal/shl */ | |
05f086f8 | 965 | emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
966 | break; |
967 | case 5: /* shr */ | |
05f086f8 | 968 | emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
969 | break; |
970 | case 7: /* sar */ | |
05f086f8 | 971 | emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
972 | break; |
973 | } | |
974 | } | |
975 | ||
976 | static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt, | |
05f086f8 | 977 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
978 | { |
979 | struct decode_cache *c = &ctxt->decode; | |
980 | int rc = 0; | |
981 | ||
982 | switch (c->modrm_reg) { | |
983 | case 0 ... 1: /* test */ | |
984 | /* | |
985 | * Special case in Grp3: test has an immediate | |
986 | * source operand. | |
987 | */ | |
988 | c->src.type = OP_IMM; | |
989 | c->src.ptr = (unsigned long *)c->eip; | |
990 | c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
991 | if (c->src.bytes == 8) | |
992 | c->src.bytes = 4; | |
993 | switch (c->src.bytes) { | |
994 | case 1: | |
995 | c->src.val = insn_fetch(s8, 1, c->eip); | |
996 | break; | |
997 | case 2: | |
998 | c->src.val = insn_fetch(s16, 2, c->eip); | |
999 | break; | |
1000 | case 4: | |
1001 | c->src.val = insn_fetch(s32, 4, c->eip); | |
1002 | break; | |
1003 | } | |
05f086f8 | 1004 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1005 | break; |
1006 | case 2: /* not */ | |
1007 | c->dst.val = ~c->dst.val; | |
1008 | break; | |
1009 | case 3: /* neg */ | |
05f086f8 | 1010 | emulate_1op("neg", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1011 | break; |
1012 | default: | |
1013 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1014 | rc = X86EMUL_UNHANDLEABLE; | |
1015 | break; | |
1016 | } | |
1017 | done: | |
1018 | return rc; | |
1019 | } | |
1020 | ||
1021 | static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt, | |
a01af5ec | 1022 | struct x86_emulate_ops *ops) |
8cdbd2c9 LV |
1023 | { |
1024 | struct decode_cache *c = &ctxt->decode; | |
1025 | int rc; | |
1026 | ||
1027 | switch (c->modrm_reg) { | |
1028 | case 0: /* inc */ | |
05f086f8 | 1029 | emulate_1op("inc", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1030 | break; |
1031 | case 1: /* dec */ | |
05f086f8 | 1032 | emulate_1op("dec", c->dst, ctxt->eflags); |
8cdbd2c9 LV |
1033 | break; |
1034 | case 4: /* jmp abs */ | |
1035 | if (c->b == 0xff) | |
1036 | c->eip = c->dst.val; | |
1037 | else { | |
1038 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1039 | return X86EMUL_UNHANDLEABLE; | |
1040 | } | |
1041 | break; | |
1042 | case 6: /* push */ | |
1043 | ||
1044 | /* 64-bit mode: PUSH always pushes a 64-bit operand. */ | |
1045 | ||
1046 | if (ctxt->mode == X86EMUL_MODE_PROT64) { | |
1047 | c->dst.bytes = 8; | |
1048 | rc = ops->read_std((unsigned long)c->dst.ptr, | |
1049 | &c->dst.val, 8, ctxt->vcpu); | |
1050 | if (rc != 0) | |
1051 | return rc; | |
1052 | } | |
1053 | register_address_increment(c->regs[VCPU_REGS_RSP], | |
1054 | -c->dst.bytes); | |
1055 | rc = ops->write_emulated(register_address(ctxt->ss_base, | |
1056 | c->regs[VCPU_REGS_RSP]), &c->dst.val, | |
1057 | c->dst.bytes, ctxt->vcpu); | |
1058 | if (rc != 0) | |
1059 | return rc; | |
a01af5ec | 1060 | c->dst.type = OP_NONE; |
8cdbd2c9 LV |
1061 | break; |
1062 | default: | |
1063 | DPRINTF("Cannot emulate %02x\n", c->b); | |
1064 | return X86EMUL_UNHANDLEABLE; | |
1065 | } | |
1066 | return 0; | |
1067 | } | |
1068 | ||
1069 | static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt, | |
1070 | struct x86_emulate_ops *ops, | |
8cdbd2c9 LV |
1071 | unsigned long cr2) |
1072 | { | |
1073 | struct decode_cache *c = &ctxt->decode; | |
1074 | u64 old, new; | |
1075 | int rc; | |
1076 | ||
1077 | rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu); | |
1078 | if (rc != 0) | |
1079 | return rc; | |
1080 | ||
1081 | if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) || | |
1082 | ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) { | |
1083 | ||
1084 | c->regs[VCPU_REGS_RAX] = (u32) (old >> 0); | |
1085 | c->regs[VCPU_REGS_RDX] = (u32) (old >> 32); | |
05f086f8 | 1086 | ctxt->eflags &= ~EFLG_ZF; |
8cdbd2c9 LV |
1087 | |
1088 | } else { | |
1089 | new = ((u64)c->regs[VCPU_REGS_RCX] << 32) | | |
1090 | (u32) c->regs[VCPU_REGS_RBX]; | |
1091 | ||
1092 | rc = ops->cmpxchg_emulated(cr2, &old, &new, 8, ctxt->vcpu); | |
1093 | if (rc != 0) | |
1094 | return rc; | |
05f086f8 | 1095 | ctxt->eflags |= EFLG_ZF; |
8cdbd2c9 LV |
1096 | } |
1097 | return 0; | |
1098 | } | |
1099 | ||
1100 | static inline int writeback(struct x86_emulate_ctxt *ctxt, | |
1101 | struct x86_emulate_ops *ops) | |
1102 | { | |
1103 | int rc; | |
1104 | struct decode_cache *c = &ctxt->decode; | |
1105 | ||
1106 | switch (c->dst.type) { | |
1107 | case OP_REG: | |
1108 | /* The 4-byte case *is* correct: | |
1109 | * in 64-bit mode we zero-extend. | |
1110 | */ | |
1111 | switch (c->dst.bytes) { | |
1112 | case 1: | |
1113 | *(u8 *)c->dst.ptr = (u8)c->dst.val; | |
1114 | break; | |
1115 | case 2: | |
1116 | *(u16 *)c->dst.ptr = (u16)c->dst.val; | |
1117 | break; | |
1118 | case 4: | |
1119 | *c->dst.ptr = (u32)c->dst.val; | |
1120 | break; /* 64b: zero-ext */ | |
1121 | case 8: | |
1122 | *c->dst.ptr = c->dst.val; | |
1123 | break; | |
1124 | } | |
1125 | break; | |
1126 | case OP_MEM: | |
1127 | if (c->lock_prefix) | |
1128 | rc = ops->cmpxchg_emulated( | |
1129 | (unsigned long)c->dst.ptr, | |
1130 | &c->dst.orig_val, | |
1131 | &c->dst.val, | |
1132 | c->dst.bytes, | |
1133 | ctxt->vcpu); | |
1134 | else | |
1135 | rc = ops->write_emulated( | |
1136 | (unsigned long)c->dst.ptr, | |
1137 | &c->dst.val, | |
1138 | c->dst.bytes, | |
1139 | ctxt->vcpu); | |
1140 | if (rc != 0) | |
1141 | return rc; | |
a01af5ec LV |
1142 | break; |
1143 | case OP_NONE: | |
1144 | /* no writeback */ | |
1145 | break; | |
8cdbd2c9 LV |
1146 | default: |
1147 | break; | |
1148 | } | |
1149 | return 0; | |
1150 | } | |
1151 | ||
8b4caf66 | 1152 | int |
1be3aa47 | 1153 | x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops) |
8b4caf66 LV |
1154 | { |
1155 | unsigned long cr2 = ctxt->cr2; | |
8b4caf66 | 1156 | u64 msr_data; |
3427318f | 1157 | unsigned long saved_eip = 0; |
8b4caf66 | 1158 | struct decode_cache *c = &ctxt->decode; |
1be3aa47 | 1159 | int rc = 0; |
8b4caf66 | 1160 | |
3427318f LV |
1161 | /* Shadow copy of register state. Committed on successful emulation. |
1162 | * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't | |
1163 | * modify them. | |
1164 | */ | |
1165 | ||
1166 | memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs); | |
1167 | saved_eip = c->eip; | |
1168 | ||
8b4caf66 LV |
1169 | if ((c->d & ModRM) && (c->modrm_mod != 3)) |
1170 | cr2 = c->modrm_ea; | |
1171 | ||
1172 | if (c->src.type == OP_MEM) { | |
1173 | c->src.ptr = (unsigned long *)cr2; | |
1174 | c->src.val = 0; | |
d77c26fc MD |
1175 | rc = ops->read_emulated((unsigned long)c->src.ptr, |
1176 | &c->src.val, | |
1177 | c->src.bytes, | |
1178 | ctxt->vcpu); | |
1179 | if (rc != 0) | |
8b4caf66 LV |
1180 | goto done; |
1181 | c->src.orig_val = c->src.val; | |
1182 | } | |
1183 | ||
1184 | if ((c->d & DstMask) == ImplicitOps) | |
1185 | goto special_insn; | |
1186 | ||
1187 | ||
1188 | if (c->dst.type == OP_MEM) { | |
1189 | c->dst.ptr = (unsigned long *)cr2; | |
1190 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1191 | c->dst.val = 0; | |
e4e03ded LV |
1192 | if (c->d & BitOp) { |
1193 | unsigned long mask = ~(c->dst.bytes * 8 - 1); | |
df513e2c | 1194 | |
e4e03ded LV |
1195 | c->dst.ptr = (void *)c->dst.ptr + |
1196 | (c->src.val & mask) / 8; | |
038e51de | 1197 | } |
e4e03ded LV |
1198 | if (!(c->d & Mov) && |
1199 | /* optimisation - avoid slow emulated read */ | |
1200 | ((rc = ops->read_emulated((unsigned long)c->dst.ptr, | |
1201 | &c->dst.val, | |
1202 | c->dst.bytes, ctxt->vcpu)) != 0)) | |
038e51de | 1203 | goto done; |
038e51de | 1204 | } |
e4e03ded | 1205 | c->dst.orig_val = c->dst.val; |
038e51de | 1206 | |
e4e03ded | 1207 | if (c->twobyte) |
6aa8b732 AK |
1208 | goto twobyte_insn; |
1209 | ||
e4e03ded | 1210 | switch (c->b) { |
6aa8b732 AK |
1211 | case 0x00 ... 0x05: |
1212 | add: /* add */ | |
05f086f8 | 1213 | emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1214 | break; |
1215 | case 0x08 ... 0x0d: | |
1216 | or: /* or */ | |
05f086f8 | 1217 | emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1218 | break; |
1219 | case 0x10 ... 0x15: | |
1220 | adc: /* adc */ | |
05f086f8 | 1221 | emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1222 | break; |
1223 | case 0x18 ... 0x1d: | |
1224 | sbb: /* sbb */ | |
05f086f8 | 1225 | emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1226 | break; |
19eb938e | 1227 | case 0x20 ... 0x23: |
6aa8b732 | 1228 | and: /* and */ |
05f086f8 | 1229 | emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1230 | break; |
19eb938e | 1231 | case 0x24: /* and al imm8 */ |
e4e03ded LV |
1232 | c->dst.type = OP_REG; |
1233 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1234 | c->dst.val = *(u8 *)c->dst.ptr; | |
1235 | c->dst.bytes = 1; | |
1236 | c->dst.orig_val = c->dst.val; | |
19eb938e NK |
1237 | goto and; |
1238 | case 0x25: /* and ax imm16, or eax imm32 */ | |
e4e03ded LV |
1239 | c->dst.type = OP_REG; |
1240 | c->dst.bytes = c->op_bytes; | |
1241 | c->dst.ptr = &c->regs[VCPU_REGS_RAX]; | |
1242 | if (c->op_bytes == 2) | |
1243 | c->dst.val = *(u16 *)c->dst.ptr; | |
19eb938e | 1244 | else |
e4e03ded LV |
1245 | c->dst.val = *(u32 *)c->dst.ptr; |
1246 | c->dst.orig_val = c->dst.val; | |
19eb938e | 1247 | goto and; |
6aa8b732 AK |
1248 | case 0x28 ... 0x2d: |
1249 | sub: /* sub */ | |
05f086f8 | 1250 | emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1251 | break; |
1252 | case 0x30 ... 0x35: | |
1253 | xor: /* xor */ | |
05f086f8 | 1254 | emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1255 | break; |
1256 | case 0x38 ... 0x3d: | |
1257 | cmp: /* cmp */ | |
05f086f8 | 1258 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1259 | break; |
1260 | case 0x63: /* movsxd */ | |
8b4caf66 | 1261 | if (ctxt->mode != X86EMUL_MODE_PROT64) |
6aa8b732 | 1262 | goto cannot_emulate; |
e4e03ded | 1263 | c->dst.val = (s32) c->src.val; |
6aa8b732 AK |
1264 | break; |
1265 | case 0x80 ... 0x83: /* Grp1 */ | |
e4e03ded | 1266 | switch (c->modrm_reg) { |
6aa8b732 AK |
1267 | case 0: |
1268 | goto add; | |
1269 | case 1: | |
1270 | goto or; | |
1271 | case 2: | |
1272 | goto adc; | |
1273 | case 3: | |
1274 | goto sbb; | |
1275 | case 4: | |
1276 | goto and; | |
1277 | case 5: | |
1278 | goto sub; | |
1279 | case 6: | |
1280 | goto xor; | |
1281 | case 7: | |
1282 | goto cmp; | |
1283 | } | |
1284 | break; | |
1285 | case 0x84 ... 0x85: | |
05f086f8 | 1286 | emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags); |
6aa8b732 AK |
1287 | break; |
1288 | case 0x86 ... 0x87: /* xchg */ | |
1289 | /* Write back the register source. */ | |
e4e03ded | 1290 | switch (c->dst.bytes) { |
6aa8b732 | 1291 | case 1: |
e4e03ded | 1292 | *(u8 *) c->src.ptr = (u8) c->dst.val; |
6aa8b732 AK |
1293 | break; |
1294 | case 2: | |
e4e03ded | 1295 | *(u16 *) c->src.ptr = (u16) c->dst.val; |
6aa8b732 AK |
1296 | break; |
1297 | case 4: | |
e4e03ded | 1298 | *c->src.ptr = (u32) c->dst.val; |
6aa8b732 AK |
1299 | break; /* 64b reg: zero-extend */ |
1300 | case 8: | |
e4e03ded | 1301 | *c->src.ptr = c->dst.val; |
6aa8b732 AK |
1302 | break; |
1303 | } | |
1304 | /* | |
1305 | * Write back the memory destination with implicit LOCK | |
1306 | * prefix. | |
1307 | */ | |
e4e03ded LV |
1308 | c->dst.val = c->src.val; |
1309 | c->lock_prefix = 1; | |
6aa8b732 | 1310 | break; |
6aa8b732 | 1311 | case 0x88 ... 0x8b: /* mov */ |
7de75248 | 1312 | goto mov; |
7e0b54b1 | 1313 | case 0x8d: /* lea r16/r32, m */ |
e4e03ded | 1314 | c->dst.val = c->modrm_val; |
7e0b54b1 | 1315 | break; |
6aa8b732 | 1316 | case 0x8f: /* pop (sole member of Grp1a) */ |
8cdbd2c9 LV |
1317 | rc = emulate_grp1a(ctxt, ops); |
1318 | if (rc != 0) | |
6aa8b732 | 1319 | goto done; |
6aa8b732 | 1320 | break; |
7de75248 | 1321 | case 0xa0 ... 0xa1: /* mov */ |
e4e03ded LV |
1322 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; |
1323 | c->dst.val = c->src.val; | |
1324 | /* skip src displacement */ | |
1325 | c->eip += c->ad_bytes; | |
7de75248 NK |
1326 | break; |
1327 | case 0xa2 ... 0xa3: /* mov */ | |
e4e03ded LV |
1328 | c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX]; |
1329 | /* skip c->dst displacement */ | |
1330 | c->eip += c->ad_bytes; | |
7de75248 | 1331 | break; |
6aa8b732 | 1332 | case 0xc0 ... 0xc1: |
05f086f8 | 1333 | emulate_grp2(ctxt); |
6aa8b732 | 1334 | break; |
7de75248 NK |
1335 | case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */ |
1336 | mov: | |
e4e03ded | 1337 | c->dst.val = c->src.val; |
7de75248 | 1338 | break; |
6aa8b732 | 1339 | case 0xd0 ... 0xd1: /* Grp2 */ |
e4e03ded | 1340 | c->src.val = 1; |
05f086f8 | 1341 | emulate_grp2(ctxt); |
8cdbd2c9 | 1342 | break; |
6aa8b732 | 1343 | case 0xd2 ... 0xd3: /* Grp2 */ |
e4e03ded | 1344 | c->src.val = c->regs[VCPU_REGS_RCX]; |
05f086f8 | 1345 | emulate_grp2(ctxt); |
8cdbd2c9 | 1346 | break; |
6aa8b732 | 1347 | case 0xf6 ... 0xf7: /* Grp3 */ |
05f086f8 | 1348 | rc = emulate_grp3(ctxt, ops); |
8cdbd2c9 LV |
1349 | if (rc != 0) |
1350 | goto done; | |
6aa8b732 AK |
1351 | break; |
1352 | case 0xfe ... 0xff: /* Grp4/Grp5 */ | |
a01af5ec | 1353 | rc = emulate_grp45(ctxt, ops); |
8cdbd2c9 LV |
1354 | if (rc != 0) |
1355 | goto done; | |
6aa8b732 AK |
1356 | break; |
1357 | } | |
1358 | ||
1359 | writeback: | |
a01af5ec LV |
1360 | rc = writeback(ctxt, ops); |
1361 | if (rc != 0) | |
1362 | goto done; | |
6aa8b732 AK |
1363 | |
1364 | /* Commit shadow register state. */ | |
e4e03ded | 1365 | memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs); |
e4e03ded | 1366 | ctxt->vcpu->rip = c->eip; |
6aa8b732 AK |
1367 | |
1368 | done: | |
3427318f LV |
1369 | if (rc == X86EMUL_UNHANDLEABLE) { |
1370 | c->eip = saved_eip; | |
1371 | return -1; | |
1372 | } | |
1373 | return 0; | |
6aa8b732 AK |
1374 | |
1375 | special_insn: | |
e4e03ded | 1376 | if (c->twobyte) |
6aa8b732 | 1377 | goto twobyte_special_insn; |
e4e03ded | 1378 | switch (c->b) { |
7e778161 | 1379 | case 0x50 ... 0x57: /* push reg */ |
e4e03ded LV |
1380 | if (c->op_bytes == 2) |
1381 | c->src.val = (u16) c->regs[c->b & 0x7]; | |
7e778161 | 1382 | else |
e4e03ded LV |
1383 | c->src.val = (u32) c->regs[c->b & 0x7]; |
1384 | c->dst.type = OP_MEM; | |
1385 | c->dst.bytes = c->op_bytes; | |
1386 | c->dst.val = c->src.val; | |
1387 | register_address_increment(c->regs[VCPU_REGS_RSP], | |
1388 | -c->op_bytes); | |
1389 | c->dst.ptr = (void *) register_address( | |
1390 | ctxt->ss_base, c->regs[VCPU_REGS_RSP]); | |
7e778161 | 1391 | break; |
7de75248 | 1392 | case 0x58 ... 0x5f: /* pop reg */ |
8cdbd2c9 | 1393 | c->dst.ptr = (unsigned long *)&c->regs[c->b & 0x7]; |
7de75248 NK |
1394 | pop_instruction: |
1395 | if ((rc = ops->read_std(register_address(ctxt->ss_base, | |
e4e03ded LV |
1396 | c->regs[VCPU_REGS_RSP]), c->dst.ptr, |
1397 | c->op_bytes, ctxt->vcpu)) != 0) | |
7de75248 NK |
1398 | goto done; |
1399 | ||
e4e03ded LV |
1400 | register_address_increment(c->regs[VCPU_REGS_RSP], |
1401 | c->op_bytes); | |
a01af5ec | 1402 | c->dst.type = OP_NONE; /* Disable writeback. */ |
7de75248 | 1403 | break; |
1e35d3c4 | 1404 | case 0x6a: /* push imm8 */ |
e4e03ded LV |
1405 | c->src.val = 0L; |
1406 | c->src.val = insn_fetch(s8, 1, c->eip); | |
8cdbd2c9 | 1407 | emulate_push(ctxt); |
1e35d3c4 | 1408 | break; |
e70669ab LV |
1409 | case 0x6c: /* insb */ |
1410 | case 0x6d: /* insw/insd */ | |
3090dd73 | 1411 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, |
e4e03ded LV |
1412 | 1, |
1413 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1414 | c->rep_prefix ? | |
1415 | address_mask(c->regs[VCPU_REGS_RCX]) : 1, | |
05f086f8 | 1416 | (ctxt->eflags & EFLG_DF), |
e70669ab | 1417 | register_address(ctxt->es_base, |
e4e03ded LV |
1418 | c->regs[VCPU_REGS_RDI]), |
1419 | c->rep_prefix, | |
3427318f LV |
1420 | c->regs[VCPU_REGS_RDX]) == 0) { |
1421 | c->eip = saved_eip; | |
e70669ab | 1422 | return -1; |
3427318f | 1423 | } |
e70669ab LV |
1424 | return 0; |
1425 | case 0x6e: /* outsb */ | |
1426 | case 0x6f: /* outsw/outsd */ | |
3090dd73 | 1427 | if (kvm_emulate_pio_string(ctxt->vcpu, NULL, |
e4e03ded LV |
1428 | 0, |
1429 | (c->d & ByteOp) ? 1 : c->op_bytes, | |
1430 | c->rep_prefix ? | |
1431 | address_mask(c->regs[VCPU_REGS_RCX]) : 1, | |
05f086f8 | 1432 | (ctxt->eflags & EFLG_DF), |
e4e03ded LV |
1433 | register_address(c->override_base ? |
1434 | *c->override_base : | |
1435 | ctxt->ds_base, | |
1436 | c->regs[VCPU_REGS_RSI]), | |
1437 | c->rep_prefix, | |
3427318f LV |
1438 | c->regs[VCPU_REGS_RDX]) == 0) { |
1439 | c->eip = saved_eip; | |
e70669ab | 1440 | return -1; |
3427318f | 1441 | } |
e70669ab | 1442 | return 0; |
55bebde4 | 1443 | case 0x70 ... 0x7f: /* jcc (short) */ { |
e4e03ded | 1444 | int rel = insn_fetch(s8, 1, c->eip); |
55bebde4 | 1445 | |
05f086f8 | 1446 | if (test_cc(c->b, ctxt->eflags)) |
55bebde4 NK |
1447 | JMP_REL(rel); |
1448 | break; | |
1449 | } | |
fd2a7608 | 1450 | case 0x9c: /* pushf */ |
05f086f8 | 1451 | c->src.val = (unsigned long) ctxt->eflags; |
8cdbd2c9 LV |
1452 | emulate_push(ctxt); |
1453 | break; | |
535eabcf | 1454 | case 0x9d: /* popf */ |
05f086f8 | 1455 | c->dst.ptr = (unsigned long *) &ctxt->eflags; |
535eabcf | 1456 | goto pop_instruction; |
7de75248 | 1457 | case 0xc3: /* ret */ |
e4e03ded | 1458 | c->dst.ptr = &c->eip; |
7de75248 NK |
1459 | goto pop_instruction; |
1460 | case 0xf4: /* hlt */ | |
1461 | ctxt->vcpu->halt_request = 1; | |
1462 | goto done; | |
e70669ab | 1463 | } |
e4e03ded LV |
1464 | if (c->rep_prefix) { |
1465 | if (c->regs[VCPU_REGS_RCX] == 0) { | |
1466 | ctxt->vcpu->rip = c->eip; | |
6aa8b732 AK |
1467 | goto done; |
1468 | } | |
e4e03ded LV |
1469 | c->regs[VCPU_REGS_RCX]--; |
1470 | c->eip = ctxt->vcpu->rip; | |
6aa8b732 | 1471 | } |
e4e03ded | 1472 | switch (c->b) { |
6aa8b732 | 1473 | case 0xa4 ... 0xa5: /* movs */ |
e4e03ded LV |
1474 | c->dst.type = OP_MEM; |
1475 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1476 | c->dst.ptr = (unsigned long *)register_address( | |
1477 | ctxt->es_base, | |
1478 | c->regs[VCPU_REGS_RDI]); | |
6aa8b732 | 1479 | if ((rc = ops->read_emulated(register_address( |
e4e03ded LV |
1480 | c->override_base ? *c->override_base : |
1481 | ctxt->ds_base, | |
1482 | c->regs[VCPU_REGS_RSI]), | |
1483 | &c->dst.val, | |
1484 | c->dst.bytes, ctxt->vcpu)) != 0) | |
6aa8b732 | 1485 | goto done; |
e4e03ded | 1486 | register_address_increment(c->regs[VCPU_REGS_RSI], |
05f086f8 | 1487 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded LV |
1488 | : c->dst.bytes); |
1489 | register_address_increment(c->regs[VCPU_REGS_RDI], | |
05f086f8 | 1490 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1491 | : c->dst.bytes); |
6aa8b732 AK |
1492 | break; |
1493 | case 0xa6 ... 0xa7: /* cmps */ | |
1494 | DPRINTF("Urk! I don't handle CMPS.\n"); | |
1495 | goto cannot_emulate; | |
1496 | case 0xaa ... 0xab: /* stos */ | |
e4e03ded LV |
1497 | c->dst.type = OP_MEM; |
1498 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1499 | c->dst.ptr = (unsigned long *)cr2; | |
1500 | c->dst.val = c->regs[VCPU_REGS_RAX]; | |
1501 | register_address_increment(c->regs[VCPU_REGS_RDI], | |
05f086f8 | 1502 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1503 | : c->dst.bytes); |
6aa8b732 AK |
1504 | break; |
1505 | case 0xac ... 0xad: /* lods */ | |
e4e03ded LV |
1506 | c->dst.type = OP_REG; |
1507 | c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes; | |
1508 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
1509 | if ((rc = ops->read_emulated(cr2, &c->dst.val, | |
1510 | c->dst.bytes, | |
cebff02b | 1511 | ctxt->vcpu)) != 0) |
6aa8b732 | 1512 | goto done; |
e4e03ded | 1513 | register_address_increment(c->regs[VCPU_REGS_RSI], |
05f086f8 | 1514 | (ctxt->eflags & EFLG_DF) ? -c->dst.bytes |
e4e03ded | 1515 | : c->dst.bytes); |
6aa8b732 AK |
1516 | break; |
1517 | case 0xae ... 0xaf: /* scas */ | |
1518 | DPRINTF("Urk! I don't handle SCAS.\n"); | |
1519 | goto cannot_emulate; | |
1a52e051 NK |
1520 | case 0xe8: /* call (near) */ { |
1521 | long int rel; | |
e4e03ded | 1522 | switch (c->op_bytes) { |
1a52e051 | 1523 | case 2: |
e4e03ded | 1524 | rel = insn_fetch(s16, 2, c->eip); |
1a52e051 NK |
1525 | break; |
1526 | case 4: | |
e4e03ded | 1527 | rel = insn_fetch(s32, 4, c->eip); |
1a52e051 NK |
1528 | break; |
1529 | case 8: | |
e4e03ded | 1530 | rel = insn_fetch(s64, 8, c->eip); |
1a52e051 NK |
1531 | break; |
1532 | default: | |
1533 | DPRINTF("Call: Invalid op_bytes\n"); | |
1534 | goto cannot_emulate; | |
1535 | } | |
e4e03ded | 1536 | c->src.val = (unsigned long) c->eip; |
1a52e051 | 1537 | JMP_REL(rel); |
e4e03ded | 1538 | c->op_bytes = c->ad_bytes; |
8cdbd2c9 LV |
1539 | emulate_push(ctxt); |
1540 | break; | |
1a52e051 NK |
1541 | } |
1542 | case 0xe9: /* jmp rel */ | |
1543 | case 0xeb: /* jmp rel short */ | |
e4e03ded | 1544 | JMP_REL(c->src.val); |
a01af5ec | 1545 | c->dst.type = OP_NONE; /* Disable writeback. */ |
1a52e051 NK |
1546 | break; |
1547 | ||
7f0aaee0 | 1548 | |
6aa8b732 AK |
1549 | } |
1550 | goto writeback; | |
1551 | ||
1552 | twobyte_insn: | |
e4e03ded | 1553 | switch (c->b) { |
6aa8b732 | 1554 | case 0x01: /* lgdt, lidt, lmsw */ |
e4e03ded | 1555 | switch (c->modrm_reg) { |
6aa8b732 AK |
1556 | u16 size; |
1557 | unsigned long address; | |
1558 | ||
aca7f966 | 1559 | case 0: /* vmcall */ |
e4e03ded | 1560 | if (c->modrm_mod != 3 || c->modrm_rm != 1) |
aca7f966 AL |
1561 | goto cannot_emulate; |
1562 | ||
7aa81cc0 AL |
1563 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1564 | if (rc) | |
1565 | goto done; | |
1566 | ||
1567 | kvm_emulate_hypercall(ctxt->vcpu); | |
aca7f966 | 1568 | break; |
6aa8b732 | 1569 | case 2: /* lgdt */ |
e4e03ded LV |
1570 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
1571 | &size, &address, c->op_bytes); | |
6aa8b732 AK |
1572 | if (rc) |
1573 | goto done; | |
1574 | realmode_lgdt(ctxt->vcpu, size, address); | |
1575 | break; | |
aca7f966 | 1576 | case 3: /* lidt/vmmcall */ |
e4e03ded | 1577 | if (c->modrm_mod == 3 && c->modrm_rm == 1) { |
7aa81cc0 AL |
1578 | rc = kvm_fix_hypercall(ctxt->vcpu); |
1579 | if (rc) | |
1580 | goto done; | |
1581 | kvm_emulate_hypercall(ctxt->vcpu); | |
aca7f966 | 1582 | } else { |
e4e03ded | 1583 | rc = read_descriptor(ctxt, ops, c->src.ptr, |
aca7f966 | 1584 | &size, &address, |
e4e03ded | 1585 | c->op_bytes); |
aca7f966 AL |
1586 | if (rc) |
1587 | goto done; | |
1588 | realmode_lidt(ctxt->vcpu, size, address); | |
1589 | } | |
6aa8b732 AK |
1590 | break; |
1591 | case 4: /* smsw */ | |
e4e03ded | 1592 | if (c->modrm_mod != 3) |
6aa8b732 | 1593 | goto cannot_emulate; |
e4e03ded | 1594 | *(u16 *)&c->regs[c->modrm_rm] |
6aa8b732 AK |
1595 | = realmode_get_cr(ctxt->vcpu, 0); |
1596 | break; | |
1597 | case 6: /* lmsw */ | |
e4e03ded | 1598 | if (c->modrm_mod != 3) |
6aa8b732 | 1599 | goto cannot_emulate; |
05f086f8 LV |
1600 | realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val, |
1601 | &ctxt->eflags); | |
6aa8b732 AK |
1602 | break; |
1603 | case 7: /* invlpg*/ | |
1604 | emulate_invlpg(ctxt->vcpu, cr2); | |
1605 | break; | |
1606 | default: | |
1607 | goto cannot_emulate; | |
1608 | } | |
a01af5ec LV |
1609 | /* Disable writeback. */ |
1610 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
1611 | break; |
1612 | case 0x21: /* mov from dr to reg */ | |
e4e03ded | 1613 | if (c->modrm_mod != 3) |
6aa8b732 | 1614 | goto cannot_emulate; |
8cdbd2c9 | 1615 | rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]); |
a01af5ec LV |
1616 | if (rc) |
1617 | goto cannot_emulate; | |
1618 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 AK |
1619 | break; |
1620 | case 0x23: /* mov from reg to dr */ | |
e4e03ded | 1621 | if (c->modrm_mod != 3) |
6aa8b732 | 1622 | goto cannot_emulate; |
e4e03ded LV |
1623 | rc = emulator_set_dr(ctxt, c->modrm_reg, |
1624 | c->regs[c->modrm_rm]); | |
a01af5ec LV |
1625 | if (rc) |
1626 | goto cannot_emulate; | |
1627 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 AK |
1628 | break; |
1629 | case 0x40 ... 0x4f: /* cmov */ | |
e4e03ded | 1630 | c->dst.val = c->dst.orig_val = c->src.val; |
a01af5ec LV |
1631 | if (!test_cc(c->b, ctxt->eflags)) |
1632 | c->dst.type = OP_NONE; /* no writeback */ | |
6aa8b732 | 1633 | break; |
7de75248 NK |
1634 | case 0xa3: |
1635 | bt: /* bt */ | |
e4f8e039 | 1636 | c->dst.type = OP_NONE; |
e4e03ded LV |
1637 | /* only subword offset */ |
1638 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1639 | emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags); |
7de75248 NK |
1640 | break; |
1641 | case 0xab: | |
1642 | bts: /* bts */ | |
e4e03ded LV |
1643 | /* only subword offset */ |
1644 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1645 | emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags); |
7de75248 | 1646 | break; |
6aa8b732 AK |
1647 | case 0xb0 ... 0xb1: /* cmpxchg */ |
1648 | /* | |
1649 | * Save real source value, then compare EAX against | |
1650 | * destination. | |
1651 | */ | |
e4e03ded LV |
1652 | c->src.orig_val = c->src.val; |
1653 | c->src.val = c->regs[VCPU_REGS_RAX]; | |
05f086f8 LV |
1654 | emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags); |
1655 | if (ctxt->eflags & EFLG_ZF) { | |
6aa8b732 | 1656 | /* Success: write back to memory. */ |
e4e03ded | 1657 | c->dst.val = c->src.orig_val; |
6aa8b732 AK |
1658 | } else { |
1659 | /* Failure: write the value we saw to EAX. */ | |
e4e03ded LV |
1660 | c->dst.type = OP_REG; |
1661 | c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX]; | |
6aa8b732 AK |
1662 | } |
1663 | break; | |
6aa8b732 AK |
1664 | case 0xb3: |
1665 | btr: /* btr */ | |
e4e03ded LV |
1666 | /* only subword offset */ |
1667 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1668 | emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags); |
6aa8b732 | 1669 | break; |
6aa8b732 | 1670 | case 0xb6 ... 0xb7: /* movzx */ |
e4e03ded LV |
1671 | c->dst.bytes = c->op_bytes; |
1672 | c->dst.val = (c->d & ByteOp) ? (u8) c->src.val | |
1673 | : (u16) c->src.val; | |
6aa8b732 | 1674 | break; |
6aa8b732 | 1675 | case 0xba: /* Grp8 */ |
e4e03ded | 1676 | switch (c->modrm_reg & 3) { |
6aa8b732 AK |
1677 | case 0: |
1678 | goto bt; | |
1679 | case 1: | |
1680 | goto bts; | |
1681 | case 2: | |
1682 | goto btr; | |
1683 | case 3: | |
1684 | goto btc; | |
1685 | } | |
1686 | break; | |
7de75248 NK |
1687 | case 0xbb: |
1688 | btc: /* btc */ | |
e4e03ded LV |
1689 | /* only subword offset */ |
1690 | c->src.val &= (c->dst.bytes << 3) - 1; | |
05f086f8 | 1691 | emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags); |
7de75248 | 1692 | break; |
6aa8b732 | 1693 | case 0xbe ... 0xbf: /* movsx */ |
e4e03ded LV |
1694 | c->dst.bytes = c->op_bytes; |
1695 | c->dst.val = (c->d & ByteOp) ? (s8) c->src.val : | |
1696 | (s16) c->src.val; | |
6aa8b732 | 1697 | break; |
a012e65a | 1698 | case 0xc3: /* movnti */ |
e4e03ded LV |
1699 | c->dst.bytes = c->op_bytes; |
1700 | c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val : | |
1701 | (u64) c->src.val; | |
a012e65a | 1702 | break; |
6aa8b732 AK |
1703 | } |
1704 | goto writeback; | |
1705 | ||
1706 | twobyte_special_insn: | |
e4e03ded | 1707 | switch (c->b) { |
7de75248 NK |
1708 | case 0x06: |
1709 | emulate_clts(ctxt->vcpu); | |
1710 | break; | |
651a3e29 AK |
1711 | case 0x08: /* invd */ |
1712 | break; | |
687fdbfe AK |
1713 | case 0x09: /* wbinvd */ |
1714 | break; | |
6aa8b732 AK |
1715 | case 0x0d: /* GrpP (prefetch) */ |
1716 | case 0x18: /* Grp16 (prefetch/nop) */ | |
1717 | break; | |
6aa8b732 | 1718 | case 0x20: /* mov cr, reg */ |
e4e03ded | 1719 | if (c->modrm_mod != 3) |
6aa8b732 | 1720 | goto cannot_emulate; |
e4e03ded LV |
1721 | c->regs[c->modrm_rm] = |
1722 | realmode_get_cr(ctxt->vcpu, c->modrm_reg); | |
6aa8b732 AK |
1723 | break; |
1724 | case 0x22: /* mov reg, cr */ | |
e4e03ded | 1725 | if (c->modrm_mod != 3) |
6aa8b732 | 1726 | goto cannot_emulate; |
e4e03ded | 1727 | realmode_set_cr(ctxt->vcpu, |
05f086f8 | 1728 | c->modrm_reg, c->modrm_val, &ctxt->eflags); |
6aa8b732 | 1729 | break; |
35f3f286 AK |
1730 | case 0x30: |
1731 | /* wrmsr */ | |
e4e03ded LV |
1732 | msr_data = (u32)c->regs[VCPU_REGS_RAX] |
1733 | | ((u64)c->regs[VCPU_REGS_RDX] << 32); | |
1734 | rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data); | |
35f3f286 | 1735 | if (rc) { |
cbdd1bea | 1736 | kvm_x86_ops->inject_gp(ctxt->vcpu, 0); |
e4e03ded | 1737 | c->eip = ctxt->vcpu->rip; |
35f3f286 AK |
1738 | } |
1739 | rc = X86EMUL_CONTINUE; | |
1740 | break; | |
1741 | case 0x32: | |
1742 | /* rdmsr */ | |
8cdbd2c9 | 1743 | rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data); |
35f3f286 | 1744 | if (rc) { |
cbdd1bea | 1745 | kvm_x86_ops->inject_gp(ctxt->vcpu, 0); |
e4e03ded | 1746 | c->eip = ctxt->vcpu->rip; |
35f3f286 | 1747 | } else { |
e4e03ded LV |
1748 | c->regs[VCPU_REGS_RAX] = (u32)msr_data; |
1749 | c->regs[VCPU_REGS_RDX] = msr_data >> 32; | |
35f3f286 AK |
1750 | } |
1751 | rc = X86EMUL_CONTINUE; | |
1752 | break; | |
bbe9abbd NK |
1753 | case 0x80 ... 0x8f: /* jnz rel, etc*/ { |
1754 | long int rel; | |
1755 | ||
e4e03ded | 1756 | switch (c->op_bytes) { |
bbe9abbd | 1757 | case 2: |
e4e03ded | 1758 | rel = insn_fetch(s16, 2, c->eip); |
bbe9abbd NK |
1759 | break; |
1760 | case 4: | |
e4e03ded | 1761 | rel = insn_fetch(s32, 4, c->eip); |
bbe9abbd NK |
1762 | break; |
1763 | case 8: | |
e4e03ded | 1764 | rel = insn_fetch(s64, 8, c->eip); |
bbe9abbd NK |
1765 | break; |
1766 | default: | |
1767 | DPRINTF("jnz: Invalid op_bytes\n"); | |
1768 | goto cannot_emulate; | |
1769 | } | |
05f086f8 | 1770 | if (test_cc(c->b, ctxt->eflags)) |
bbe9abbd NK |
1771 | JMP_REL(rel); |
1772 | break; | |
1773 | } | |
6aa8b732 | 1774 | case 0xc7: /* Grp9 (cmpxchg8b) */ |
05f086f8 | 1775 | rc = emulate_grp9(ctxt, ops, cr2); |
8cdbd2c9 LV |
1776 | if (rc != 0) |
1777 | goto done; | |
1778 | break; | |
6aa8b732 | 1779 | } |
a01af5ec LV |
1780 | /* Disable writeback. */ |
1781 | c->dst.type = OP_NONE; | |
6aa8b732 AK |
1782 | goto writeback; |
1783 | ||
1784 | cannot_emulate: | |
e4e03ded | 1785 | DPRINTF("Cannot emulate %02x\n", c->b); |
3427318f | 1786 | c->eip = saved_eip; |
6aa8b732 AK |
1787 | return -1; |
1788 | } |