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KVM: VMX: Force vm86 mode if setting flags during real mode
[mirror_ubuntu-bionic-kernel.git] / drivers / kvm / x86_emulate.c
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6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
26#define DPRINTF(_f, _a ...) printf( _f , ## _a )
27#else
28#include "kvm.h"
29#define DPRINTF(x...) do {} while (0)
30#endif
31#include "x86_emulate.h"
32#include <linux/module.h>
33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
6aa8b732
AK		 65
66static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 86 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7f0aaee0 101 /* 0x50 - 0x57 */
7e778161
NK		 102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7f0aaee0
NK		 104 /* 0x58 - 0x5F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7d316911 107 /* 0x60 - 0x67 */
6aa8b732 108 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 109 0, 0, 0, 0,
110 /* 0x68 - 0x6F */
111 0, 0, ImplicitOps|Mov, 0,
e70669ab
LV		 112 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
113 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 114 /* 0x70 - 0x77 */
115 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 /* 0x78 - 0x7F */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 120 /* 0x80 - 0x87 */
121 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
122 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 /* 0x88 - 0x8F */
126 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
127 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
7e0b54b1 128 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
6aa8b732 129 /* 0x90 - 0x9F */
535eabcf 130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
6aa8b732
AK		 131 /* 0xA0 - 0xA7 */
132 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
133 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
134 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
135 ByteOp | ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
138 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
139 ByteOp | ImplicitOps, ImplicitOps,
140 /* 0xB0 - 0xBF */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xC0 - 0xC7 */
d9413cd7
NK		 143 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
144 0, ImplicitOps, 0, 0,
145 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 146 /* 0xC8 - 0xCF */
147 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xD0 - 0xD7 */
149 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
150 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
151 0, 0, 0, 0,
152 /* 0xD8 - 0xDF */
153 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 154 /* 0xE0 - 0xE7 */
155 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xE8 - 0xEF */
f6eed391 157 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
6aa8b732
AK		 158 /* 0xF0 - 0xF7 */
159 0, 0, 0, 0,
72d6e5a0
AK		 160 ImplicitOps, 0,
161 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
6aa8b732
AK		 162 /* 0xF8 - 0xFF */
163 0, 0, 0, 0,
164 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
165};
166
038e51de 167static u16 twobyte_table[256] = {
6aa8b732
AK		 168 /* 0x00 - 0x0F */
169 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
687fdbfe 170 0, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 171 /* 0x10 - 0x1F */
172 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x20 - 0x2F */
174 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
175 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x30 - 0x3F */
35f3f286 177 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 178 /* 0x40 - 0x47 */
179 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
180 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
181 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 /* 0x48 - 0x4F */
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 /* 0x50 - 0x5F */
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x60 - 0x6F */
191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x70 - 0x7F */
193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x80 - 0x8F */
bbe9abbd
NK		 195 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
196 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
197 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 199 /* 0x90 - 0x9F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xA0 - 0xA7 */
038e51de 202 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 203 /* 0xA8 - 0xAF */
038e51de 204 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 205 /* 0xB0 - 0xB7 */
206 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 207 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 208 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem16 | ModRM | Mov,
210 /* 0xB8 - 0xBF */
038e51de 211 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 212 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem16 | ModRM | Mov,
214 /* 0xC0 - 0xCF */
a012e65a
SY		 215 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
216 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 217 /* 0xD0 - 0xDF */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xE0 - 0xEF */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0xF0 - 0xFF */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
223};
224
6aa8b732
AK		 225/* Type, address-of, and value of an instruction's operand. */
226struct operand {
227 enum { OP_REG, OP_MEM, OP_IMM } type;
228 unsigned int bytes;
229 unsigned long val, orig_val, *ptr;
230};
231
232/* EFLAGS bit definitions. */
233#define EFLG_OF (1<<11)
234#define EFLG_DF (1<<10)
235#define EFLG_SF (1<<7)
236#define EFLG_ZF (1<<6)
237#define EFLG_AF (1<<4)
238#define EFLG_PF (1<<2)
239#define EFLG_CF (1<<0)
240
241/*
242 * Instruction emulation:
243 * Most instructions are emulated directly via a fragment of inline assembly
244 * code. This allows us to save/restore EFLAGS and thus very easily pick up
245 * any modified flags.
246 */
247
05b3e0c2 248#if defined(CONFIG_X86_64)
6aa8b732
AK		 249#define _LO32 "k" /* force 32-bit operand */
250#define _STK "%%rsp" /* stack pointer */
251#elif defined(__i386__)
252#define _LO32 "" /* force 32-bit operand */
253#define _STK "%%esp" /* stack pointer */
254#endif
255
256/*
257 * These EFLAGS bits are restored from saved value during emulation, and
258 * any changes are written back to the saved value after emulation.
259 */
260#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
261
262/* Before executing instruction: restore necessary bits in EFLAGS. */
263#define _PRE_EFLAGS(_sav, _msk, _tmp) \
264 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
265 "push %"_sav"; " \
266 "movl %"_msk",%"_LO32 _tmp"; " \
267 "andl %"_LO32 _tmp",("_STK"); " \
268 "pushf; " \
269 "notl %"_LO32 _tmp"; " \
270 "andl %"_LO32 _tmp",("_STK"); " \
271 "pop %"_tmp"; " \
272 "orl %"_LO32 _tmp",("_STK"); " \
273 "popf; " \
274 /* _sav &= ~msk; */ \
275 "movl %"_msk",%"_LO32 _tmp"; " \
276 "notl %"_LO32 _tmp"; " \
277 "andl %"_LO32 _tmp",%"_sav"; "
278
279/* After executing instruction: write-back necessary bits in EFLAGS. */
280#define _POST_EFLAGS(_sav, _msk, _tmp) \
281 /* _sav |= EFLAGS & _msk; */ \
282 "pushf; " \
283 "pop %"_tmp"; " \
284 "andl %"_msk",%"_LO32 _tmp"; " \
285 "orl %"_LO32 _tmp",%"_sav"; "
286
287/* Raw emulation: instruction has two explicit operands. */
288#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
289 do { \
290 unsigned long _tmp; \
291 \
292 switch ((_dst).bytes) { \
293 case 2: \
294 __asm__ __volatile__ ( \
295 _PRE_EFLAGS("0","4","2") \
296 _op"w %"_wx"3,%1; " \
297 _POST_EFLAGS("0","4","2") \
298 : "=m" (_eflags), "=m" ((_dst).val), \
299 "=&r" (_tmp) \
300 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
301 break; \
302 case 4: \
303 __asm__ __volatile__ ( \
304 _PRE_EFLAGS("0","4","2") \
305 _op"l %"_lx"3,%1; " \
306 _POST_EFLAGS("0","4","2") \
307 : "=m" (_eflags), "=m" ((_dst).val), \
308 "=&r" (_tmp) \
309 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
310 break; \
311 case 8: \
312 __emulate_2op_8byte(_op, _src, _dst, \
313 _eflags, _qx, _qy); \
314 break; \
315 } \
316 } while (0)
317
318#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
319 do { \
320 unsigned long _tmp; \
321 switch ( (_dst).bytes ) \
322 { \
323 case 1: \
324 __asm__ __volatile__ ( \
325 _PRE_EFLAGS("0","4","2") \
326 _op"b %"_bx"3,%1; " \
327 _POST_EFLAGS("0","4","2") \
328 : "=m" (_eflags), "=m" ((_dst).val), \
329 "=&r" (_tmp) \
330 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
331 break; \
332 default: \
333 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
334 _wx, _wy, _lx, _ly, _qx, _qy); \
335 break; \
336 } \
337 } while (0)
338
339/* Source operand is byte-sized and may be restricted to just %cl. */
340#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
341 __emulate_2op(_op, _src, _dst, _eflags, \
342 "b", "c", "b", "c", "b", "c", "b", "c")
343
344/* Source operand is byte, word, long or quad sized. */
345#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
346 __emulate_2op(_op, _src, _dst, _eflags, \
347 "b", "q", "w", "r", _LO32, "r", "", "r")
348
349/* Source operand is word, long or quad sized. */
350#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
351 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
352 "w", "r", _LO32, "r", "", "r")
353
354/* Instruction has only one explicit operand (no source operand). */
355#define emulate_1op(_op, _dst, _eflags) \
356 do { \
357 unsigned long _tmp; \
358 \
359 switch ( (_dst).bytes ) \
360 { \
361 case 1: \
362 __asm__ __volatile__ ( \
363 _PRE_EFLAGS("0","3","2") \
364 _op"b %1; " \
365 _POST_EFLAGS("0","3","2") \
366 : "=m" (_eflags), "=m" ((_dst).val), \
367 "=&r" (_tmp) \
368 : "i" (EFLAGS_MASK) ); \
369 break; \
370 case 2: \
371 __asm__ __volatile__ ( \
372 _PRE_EFLAGS("0","3","2") \
373 _op"w %1; " \
374 _POST_EFLAGS("0","3","2") \
375 : "=m" (_eflags), "=m" ((_dst).val), \
376 "=&r" (_tmp) \
377 : "i" (EFLAGS_MASK) ); \
378 break; \
379 case 4: \
380 __asm__ __volatile__ ( \
381 _PRE_EFLAGS("0","3","2") \
382 _op"l %1; " \
383 _POST_EFLAGS("0","3","2") \
384 : "=m" (_eflags), "=m" ((_dst).val), \
385 "=&r" (_tmp) \
386 : "i" (EFLAGS_MASK) ); \
387 break; \
388 case 8: \
389 __emulate_1op_8byte(_op, _dst, _eflags); \
390 break; \
391 } \
392 } while (0)
393
394/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 395#if defined(CONFIG_X86_64)
6aa8b732
AK		 396#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
397 do { \
398 __asm__ __volatile__ ( \
399 _PRE_EFLAGS("0","4","2") \
400 _op"q %"_qx"3,%1; " \
401 _POST_EFLAGS("0","4","2") \
402 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
403 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
404 } while (0)
405
406#define __emulate_1op_8byte(_op, _dst, _eflags) \
407 do { \
408 __asm__ __volatile__ ( \
409 _PRE_EFLAGS("0","3","2") \
410 _op"q %1; " \
411 _POST_EFLAGS("0","3","2") \
412 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
413 : "i" (EFLAGS_MASK) ); \
414 } while (0)
415
416#elif defined(__i386__)
417#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
418#define __emulate_1op_8byte(_op, _dst, _eflags)
419#endif /* __i386__ */
420
421/* Fetch next part of the instruction being emulated. */
422#define insn_fetch(_type, _size, _eip) \
423({ unsigned long _x; \
424 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
cebff02b 425 (_size), ctxt->vcpu); \
6aa8b732
AK		 426 if ( rc != 0 ) \
427 goto done; \
428 (_eip) += (_size); \
429 (_type)_x; \
430})
431
432/* Access/update address held in a register, based on addressing mode. */
e70669ab
LV		 433#define address_mask(reg) \
434 ((ad_bytes == sizeof(unsigned long)) ? \
435 (reg) : ((reg) & ((1UL << (ad_bytes << 3)) - 1)))
6aa8b732 436#define register_address(base, reg) \
e70669ab 437 ((base) + address_mask(reg))
6aa8b732
AK		 438#define register_address_increment(reg, inc) \
439 do { \
440 /* signed type ensures sign extension to long */ \
441 int _inc = (inc); \
442 if ( ad_bytes == sizeof(unsigned long) ) \
443 (reg) += _inc; \
444 else \
445 (reg) = ((reg) & ~((1UL << (ad_bytes << 3)) - 1)) | \
446 (((reg) + _inc) & ((1UL << (ad_bytes << 3)) - 1)); \
447 } while (0)
448
098c937b
NK		 449#define JMP_REL(rel) \
450 do { \
451 _eip += (int)(rel); \
452 _eip = ((op_bytes == 2) ? (uint16_t)_eip : (uint32_t)_eip); \
453 } while (0)
454
1e3c5cb0
RR		 455/*
456 * Given the 'reg' portion of a ModRM byte, and a register block, return a
457 * pointer into the block that addresses the relevant register.
458 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
459 */
460static void *decode_register(u8 modrm_reg, unsigned long *regs,
461 int highbyte_regs)
6aa8b732
AK		 462{
463 void *p;
464
465 p = &regs[modrm_reg];
466 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
467 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
468 return p;
469}
470
471static int read_descriptor(struct x86_emulate_ctxt *ctxt,
472 struct x86_emulate_ops *ops,
473 void *ptr,
474 u16 *size, unsigned long *address, int op_bytes)
475{
476 int rc;
477
478 if (op_bytes == 2)
479 op_bytes = 3;
480 *address = 0;
cebff02b
LV		 481 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
482 ctxt->vcpu);
6aa8b732
AK		 483 if (rc)
484 return rc;
cebff02b
LV		 485 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
486 ctxt->vcpu);
6aa8b732
AK		 487 return rc;
488}
489
bbe9abbd
NK		 490static int test_cc(unsigned int condition, unsigned int flags)
491{
492 int rc = 0;
493
494 switch ((condition & 15) >> 1) {
495 case 0: /* o */
496 rc |= (flags & EFLG_OF);
497 break;
498 case 1: /* b/c/nae */
499 rc |= (flags & EFLG_CF);
500 break;
501 case 2: /* z/e */
502 rc |= (flags & EFLG_ZF);
503 break;
504 case 3: /* be/na */
505 rc |= (flags & (EFLG_CF|EFLG_ZF));
506 break;
507 case 4: /* s */
508 rc |= (flags & EFLG_SF);
509 break;
510 case 5: /* p/pe */
511 rc |= (flags & EFLG_PF);
512 break;
513 case 7: /* le/ng */
514 rc |= (flags & EFLG_ZF);
515 /* fall through */
516 case 6: /* l/nge */
517 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
518 break;
519 }
520
521 /* Odd condition identifiers (lsb == 1) have inverted sense. */
522 return (!!rc ^ (condition & 1));
523}
524
6aa8b732
AK		 525int
526x86_emulate_memop(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
527{
038e51de
AK		 528 unsigned d;
529 u8 b, sib, twobyte = 0, rex_prefix = 0;
6aa8b732
AK		 530 u8 modrm, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
531 unsigned long *override_base = NULL;
532 unsigned int op_bytes, ad_bytes, lock_prefix = 0, rep_prefix = 0, i;
533 int rc = 0;
534 struct operand src, dst;
535 unsigned long cr2 = ctxt->cr2;
536 int mode = ctxt->mode;
537 unsigned long modrm_ea;
538 int use_modrm_ea, index_reg = 0, base_reg = 0, scale, rip_relative = 0;
02c03a32 539 int no_wb = 0;
35f3f286 540 u64 msr_data;
6aa8b732
AK		 541
542 /* Shadow copy of register state. Committed on successful emulation. */
543 unsigned long _regs[NR_VCPU_REGS];
544 unsigned long _eip = ctxt->vcpu->rip, _eflags = ctxt->eflags;
545 unsigned long modrm_val = 0;
546
547 memcpy(_regs, ctxt->vcpu->regs, sizeof _regs);
548
549 switch (mode) {
550 case X86EMUL_MODE_REAL:
551 case X86EMUL_MODE_PROT16:
552 op_bytes = ad_bytes = 2;
553 break;
554 case X86EMUL_MODE_PROT32:
555 op_bytes = ad_bytes = 4;
556 break;
05b3e0c2 557#ifdef CONFIG_X86_64
6aa8b732
AK		 558 case X86EMUL_MODE_PROT64:
559 op_bytes = 4;
560 ad_bytes = 8;
561 break;
562#endif
563 default:
564 return -1;
565 }
566
567 /* Legacy prefixes. */
568 for (i = 0; i < 8; i++) {
569 switch (b = insn_fetch(u8, 1, _eip)) {
570 case 0x66: /* operand-size override */
571 op_bytes ^= 6; /* switch between 2/4 bytes */
572 break;
573 case 0x67: /* address-size override */
574 if (mode == X86EMUL_MODE_PROT64)
575 ad_bytes ^= 12; /* switch between 4/8 bytes */
576 else
577 ad_bytes ^= 6; /* switch between 2/4 bytes */
578 break;
579 case 0x2e: /* CS override */
580 override_base = &ctxt->cs_base;
581 break;
582 case 0x3e: /* DS override */
583 override_base = &ctxt->ds_base;
584 break;
585 case 0x26: /* ES override */
586 override_base = &ctxt->es_base;
587 break;
588 case 0x64: /* FS override */
589 override_base = &ctxt->fs_base;
590 break;
591 case 0x65: /* GS override */
592 override_base = &ctxt->gs_base;
593 break;
594 case 0x36: /* SS override */
595 override_base = &ctxt->ss_base;
596 break;
597 case 0xf0: /* LOCK */
598 lock_prefix = 1;
599 break;
ae6200ba 600 case 0xf2: /* REPNE/REPNZ */
6aa8b732
AK		 601 case 0xf3: /* REP/REPE/REPZ */
602 rep_prefix = 1;
603 break;
6aa8b732
AK		 604 default:
605 goto done_prefixes;
606 }
607 }
608
609done_prefixes:
610
611 /* REX prefix. */
612 if ((mode == X86EMUL_MODE_PROT64) && ((b & 0xf0) == 0x40)) {
613 rex_prefix = b;
614 if (b & 8)
615 op_bytes = 8; /* REX.W */
616 modrm_reg = (b & 4) << 1; /* REX.R */
617 index_reg = (b & 2) << 2; /* REX.X */
618 modrm_rm = base_reg = (b & 1) << 3; /* REG.B */
619 b = insn_fetch(u8, 1, _eip);
620 }
621
622 /* Opcode byte(s). */
623 d = opcode_table[b];
624 if (d == 0) {
625 /* Two-byte opcode? */
626 if (b == 0x0f) {
627 twobyte = 1;
628 b = insn_fetch(u8, 1, _eip);
629 d = twobyte_table[b];
630 }
631
632 /* Unrecognised? */
633 if (d == 0)
634 goto cannot_emulate;
635 }
636
637 /* ModRM and SIB bytes. */
638 if (d & ModRM) {
639 modrm = insn_fetch(u8, 1, _eip);
640 modrm_mod |= (modrm & 0xc0) >> 6;
641 modrm_reg |= (modrm & 0x38) >> 3;
642 modrm_rm |= (modrm & 0x07);
643 modrm_ea = 0;
644 use_modrm_ea = 1;
645
646 if (modrm_mod == 3) {
647 modrm_val = *(unsigned long *)
648 decode_register(modrm_rm, _regs, d & ByteOp);
649 goto modrm_done;
650 }
651
652 if (ad_bytes == 2) {
653 unsigned bx = _regs[VCPU_REGS_RBX];
654 unsigned bp = _regs[VCPU_REGS_RBP];
655 unsigned si = _regs[VCPU_REGS_RSI];
656 unsigned di = _regs[VCPU_REGS_RDI];
657
658 /* 16-bit ModR/M decode. */
659 switch (modrm_mod) {
660 case 0:
661 if (modrm_rm == 6)
662 modrm_ea += insn_fetch(u16, 2, _eip);
663 break;
664 case 1:
665 modrm_ea += insn_fetch(s8, 1, _eip);
666 break;
667 case 2:
668 modrm_ea += insn_fetch(u16, 2, _eip);
669 break;
670 }
671 switch (modrm_rm) {
672 case 0:
673 modrm_ea += bx + si;
674 break;
675 case 1:
676 modrm_ea += bx + di;
677 break;
678 case 2:
679 modrm_ea += bp + si;
680 break;
681 case 3:
682 modrm_ea += bp + di;
683 break;
684 case 4:
685 modrm_ea += si;
686 break;
687 case 5:
688 modrm_ea += di;
689 break;
690 case 6:
691 if (modrm_mod != 0)
692 modrm_ea += bp;
693 break;
694 case 7:
695 modrm_ea += bx;
696 break;
697 }
698 if (modrm_rm == 2 || modrm_rm == 3 ||
699 (modrm_rm == 6 && modrm_mod != 0))
700 if (!override_base)
701 override_base = &ctxt->ss_base;
702 modrm_ea = (u16)modrm_ea;
703 } else {
704 /* 32/64-bit ModR/M decode. */
705 switch (modrm_rm) {
706 case 4:
707 case 12:
708 sib = insn_fetch(u8, 1, _eip);
709 index_reg |= (sib >> 3) & 7;
710 base_reg |= sib & 7;
711 scale = sib >> 6;
712
713 switch (base_reg) {
714 case 5:
715 if (modrm_mod != 0)
716 modrm_ea += _regs[base_reg];
717 else
718 modrm_ea += insn_fetch(s32, 4, _eip);
719 break;
720 default:
721 modrm_ea += _regs[base_reg];
722 }
723 switch (index_reg) {
724 case 4:
725 break;
726 default:
727 modrm_ea += _regs[index_reg] << scale;
728
729 }
730 break;
731 case 5:
732 if (modrm_mod != 0)
733 modrm_ea += _regs[modrm_rm];
734 else if (mode == X86EMUL_MODE_PROT64)
735 rip_relative = 1;
736 break;
737 default:
738 modrm_ea += _regs[modrm_rm];
739 break;
740 }
741 switch (modrm_mod) {
742 case 0:
743 if (modrm_rm == 5)
744 modrm_ea += insn_fetch(s32, 4, _eip);
745 break;
746 case 1:
747 modrm_ea += insn_fetch(s8, 1, _eip);
748 break;
749 case 2:
750 modrm_ea += insn_fetch(s32, 4, _eip);
751 break;
752 }
753 }
754 if (!override_base)
755 override_base = &ctxt->ds_base;
756 if (mode == X86EMUL_MODE_PROT64 &&
757 override_base != &ctxt->fs_base &&
758 override_base != &ctxt->gs_base)
759 override_base = NULL;
760
761 if (override_base)
762 modrm_ea += *override_base;
763
764 if (rip_relative) {
765 modrm_ea += _eip;
766 switch (d & SrcMask) {
767 case SrcImmByte:
768 modrm_ea += 1;
769 break;
770 case SrcImm:
771 if (d & ByteOp)
772 modrm_ea += 1;
773 else
774 if (op_bytes == 8)
775 modrm_ea += 4;
776 else
777 modrm_ea += op_bytes;
778 }
779 }
780 if (ad_bytes != 8)
781 modrm_ea = (u32)modrm_ea;
782 cr2 = modrm_ea;
783 modrm_done:
784 ;
785 }
786
6aa8b732
AK		 787 /*
788 * Decode and fetch the source operand: register, memory
789 * or immediate.
790 */
791 switch (d & SrcMask) {
792 case SrcNone:
793 break;
794 case SrcReg:
795 src.type = OP_REG;
796 if (d & ByteOp) {
797 src.ptr = decode_register(modrm_reg, _regs,
798 (rex_prefix == 0));
799 src.val = src.orig_val = *(u8 *) src.ptr;
800 src.bytes = 1;
801 } else {
802 src.ptr = decode_register(modrm_reg, _regs, 0);
803 switch ((src.bytes = op_bytes)) {
804 case 2:
805 src.val = src.orig_val = *(u16 *) src.ptr;
806 break;
807 case 4:
808 src.val = src.orig_val = *(u32 *) src.ptr;
809 break;
810 case 8:
811 src.val = src.orig_val = *(u64 *) src.ptr;
812 break;
813 }
814 }
815 break;
816 case SrcMem16:
817 src.bytes = 2;
818 goto srcmem_common;
819 case SrcMem32:
820 src.bytes = 4;
821 goto srcmem_common;
822 case SrcMem:
823 src.bytes = (d & ByteOp) ? 1 : op_bytes;
b85b9ee9
RR		 824 /* Don't fetch the address for invlpg: it could be unmapped. */
825 if (twobyte && b == 0x01 && modrm_reg == 7)
826 break;
6aa8b732
AK		 827 srcmem_common:
828 src.type = OP_MEM;
829 src.ptr = (unsigned long *)cr2;
12fa272e 830 src.val = 0;
6aa8b732 831 if ((rc = ops->read_emulated((unsigned long)src.ptr,
cebff02b 832 &src.val, src.bytes, ctxt->vcpu)) != 0)
6aa8b732
AK		 833 goto done;
834 src.orig_val = src.val;
835 break;
836 case SrcImm:
837 src.type = OP_IMM;
838 src.ptr = (unsigned long *)_eip;
839 src.bytes = (d & ByteOp) ? 1 : op_bytes;
840 if (src.bytes == 8)
841 src.bytes = 4;
842 /* NB. Immediates are sign-extended as necessary. */
843 switch (src.bytes) {
844 case 1:
845 src.val = insn_fetch(s8, 1, _eip);
846 break;
847 case 2:
848 src.val = insn_fetch(s16, 2, _eip);
849 break;
850 case 4:
851 src.val = insn_fetch(s32, 4, _eip);
852 break;
853 }
854 break;
855 case SrcImmByte:
856 src.type = OP_IMM;
857 src.ptr = (unsigned long *)_eip;
858 src.bytes = 1;
859 src.val = insn_fetch(s8, 1, _eip);
860 break;
861 }
862
038e51de
AK		 863 /* Decode and fetch the destination operand: register or memory. */
864 switch (d & DstMask) {
865 case ImplicitOps:
866 /* Special instructions do their own operand decoding. */
867 goto special_insn;
868 case DstReg:
869 dst.type = OP_REG;
870 if ((d & ByteOp)
394b6e59 871 && !(twobyte && (b == 0xb6 || b == 0xb7))) {
038e51de
AK		 872 dst.ptr = decode_register(modrm_reg, _regs,
873 (rex_prefix == 0));
874 dst.val = *(u8 *) dst.ptr;
875 dst.bytes = 1;
876 } else {
877 dst.ptr = decode_register(modrm_reg, _regs, 0);
878 switch ((dst.bytes = op_bytes)) {
879 case 2:
880 dst.val = *(u16 *)dst.ptr;
881 break;
882 case 4:
883 dst.val = *(u32 *)dst.ptr;
884 break;
885 case 8:
886 dst.val = *(u64 *)dst.ptr;
887 break;
888 }
889 }
890 break;
891 case DstMem:
892 dst.type = OP_MEM;
893 dst.ptr = (unsigned long *)cr2;
894 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
12fa272e 895 dst.val = 0;
038e51de 896 if (d & BitOp) {
df513e2c
AK		 897 unsigned long mask = ~(dst.bytes * 8 - 1);
898
899 dst.ptr = (void *)dst.ptr + (src.val & mask) / 8;
038e51de
AK		 900 }
901 if (!(d & Mov) && /* optimisation - avoid slow emulated read */
902 ((rc = ops->read_emulated((unsigned long)dst.ptr,
cebff02b 903 &dst.val, dst.bytes, ctxt->vcpu)) != 0))
038e51de
AK		 904 goto done;
905 break;
906 }
907 dst.orig_val = dst.val;
908
6aa8b732
AK		 909 if (twobyte)
910 goto twobyte_insn;
911
912 switch (b) {
913 case 0x00 ... 0x05:
914 add: /* add */
915 emulate_2op_SrcV("add", src, dst, _eflags);
916 break;
917 case 0x08 ... 0x0d:
918 or: /* or */
919 emulate_2op_SrcV("or", src, dst, _eflags);
920 break;
921 case 0x10 ... 0x15:
922 adc: /* adc */
923 emulate_2op_SrcV("adc", src, dst, _eflags);
924 break;
925 case 0x18 ... 0x1d:
926 sbb: /* sbb */
927 emulate_2op_SrcV("sbb", src, dst, _eflags);
928 break;
19eb938e 929 case 0x20 ... 0x23:
6aa8b732
AK		 930 and: /* and */
931 emulate_2op_SrcV("and", src, dst, _eflags);
932 break;
19eb938e
NK		 933 case 0x24: /* and al imm8 */
934 dst.type = OP_REG;
935 dst.ptr = &_regs[VCPU_REGS_RAX];
936 dst.val = *(u8 *)dst.ptr;
937 dst.bytes = 1;
938 dst.orig_val = dst.val;
939 goto and;
940 case 0x25: /* and ax imm16, or eax imm32 */
941 dst.type = OP_REG;
942 dst.bytes = op_bytes;
943 dst.ptr = &_regs[VCPU_REGS_RAX];
944 if (op_bytes == 2)
945 dst.val = *(u16 *)dst.ptr;
946 else
947 dst.val = *(u32 *)dst.ptr;
948 dst.orig_val = dst.val;
949 goto and;
6aa8b732
AK		 950 case 0x28 ... 0x2d:
951 sub: /* sub */
952 emulate_2op_SrcV("sub", src, dst, _eflags);
953 break;
954 case 0x30 ... 0x35:
955 xor: /* xor */
956 emulate_2op_SrcV("xor", src, dst, _eflags);
957 break;
958 case 0x38 ... 0x3d:
959 cmp: /* cmp */
960 emulate_2op_SrcV("cmp", src, dst, _eflags);
961 break;
962 case 0x63: /* movsxd */
963 if (mode != X86EMUL_MODE_PROT64)
964 goto cannot_emulate;
965 dst.val = (s32) src.val;
966 break;
7d316911
NK		 967 case 0x6a: /* push imm8 */
968 src.val = 0L;
969 src.val = insn_fetch(s8, 1, _eip);
970push:
971 dst.type = OP_MEM;
972 dst.bytes = op_bytes;
973 dst.val = src.val;
974 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
fd2a7608
NK		 975 dst.ptr = (void *) register_address(ctxt->ss_base,
976 _regs[VCPU_REGS_RSP]);
7d316911 977 break;
6aa8b732
AK		 978 case 0x80 ... 0x83: /* Grp1 */
979 switch (modrm_reg) {
980 case 0:
981 goto add;
982 case 1:
983 goto or;
984 case 2:
985 goto adc;
986 case 3:
987 goto sbb;
988 case 4:
989 goto and;
990 case 5:
991 goto sub;
992 case 6:
993 goto xor;
994 case 7:
995 goto cmp;
996 }
997 break;
998 case 0x84 ... 0x85:
999 test: /* test */
1000 emulate_2op_SrcV("test", src, dst, _eflags);
1001 break;
1002 case 0x86 ... 0x87: /* xchg */
1003 /* Write back the register source. */
1004 switch (dst.bytes) {
1005 case 1:
1006 *(u8 *) src.ptr = (u8) dst.val;
1007 break;
1008 case 2:
1009 *(u16 *) src.ptr = (u16) dst.val;
1010 break;
1011 case 4:
1012 *src.ptr = (u32) dst.val;
1013 break; /* 64b reg: zero-extend */
1014 case 8:
1015 *src.ptr = dst.val;
1016 break;
1017 }
1018 /*
1019 * Write back the memory destination with implicit LOCK
1020 * prefix.
1021 */
1022 dst.val = src.val;
1023 lock_prefix = 1;
1024 break;
6aa8b732 1025 case 0x88 ... 0x8b: /* mov */
7de75248 1026 goto mov;
7e0b54b1
NK		 1027 case 0x8d: /* lea r16/r32, m */
1028 dst.val = modrm_val;
1029 break;
6aa8b732
AK		 1030 case 0x8f: /* pop (sole member of Grp1a) */
1031 /* 64-bit mode: POP always pops a 64-bit operand. */
1032 if (mode == X86EMUL_MODE_PROT64)
1033 dst.bytes = 8;
1034 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1035 _regs[VCPU_REGS_RSP]),
cebff02b 1036 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
6aa8b732
AK		 1037 goto done;
1038 register_address_increment(_regs[VCPU_REGS_RSP], dst.bytes);
1039 break;
7de75248
NK		 1040 case 0xa0 ... 0xa1: /* mov */
1041 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1042 dst.val = src.val;
1043 _eip += ad_bytes; /* skip src displacement */
1044 break;
1045 case 0xa2 ... 0xa3: /* mov */
1046 dst.val = (unsigned long)_regs[VCPU_REGS_RAX];
1047 _eip += ad_bytes; /* skip dst displacement */
1048 break;
6aa8b732
AK		 1049 case 0xc0 ... 0xc1:
1050 grp2: /* Grp2 */
1051 switch (modrm_reg) {
1052 case 0: /* rol */
1053 emulate_2op_SrcB("rol", src, dst, _eflags);
1054 break;
1055 case 1: /* ror */
1056 emulate_2op_SrcB("ror", src, dst, _eflags);
1057 break;
1058 case 2: /* rcl */
1059 emulate_2op_SrcB("rcl", src, dst, _eflags);
1060 break;
1061 case 3: /* rcr */
1062 emulate_2op_SrcB("rcr", src, dst, _eflags);
1063 break;
1064 case 4: /* sal/shl */
1065 case 6: /* sal/shl */
1066 emulate_2op_SrcB("sal", src, dst, _eflags);
1067 break;
1068 case 5: /* shr */
1069 emulate_2op_SrcB("shr", src, dst, _eflags);
1070 break;
1071 case 7: /* sar */
1072 emulate_2op_SrcB("sar", src, dst, _eflags);
1073 break;
1074 }
1075 break;
7de75248
NK		 1076 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1077 mov:
1078 dst.val = src.val;
1079 break;
6aa8b732
AK		 1080 case 0xd0 ... 0xd1: /* Grp2 */
1081 src.val = 1;
1082 goto grp2;
1083 case 0xd2 ... 0xd3: /* Grp2 */
1084 src.val = _regs[VCPU_REGS_RCX];
1085 goto grp2;
1086 case 0xf6 ... 0xf7: /* Grp3 */
1087 switch (modrm_reg) {
1088 case 0 ... 1: /* test */
1089 /*
1090 * Special case in Grp3: test has an immediate
1091 * source operand.
1092 */
1093 src.type = OP_IMM;
1094 src.ptr = (unsigned long *)_eip;
1095 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1096 if (src.bytes == 8)
1097 src.bytes = 4;
1098 switch (src.bytes) {
1099 case 1:
1100 src.val = insn_fetch(s8, 1, _eip);
1101 break;
1102 case 2:
1103 src.val = insn_fetch(s16, 2, _eip);
1104 break;
1105 case 4:
1106 src.val = insn_fetch(s32, 4, _eip);
1107 break;
1108 }
1109 goto test;
1110 case 2: /* not */
1111 dst.val = ~dst.val;
1112 break;
1113 case 3: /* neg */
1114 emulate_1op("neg", dst, _eflags);
1115 break;
1116 default:
1117 goto cannot_emulate;
1118 }
1119 break;
1120 case 0xfe ... 0xff: /* Grp4/Grp5 */
1121 switch (modrm_reg) {
1122 case 0: /* inc */
1123 emulate_1op("inc", dst, _eflags);
1124 break;
1125 case 1: /* dec */
1126 emulate_1op("dec", dst, _eflags);
1127 break;
26a3e983
NK		 1128 case 4: /* jmp abs */
1129 if (b == 0xff)
1130 _eip = dst.val;
1131 else
1132 goto cannot_emulate;
1133 break;
6aa8b732
AK		 1134 case 6: /* push */
1135 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1136 if (mode == X86EMUL_MODE_PROT64) {
1137 dst.bytes = 8;
1138 if ((rc = ops->read_std((unsigned long)dst.ptr,
1139 &dst.val, 8,
cebff02b 1140 ctxt->vcpu)) != 0)
6aa8b732
AK		 1141 goto done;
1142 }
1143 register_address_increment(_regs[VCPU_REGS_RSP],
1144 -dst.bytes);
1145 if ((rc = ops->write_std(
1146 register_address(ctxt->ss_base,
1147 _regs[VCPU_REGS_RSP]),
cebff02b 1148 &dst.val, dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1149 goto done;
02c03a32 1150 no_wb = 1;
6aa8b732
AK		 1151 break;
1152 default:
1153 goto cannot_emulate;
1154 }
1155 break;
1156 }
1157
1158writeback:
02c03a32 1159 if (!no_wb) {
6aa8b732
AK		 1160 switch (dst.type) {
1161 case OP_REG:
1162 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1163 switch (dst.bytes) {
1164 case 1:
1165 *(u8 *)dst.ptr = (u8)dst.val;
1166 break;
1167 case 2:
1168 *(u16 *)dst.ptr = (u16)dst.val;
1169 break;
1170 case 4:
1171 *dst.ptr = (u32)dst.val;
1172 break; /* 64b: zero-ext */
1173 case 8:
1174 *dst.ptr = dst.val;
1175 break;
1176 }
1177 break;
1178 case OP_MEM:
1179 if (lock_prefix)
1180 rc = ops->cmpxchg_emulated((unsigned long)dst.
4c690a1e
AK		 1181 ptr, &dst.orig_val,
1182 &dst.val, dst.bytes,
cebff02b 1183 ctxt->vcpu);
6aa8b732
AK		 1184 else
1185 rc = ops->write_emulated((unsigned long)dst.ptr,
4c690a1e 1186 &dst.val, dst.bytes,
cebff02b 1187 ctxt->vcpu);
6aa8b732
AK		 1188 if (rc != 0)
1189 goto done;
1190 default:
1191 break;
1192 }
1193 }
1194
1195 /* Commit shadow register state. */
1196 memcpy(ctxt->vcpu->regs, _regs, sizeof _regs);
1197 ctxt->eflags = _eflags;
1198 ctxt->vcpu->rip = _eip;
1199
1200done:
1201 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1202
1203special_insn:
1204 if (twobyte)
1205 goto twobyte_special_insn;
e70669ab 1206 switch(b) {
7e778161
NK		 1207 case 0x50 ... 0x57: /* push reg */
1208 if (op_bytes == 2)
1209 src.val = (u16) _regs[b & 0x7];
1210 else
1211 src.val = (u32) _regs[b & 0x7];
1212 dst.type = OP_MEM;
1213 dst.bytes = op_bytes;
1214 dst.val = src.val;
1215 register_address_increment(_regs[VCPU_REGS_RSP], -op_bytes);
1216 dst.ptr = (void *) register_address(
1217 ctxt->ss_base, _regs[VCPU_REGS_RSP]);
7e778161 1218 break;
7de75248
NK		 1219 case 0x58 ... 0x5f: /* pop reg */
1220 dst.ptr = (unsigned long *)&_regs[b & 0x7];
1221 pop_instruction:
1222 if ((rc = ops->read_std(register_address(ctxt->ss_base,
1223 _regs[VCPU_REGS_RSP]), dst.ptr, op_bytes, ctxt->vcpu))
1224 != 0)
1225 goto done;
1226
1227 register_address_increment(_regs[VCPU_REGS_RSP], op_bytes);
1228 no_wb = 1; /* Disable writeback. */
1229 break;
e70669ab
LV		 1230 case 0x6c: /* insb */
1231 case 0x6d: /* insw/insd */
3090dd73 1232 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e70669ab
LV		 1233 1, /* in */
1234 (d & ByteOp) ? 1 : op_bytes, /* size */
1235 rep_prefix ?
1236 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
e70669ab
LV		 1237 (_eflags & EFLG_DF), /* down */
1238 register_address(ctxt->es_base,
1239 _regs[VCPU_REGS_RDI]), /* address */
1240 rep_prefix,
1241 _regs[VCPU_REGS_RDX] /* port */
1242 ) == 0)
1243 return -1;
1244 return 0;
1245 case 0x6e: /* outsb */
1246 case 0x6f: /* outsw/outsd */
3090dd73 1247 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e70669ab
LV		 1248 0, /* in */
1249 (d & ByteOp) ? 1 : op_bytes, /* size */
1250 rep_prefix ?
1251 address_mask(_regs[VCPU_REGS_RCX]) : 1, /* count */
e70669ab
LV		 1252 (_eflags & EFLG_DF), /* down */
1253 register_address(override_base ?
1254 *override_base : ctxt->ds_base,
1255 _regs[VCPU_REGS_RSI]), /* address */
1256 rep_prefix,
1257 _regs[VCPU_REGS_RDX] /* port */
1258 ) == 0)
1259 return -1;
1260 return 0;
55bebde4
NK		 1261 case 0x70 ... 0x7f: /* jcc (short) */ {
1262 int rel = insn_fetch(s8, 1, _eip);
1263
1264 if (test_cc(b, _eflags))
1265 JMP_REL(rel);
1266 break;
1267 }
fd2a7608
NK		 1268 case 0x9c: /* pushf */
1269 src.val = (unsigned long) _eflags;
1270 goto push;
535eabcf
NK		 1271 case 0x9d: /* popf */
1272 dst.ptr = (unsigned long *) &_eflags;
1273 goto pop_instruction;
7de75248
NK		 1274 case 0xc3: /* ret */
1275 dst.ptr = &_eip;
1276 goto pop_instruction;
1277 case 0xf4: /* hlt */
1278 ctxt->vcpu->halt_request = 1;
1279 goto done;
e70669ab 1280 }
6aa8b732
AK		 1281 if (rep_prefix) {
1282 if (_regs[VCPU_REGS_RCX] == 0) {
1283 ctxt->vcpu->rip = _eip;
1284 goto done;
1285 }
1286 _regs[VCPU_REGS_RCX]--;
1287 _eip = ctxt->vcpu->rip;
1288 }
1289 switch (b) {
1290 case 0xa4 ... 0xa5: /* movs */
1291 dst.type = OP_MEM;
1292 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1293 dst.ptr = (unsigned long *)register_address(ctxt->es_base,
1294 _regs[VCPU_REGS_RDI]);
1295 if ((rc = ops->read_emulated(register_address(
1296 override_base ? *override_base : ctxt->ds_base,
cebff02b 1297 _regs[VCPU_REGS_RSI]), &dst.val, dst.bytes, ctxt->vcpu)) != 0)
6aa8b732
AK		 1298 goto done;
1299 register_address_increment(_regs[VCPU_REGS_RSI],
1300 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1301 register_address_increment(_regs[VCPU_REGS_RDI],
1302 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1303 break;
1304 case 0xa6 ... 0xa7: /* cmps */
1305 DPRINTF("Urk! I don't handle CMPS.\n");
1306 goto cannot_emulate;
1307 case 0xaa ... 0xab: /* stos */
1308 dst.type = OP_MEM;
1309 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1310 dst.ptr = (unsigned long *)cr2;
1311 dst.val = _regs[VCPU_REGS_RAX];
1312 register_address_increment(_regs[VCPU_REGS_RDI],
1313 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1314 break;
1315 case 0xac ... 0xad: /* lods */
1316 dst.type = OP_REG;
1317 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
1318 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
cebff02b
LV		 1319 if ((rc = ops->read_emulated(cr2, &dst.val, dst.bytes,
1320 ctxt->vcpu)) != 0)
6aa8b732
AK		 1321 goto done;
1322 register_address_increment(_regs[VCPU_REGS_RSI],
1323 (_eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
1324 break;
1325 case 0xae ... 0xaf: /* scas */
1326 DPRINTF("Urk! I don't handle SCAS.\n");
1327 goto cannot_emulate;
1a52e051
NK		 1328 case 0xe8: /* call (near) */ {
1329 long int rel;
1330 switch (op_bytes) {
1331 case 2:
1332 rel = insn_fetch(s16, 2, _eip);
1333 break;
1334 case 4:
1335 rel = insn_fetch(s32, 4, _eip);
1336 break;
1337 case 8:
1338 rel = insn_fetch(s64, 8, _eip);
1339 break;
1340 default:
1341 DPRINTF("Call: Invalid op_bytes\n");
1342 goto cannot_emulate;
1343 }
1344 src.val = (unsigned long) _eip;
1345 JMP_REL(rel);
1346 goto push;
1347 }
1348 case 0xe9: /* jmp rel */
1349 case 0xeb: /* jmp rel short */
1350 JMP_REL(src.val);
1351 no_wb = 1; /* Disable writeback. */
1352 break;
1353
7f0aaee0 1354
6aa8b732
AK		 1355 }
1356 goto writeback;
1357
1358twobyte_insn:
1359 switch (b) {
1360 case 0x01: /* lgdt, lidt, lmsw */
d37c8557
AJ		 1361 /* Disable writeback. */
1362 no_wb = 1;
6aa8b732
AK		 1363 switch (modrm_reg) {
1364 u16 size;
1365 unsigned long address;
1366
1367 case 2: /* lgdt */
1368 rc = read_descriptor(ctxt, ops, src.ptr,
1369 &size, &address, op_bytes);
1370 if (rc)
1371 goto done;
1372 realmode_lgdt(ctxt->vcpu, size, address);
1373 break;
1374 case 3: /* lidt */
1375 rc = read_descriptor(ctxt, ops, src.ptr,
1376 &size, &address, op_bytes);
1377 if (rc)
1378 goto done;
1379 realmode_lidt(ctxt->vcpu, size, address);
1380 break;
1381 case 4: /* smsw */
1382 if (modrm_mod != 3)
1383 goto cannot_emulate;
1384 *(u16 *)&_regs[modrm_rm]
1385 = realmode_get_cr(ctxt->vcpu, 0);
1386 break;
1387 case 6: /* lmsw */
1388 if (modrm_mod != 3)
1389 goto cannot_emulate;
1390 realmode_lmsw(ctxt->vcpu, (u16)modrm_val, &_eflags);
1391 break;
1392 case 7: /* invlpg*/
1393 emulate_invlpg(ctxt->vcpu, cr2);
1394 break;
1395 default:
1396 goto cannot_emulate;
1397 }
1398 break;
1399 case 0x21: /* mov from dr to reg */
bac27d35 1400 no_wb = 1;
6aa8b732
AK		 1401 if (modrm_mod != 3)
1402 goto cannot_emulate;
1403 rc = emulator_get_dr(ctxt, modrm_reg, &_regs[modrm_rm]);
1404 break;
1405 case 0x23: /* mov from reg to dr */
bac27d35 1406 no_wb = 1;
6aa8b732
AK		 1407 if (modrm_mod != 3)
1408 goto cannot_emulate;
1409 rc = emulator_set_dr(ctxt, modrm_reg, _regs[modrm_rm]);
1410 break;
1411 case 0x40 ... 0x4f: /* cmov */
1412 dst.val = dst.orig_val = src.val;
e3243452 1413 no_wb = 1;
6aa8b732
AK		 1414 /*
1415 * First, assume we're decoding an even cmov opcode
1416 * (lsb == 0).
1417 */
1418 switch ((b & 15) >> 1) {
1419 case 0: /* cmovo */
e3243452 1420 no_wb = (_eflags & EFLG_OF) ? 0 : 1;
6aa8b732
AK		 1421 break;
1422 case 1: /* cmovb/cmovc/cmovnae */
e3243452 1423 no_wb = (_eflags & EFLG_CF) ? 0 : 1;
6aa8b732
AK		 1424 break;
1425 case 2: /* cmovz/cmove */
e3243452 1426 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
6aa8b732
AK		 1427 break;
1428 case 3: /* cmovbe/cmovna */
e3243452 1429 no_wb = (_eflags & (EFLG_CF | EFLG_ZF)) ? 0 : 1;
6aa8b732
AK		 1430 break;
1431 case 4: /* cmovs */
e3243452 1432 no_wb = (_eflags & EFLG_SF) ? 0 : 1;
6aa8b732
AK		 1433 break;
1434 case 5: /* cmovp/cmovpe */
e3243452 1435 no_wb = (_eflags & EFLG_PF) ? 0 : 1;
6aa8b732
AK		 1436 break;
1437 case 7: /* cmovle/cmovng */
e3243452 1438 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
6aa8b732
AK		 1439 /* fall through */
1440 case 6: /* cmovl/cmovnge */
e3243452
AK		 1441 no_wb &= (!(_eflags & EFLG_SF) !=
1442 !(_eflags & EFLG_OF)) ? 0 : 1;
6aa8b732
AK		 1443 break;
1444 }
1445 /* Odd cmov opcodes (lsb == 1) have inverted sense. */
e3243452 1446 no_wb ^= b & 1;
6aa8b732 1447 break;
7de75248
NK		 1448 case 0xa3:
1449 bt: /* bt */
1450 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1451 emulate_2op_SrcV_nobyte("bt", src, dst, _eflags);
1452 break;
1453 case 0xab:
1454 bts: /* bts */
1455 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1456 emulate_2op_SrcV_nobyte("bts", src, dst, _eflags);
1457 break;
6aa8b732
AK		 1458 case 0xb0 ... 0xb1: /* cmpxchg */
1459 /*
1460 * Save real source value, then compare EAX against
1461 * destination.
1462 */
1463 src.orig_val = src.val;
1464 src.val = _regs[VCPU_REGS_RAX];
1465 emulate_2op_SrcV("cmp", src, dst, _eflags);
6aa8b732
AK		 1466 if (_eflags & EFLG_ZF) {
1467 /* Success: write back to memory. */
1468 dst.val = src.orig_val;
1469 } else {
1470 /* Failure: write the value we saw to EAX. */
1471 dst.type = OP_REG;
1472 dst.ptr = (unsigned long *)&_regs[VCPU_REGS_RAX];
1473 }
1474 break;
6aa8b732
AK		 1475 case 0xb3:
1476 btr: /* btr */
1477 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1478 emulate_2op_SrcV_nobyte("btr", src, dst, _eflags);
1479 break;
6aa8b732
AK		 1480 case 0xb6 ... 0xb7: /* movzx */
1481 dst.bytes = op_bytes;
1482 dst.val = (d & ByteOp) ? (u8) src.val : (u16) src.val;
1483 break;
6aa8b732
AK		 1484 case 0xba: /* Grp8 */
1485 switch (modrm_reg & 3) {
1486 case 0:
1487 goto bt;
1488 case 1:
1489 goto bts;
1490 case 2:
1491 goto btr;
1492 case 3:
1493 goto btc;
1494 }
1495 break;
7de75248
NK		 1496 case 0xbb:
1497 btc: /* btc */
1498 src.val &= (dst.bytes << 3) - 1; /* only subword offset */
1499 emulate_2op_SrcV_nobyte("btc", src, dst, _eflags);
1500 break;
6aa8b732
AK		 1501 case 0xbe ... 0xbf: /* movsx */
1502 dst.bytes = op_bytes;
1503 dst.val = (d & ByteOp) ? (s8) src.val : (s16) src.val;
1504 break;
a012e65a
SY		 1505 case 0xc3: /* movnti */
1506 dst.bytes = op_bytes;
1507 dst.val = (op_bytes == 4) ? (u32) src.val : (u64) src.val;
1508 break;
6aa8b732
AK		 1509 }
1510 goto writeback;
1511
1512twobyte_special_insn:
1513 /* Disable writeback. */
02c03a32 1514 no_wb = 1;
6aa8b732 1515 switch (b) {
7de75248
NK		 1516 case 0x06:
1517 emulate_clts(ctxt->vcpu);
1518 break;
687fdbfe
AK		 1519 case 0x09: /* wbinvd */
1520 break;
6aa8b732
AK		 1521 case 0x0d: /* GrpP (prefetch) */
1522 case 0x18: /* Grp16 (prefetch/nop) */
1523 break;
6aa8b732
AK		 1524 case 0x20: /* mov cr, reg */
1525 if (modrm_mod != 3)
1526 goto cannot_emulate;
1527 _regs[modrm_rm] = realmode_get_cr(ctxt->vcpu, modrm_reg);
1528 break;
1529 case 0x22: /* mov reg, cr */
1530 if (modrm_mod != 3)
1531 goto cannot_emulate;
1532 realmode_set_cr(ctxt->vcpu, modrm_reg, modrm_val, &_eflags);
1533 break;
35f3f286
AK		 1534 case 0x30:
1535 /* wrmsr */
1536 msr_data = (u32)_regs[VCPU_REGS_RAX]
1537 | ((u64)_regs[VCPU_REGS_RDX] << 32);
1538 rc = kvm_set_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], msr_data);
1539 if (rc) {
cbdd1bea 1540 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
35f3f286
AK		 1541 _eip = ctxt->vcpu->rip;
1542 }
1543 rc = X86EMUL_CONTINUE;
1544 break;
1545 case 0x32:
1546 /* rdmsr */
1547 rc = kvm_get_msr(ctxt->vcpu, _regs[VCPU_REGS_RCX], &msr_data);
1548 if (rc) {
cbdd1bea 1549 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
35f3f286
AK		 1550 _eip = ctxt->vcpu->rip;
1551 } else {
1552 _regs[VCPU_REGS_RAX] = (u32)msr_data;
1553 _regs[VCPU_REGS_RDX] = msr_data >> 32;
1554 }
1555 rc = X86EMUL_CONTINUE;
1556 break;
bbe9abbd
NK		 1557 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1558 long int rel;
1559
1560 switch (op_bytes) {
1561 case 2:
1562 rel = insn_fetch(s16, 2, _eip);
1563 break;
1564 case 4:
1565 rel = insn_fetch(s32, 4, _eip);
1566 break;
1567 case 8:
1568 rel = insn_fetch(s64, 8, _eip);
1569 break;
1570 default:
1571 DPRINTF("jnz: Invalid op_bytes\n");
1572 goto cannot_emulate;
1573 }
1574 if (test_cc(b, _eflags))
1575 JMP_REL(rel);
1576 break;
1577 }
6aa8b732 1578 case 0xc7: /* Grp9 (cmpxchg8b) */
6aa8b732 1579 {
4c690a1e 1580 u64 old, new;
cebff02b
LV		 1581 if ((rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu))
1582 != 0)
6aa8b732
AK		 1583 goto done;
1584 if (((u32) (old >> 0) != (u32) _regs[VCPU_REGS_RAX]) ||
1585 ((u32) (old >> 32) != (u32) _regs[VCPU_REGS_RDX])) {
1586 _regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1587 _regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1588 _eflags &= ~EFLG_ZF;
1589 } else {
4c690a1e
AK		 1590 new = ((u64)_regs[VCPU_REGS_RCX] << 32)
1591 | (u32) _regs[VCPU_REGS_RBX];
1592 if ((rc = ops->cmpxchg_emulated(cr2, &old,
cebff02b 1593 &new, 8, ctxt->vcpu)) != 0)
6aa8b732
AK		 1594 goto done;
1595 _eflags |= EFLG_ZF;
1596 }
1597 break;
1598 }
6aa8b732
AK		 1599 }
1600 goto writeback;
1601
1602cannot_emulate:
1603 DPRINTF("Cannot emulate %02x\n", b);
1604 return -1;
1605}
1606
1607#ifdef __XEN__
1608
1609#include <asm/mm.h>
1610#include <asm/uaccess.h>
1611
1612int
1613x86_emulate_read_std(unsigned long addr,
1614 unsigned long *val,
1615 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1616{
1617 unsigned int rc;
1618
1619 *val = 0;
1620
1621 if ((rc = copy_from_user((void *)val, (void *)addr, bytes)) != 0) {
1622 propagate_page_fault(addr + bytes - rc, 0); /* read fault */
1623 return X86EMUL_PROPAGATE_FAULT;
1624 }
1625
1626 return X86EMUL_CONTINUE;
1627}
1628
1629int
1630x86_emulate_write_std(unsigned long addr,
1631 unsigned long val,
1632 unsigned int bytes, struct x86_emulate_ctxt *ctxt)
1633{
1634 unsigned int rc;
1635
1636 if ((rc = copy_to_user((void *)addr, (void *)&val, bytes)) != 0) {
1637 propagate_page_fault(addr + bytes - rc, PGERR_write_access);
1638 return X86EMUL_PROPAGATE_FAULT;
1639 }
1640
1641 return X86EMUL_CONTINUE;
1642}
1643
1644#endif
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