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KVM: x86 emulator: Any legacy prefix after a REX prefix nullifies its effect
[mirror_ubuntu-zesty-kernel.git] / drivers / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
26#define DPRINTF(_f, _a ...) printf( _f , ## _a )
27#else
28#include "kvm.h"
29#define DPRINTF(x...) do {} while (0)
30#endif
31#include "x86_emulate.h"
32#include <linux/module.h>
33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
6aa8b732
AK		 65
66static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 86 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7f0aaee0 101 /* 0x50 - 0x57 */
7e778161
NK		 102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7f0aaee0
NK		 104 /* 0x58 - 0x5F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7d316911 107 /* 0x60 - 0x67 */
6aa8b732 108 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 109 0, 0, 0, 0,
110 /* 0x68 - 0x6F */
111 0, 0, ImplicitOps|Mov, 0,
e70669ab
LV		 112 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
113 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 114 /* 0x70 - 0x77 */
115 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 /* 0x78 - 0x7F */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 120 /* 0x80 - 0x87 */
121 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
122 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 /* 0x88 - 0x8F */
126 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
127 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
7e0b54b1 128 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
6aa8b732 129 /* 0x90 - 0x9F */
535eabcf 130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
6aa8b732
AK		 131 /* 0xA0 - 0xA7 */
132 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
133 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
134 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
135 ByteOp | ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
138 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
139 ByteOp | ImplicitOps, ImplicitOps,
140 /* 0xB0 - 0xBF */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xC0 - 0xC7 */
d9413cd7
NK		 143 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
144 0, ImplicitOps, 0, 0,
145 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 146 /* 0xC8 - 0xCF */
147 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xD0 - 0xD7 */
149 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
150 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
151 0, 0, 0, 0,
152 /* 0xD8 - 0xDF */
153 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 154 /* 0xE0 - 0xE7 */
155 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xE8 - 0xEF */
f6eed391 157 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
6aa8b732
AK		 158 /* 0xF0 - 0xF7 */
159 0, 0, 0, 0,
72d6e5a0
AK		 160 ImplicitOps, 0,
161 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
6aa8b732
AK		 162 /* 0xF8 - 0xFF */
163 0, 0, 0, 0,
164 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
165};
166
038e51de 167static u16 twobyte_table[256] = {
6aa8b732
AK		 168 /* 0x00 - 0x0F */
169 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 170 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 171 /* 0x10 - 0x1F */
172 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x20 - 0x2F */
174 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
175 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x30 - 0x3F */
35f3f286 177 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 178 /* 0x40 - 0x47 */
179 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
180 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
181 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 /* 0x48 - 0x4F */
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 /* 0x50 - 0x5F */
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x60 - 0x6F */
191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x70 - 0x7F */
193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x80 - 0x8F */
bbe9abbd
NK		 195 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
196 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
197 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 199 /* 0x90 - 0x9F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xA0 - 0xA7 */
038e51de 202 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 203 /* 0xA8 - 0xAF */
038e51de 204 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 205 /* 0xB0 - 0xB7 */
206 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 207 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 208 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem16 | ModRM | Mov,
210 /* 0xB8 - 0xBF */
038e51de 211 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 212 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem16 | ModRM | Mov,
214 /* 0xC0 - 0xCF */
a012e65a
SY		 215 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
216 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 217 /* 0xD0 - 0xDF */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xE0 - 0xEF */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0xF0 - 0xFF */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
223};
224
6aa8b732
AK		 225/* EFLAGS bit definitions. */
226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
228#define EFLG_SF (1<<7)
229#define EFLG_ZF (1<<6)
230#define EFLG_AF (1<<4)
231#define EFLG_PF (1<<2)
232#define EFLG_CF (1<<0)
233
234/*
235 * Instruction emulation:
236 * Most instructions are emulated directly via a fragment of inline assembly
237 * code. This allows us to save/restore EFLAGS and thus very easily pick up
238 * any modified flags.
239 */
240
05b3e0c2 241#if defined(CONFIG_X86_64)
6aa8b732
AK		 242#define _LO32 "k" /* force 32-bit operand */
243#define _STK "%%rsp" /* stack pointer */
244#elif defined(__i386__)
245#define _LO32 "" /* force 32-bit operand */
246#define _STK "%%esp" /* stack pointer */
247#endif
248
249/*
250 * These EFLAGS bits are restored from saved value during emulation, and
251 * any changes are written back to the saved value after emulation.
252 */
253#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
254
255/* Before executing instruction: restore necessary bits in EFLAGS. */
256#define _PRE_EFLAGS(_sav, _msk, _tmp) \
257 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
258 "push %"_sav"; " \
259 "movl %"_msk",%"_LO32 _tmp"; " \
260 "andl %"_LO32 _tmp",("_STK"); " \
261 "pushf; " \
262 "notl %"_LO32 _tmp"; " \
263 "andl %"_LO32 _tmp",("_STK"); " \
264 "pop %"_tmp"; " \
265 "orl %"_LO32 _tmp",("_STK"); " \
266 "popf; " \
267 /* _sav &= ~msk; */ \
268 "movl %"_msk",%"_LO32 _tmp"; " \
269 "notl %"_LO32 _tmp"; " \
270 "andl %"_LO32 _tmp",%"_sav"; "
271
272/* After executing instruction: write-back necessary bits in EFLAGS. */
273#define _POST_EFLAGS(_sav, _msk, _tmp) \
274 /* _sav |= EFLAGS & _msk; */ \
275 "pushf; " \
276 "pop %"_tmp"; " \
277 "andl %"_msk",%"_LO32 _tmp"; " \
278 "orl %"_LO32 _tmp",%"_sav"; "
279
280/* Raw emulation: instruction has two explicit operands. */
281#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
282 do { \
283 unsigned long _tmp; \
284 \
285 switch ((_dst).bytes) { \
286 case 2: \
287 __asm__ __volatile__ ( \
288 _PRE_EFLAGS("0","4","2") \
289 _op"w %"_wx"3,%1; " \
290 _POST_EFLAGS("0","4","2") \
291 : "=m" (_eflags), "=m" ((_dst).val), \
292 "=&r" (_tmp) \
293 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
294 break; \
295 case 4: \
296 __asm__ __volatile__ ( \
297 _PRE_EFLAGS("0","4","2") \
298 _op"l %"_lx"3,%1; " \
299 _POST_EFLAGS("0","4","2") \
300 : "=m" (_eflags), "=m" ((_dst).val), \
301 "=&r" (_tmp) \
302 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
303 break; \
304 case 8: \
305 __emulate_2op_8byte(_op, _src, _dst, \
306 _eflags, _qx, _qy); \
307 break; \
308 } \
309 } while (0)
310
311#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
312 do { \
313 unsigned long _tmp; \
314 switch ( (_dst).bytes ) \
315 { \
316 case 1: \
317 __asm__ __volatile__ ( \
318 _PRE_EFLAGS("0","4","2") \
319 _op"b %"_bx"3,%1; " \
320 _POST_EFLAGS("0","4","2") \
321 : "=m" (_eflags), "=m" ((_dst).val), \
322 "=&r" (_tmp) \
323 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
324 break; \
325 default: \
326 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
327 _wx, _wy, _lx, _ly, _qx, _qy); \
328 break; \
329 } \
330 } while (0)
331
332/* Source operand is byte-sized and may be restricted to just %cl. */
333#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
334 __emulate_2op(_op, _src, _dst, _eflags, \
335 "b", "c", "b", "c", "b", "c", "b", "c")
336
337/* Source operand is byte, word, long or quad sized. */
338#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
339 __emulate_2op(_op, _src, _dst, _eflags, \
340 "b", "q", "w", "r", _LO32, "r", "", "r")
341
342/* Source operand is word, long or quad sized. */
343#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
344 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
345 "w", "r", _LO32, "r", "", "r")
346
347/* Instruction has only one explicit operand (no source operand). */
348#define emulate_1op(_op, _dst, _eflags) \
349 do { \
350 unsigned long _tmp; \
351 \
352 switch ( (_dst).bytes ) \
353 { \
354 case 1: \
355 __asm__ __volatile__ ( \
356 _PRE_EFLAGS("0","3","2") \
357 _op"b %1; " \
358 _POST_EFLAGS("0","3","2") \
359 : "=m" (_eflags), "=m" ((_dst).val), \
360 "=&r" (_tmp) \
361 : "i" (EFLAGS_MASK) ); \
362 break; \
363 case 2: \
364 __asm__ __volatile__ ( \
365 _PRE_EFLAGS("0","3","2") \
366 _op"w %1; " \
367 _POST_EFLAGS("0","3","2") \
368 : "=m" (_eflags), "=m" ((_dst).val), \
369 "=&r" (_tmp) \
370 : "i" (EFLAGS_MASK) ); \
371 break; \
372 case 4: \
373 __asm__ __volatile__ ( \
374 _PRE_EFLAGS("0","3","2") \
375 _op"l %1; " \
376 _POST_EFLAGS("0","3","2") \
377 : "=m" (_eflags), "=m" ((_dst).val), \
378 "=&r" (_tmp) \
379 : "i" (EFLAGS_MASK) ); \
380 break; \
381 case 8: \
382 __emulate_1op_8byte(_op, _dst, _eflags); \
383 break; \
384 } \
385 } while (0)
386
387/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 388#if defined(CONFIG_X86_64)
6aa8b732
AK		 389#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
390 do { \
391 __asm__ __volatile__ ( \
392 _PRE_EFLAGS("0","4","2") \
393 _op"q %"_qx"3,%1; " \
394 _POST_EFLAGS("0","4","2") \
395 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
396 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
397 } while (0)
398
399#define __emulate_1op_8byte(_op, _dst, _eflags) \
400 do { \
401 __asm__ __volatile__ ( \
402 _PRE_EFLAGS("0","3","2") \
403 _op"q %1; " \
404 _POST_EFLAGS("0","3","2") \
405 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
406 : "i" (EFLAGS_MASK) ); \
407 } while (0)
408
409#elif defined(__i386__)
410#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
411#define __emulate_1op_8byte(_op, _dst, _eflags)
412#endif /* __i386__ */
413
414/* Fetch next part of the instruction being emulated. */
415#define insn_fetch(_type, _size, _eip) \
416({ unsigned long _x; \
417 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
cebff02b 418 (_size), ctxt->vcpu); \
6aa8b732
AK		 419 if ( rc != 0 ) \
420 goto done; \
421 (_eip) += (_size); \
422 (_type)_x; \
423})
424
425/* Access/update address held in a register, based on addressing mode. */
e70669ab 426#define address_mask(reg) \
e4e03ded
LV		 427 ((c->ad_bytes == sizeof(unsigned long)) ? \
428 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
6aa8b732 429#define register_address(base, reg) \
e70669ab 430 ((base) + address_mask(reg))
6aa8b732
AK		 431#define register_address_increment(reg, inc) \
432 do { \
433 /* signed type ensures sign extension to long */ \
434 int _inc = (inc); \
e4e03ded 435 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 436 (reg) += _inc; \
437 else \
e4e03ded
LV		 438 (reg) = ((reg) & \
439 ~((1UL << (c->ad_bytes << 3)) - 1)) | \
440 (((reg) + _inc) & \
441 ((1UL << (c->ad_bytes << 3)) - 1)); \
6aa8b732
AK		 442 } while (0)
443
098c937b
NK		 444#define JMP_REL(rel) \
445 do { \
e4e03ded 446 register_address_increment(c->eip, rel); \
098c937b
NK		 447 } while (0)
448
1e3c5cb0
RR		 449/*
450 * Given the 'reg' portion of a ModRM byte, and a register block, return a
451 * pointer into the block that addresses the relevant register.
452 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
453 */
454static void *decode_register(u8 modrm_reg, unsigned long *regs,
455 int highbyte_regs)
6aa8b732
AK		 456{
457 void *p;
458
459 p = &regs[modrm_reg];
460 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
461 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
462 return p;
463}
464
465static int read_descriptor(struct x86_emulate_ctxt *ctxt,
466 struct x86_emulate_ops *ops,
467 void *ptr,
468 u16 *size, unsigned long *address, int op_bytes)
469{
470 int rc;
471
472 if (op_bytes == 2)
473 op_bytes = 3;
474 *address = 0;
cebff02b
LV		 475 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
476 ctxt->vcpu);
6aa8b732
AK		 477 if (rc)
478 return rc;
cebff02b
LV		 479 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
480 ctxt->vcpu);
6aa8b732
AK		 481 return rc;
482}
483
bbe9abbd
NK		 484static int test_cc(unsigned int condition, unsigned int flags)
485{
486 int rc = 0;
487
488 switch ((condition & 15) >> 1) {
489 case 0: /* o */
490 rc |= (flags & EFLG_OF);
491 break;
492 case 1: /* b/c/nae */
493 rc |= (flags & EFLG_CF);
494 break;
495 case 2: /* z/e */
496 rc |= (flags & EFLG_ZF);
497 break;
498 case 3: /* be/na */
499 rc |= (flags & (EFLG_CF|EFLG_ZF));
500 break;
501 case 4: /* s */
502 rc |= (flags & EFLG_SF);
503 break;
504 case 5: /* p/pe */
505 rc |= (flags & EFLG_PF);
506 break;
507 case 7: /* le/ng */
508 rc |= (flags & EFLG_ZF);
509 /* fall through */
510 case 6: /* l/nge */
511 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
512 break;
513 }
514
515 /* Odd condition identifiers (lsb == 1) have inverted sense. */
516 return (!!rc ^ (condition & 1));
517}
518
6aa8b732 519int
8b4caf66 520x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
6aa8b732 521{
e4e03ded
LV		 522 struct decode_cache *c = &ctxt->decode;
523 u8 sib, rex_prefix = 0;
6aa8b732 524 int rc = 0;
6aa8b732 525 int mode = ctxt->mode;
e4e03ded 526 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
6aa8b732
AK		 527
528 /* Shadow copy of register state. Committed on successful emulation. */
6aa8b732 529
e4e03ded
LV		 530 memset(c, 0, sizeof(struct decode_cache));
531 c->eip = ctxt->vcpu->rip;
532 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
6aa8b732
AK		 533
534 switch (mode) {
535 case X86EMUL_MODE_REAL:
536 case X86EMUL_MODE_PROT16:
e4e03ded 537 c->op_bytes = c->ad_bytes = 2;
6aa8b732
AK		 538 break;
539 case X86EMUL_MODE_PROT32:
e4e03ded 540 c->op_bytes = c->ad_bytes = 4;
6aa8b732 541 break;
05b3e0c2 542#ifdef CONFIG_X86_64
6aa8b732 543 case X86EMUL_MODE_PROT64:
e4e03ded
LV		 544 c->op_bytes = 4;
545 c->ad_bytes = 8;
6aa8b732
AK		 546 break;
547#endif
548 default:
549 return -1;
550 }
551
552 /* Legacy prefixes. */
b4c6abfe 553 for (;;) {
e4e03ded 554 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 555 case 0x66: /* operand-size override */
e4e03ded 556 c->op_bytes ^= 6; /* switch between 2/4 bytes */
6aa8b732
AK		 557 break;
558 case 0x67: /* address-size override */
559 if (mode == X86EMUL_MODE_PROT64)
e4e03ded
LV		 560 /* switch between 4/8 bytes */
561 c->ad_bytes ^= 12;
6aa8b732 562 else
e4e03ded
LV		 563 /* switch between 2/4 bytes */
564 c->ad_bytes ^= 6;
6aa8b732
AK		 565 break;
566 case 0x2e: /* CS override */
e4e03ded 567 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 568 break;
569 case 0x3e: /* DS override */
e4e03ded 570 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 571 break;
572 case 0x26: /* ES override */
e4e03ded 573 c->override_base = &ctxt->es_base;
6aa8b732
AK		 574 break;
575 case 0x64: /* FS override */
e4e03ded 576 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 577 break;
578 case 0x65: /* GS override */
e4e03ded 579 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 580 break;
581 case 0x36: /* SS override */
e4e03ded 582 c->override_base = &ctxt->ss_base;
6aa8b732 583 break;
b4c6abfe
LV		 584 case 0x40 ... 0x4f: /* REX */
585 if (mode != X86EMUL_MODE_PROT64)
586 goto done_prefixes;
587 rex_prefix = c->b;
588 continue;
6aa8b732 589 case 0xf0: /* LOCK */
e4e03ded 590 c->lock_prefix = 1;
6aa8b732 591 break;
ae6200ba 592 case 0xf2: /* REPNE/REPNZ */
6aa8b732 593 case 0xf3: /* REP/REPE/REPZ */
e4e03ded 594 c->rep_prefix = 1;
6aa8b732 595 break;
6aa8b732
AK		 596 default:
597 goto done_prefixes;
598 }
b4c6abfe
LV		 599
600 /* Any legacy prefix after a REX prefix nullifies its effect. */
601
602 rex_prefix = 0;
6aa8b732
AK		 603 }
604
605done_prefixes:
606
607 /* REX prefix. */
b4c6abfe
LV		 608 if (rex_prefix) {
609 if (rex_prefix & 8)
e4e03ded 610 c->op_bytes = 8; /* REX.W */
b4c6abfe
LV		 611 c->modrm_reg = (rex_prefix & 4) << 1; /* REX.R */
612 index_reg = (rex_prefix & 2) << 2; /* REX.X */
613 c->modrm_rm = base_reg = (rex_prefix & 1) << 3; /* REG.B */
6aa8b732
AK		 614 }
615
616 /* Opcode byte(s). */
e4e03ded
LV		 617 c->d = opcode_table[c->b];
618 if (c->d == 0) {
6aa8b732 619 /* Two-byte opcode? */
e4e03ded
LV		 620 if (c->b == 0x0f) {
621 c->twobyte = 1;
622 c->b = insn_fetch(u8, 1, c->eip);
623 c->d = twobyte_table[c->b];
6aa8b732
AK		 624 }
625
626 /* Unrecognised? */
8b4caf66
LV		 627 if (c->d == 0) {
628 DPRINTF("Cannot emulate %02x\n", c->b);
629 return -1;
630 }
6aa8b732
AK		 631 }
632
633 /* ModRM and SIB bytes. */
e4e03ded
LV		 634 if (c->d & ModRM) {
635 c->modrm = insn_fetch(u8, 1, c->eip);
636 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
637 c->modrm_reg |= (c->modrm & 0x38) >> 3;
638 c->modrm_rm |= (c->modrm & 0x07);
639 c->modrm_ea = 0;
640 c->use_modrm_ea = 1;
641
642 if (c->modrm_mod == 3) {
643 c->modrm_val = *(unsigned long *)
644 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
6aa8b732
AK		 645 goto modrm_done;
646 }
647
e4e03ded
LV		 648 if (c->ad_bytes == 2) {
649 unsigned bx = c->regs[VCPU_REGS_RBX];
650 unsigned bp = c->regs[VCPU_REGS_RBP];
651 unsigned si = c->regs[VCPU_REGS_RSI];
652 unsigned di = c->regs[VCPU_REGS_RDI];
6aa8b732
AK		 653
654 /* 16-bit ModR/M decode. */
e4e03ded 655 switch (c->modrm_mod) {
6aa8b732 656 case 0:
e4e03ded
LV		 657 if (c->modrm_rm == 6)
658 c->modrm_ea +=
659 insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 660 break;
661 case 1:
e4e03ded 662 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 663 break;
664 case 2:
e4e03ded 665 c->modrm_ea += insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 666 break;
667 }
e4e03ded 668 switch (c->modrm_rm) {
6aa8b732 669 case 0:
e4e03ded 670 c->modrm_ea += bx + si;
6aa8b732
AK		 671 break;
672 case 1:
e4e03ded 673 c->modrm_ea += bx + di;
6aa8b732
AK		 674 break;
675 case 2:
e4e03ded 676 c->modrm_ea += bp + si;
6aa8b732
AK		 677 break;
678 case 3:
e4e03ded 679 c->modrm_ea += bp + di;
6aa8b732
AK		 680 break;
681 case 4:
e4e03ded 682 c->modrm_ea += si;
6aa8b732
AK		 683 break;
684 case 5:
e4e03ded 685 c->modrm_ea += di;
6aa8b732
AK		 686 break;
687 case 6:
e4e03ded
LV		 688 if (c->modrm_mod != 0)
689 c->modrm_ea += bp;
6aa8b732
AK		 690 break;
691 case 7:
e4e03ded 692 c->modrm_ea += bx;
6aa8b732
AK		 693 break;
694 }
e4e03ded
LV		 695 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
696 (c->modrm_rm == 6 && c->modrm_mod != 0))
697 if (!c->override_base)
698 c->override_base = &ctxt->ss_base;
699 c->modrm_ea = (u16)c->modrm_ea;
6aa8b732
AK		 700 } else {
701 /* 32/64-bit ModR/M decode. */
e4e03ded 702 switch (c->modrm_rm) {
6aa8b732
AK		 703 case 4:
704 case 12:
e4e03ded 705 sib = insn_fetch(u8, 1, c->eip);
6aa8b732
AK		 706 index_reg |= (sib >> 3) & 7;
707 base_reg |= sib & 7;
708 scale = sib >> 6;
709
710 switch (base_reg) {
711 case 5:
e4e03ded
LV		 712 if (c->modrm_mod != 0)
713 c->modrm_ea +=
714 c->regs[base_reg];
6aa8b732 715 else
e4e03ded
LV		 716 c->modrm_ea +=
717 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 718 break;
719 default:
e4e03ded 720 c->modrm_ea += c->regs[base_reg];
6aa8b732
AK		 721 }
722 switch (index_reg) {
723 case 4:
724 break;
725 default:
e4e03ded
LV		 726 c->modrm_ea +=
727 c->regs[index_reg] << scale;
6aa8b732
AK		 728
729 }
730 break;
731 case 5:
e4e03ded
LV		 732 if (c->modrm_mod != 0)
733 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 734 else if (mode == X86EMUL_MODE_PROT64)
735 rip_relative = 1;
736 break;
737 default:
e4e03ded 738 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 739 break;
740 }
e4e03ded 741 switch (c->modrm_mod) {
6aa8b732 742 case 0:
e4e03ded
LV		 743 if (c->modrm_rm == 5)
744 c->modrm_ea +=
745 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 746 break;
747 case 1:
e4e03ded 748 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 749 break;
750 case 2:
e4e03ded 751 c->modrm_ea += insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 752 break;
753 }
754 }
e4e03ded
LV		 755 if (!c->override_base)
756 c->override_base = &ctxt->ds_base;
6aa8b732 757 if (mode == X86EMUL_MODE_PROT64 &&
e4e03ded
LV		 758 c->override_base != &ctxt->fs_base &&
759 c->override_base != &ctxt->gs_base)
760 c->override_base = NULL;
6aa8b732 761
e4e03ded
LV		 762 if (c->override_base)
763 c->modrm_ea += *c->override_base;
6aa8b732
AK		 764
765 if (rip_relative) {
e4e03ded
LV		 766 c->modrm_ea += c->eip;
767 switch (c->d & SrcMask) {
6aa8b732 768 case SrcImmByte:
e4e03ded 769 c->modrm_ea += 1;
6aa8b732
AK		 770 break;
771 case SrcImm:
e4e03ded
LV		 772 if (c->d & ByteOp)
773 c->modrm_ea += 1;
6aa8b732 774 else
e4e03ded
LV		 775 if (c->op_bytes == 8)
776 c->modrm_ea += 4;
6aa8b732 777 else
e4e03ded 778 c->modrm_ea += c->op_bytes;
6aa8b732
AK		 779 }
780 }
e4e03ded
LV		 781 if (c->ad_bytes != 8)
782 c->modrm_ea = (u32)c->modrm_ea;
6aa8b732
AK		 783 modrm_done:
784 ;
785 }
786
6aa8b732
AK		 787 /*
788 * Decode and fetch the source operand: register, memory
789 * or immediate.
790 */
e4e03ded 791 switch (c->d & SrcMask) {
6aa8b732
AK		 792 case SrcNone:
793 break;
794 case SrcReg:
e4e03ded
LV		 795 c->src.type = OP_REG;
796 if (c->d & ByteOp) {
797 c->src.ptr =
798 decode_register(c->modrm_reg, c->regs,
6aa8b732 799 (rex_prefix == 0));
e4e03ded
LV		 800 c->src.val = c->src.orig_val = *(u8 *)c->src.ptr;
801 c->src.bytes = 1;
6aa8b732 802 } else {
e4e03ded
LV		 803 c->src.ptr =
804 decode_register(c->modrm_reg, c->regs, 0);
805 switch ((c->src.bytes = c->op_bytes)) {
6aa8b732 806 case 2:
e4e03ded
LV		 807 c->src.val = c->src.orig_val =
808 *(u16 *) c->src.ptr;
6aa8b732
AK		 809 break;
810 case 4:
e4e03ded
LV		 811 c->src.val = c->src.orig_val =
812 *(u32 *) c->src.ptr;
6aa8b732
AK		 813 break;
814 case 8:
e4e03ded
LV		 815 c->src.val = c->src.orig_val =
816 *(u64 *) c->src.ptr;
6aa8b732
AK		 817 break;
818 }
819 }
820 break;
821 case SrcMem16:
e4e03ded 822 c->src.bytes = 2;
6aa8b732
AK		 823 goto srcmem_common;
824 case SrcMem32:
e4e03ded 825 c->src.bytes = 4;
6aa8b732
AK		 826 goto srcmem_common;
827 case SrcMem:
e4e03ded
LV		 828 c->src.bytes = (c->d & ByteOp) ? 1 :
829 c->op_bytes;
b85b9ee9 830 /* Don't fetch the address for invlpg: it could be unmapped. */
e4e03ded
LV		 831 if (c->twobyte && c->b == 0x01
832 && c->modrm_reg == 7)
b85b9ee9 833 break;
6aa8b732 834 srcmem_common:
4e62417b
AJ		 835 /*
836 * For instructions with a ModR/M byte, switch to register
837 * access if Mod = 3.
838 */
e4e03ded
LV		 839 if ((c->d & ModRM) && c->modrm_mod == 3) {
840 c->src.type = OP_REG;
4e62417b
AJ		 841 break;
842 }
e4e03ded 843 c->src.type = OP_MEM;
6aa8b732
AK		 844 break;
845 case SrcImm:
e4e03ded
LV		 846 c->src.type = OP_IMM;
847 c->src.ptr = (unsigned long *)c->eip;
848 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
849 if (c->src.bytes == 8)
850 c->src.bytes = 4;
6aa8b732 851 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 852 switch (c->src.bytes) {
6aa8b732 853 case 1:
e4e03ded 854 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 855 break;
856 case 2:
e4e03ded 857 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 858 break;
859 case 4:
e4e03ded 860 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 861 break;
862 }
863 break;
864 case SrcImmByte:
e4e03ded
LV		 865 c->src.type = OP_IMM;
866 c->src.ptr = (unsigned long *)c->eip;
867 c->src.bytes = 1;
868 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 869 break;
870 }
871
038e51de 872 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 873 switch (c->d & DstMask) {
038e51de
AK		 874 case ImplicitOps:
875 /* Special instructions do their own operand decoding. */
8b4caf66 876 return 0;
038e51de 877 case DstReg:
e4e03ded
LV		 878 c->dst.type = OP_REG;
879 if ((c->d & ByteOp)
880 && !(c->twobyte &&
881 (c->b == 0xb6 || c->b == 0xb7))) {
882 c->dst.ptr =
883 decode_register(c->modrm_reg, c->regs,
038e51de 884 (rex_prefix == 0));
e4e03ded
LV		 885 c->dst.val = *(u8 *) c->dst.ptr;
886 c->dst.bytes = 1;
038e51de 887 } else {
e4e03ded
LV		 888 c->dst.ptr =
889 decode_register(c->modrm_reg, c->regs, 0);
890 switch ((c->dst.bytes = c->op_bytes)) {
038e51de 891 case 2:
e4e03ded 892 c->dst.val = *(u16 *)c->dst.ptr;
038e51de
AK		 893 break;
894 case 4:
e4e03ded 895 c->dst.val = *(u32 *)c->dst.ptr;
038e51de
AK		 896 break;
897 case 8:
e4e03ded 898 c->dst.val = *(u64 *)c->dst.ptr;
038e51de
AK		 899 break;
900 }
901 }
902 break;
903 case DstMem:
e4e03ded
LV		 904 if ((c->d & ModRM) && c->modrm_mod == 3) {
905 c->dst.type = OP_REG;
4e62417b
AJ		 906 break;
907 }
8b4caf66
LV		 908 c->dst.type = OP_MEM;
909 break;
910 }
911
912done:
913 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
914}
915
8cdbd2c9
LV		 916static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
917{
918 struct decode_cache *c = &ctxt->decode;
919
920 c->dst.type = OP_MEM;
921 c->dst.bytes = c->op_bytes;
922 c->dst.val = c->src.val;
923 register_address_increment(c->regs[VCPU_REGS_RSP], -c->op_bytes);
924 c->dst.ptr = (void *) register_address(ctxt->ss_base,
925 c->regs[VCPU_REGS_RSP]);
926}
927
928static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
929 struct x86_emulate_ops *ops)
930{
931 struct decode_cache *c = &ctxt->decode;
932 int rc;
933
934 /* 64-bit mode: POP always pops a 64-bit operand. */
935
936 if (ctxt->mode == X86EMUL_MODE_PROT64)
937 c->dst.bytes = 8;
938
939 rc = ops->read_std(register_address(ctxt->ss_base,
940 c->regs[VCPU_REGS_RSP]),
941 &c->dst.val, c->dst.bytes, ctxt->vcpu);
942 if (rc != 0)
943 return rc;
944
945 register_address_increment(c->regs[VCPU_REGS_RSP], c->dst.bytes);
946
947 return 0;
948}
949
05f086f8 950static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
8cdbd2c9 951{
05f086f8 952 struct decode_cache *c = &ctxt->decode;
8cdbd2c9
LV		 953 switch (c->modrm_reg) {
954 case 0: /* rol */
05f086f8 955 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 956 break;
957 case 1: /* ror */
05f086f8 958 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 959 break;
960 case 2: /* rcl */
05f086f8 961 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 962 break;
963 case 3: /* rcr */
05f086f8 964 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 965 break;
966 case 4: /* sal/shl */
967 case 6: /* sal/shl */
05f086f8 968 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 969 break;
970 case 5: /* shr */
05f086f8 971 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 972 break;
973 case 7: /* sar */
05f086f8 974 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 975 break;
976 }
977}
978
979static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
05f086f8 980 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 981{
982 struct decode_cache *c = &ctxt->decode;
983 int rc = 0;
984
985 switch (c->modrm_reg) {
986 case 0 ... 1: /* test */
987 /*
988 * Special case in Grp3: test has an immediate
989 * source operand.
990 */
991 c->src.type = OP_IMM;
992 c->src.ptr = (unsigned long *)c->eip;
993 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
994 if (c->src.bytes == 8)
995 c->src.bytes = 4;
996 switch (c->src.bytes) {
997 case 1:
998 c->src.val = insn_fetch(s8, 1, c->eip);
999 break;
1000 case 2:
1001 c->src.val = insn_fetch(s16, 2, c->eip);
1002 break;
1003 case 4:
1004 c->src.val = insn_fetch(s32, 4, c->eip);
1005 break;
1006 }
05f086f8 1007 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
8cdbd2c9
LV		 1008 break;
1009 case 2: /* not */
1010 c->dst.val = ~c->dst.val;
1011 break;
1012 case 3: /* neg */
05f086f8 1013 emulate_1op("neg", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1014 break;
1015 default:
1016 DPRINTF("Cannot emulate %02x\n", c->b);
1017 rc = X86EMUL_UNHANDLEABLE;
1018 break;
1019 }
1020done:
1021 return rc;
1022}
1023
1024static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
a01af5ec 1025 struct x86_emulate_ops *ops)
8cdbd2c9
LV		 1026{
1027 struct decode_cache *c = &ctxt->decode;
1028 int rc;
1029
1030 switch (c->modrm_reg) {
1031 case 0: /* inc */
05f086f8 1032 emulate_1op("inc", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1033 break;
1034 case 1: /* dec */
05f086f8 1035 emulate_1op("dec", c->dst, ctxt->eflags);
8cdbd2c9
LV		 1036 break;
1037 case 4: /* jmp abs */
1038 if (c->b == 0xff)
1039 c->eip = c->dst.val;
1040 else {
1041 DPRINTF("Cannot emulate %02x\n", c->b);
1042 return X86EMUL_UNHANDLEABLE;
1043 }
1044 break;
1045 case 6: /* push */
1046
1047 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1048
1049 if (ctxt->mode == X86EMUL_MODE_PROT64) {
1050 c->dst.bytes = 8;
1051 rc = ops->read_std((unsigned long)c->dst.ptr,
1052 &c->dst.val, 8, ctxt->vcpu);
1053 if (rc != 0)
1054 return rc;
1055 }
1056 register_address_increment(c->regs[VCPU_REGS_RSP],
1057 -c->dst.bytes);
1058 rc = ops->write_emulated(register_address(ctxt->ss_base,
1059 c->regs[VCPU_REGS_RSP]), &c->dst.val,
1060 c->dst.bytes, ctxt->vcpu);
1061 if (rc != 0)
1062 return rc;
a01af5ec 1063 c->dst.type = OP_NONE;
8cdbd2c9
LV		 1064 break;
1065 default:
1066 DPRINTF("Cannot emulate %02x\n", c->b);
1067 return X86EMUL_UNHANDLEABLE;
1068 }
1069 return 0;
1070}
1071
1072static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1073 struct x86_emulate_ops *ops,
8cdbd2c9
LV		 1074 unsigned long cr2)
1075{
1076 struct decode_cache *c = &ctxt->decode;
1077 u64 old, new;
1078 int rc;
1079
1080 rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu);
1081 if (rc != 0)
1082 return rc;
1083
1084 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1085 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1086
1087 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1088 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
05f086f8 1089 ctxt->eflags &= ~EFLG_ZF;
8cdbd2c9
LV		 1090
1091 } else {
1092 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1093 (u32) c->regs[VCPU_REGS_RBX];
1094
1095 rc = ops->cmpxchg_emulated(cr2, &old, &new, 8, ctxt->vcpu);
1096 if (rc != 0)
1097 return rc;
05f086f8 1098 ctxt->eflags |= EFLG_ZF;
8cdbd2c9
LV		 1099 }
1100 return 0;
1101}
1102
1103static inline int writeback(struct x86_emulate_ctxt *ctxt,
1104 struct x86_emulate_ops *ops)
1105{
1106 int rc;
1107 struct decode_cache *c = &ctxt->decode;
1108
1109 switch (c->dst.type) {
1110 case OP_REG:
1111 /* The 4-byte case *is* correct:
1112 * in 64-bit mode we zero-extend.
1113 */
1114 switch (c->dst.bytes) {
1115 case 1:
1116 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1117 break;
1118 case 2:
1119 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1120 break;
1121 case 4:
1122 *c->dst.ptr = (u32)c->dst.val;
1123 break; /* 64b: zero-ext */
1124 case 8:
1125 *c->dst.ptr = c->dst.val;
1126 break;
1127 }
1128 break;
1129 case OP_MEM:
1130 if (c->lock_prefix)
1131 rc = ops->cmpxchg_emulated(
1132 (unsigned long)c->dst.ptr,
1133 &c->dst.orig_val,
1134 &c->dst.val,
1135 c->dst.bytes,
1136 ctxt->vcpu);
1137 else
1138 rc = ops->write_emulated(
1139 (unsigned long)c->dst.ptr,
1140 &c->dst.val,
1141 c->dst.bytes,
1142 ctxt->vcpu);
1143 if (rc != 0)
1144 return rc;
a01af5ec
LV		 1145 break;
1146 case OP_NONE:
1147 /* no writeback */
1148 break;
8cdbd2c9
LV		 1149 default:
1150 break;
1151 }
1152 return 0;
1153}
1154
8b4caf66 1155int
1be3aa47 1156x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
8b4caf66
LV		 1157{
1158 unsigned long cr2 = ctxt->cr2;
8b4caf66 1159 u64 msr_data;
3427318f 1160 unsigned long saved_eip = 0;
8b4caf66 1161 struct decode_cache *c = &ctxt->decode;
1be3aa47 1162 int rc = 0;
8b4caf66 1163
3427318f
LV		 1164 /* Shadow copy of register state. Committed on successful emulation.
1165 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1166 * modify them.
1167 */
1168
1169 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
1170 saved_eip = c->eip;
1171
8b4caf66
LV		 1172 if ((c->d & ModRM) && (c->modrm_mod != 3))
1173 cr2 = c->modrm_ea;
1174
1175 if (c->src.type == OP_MEM) {
1176 c->src.ptr = (unsigned long *)cr2;
1177 c->src.val = 0;
1178 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1179 &c->src.val,
1180 c->src.bytes,
1181 ctxt->vcpu)) != 0)
1182 goto done;
1183 c->src.orig_val = c->src.val;
1184 }
1185
1186 if ((c->d & DstMask) == ImplicitOps)
1187 goto special_insn;
1188
1189
1190 if (c->dst.type == OP_MEM) {
1191 c->dst.ptr = (unsigned long *)cr2;
1192 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1193 c->dst.val = 0;
e4e03ded
LV		 1194 if (c->d & BitOp) {
1195 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 1196
e4e03ded
LV		 1197 c->dst.ptr = (void *)c->dst.ptr +
1198 (c->src.val & mask) / 8;
038e51de 1199 }
e4e03ded
LV		 1200 if (!(c->d & Mov) &&
1201 /* optimisation - avoid slow emulated read */
1202 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1203 &c->dst.val,
1204 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de 1205 goto done;
038e51de 1206 }
e4e03ded 1207 c->dst.orig_val = c->dst.val;
038e51de 1208
e4e03ded 1209 if (c->twobyte)
6aa8b732
AK		 1210 goto twobyte_insn;
1211
e4e03ded 1212 switch (c->b) {
6aa8b732
AK		 1213 case 0x00 ... 0x05:
1214 add: /* add */
05f086f8 1215 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1216 break;
1217 case 0x08 ... 0x0d:
1218 or: /* or */
05f086f8 1219 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1220 break;
1221 case 0x10 ... 0x15:
1222 adc: /* adc */
05f086f8 1223 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1224 break;
1225 case 0x18 ... 0x1d:
1226 sbb: /* sbb */
05f086f8 1227 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
6aa8b732 1228 break;
19eb938e 1229 case 0x20 ... 0x23:
6aa8b732 1230 and: /* and */
05f086f8 1231 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
6aa8b732 1232 break;
19eb938e 1233 case 0x24: /* and al imm8 */
e4e03ded
LV		 1234 c->dst.type = OP_REG;
1235 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1236 c->dst.val = *(u8 *)c->dst.ptr;
1237 c->dst.bytes = 1;
1238 c->dst.orig_val = c->dst.val;
19eb938e
NK		 1239 goto and;
1240 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 1241 c->dst.type = OP_REG;
1242 c->dst.bytes = c->op_bytes;
1243 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1244 if (c->op_bytes == 2)
1245 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 1246 else
e4e03ded
LV		 1247 c->dst.val = *(u32 *)c->dst.ptr;
1248 c->dst.orig_val = c->dst.val;
19eb938e 1249 goto and;
6aa8b732
AK		 1250 case 0x28 ... 0x2d:
1251 sub: /* sub */
05f086f8 1252 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1253 break;
1254 case 0x30 ... 0x35:
1255 xor: /* xor */
05f086f8 1256 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1257 break;
1258 case 0x38 ... 0x3d:
1259 cmp: /* cmp */
05f086f8 1260 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1261 break;
1262 case 0x63: /* movsxd */
8b4caf66 1263 if (ctxt->mode != X86EMUL_MODE_PROT64)
6aa8b732 1264 goto cannot_emulate;
e4e03ded 1265 c->dst.val = (s32) c->src.val;
6aa8b732
AK		 1266 break;
1267 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 1268 switch (c->modrm_reg) {
6aa8b732
AK		 1269 case 0:
1270 goto add;
1271 case 1:
1272 goto or;
1273 case 2:
1274 goto adc;
1275 case 3:
1276 goto sbb;
1277 case 4:
1278 goto and;
1279 case 5:
1280 goto sub;
1281 case 6:
1282 goto xor;
1283 case 7:
1284 goto cmp;
1285 }
1286 break;
1287 case 0x84 ... 0x85:
05f086f8 1288 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
6aa8b732
AK		 1289 break;
1290 case 0x86 ... 0x87: /* xchg */
1291 /* Write back the register source. */
e4e03ded 1292 switch (c->dst.bytes) {
6aa8b732 1293 case 1:
e4e03ded 1294 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1295 break;
1296 case 2:
e4e03ded 1297 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1298 break;
1299 case 4:
e4e03ded 1300 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1301 break; /* 64b reg: zero-extend */
1302 case 8:
e4e03ded 1303 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1304 break;
1305 }
1306 /*
1307 * Write back the memory destination with implicit LOCK
1308 * prefix.
1309 */
e4e03ded
LV		 1310 c->dst.val = c->src.val;
1311 c->lock_prefix = 1;
6aa8b732 1312 break;
6aa8b732 1313 case 0x88 ... 0x8b: /* mov */
7de75248 1314 goto mov;
7e0b54b1 1315 case 0x8d: /* lea r16/r32, m */
e4e03ded 1316 c->dst.val = c->modrm_val;
7e0b54b1 1317 break;
6aa8b732 1318 case 0x8f: /* pop (sole member of Grp1a) */
8cdbd2c9
LV		 1319 rc = emulate_grp1a(ctxt, ops);
1320 if (rc != 0)
6aa8b732 1321 goto done;
6aa8b732 1322 break;
7de75248 1323 case 0xa0 ... 0xa1: /* mov */
e4e03ded
LV		 1324 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1325 c->dst.val = c->src.val;
1326 /* skip src displacement */
1327 c->eip += c->ad_bytes;
7de75248
NK		 1328 break;
1329 case 0xa2 ... 0xa3: /* mov */
e4e03ded
LV		 1330 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1331 /* skip c->dst displacement */
1332 c->eip += c->ad_bytes;
7de75248 1333 break;
6aa8b732 1334 case 0xc0 ... 0xc1:
05f086f8 1335 emulate_grp2(ctxt);
6aa8b732 1336 break;
7de75248
NK		 1337 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1338 mov:
e4e03ded 1339 c->dst.val = c->src.val;
7de75248 1340 break;
6aa8b732 1341 case 0xd0 ... 0xd1: /* Grp2 */
e4e03ded 1342 c->src.val = 1;
05f086f8 1343 emulate_grp2(ctxt);
8cdbd2c9 1344 break;
6aa8b732 1345 case 0xd2 ... 0xd3: /* Grp2 */
e4e03ded 1346 c->src.val = c->regs[VCPU_REGS_RCX];
05f086f8 1347 emulate_grp2(ctxt);
8cdbd2c9 1348 break;
6aa8b732 1349 case 0xf6 ... 0xf7: /* Grp3 */
05f086f8 1350 rc = emulate_grp3(ctxt, ops);
8cdbd2c9
LV		 1351 if (rc != 0)
1352 goto done;
6aa8b732
AK		 1353 break;
1354 case 0xfe ... 0xff: /* Grp4/Grp5 */
a01af5ec 1355 rc = emulate_grp45(ctxt, ops);
8cdbd2c9
LV		 1356 if (rc != 0)
1357 goto done;
6aa8b732
AK		 1358 break;
1359 }
1360
1361writeback:
a01af5ec
LV		 1362 rc = writeback(ctxt, ops);
1363 if (rc != 0)
1364 goto done;
6aa8b732
AK		 1365
1366 /* Commit shadow register state. */
e4e03ded 1367 memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs);
e4e03ded 1368 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1369
1370done:
3427318f
LV		 1371 if (rc == X86EMUL_UNHANDLEABLE) {
1372 c->eip = saved_eip;
1373 return -1;
1374 }
1375 return 0;
6aa8b732
AK		 1376
1377special_insn:
e4e03ded 1378 if (c->twobyte)
6aa8b732 1379 goto twobyte_special_insn;
e4e03ded 1380 switch (c->b) {
7e778161 1381 case 0x50 ... 0x57: /* push reg */
e4e03ded
LV		 1382 if (c->op_bytes == 2)
1383 c->src.val = (u16) c->regs[c->b & 0x7];
7e778161 1384 else
e4e03ded
LV		 1385 c->src.val = (u32) c->regs[c->b & 0x7];
1386 c->dst.type = OP_MEM;
1387 c->dst.bytes = c->op_bytes;
1388 c->dst.val = c->src.val;
1389 register_address_increment(c->regs[VCPU_REGS_RSP],
1390 -c->op_bytes);
1391 c->dst.ptr = (void *) register_address(
1392 ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
7e778161 1393 break;
7de75248 1394 case 0x58 ... 0x5f: /* pop reg */
8cdbd2c9 1395 c->dst.ptr = (unsigned long *)&c->regs[c->b & 0x7];
7de75248
NK		 1396 pop_instruction:
1397 if ((rc = ops->read_std(register_address(ctxt->ss_base,
e4e03ded
LV		 1398 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1399 c->op_bytes, ctxt->vcpu)) != 0)
7de75248
NK		 1400 goto done;
1401
e4e03ded
LV		 1402 register_address_increment(c->regs[VCPU_REGS_RSP],
1403 c->op_bytes);
a01af5ec 1404 c->dst.type = OP_NONE; /* Disable writeback. */
7de75248 1405 break;
1e35d3c4 1406 case 0x6a: /* push imm8 */
e4e03ded
LV		 1407 c->src.val = 0L;
1408 c->src.val = insn_fetch(s8, 1, c->eip);
8cdbd2c9 1409 emulate_push(ctxt);
1e35d3c4 1410 break;
e70669ab
LV		 1411 case 0x6c: /* insb */
1412 case 0x6d: /* insw/insd */
3090dd73 1413 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1414 1,
1415 (c->d & ByteOp) ? 1 : c->op_bytes,
1416 c->rep_prefix ?
1417 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
05f086f8 1418 (ctxt->eflags & EFLG_DF),
e70669ab 1419 register_address(ctxt->es_base,
e4e03ded
LV		 1420 c->regs[VCPU_REGS_RDI]),
1421 c->rep_prefix,
3427318f
LV		 1422 c->regs[VCPU_REGS_RDX]) == 0) {
1423 c->eip = saved_eip;
e70669ab 1424 return -1;
3427318f 1425 }
e70669ab
LV		 1426 return 0;
1427 case 0x6e: /* outsb */
1428 case 0x6f: /* outsw/outsd */
3090dd73 1429 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1430 0,
1431 (c->d & ByteOp) ? 1 : c->op_bytes,
1432 c->rep_prefix ?
1433 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
05f086f8 1434 (ctxt->eflags & EFLG_DF),
e4e03ded
LV		 1435 register_address(c->override_base ?
1436 *c->override_base :
1437 ctxt->ds_base,
1438 c->regs[VCPU_REGS_RSI]),
1439 c->rep_prefix,
3427318f
LV		 1440 c->regs[VCPU_REGS_RDX]) == 0) {
1441 c->eip = saved_eip;
e70669ab 1442 return -1;
3427318f 1443 }
e70669ab 1444 return 0;
55bebde4 1445 case 0x70 ... 0x7f: /* jcc (short) */ {
e4e03ded 1446 int rel = insn_fetch(s8, 1, c->eip);
55bebde4 1447
05f086f8 1448 if (test_cc(c->b, ctxt->eflags))
55bebde4
NK		 1449 JMP_REL(rel);
1450 break;
1451 }
fd2a7608 1452 case 0x9c: /* pushf */
05f086f8 1453 c->src.val = (unsigned long) ctxt->eflags;
8cdbd2c9
LV		 1454 emulate_push(ctxt);
1455 break;
535eabcf 1456 case 0x9d: /* popf */
05f086f8 1457 c->dst.ptr = (unsigned long *) &ctxt->eflags;
535eabcf 1458 goto pop_instruction;
7de75248 1459 case 0xc3: /* ret */
e4e03ded 1460 c->dst.ptr = &c->eip;
7de75248
NK		 1461 goto pop_instruction;
1462 case 0xf4: /* hlt */
1463 ctxt->vcpu->halt_request = 1;
1464 goto done;
e70669ab 1465 }
e4e03ded
LV		 1466 if (c->rep_prefix) {
1467 if (c->regs[VCPU_REGS_RCX] == 0) {
1468 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1469 goto done;
1470 }
e4e03ded
LV		 1471 c->regs[VCPU_REGS_RCX]--;
1472 c->eip = ctxt->vcpu->rip;
6aa8b732 1473 }
e4e03ded 1474 switch (c->b) {
6aa8b732 1475 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1476 c->dst.type = OP_MEM;
1477 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1478 c->dst.ptr = (unsigned long *)register_address(
1479 ctxt->es_base,
1480 c->regs[VCPU_REGS_RDI]);
6aa8b732 1481 if ((rc = ops->read_emulated(register_address(
e4e03ded
LV		 1482 c->override_base ? *c->override_base :
1483 ctxt->ds_base,
1484 c->regs[VCPU_REGS_RSI]),
1485 &c->dst.val,
1486 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1487 goto done;
e4e03ded 1488 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1489 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded
LV		 1490 : c->dst.bytes);
1491 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1492 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1493 : c->dst.bytes);
6aa8b732
AK		 1494 break;
1495 case 0xa6 ... 0xa7: /* cmps */
1496 DPRINTF("Urk! I don't handle CMPS.\n");
1497 goto cannot_emulate;
1498 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1499 c->dst.type = OP_MEM;
1500 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1501 c->dst.ptr = (unsigned long *)cr2;
1502 c->dst.val = c->regs[VCPU_REGS_RAX];
1503 register_address_increment(c->regs[VCPU_REGS_RDI],
05f086f8 1504 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1505 : c->dst.bytes);
6aa8b732
AK		 1506 break;
1507 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1508 c->dst.type = OP_REG;
1509 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1510 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1511 if ((rc = ops->read_emulated(cr2, &c->dst.val,
1512 c->dst.bytes,
cebff02b 1513 ctxt->vcpu)) != 0)
6aa8b732 1514 goto done;
e4e03ded 1515 register_address_increment(c->regs[VCPU_REGS_RSI],
05f086f8 1516 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
e4e03ded 1517 : c->dst.bytes);
6aa8b732
AK		 1518 break;
1519 case 0xae ... 0xaf: /* scas */
1520 DPRINTF("Urk! I don't handle SCAS.\n");
1521 goto cannot_emulate;
1a52e051
NK		 1522 case 0xe8: /* call (near) */ {
1523 long int rel;
e4e03ded 1524 switch (c->op_bytes) {
1a52e051 1525 case 2:
e4e03ded 1526 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1527 break;
1528 case 4:
e4e03ded 1529 rel = insn_fetch(s32, 4, c->eip);
1a52e051
NK		 1530 break;
1531 case 8:
e4e03ded 1532 rel = insn_fetch(s64, 8, c->eip);
1a52e051
NK		 1533 break;
1534 default:
1535 DPRINTF("Call: Invalid op_bytes\n");
1536 goto cannot_emulate;
1537 }
e4e03ded 1538 c->src.val = (unsigned long) c->eip;
1a52e051 1539 JMP_REL(rel);
e4e03ded 1540 c->op_bytes = c->ad_bytes;
8cdbd2c9
LV		 1541 emulate_push(ctxt);
1542 break;
1a52e051
NK		 1543 }
1544 case 0xe9: /* jmp rel */
1545 case 0xeb: /* jmp rel short */
e4e03ded 1546 JMP_REL(c->src.val);
a01af5ec 1547 c->dst.type = OP_NONE; /* Disable writeback. */
1a52e051
NK		 1548 break;
1549
7f0aaee0 1550
6aa8b732
AK		 1551 }
1552 goto writeback;
1553
1554twobyte_insn:
e4e03ded 1555 switch (c->b) {
6aa8b732 1556 case 0x01: /* lgdt, lidt, lmsw */
e4e03ded 1557 switch (c->modrm_reg) {
6aa8b732
AK		 1558 u16 size;
1559 unsigned long address;
1560
aca7f966 1561 case 0: /* vmcall */
e4e03ded 1562 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1563 goto cannot_emulate;
1564
7aa81cc0
AL		 1565 rc = kvm_fix_hypercall(ctxt->vcpu);
1566 if (rc)
1567 goto done;
1568
1569 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1570 break;
6aa8b732 1571 case 2: /* lgdt */
e4e03ded
LV		 1572 rc = read_descriptor(ctxt, ops, c->src.ptr,
1573 &size, &address, c->op_bytes);
6aa8b732
AK		 1574 if (rc)
1575 goto done;
1576 realmode_lgdt(ctxt->vcpu, size, address);
1577 break;
aca7f966 1578 case 3: /* lidt/vmmcall */
e4e03ded 1579 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1580 rc = kvm_fix_hypercall(ctxt->vcpu);
1581 if (rc)
1582 goto done;
1583 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1584 } else {
e4e03ded 1585 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1586 &size, &address,
e4e03ded 1587 c->op_bytes);
aca7f966
AL		 1588 if (rc)
1589 goto done;
1590 realmode_lidt(ctxt->vcpu, size, address);
1591 }
6aa8b732
AK		 1592 break;
1593 case 4: /* smsw */
e4e03ded 1594 if (c->modrm_mod != 3)
6aa8b732 1595 goto cannot_emulate;
e4e03ded 1596 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1597 = realmode_get_cr(ctxt->vcpu, 0);
1598 break;
1599 case 6: /* lmsw */
e4e03ded 1600 if (c->modrm_mod != 3)
6aa8b732 1601 goto cannot_emulate;
05f086f8
LV		 1602 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val,
1603 &ctxt->eflags);
6aa8b732
AK		 1604 break;
1605 case 7: /* invlpg*/
1606 emulate_invlpg(ctxt->vcpu, cr2);
1607 break;
1608 default:
1609 goto cannot_emulate;
1610 }
a01af5ec
LV		 1611 /* Disable writeback. */
1612 c->dst.type = OP_NONE;
6aa8b732
AK		 1613 break;
1614 case 0x21: /* mov from dr to reg */
e4e03ded 1615 if (c->modrm_mod != 3)
6aa8b732 1616 goto cannot_emulate;
8cdbd2c9 1617 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
a01af5ec
LV		 1618 if (rc)
1619 goto cannot_emulate;
1620 c->dst.type = OP_NONE; /* no writeback */
6aa8b732
AK		 1621 break;
1622 case 0x23: /* mov from reg to dr */
e4e03ded 1623 if (c->modrm_mod != 3)
6aa8b732 1624 goto cannot_emulate;
e4e03ded
LV		 1625 rc = emulator_set_dr(ctxt, c->modrm_reg,
1626 c->regs[c->modrm_rm]);
a01af5ec
LV		 1627 if (rc)
1628 goto cannot_emulate;
1629 c->dst.type = OP_NONE; /* no writeback */
6aa8b732
AK		 1630 break;
1631 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1632 c->dst.val = c->dst.orig_val = c->src.val;
a01af5ec
LV		 1633 if (!test_cc(c->b, ctxt->eflags))
1634 c->dst.type = OP_NONE; /* no writeback */
6aa8b732 1635 break;
7de75248
NK		 1636 case 0xa3:
1637 bt: /* bt */
e4f8e039 1638 c->dst.type = OP_NONE;
e4e03ded
LV		 1639 /* only subword offset */
1640 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1641 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
7de75248
NK		 1642 break;
1643 case 0xab:
1644 bts: /* bts */
e4e03ded
LV		 1645 /* only subword offset */
1646 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1647 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
7de75248 1648 break;
6aa8b732
AK		 1649 case 0xb0 ... 0xb1: /* cmpxchg */
1650 /*
1651 * Save real source value, then compare EAX against
1652 * destination.
1653 */
e4e03ded
LV		 1654 c->src.orig_val = c->src.val;
1655 c->src.val = c->regs[VCPU_REGS_RAX];
05f086f8
LV		 1656 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1657 if (ctxt->eflags & EFLG_ZF) {
6aa8b732 1658 /* Success: write back to memory. */
e4e03ded 1659 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1660 } else {
1661 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1662 c->dst.type = OP_REG;
1663 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1664 }
1665 break;
6aa8b732
AK		 1666 case 0xb3:
1667 btr: /* btr */
e4e03ded
LV		 1668 /* only subword offset */
1669 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1670 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
6aa8b732 1671 break;
6aa8b732 1672 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1673 c->dst.bytes = c->op_bytes;
1674 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1675 : (u16) c->src.val;
6aa8b732 1676 break;
6aa8b732 1677 case 0xba: /* Grp8 */
e4e03ded 1678 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1679 case 0:
1680 goto bt;
1681 case 1:
1682 goto bts;
1683 case 2:
1684 goto btr;
1685 case 3:
1686 goto btc;
1687 }
1688 break;
7de75248
NK		 1689 case 0xbb:
1690 btc: /* btc */
e4e03ded
LV		 1691 /* only subword offset */
1692 c->src.val &= (c->dst.bytes << 3) - 1;
05f086f8 1693 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
7de75248 1694 break;
6aa8b732 1695 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1696 c->dst.bytes = c->op_bytes;
1697 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1698 (s16) c->src.val;
6aa8b732 1699 break;
a012e65a 1700 case 0xc3: /* movnti */
e4e03ded
LV		 1701 c->dst.bytes = c->op_bytes;
1702 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1703 (u64) c->src.val;
a012e65a 1704 break;
6aa8b732
AK		 1705 }
1706 goto writeback;
1707
1708twobyte_special_insn:
e4e03ded 1709 switch (c->b) {
7de75248
NK		 1710 case 0x06:
1711 emulate_clts(ctxt->vcpu);
1712 break;
651a3e29
AK		 1713 case 0x08: /* invd */
1714 break;
687fdbfe
AK		 1715 case 0x09: /* wbinvd */
1716 break;
6aa8b732
AK		 1717 case 0x0d: /* GrpP (prefetch) */
1718 case 0x18: /* Grp16 (prefetch/nop) */
1719 break;
6aa8b732 1720 case 0x20: /* mov cr, reg */
e4e03ded 1721 if (c->modrm_mod != 3)
6aa8b732 1722 goto cannot_emulate;
e4e03ded
LV		 1723 c->regs[c->modrm_rm] =
1724 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
6aa8b732
AK		 1725 break;
1726 case 0x22: /* mov reg, cr */
e4e03ded 1727 if (c->modrm_mod != 3)
6aa8b732 1728 goto cannot_emulate;
e4e03ded 1729 realmode_set_cr(ctxt->vcpu,
05f086f8 1730 c->modrm_reg, c->modrm_val, &ctxt->eflags);
6aa8b732 1731 break;
35f3f286
AK		 1732 case 0x30:
1733 /* wrmsr */
e4e03ded
LV		 1734 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1735 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1736 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
35f3f286 1737 if (rc) {
cbdd1bea 1738 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1739 c->eip = ctxt->vcpu->rip;
35f3f286
AK		 1740 }
1741 rc = X86EMUL_CONTINUE;
1742 break;
1743 case 0x32:
1744 /* rdmsr */
8cdbd2c9 1745 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
35f3f286 1746 if (rc) {
cbdd1bea 1747 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1748 c->eip = ctxt->vcpu->rip;
35f3f286 1749 } else {
e4e03ded
LV		 1750 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1751 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
35f3f286
AK		 1752 }
1753 rc = X86EMUL_CONTINUE;
1754 break;
bbe9abbd
NK		 1755 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1756 long int rel;
1757
e4e03ded 1758 switch (c->op_bytes) {
bbe9abbd 1759 case 2:
e4e03ded 1760 rel = insn_fetch(s16, 2, c->eip);
bbe9abbd
NK		 1761 break;
1762 case 4:
e4e03ded 1763 rel = insn_fetch(s32, 4, c->eip);
bbe9abbd
NK		 1764 break;
1765 case 8:
e4e03ded 1766 rel = insn_fetch(s64, 8, c->eip);
bbe9abbd
NK		 1767 break;
1768 default:
1769 DPRINTF("jnz: Invalid op_bytes\n");
1770 goto cannot_emulate;
1771 }
05f086f8 1772 if (test_cc(c->b, ctxt->eflags))
bbe9abbd
NK		 1773 JMP_REL(rel);
1774 break;
1775 }
6aa8b732 1776 case 0xc7: /* Grp9 (cmpxchg8b) */
05f086f8 1777 rc = emulate_grp9(ctxt, ops, cr2);
8cdbd2c9
LV		 1778 if (rc != 0)
1779 goto done;
1780 break;
6aa8b732 1781 }
a01af5ec
LV		 1782 /* Disable writeback. */
1783 c->dst.type = OP_NONE;
6aa8b732
AK		 1784 goto writeback;
1785
1786cannot_emulate:
e4e03ded 1787 DPRINTF("Cannot emulate %02x\n", c->b);
3427318f 1788 c->eip = saved_eip;
6aa8b732
AK		 1789 return -1;
1790}
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