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KVM: x86 emulator: move all x86_emulate_memop() to a structure
[mirror_ubuntu-zesty-kernel.git] / drivers / kvm / x86_emulate.c
CommitLineData
6aa8b732
AK		 1/******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
dcc0766b 9 * privileged instructions:
6aa8b732
AK		 10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22#ifndef __KERNEL__
23#include <stdio.h>
24#include <stdint.h>
25#include <public/xen.h>
26#define DPRINTF(_f, _a ...) printf( _f , ## _a )
27#else
28#include "kvm.h"
29#define DPRINTF(x...) do {} while (0)
30#endif
31#include "x86_emulate.h"
32#include <linux/module.h>
33
34/*
35 * Opcode effective-address decode tables.
36 * Note that we only emulate instructions that have at least one memory
37 * operand (excluding implicit stack references). We assume that stack
38 * references and instruction fetches will never occur in special memory
39 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
40 * not be handled.
41 */
42
43/* Operand sizes: 8-bit operands or specified/overridden size. */
44#define ByteOp (1<<0) /* 8-bit operands. */
45/* Destination operand type. */
46#define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
47#define DstReg (2<<1) /* Register operand. */
48#define DstMem (3<<1) /* Memory operand. */
49#define DstMask (3<<1)
50/* Source operand type. */
51#define SrcNone (0<<3) /* No source operand. */
52#define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
53#define SrcReg (1<<3) /* Register operand. */
54#define SrcMem (2<<3) /* Memory operand. */
55#define SrcMem16 (3<<3) /* Memory operand (16-bit). */
56#define SrcMem32 (4<<3) /* Memory operand (32-bit). */
57#define SrcImm (5<<3) /* Immediate operand. */
58#define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */
59#define SrcMask (7<<3)
60/* Generic ModRM decode. */
61#define ModRM (1<<6)
62/* Destination is only written; never read. */
63#define Mov (1<<7)
038e51de 64#define BitOp (1<<8)
6aa8b732
AK		 65
66static u8 opcode_table[256] = {
67 /* 0x00 - 0x07 */
68 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
69 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
70 0, 0, 0, 0,
71 /* 0x08 - 0x0F */
72 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
73 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
74 0, 0, 0, 0,
75 /* 0x10 - 0x17 */
76 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
77 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
78 0, 0, 0, 0,
79 /* 0x18 - 0x1F */
80 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
81 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
82 0, 0, 0, 0,
83 /* 0x20 - 0x27 */
84 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
85 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
19eb938e 86 SrcImmByte, SrcImm, 0, 0,
6aa8b732
AK		 87 /* 0x28 - 0x2F */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 0, 0, 0, 0,
91 /* 0x30 - 0x37 */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x38 - 0x3F */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x40 - 0x4F */
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7f0aaee0 101 /* 0x50 - 0x57 */
7e778161
NK		 102 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
103 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7f0aaee0
NK		 104 /* 0x58 - 0x5F */
105 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
106 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
7d316911 107 /* 0x60 - 0x67 */
6aa8b732 108 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
7d316911
NK		 109 0, 0, 0, 0,
110 /* 0x68 - 0x6F */
111 0, 0, ImplicitOps|Mov, 0,
e70669ab
LV		 112 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
113 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
55bebde4
NK		 114 /* 0x70 - 0x77 */
115 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 /* 0x78 - 0x7F */
118 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
119 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 120 /* 0x80 - 0x87 */
121 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
122 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
123 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
124 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
125 /* 0x88 - 0x8F */
126 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
127 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
7e0b54b1 128 0, ModRM | DstReg, 0, DstMem | SrcNone | ModRM | Mov,
6aa8b732 129 /* 0x90 - 0x9F */
535eabcf 130 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps, ImplicitOps, 0, 0,
6aa8b732
AK		 131 /* 0xA0 - 0xA7 */
132 ByteOp | DstReg | SrcMem | Mov, DstReg | SrcMem | Mov,
133 ByteOp | DstMem | SrcReg | Mov, DstMem | SrcReg | Mov,
134 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
135 ByteOp | ImplicitOps, ImplicitOps,
136 /* 0xA8 - 0xAF */
137 0, 0, ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
138 ByteOp | ImplicitOps | Mov, ImplicitOps | Mov,
139 ByteOp | ImplicitOps, ImplicitOps,
140 /* 0xB0 - 0xBF */
141 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
142 /* 0xC0 - 0xC7 */
d9413cd7
NK		 143 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
144 0, ImplicitOps, 0, 0,
145 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
6aa8b732
AK		 146 /* 0xC8 - 0xCF */
147 0, 0, 0, 0, 0, 0, 0, 0,
148 /* 0xD0 - 0xD7 */
149 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
150 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
151 0, 0, 0, 0,
152 /* 0xD8 - 0xDF */
153 0, 0, 0, 0, 0, 0, 0, 0,
098c937b
NK		 154 /* 0xE0 - 0xE7 */
155 0, 0, 0, 0, 0, 0, 0, 0,
156 /* 0xE8 - 0xEF */
f6eed391 157 ImplicitOps, SrcImm|ImplicitOps, 0, SrcImmByte|ImplicitOps, 0, 0, 0, 0,
6aa8b732
AK		 158 /* 0xF0 - 0xF7 */
159 0, 0, 0, 0,
72d6e5a0
AK		 160 ImplicitOps, 0,
161 ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
6aa8b732
AK		 162 /* 0xF8 - 0xFF */
163 0, 0, 0, 0,
164 0, 0, ByteOp | DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM
165};
166
038e51de 167static u16 twobyte_table[256] = {
6aa8b732
AK		 168 /* 0x00 - 0x0F */
169 0, SrcMem | ModRM | DstReg, 0, 0, 0, 0, ImplicitOps, 0,
651a3e29 170 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
6aa8b732
AK		 171 /* 0x10 - 0x1F */
172 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x20 - 0x2F */
174 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
175 0, 0, 0, 0, 0, 0, 0, 0,
176 /* 0x30 - 0x3F */
35f3f286 177 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 178 /* 0x40 - 0x47 */
179 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
180 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
181 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
182 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
183 /* 0x48 - 0x4F */
184 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
185 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
186 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
187 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
188 /* 0x50 - 0x5F */
189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 /* 0x60 - 0x6F */
191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* 0x70 - 0x7F */
193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* 0x80 - 0x8F */
bbe9abbd
NK		 195 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
196 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
197 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
198 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
6aa8b732
AK		 199 /* 0x90 - 0x9F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 /* 0xA0 - 0xA7 */
038e51de 202 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732 203 /* 0xA8 - 0xAF */
038e51de 204 0, 0, 0, DstMem | SrcReg | ModRM | BitOp, 0, 0, 0, 0,
6aa8b732
AK		 205 /* 0xB0 - 0xB7 */
206 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
038e51de 207 DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 208 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
209 DstReg | SrcMem16 | ModRM | Mov,
210 /* 0xB8 - 0xBF */
038e51de 211 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
6aa8b732
AK		 212 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
213 DstReg | SrcMem16 | ModRM | Mov,
214 /* 0xC0 - 0xCF */
a012e65a
SY		 215 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
216 0, 0, 0, 0, 0, 0, 0, 0,
6aa8b732
AK		 217 /* 0xD0 - 0xDF */
218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
219 /* 0xE0 - 0xEF */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
221 /* 0xF0 - 0xFF */
222 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
223};
224
6aa8b732
AK		 225/* EFLAGS bit definitions. */
226#define EFLG_OF (1<<11)
227#define EFLG_DF (1<<10)
228#define EFLG_SF (1<<7)
229#define EFLG_ZF (1<<6)
230#define EFLG_AF (1<<4)
231#define EFLG_PF (1<<2)
232#define EFLG_CF (1<<0)
233
234/*
235 * Instruction emulation:
236 * Most instructions are emulated directly via a fragment of inline assembly
237 * code. This allows us to save/restore EFLAGS and thus very easily pick up
238 * any modified flags.
239 */
240
05b3e0c2 241#if defined(CONFIG_X86_64)
6aa8b732
AK		 242#define _LO32 "k" /* force 32-bit operand */
243#define _STK "%%rsp" /* stack pointer */
244#elif defined(__i386__)
245#define _LO32 "" /* force 32-bit operand */
246#define _STK "%%esp" /* stack pointer */
247#endif
248
249/*
250 * These EFLAGS bits are restored from saved value during emulation, and
251 * any changes are written back to the saved value after emulation.
252 */
253#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
254
255/* Before executing instruction: restore necessary bits in EFLAGS. */
256#define _PRE_EFLAGS(_sav, _msk, _tmp) \
257 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); */ \
258 "push %"_sav"; " \
259 "movl %"_msk",%"_LO32 _tmp"; " \
260 "andl %"_LO32 _tmp",("_STK"); " \
261 "pushf; " \
262 "notl %"_LO32 _tmp"; " \
263 "andl %"_LO32 _tmp",("_STK"); " \
264 "pop %"_tmp"; " \
265 "orl %"_LO32 _tmp",("_STK"); " \
266 "popf; " \
267 /* _sav &= ~msk; */ \
268 "movl %"_msk",%"_LO32 _tmp"; " \
269 "notl %"_LO32 _tmp"; " \
270 "andl %"_LO32 _tmp",%"_sav"; "
271
272/* After executing instruction: write-back necessary bits in EFLAGS. */
273#define _POST_EFLAGS(_sav, _msk, _tmp) \
274 /* _sav |= EFLAGS & _msk; */ \
275 "pushf; " \
276 "pop %"_tmp"; " \
277 "andl %"_msk",%"_LO32 _tmp"; " \
278 "orl %"_LO32 _tmp",%"_sav"; "
279
280/* Raw emulation: instruction has two explicit operands. */
281#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
282 do { \
283 unsigned long _tmp; \
284 \
285 switch ((_dst).bytes) { \
286 case 2: \
287 __asm__ __volatile__ ( \
288 _PRE_EFLAGS("0","4","2") \
289 _op"w %"_wx"3,%1; " \
290 _POST_EFLAGS("0","4","2") \
291 : "=m" (_eflags), "=m" ((_dst).val), \
292 "=&r" (_tmp) \
293 : _wy ((_src).val), "i" (EFLAGS_MASK) ); \
294 break; \
295 case 4: \
296 __asm__ __volatile__ ( \
297 _PRE_EFLAGS("0","4","2") \
298 _op"l %"_lx"3,%1; " \
299 _POST_EFLAGS("0","4","2") \
300 : "=m" (_eflags), "=m" ((_dst).val), \
301 "=&r" (_tmp) \
302 : _ly ((_src).val), "i" (EFLAGS_MASK) ); \
303 break; \
304 case 8: \
305 __emulate_2op_8byte(_op, _src, _dst, \
306 _eflags, _qx, _qy); \
307 break; \
308 } \
309 } while (0)
310
311#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
312 do { \
313 unsigned long _tmp; \
314 switch ( (_dst).bytes ) \
315 { \
316 case 1: \
317 __asm__ __volatile__ ( \
318 _PRE_EFLAGS("0","4","2") \
319 _op"b %"_bx"3,%1; " \
320 _POST_EFLAGS("0","4","2") \
321 : "=m" (_eflags), "=m" ((_dst).val), \
322 "=&r" (_tmp) \
323 : _by ((_src).val), "i" (EFLAGS_MASK) ); \
324 break; \
325 default: \
326 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
327 _wx, _wy, _lx, _ly, _qx, _qy); \
328 break; \
329 } \
330 } while (0)
331
332/* Source operand is byte-sized and may be restricted to just %cl. */
333#define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
334 __emulate_2op(_op, _src, _dst, _eflags, \
335 "b", "c", "b", "c", "b", "c", "b", "c")
336
337/* Source operand is byte, word, long or quad sized. */
338#define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
339 __emulate_2op(_op, _src, _dst, _eflags, \
340 "b", "q", "w", "r", _LO32, "r", "", "r")
341
342/* Source operand is word, long or quad sized. */
343#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
344 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
345 "w", "r", _LO32, "r", "", "r")
346
347/* Instruction has only one explicit operand (no source operand). */
348#define emulate_1op(_op, _dst, _eflags) \
349 do { \
350 unsigned long _tmp; \
351 \
352 switch ( (_dst).bytes ) \
353 { \
354 case 1: \
355 __asm__ __volatile__ ( \
356 _PRE_EFLAGS("0","3","2") \
357 _op"b %1; " \
358 _POST_EFLAGS("0","3","2") \
359 : "=m" (_eflags), "=m" ((_dst).val), \
360 "=&r" (_tmp) \
361 : "i" (EFLAGS_MASK) ); \
362 break; \
363 case 2: \
364 __asm__ __volatile__ ( \
365 _PRE_EFLAGS("0","3","2") \
366 _op"w %1; " \
367 _POST_EFLAGS("0","3","2") \
368 : "=m" (_eflags), "=m" ((_dst).val), \
369 "=&r" (_tmp) \
370 : "i" (EFLAGS_MASK) ); \
371 break; \
372 case 4: \
373 __asm__ __volatile__ ( \
374 _PRE_EFLAGS("0","3","2") \
375 _op"l %1; " \
376 _POST_EFLAGS("0","3","2") \
377 : "=m" (_eflags), "=m" ((_dst).val), \
378 "=&r" (_tmp) \
379 : "i" (EFLAGS_MASK) ); \
380 break; \
381 case 8: \
382 __emulate_1op_8byte(_op, _dst, _eflags); \
383 break; \
384 } \
385 } while (0)
386
387/* Emulate an instruction with quadword operands (x86/64 only). */
05b3e0c2 388#if defined(CONFIG_X86_64)
6aa8b732
AK		 389#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
390 do { \
391 __asm__ __volatile__ ( \
392 _PRE_EFLAGS("0","4","2") \
393 _op"q %"_qx"3,%1; " \
394 _POST_EFLAGS("0","4","2") \
395 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
396 : _qy ((_src).val), "i" (EFLAGS_MASK) ); \
397 } while (0)
398
399#define __emulate_1op_8byte(_op, _dst, _eflags) \
400 do { \
401 __asm__ __volatile__ ( \
402 _PRE_EFLAGS("0","3","2") \
403 _op"q %1; " \
404 _POST_EFLAGS("0","3","2") \
405 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
406 : "i" (EFLAGS_MASK) ); \
407 } while (0)
408
409#elif defined(__i386__)
410#define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
411#define __emulate_1op_8byte(_op, _dst, _eflags)
412#endif /* __i386__ */
413
414/* Fetch next part of the instruction being emulated. */
415#define insn_fetch(_type, _size, _eip) \
416({ unsigned long _x; \
417 rc = ops->read_std((unsigned long)(_eip) + ctxt->cs_base, &_x, \
cebff02b 418 (_size), ctxt->vcpu); \
6aa8b732
AK		 419 if ( rc != 0 ) \
420 goto done; \
421 (_eip) += (_size); \
422 (_type)_x; \
423})
424
425/* Access/update address held in a register, based on addressing mode. */
e70669ab 426#define address_mask(reg) \
e4e03ded
LV		 427 ((c->ad_bytes == sizeof(unsigned long)) ? \
428 (reg) : ((reg) & ((1UL << (c->ad_bytes << 3)) - 1)))
6aa8b732 429#define register_address(base, reg) \
e70669ab 430 ((base) + address_mask(reg))
6aa8b732
AK		 431#define register_address_increment(reg, inc) \
432 do { \
433 /* signed type ensures sign extension to long */ \
434 int _inc = (inc); \
e4e03ded 435 if (c->ad_bytes == sizeof(unsigned long)) \
6aa8b732
AK		 436 (reg) += _inc; \
437 else \
e4e03ded
LV		 438 (reg) = ((reg) & \
439 ~((1UL << (c->ad_bytes << 3)) - 1)) | \
440 (((reg) + _inc) & \
441 ((1UL << (c->ad_bytes << 3)) - 1)); \
6aa8b732
AK		 442 } while (0)
443
098c937b
NK		 444#define JMP_REL(rel) \
445 do { \
e4e03ded 446 register_address_increment(c->eip, rel); \
098c937b
NK		 447 } while (0)
448
1e3c5cb0
RR		 449/*
450 * Given the 'reg' portion of a ModRM byte, and a register block, return a
451 * pointer into the block that addresses the relevant register.
452 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
453 */
454static void *decode_register(u8 modrm_reg, unsigned long *regs,
455 int highbyte_regs)
6aa8b732
AK		 456{
457 void *p;
458
459 p = &regs[modrm_reg];
460 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
461 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
462 return p;
463}
464
465static int read_descriptor(struct x86_emulate_ctxt *ctxt,
466 struct x86_emulate_ops *ops,
467 void *ptr,
468 u16 *size, unsigned long *address, int op_bytes)
469{
470 int rc;
471
472 if (op_bytes == 2)
473 op_bytes = 3;
474 *address = 0;
cebff02b
LV		 475 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
476 ctxt->vcpu);
6aa8b732
AK		 477 if (rc)
478 return rc;
cebff02b
LV		 479 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
480 ctxt->vcpu);
6aa8b732
AK		 481 return rc;
482}
483
bbe9abbd
NK		 484static int test_cc(unsigned int condition, unsigned int flags)
485{
486 int rc = 0;
487
488 switch ((condition & 15) >> 1) {
489 case 0: /* o */
490 rc |= (flags & EFLG_OF);
491 break;
492 case 1: /* b/c/nae */
493 rc |= (flags & EFLG_CF);
494 break;
495 case 2: /* z/e */
496 rc |= (flags & EFLG_ZF);
497 break;
498 case 3: /* be/na */
499 rc |= (flags & (EFLG_CF|EFLG_ZF));
500 break;
501 case 4: /* s */
502 rc |= (flags & EFLG_SF);
503 break;
504 case 5: /* p/pe */
505 rc |= (flags & EFLG_PF);
506 break;
507 case 7: /* le/ng */
508 rc |= (flags & EFLG_ZF);
509 /* fall through */
510 case 6: /* l/nge */
511 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
512 break;
513 }
514
515 /* Odd condition identifiers (lsb == 1) have inverted sense. */
516 return (!!rc ^ (condition & 1));
517}
518
6aa8b732
AK		 519int
520x86_emulate_memop(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
521{
e4e03ded
LV		 522 struct decode_cache *c = &ctxt->decode;
523 u8 sib, rex_prefix = 0;
524 unsigned int i;
6aa8b732 525 int rc = 0;
6aa8b732
AK		 526 unsigned long cr2 = ctxt->cr2;
527 int mode = ctxt->mode;
e4e03ded 528 int index_reg = 0, base_reg = 0, scale, rip_relative = 0;
02c03a32 529 int no_wb = 0;
35f3f286 530 u64 msr_data;
6aa8b732
AK		 531
532 /* Shadow copy of register state. Committed on successful emulation. */
e4e03ded 533 unsigned long _eflags = ctxt->eflags;
6aa8b732 534
e4e03ded
LV		 535 memset(c, 0, sizeof(struct decode_cache));
536 c->eip = ctxt->vcpu->rip;
537 memcpy(c->regs, ctxt->vcpu->regs, sizeof c->regs);
6aa8b732
AK		 538
539 switch (mode) {
540 case X86EMUL_MODE_REAL:
541 case X86EMUL_MODE_PROT16:
e4e03ded 542 c->op_bytes = c->ad_bytes = 2;
6aa8b732
AK		 543 break;
544 case X86EMUL_MODE_PROT32:
e4e03ded 545 c->op_bytes = c->ad_bytes = 4;
6aa8b732 546 break;
05b3e0c2 547#ifdef CONFIG_X86_64
6aa8b732 548 case X86EMUL_MODE_PROT64:
e4e03ded
LV		 549 c->op_bytes = 4;
550 c->ad_bytes = 8;
6aa8b732
AK		 551 break;
552#endif
553 default:
554 return -1;
555 }
556
557 /* Legacy prefixes. */
558 for (i = 0; i < 8; i++) {
e4e03ded 559 switch (c->b = insn_fetch(u8, 1, c->eip)) {
6aa8b732 560 case 0x66: /* operand-size override */
e4e03ded 561 c->op_bytes ^= 6; /* switch between 2/4 bytes */
6aa8b732
AK		 562 break;
563 case 0x67: /* address-size override */
564 if (mode == X86EMUL_MODE_PROT64)
e4e03ded
LV		 565 /* switch between 4/8 bytes */
566 c->ad_bytes ^= 12;
6aa8b732 567 else
e4e03ded
LV		 568 /* switch between 2/4 bytes */
569 c->ad_bytes ^= 6;
6aa8b732
AK		 570 break;
571 case 0x2e: /* CS override */
e4e03ded 572 c->override_base = &ctxt->cs_base;
6aa8b732
AK		 573 break;
574 case 0x3e: /* DS override */
e4e03ded 575 c->override_base = &ctxt->ds_base;
6aa8b732
AK		 576 break;
577 case 0x26: /* ES override */
e4e03ded 578 c->override_base = &ctxt->es_base;
6aa8b732
AK		 579 break;
580 case 0x64: /* FS override */
e4e03ded 581 c->override_base = &ctxt->fs_base;
6aa8b732
AK		 582 break;
583 case 0x65: /* GS override */
e4e03ded 584 c->override_base = &ctxt->gs_base;
6aa8b732
AK		 585 break;
586 case 0x36: /* SS override */
e4e03ded 587 c->override_base = &ctxt->ss_base;
6aa8b732
AK		 588 break;
589 case 0xf0: /* LOCK */
e4e03ded 590 c->lock_prefix = 1;
6aa8b732 591 break;
ae6200ba 592 case 0xf2: /* REPNE/REPNZ */
6aa8b732 593 case 0xf3: /* REP/REPE/REPZ */
e4e03ded 594 c->rep_prefix = 1;
6aa8b732 595 break;
6aa8b732
AK		 596 default:
597 goto done_prefixes;
598 }
599 }
600
601done_prefixes:
602
603 /* REX prefix. */
e4e03ded
LV		 604 if ((mode == X86EMUL_MODE_PROT64) && ((c->b & 0xf0) == 0x40)) {
605 rex_prefix = c->b;
606 if (c->b & 8)
607 c->op_bytes = 8; /* REX.W */
608 c->modrm_reg = (c->b & 4) << 1; /* REX.R */
609 index_reg = (c->b & 2) << 2; /* REX.X */
610 c->modrm_rm = base_reg = (c->b & 1) << 3; /* REG.B */
611 c->b = insn_fetch(u8, 1, c->eip);
6aa8b732
AK		 612 }
613
614 /* Opcode byte(s). */
e4e03ded
LV		 615 c->d = opcode_table[c->b];
616 if (c->d == 0) {
6aa8b732 617 /* Two-byte opcode? */
e4e03ded
LV		 618 if (c->b == 0x0f) {
619 c->twobyte = 1;
620 c->b = insn_fetch(u8, 1, c->eip);
621 c->d = twobyte_table[c->b];
6aa8b732
AK		 622 }
623
624 /* Unrecognised? */
e4e03ded 625 if (c->d == 0)
6aa8b732
AK		 626 goto cannot_emulate;
627 }
628
629 /* ModRM and SIB bytes. */
e4e03ded
LV		 630 if (c->d & ModRM) {
631 c->modrm = insn_fetch(u8, 1, c->eip);
632 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
633 c->modrm_reg |= (c->modrm & 0x38) >> 3;
634 c->modrm_rm |= (c->modrm & 0x07);
635 c->modrm_ea = 0;
636 c->use_modrm_ea = 1;
637
638 if (c->modrm_mod == 3) {
639 c->modrm_val = *(unsigned long *)
640 decode_register(c->modrm_rm, c->regs, c->d & ByteOp);
6aa8b732
AK		 641 goto modrm_done;
642 }
643
e4e03ded
LV		 644 if (c->ad_bytes == 2) {
645 unsigned bx = c->regs[VCPU_REGS_RBX];
646 unsigned bp = c->regs[VCPU_REGS_RBP];
647 unsigned si = c->regs[VCPU_REGS_RSI];
648 unsigned di = c->regs[VCPU_REGS_RDI];
6aa8b732
AK		 649
650 /* 16-bit ModR/M decode. */
e4e03ded 651 switch (c->modrm_mod) {
6aa8b732 652 case 0:
e4e03ded
LV		 653 if (c->modrm_rm == 6)
654 c->modrm_ea +=
655 insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 656 break;
657 case 1:
e4e03ded 658 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 659 break;
660 case 2:
e4e03ded 661 c->modrm_ea += insn_fetch(u16, 2, c->eip);
6aa8b732
AK		 662 break;
663 }
e4e03ded 664 switch (c->modrm_rm) {
6aa8b732 665 case 0:
e4e03ded 666 c->modrm_ea += bx + si;
6aa8b732
AK		 667 break;
668 case 1:
e4e03ded 669 c->modrm_ea += bx + di;
6aa8b732
AK		 670 break;
671 case 2:
e4e03ded 672 c->modrm_ea += bp + si;
6aa8b732
AK		 673 break;
674 case 3:
e4e03ded 675 c->modrm_ea += bp + di;
6aa8b732
AK		 676 break;
677 case 4:
e4e03ded 678 c->modrm_ea += si;
6aa8b732
AK		 679 break;
680 case 5:
e4e03ded 681 c->modrm_ea += di;
6aa8b732
AK		 682 break;
683 case 6:
e4e03ded
LV		 684 if (c->modrm_mod != 0)
685 c->modrm_ea += bp;
6aa8b732
AK		 686 break;
687 case 7:
e4e03ded 688 c->modrm_ea += bx;
6aa8b732
AK		 689 break;
690 }
e4e03ded
LV		 691 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
692 (c->modrm_rm == 6 && c->modrm_mod != 0))
693 if (!c->override_base)
694 c->override_base = &ctxt->ss_base;
695 c->modrm_ea = (u16)c->modrm_ea;
6aa8b732
AK		 696 } else {
697 /* 32/64-bit ModR/M decode. */
e4e03ded 698 switch (c->modrm_rm) {
6aa8b732
AK		 699 case 4:
700 case 12:
e4e03ded 701 sib = insn_fetch(u8, 1, c->eip);
6aa8b732
AK		 702 index_reg |= (sib >> 3) & 7;
703 base_reg |= sib & 7;
704 scale = sib >> 6;
705
706 switch (base_reg) {
707 case 5:
e4e03ded
LV		 708 if (c->modrm_mod != 0)
709 c->modrm_ea +=
710 c->regs[base_reg];
6aa8b732 711 else
e4e03ded
LV		 712 c->modrm_ea +=
713 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 714 break;
715 default:
e4e03ded 716 c->modrm_ea += c->regs[base_reg];
6aa8b732
AK		 717 }
718 switch (index_reg) {
719 case 4:
720 break;
721 default:
e4e03ded
LV		 722 c->modrm_ea +=
723 c->regs[index_reg] << scale;
6aa8b732
AK		 724
725 }
726 break;
727 case 5:
e4e03ded
LV		 728 if (c->modrm_mod != 0)
729 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 730 else if (mode == X86EMUL_MODE_PROT64)
731 rip_relative = 1;
732 break;
733 default:
e4e03ded 734 c->modrm_ea += c->regs[c->modrm_rm];
6aa8b732
AK		 735 break;
736 }
e4e03ded 737 switch (c->modrm_mod) {
6aa8b732 738 case 0:
e4e03ded
LV		 739 if (c->modrm_rm == 5)
740 c->modrm_ea +=
741 insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 742 break;
743 case 1:
e4e03ded 744 c->modrm_ea += insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 745 break;
746 case 2:
e4e03ded 747 c->modrm_ea += insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 748 break;
749 }
750 }
e4e03ded
LV		 751 if (!c->override_base)
752 c->override_base = &ctxt->ds_base;
6aa8b732 753 if (mode == X86EMUL_MODE_PROT64 &&
e4e03ded
LV		 754 c->override_base != &ctxt->fs_base &&
755 c->override_base != &ctxt->gs_base)
756 c->override_base = NULL;
6aa8b732 757
e4e03ded
LV		 758 if (c->override_base)
759 c->modrm_ea += *c->override_base;
6aa8b732
AK		 760
761 if (rip_relative) {
e4e03ded
LV		 762 c->modrm_ea += c->eip;
763 switch (c->d & SrcMask) {
6aa8b732 764 case SrcImmByte:
e4e03ded 765 c->modrm_ea += 1;
6aa8b732
AK		 766 break;
767 case SrcImm:
e4e03ded
LV		 768 if (c->d & ByteOp)
769 c->modrm_ea += 1;
6aa8b732 770 else
e4e03ded
LV		 771 if (c->op_bytes == 8)
772 c->modrm_ea += 4;
6aa8b732 773 else
e4e03ded 774 c->modrm_ea += c->op_bytes;
6aa8b732
AK		 775 }
776 }
e4e03ded
LV		 777 if (c->ad_bytes != 8)
778 c->modrm_ea = (u32)c->modrm_ea;
779 cr2 = c->modrm_ea;
6aa8b732
AK		 780 modrm_done:
781 ;
782 }
783
6aa8b732
AK		 784 /*
785 * Decode and fetch the source operand: register, memory
786 * or immediate.
787 */
e4e03ded 788 switch (c->d & SrcMask) {
6aa8b732
AK		 789 case SrcNone:
790 break;
791 case SrcReg:
e4e03ded
LV		 792 c->src.type = OP_REG;
793 if (c->d & ByteOp) {
794 c->src.ptr =
795 decode_register(c->modrm_reg, c->regs,
6aa8b732 796 (rex_prefix == 0));
e4e03ded
LV		 797 c->src.val = c->src.orig_val = *(u8 *)c->src.ptr;
798 c->src.bytes = 1;
6aa8b732 799 } else {
e4e03ded
LV		 800 c->src.ptr =
801 decode_register(c->modrm_reg, c->regs, 0);
802 switch ((c->src.bytes = c->op_bytes)) {
6aa8b732 803 case 2:
e4e03ded
LV		 804 c->src.val = c->src.orig_val =
805 *(u16 *) c->src.ptr;
6aa8b732
AK		 806 break;
807 case 4:
e4e03ded
LV		 808 c->src.val = c->src.orig_val =
809 *(u32 *) c->src.ptr;
6aa8b732
AK		 810 break;
811 case 8:
e4e03ded
LV		 812 c->src.val = c->src.orig_val =
813 *(u64 *) c->src.ptr;
6aa8b732
AK		 814 break;
815 }
816 }
817 break;
818 case SrcMem16:
e4e03ded 819 c->src.bytes = 2;
6aa8b732
AK		 820 goto srcmem_common;
821 case SrcMem32:
e4e03ded 822 c->src.bytes = 4;
6aa8b732
AK		 823 goto srcmem_common;
824 case SrcMem:
e4e03ded
LV		 825 c->src.bytes = (c->d & ByteOp) ? 1 :
826 c->op_bytes;
b85b9ee9 827 /* Don't fetch the address for invlpg: it could be unmapped. */
e4e03ded
LV		 828 if (c->twobyte && c->b == 0x01
829 && c->modrm_reg == 7)
b85b9ee9 830 break;
6aa8b732 831 srcmem_common:
4e62417b
AJ		 832 /*
833 * For instructions with a ModR/M byte, switch to register
834 * access if Mod = 3.
835 */
e4e03ded
LV		 836 if ((c->d & ModRM) && c->modrm_mod == 3) {
837 c->src.type = OP_REG;
4e62417b
AJ		 838 break;
839 }
e4e03ded
LV		 840 c->src.type = OP_MEM;
841 c->src.ptr = (unsigned long *)cr2;
842 c->src.val = 0;
843 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
844 &c->src.val,
845 c->src.bytes, ctxt->vcpu)) != 0)
6aa8b732 846 goto done;
e4e03ded 847 c->src.orig_val = c->src.val;
6aa8b732
AK		 848 break;
849 case SrcImm:
e4e03ded
LV		 850 c->src.type = OP_IMM;
851 c->src.ptr = (unsigned long *)c->eip;
852 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
853 if (c->src.bytes == 8)
854 c->src.bytes = 4;
6aa8b732 855 /* NB. Immediates are sign-extended as necessary. */
e4e03ded 856 switch (c->src.bytes) {
6aa8b732 857 case 1:
e4e03ded 858 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 859 break;
860 case 2:
e4e03ded 861 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 862 break;
863 case 4:
e4e03ded 864 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 865 break;
866 }
867 break;
868 case SrcImmByte:
e4e03ded
LV		 869 c->src.type = OP_IMM;
870 c->src.ptr = (unsigned long *)c->eip;
871 c->src.bytes = 1;
872 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 873 break;
874 }
875
038e51de 876 /* Decode and fetch the destination operand: register or memory. */
e4e03ded 877 switch (c->d & DstMask) {
038e51de
AK		 878 case ImplicitOps:
879 /* Special instructions do their own operand decoding. */
880 goto special_insn;
881 case DstReg:
e4e03ded
LV		 882 c->dst.type = OP_REG;
883 if ((c->d & ByteOp)
884 && !(c->twobyte &&
885 (c->b == 0xb6 || c->b == 0xb7))) {
886 c->dst.ptr =
887 decode_register(c->modrm_reg, c->regs,
038e51de 888 (rex_prefix == 0));
e4e03ded
LV		 889 c->dst.val = *(u8 *) c->dst.ptr;
890 c->dst.bytes = 1;
038e51de 891 } else {
e4e03ded
LV		 892 c->dst.ptr =
893 decode_register(c->modrm_reg, c->regs, 0);
894 switch ((c->dst.bytes = c->op_bytes)) {
038e51de 895 case 2:
e4e03ded 896 c->dst.val = *(u16 *)c->dst.ptr;
038e51de
AK		 897 break;
898 case 4:
e4e03ded 899 c->dst.val = *(u32 *)c->dst.ptr;
038e51de
AK		 900 break;
901 case 8:
e4e03ded 902 c->dst.val = *(u64 *)c->dst.ptr;
038e51de
AK		 903 break;
904 }
905 }
906 break;
907 case DstMem:
e4e03ded
LV		 908 c->dst.type = OP_MEM;
909 c->dst.ptr = (unsigned long *)cr2;
910 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
911 c->dst.val = 0;
912 if ((c->d & ModRM) && c->modrm_mod == 3) {
913 c->dst.type = OP_REG;
4e62417b
AJ		 914 break;
915 }
e4e03ded
LV		 916 if (c->d & BitOp) {
917 unsigned long mask = ~(c->dst.bytes * 8 - 1);
df513e2c 918
e4e03ded
LV		 919 c->dst.ptr = (void *)c->dst.ptr +
920 (c->src.val & mask) / 8;
038e51de 921 }
e4e03ded
LV		 922 if (!(c->d & Mov) &&
923 /* optimisation - avoid slow emulated read */
924 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
925 &c->dst.val,
926 c->dst.bytes, ctxt->vcpu)) != 0))
038e51de
AK		 927 goto done;
928 break;
929 }
e4e03ded 930 c->dst.orig_val = c->dst.val;
038e51de 931
e4e03ded 932 if (c->twobyte)
6aa8b732
AK		 933 goto twobyte_insn;
934
e4e03ded 935 switch (c->b) {
6aa8b732
AK		 936 case 0x00 ... 0x05:
937 add: /* add */
e4e03ded 938 emulate_2op_SrcV("add", c->src, c->dst, _eflags);
6aa8b732
AK		 939 break;
940 case 0x08 ... 0x0d:
941 or: /* or */
e4e03ded 942 emulate_2op_SrcV("or", c->src, c->dst, _eflags);
6aa8b732
AK		 943 break;
944 case 0x10 ... 0x15:
945 adc: /* adc */
e4e03ded 946 emulate_2op_SrcV("adc", c->src, c->dst, _eflags);
6aa8b732
AK		 947 break;
948 case 0x18 ... 0x1d:
949 sbb: /* sbb */
e4e03ded 950 emulate_2op_SrcV("sbb", c->src, c->dst, _eflags);
6aa8b732 951 break;
19eb938e 952 case 0x20 ... 0x23:
6aa8b732 953 and: /* and */
e4e03ded 954 emulate_2op_SrcV("and", c->src, c->dst, _eflags);
6aa8b732 955 break;
19eb938e 956 case 0x24: /* and al imm8 */
e4e03ded
LV		 957 c->dst.type = OP_REG;
958 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
959 c->dst.val = *(u8 *)c->dst.ptr;
960 c->dst.bytes = 1;
961 c->dst.orig_val = c->dst.val;
19eb938e
NK		 962 goto and;
963 case 0x25: /* and ax imm16, or eax imm32 */
e4e03ded
LV		 964 c->dst.type = OP_REG;
965 c->dst.bytes = c->op_bytes;
966 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
967 if (c->op_bytes == 2)
968 c->dst.val = *(u16 *)c->dst.ptr;
19eb938e 969 else
e4e03ded
LV		 970 c->dst.val = *(u32 *)c->dst.ptr;
971 c->dst.orig_val = c->dst.val;
19eb938e 972 goto and;
6aa8b732
AK		 973 case 0x28 ... 0x2d:
974 sub: /* sub */
e4e03ded 975 emulate_2op_SrcV("sub", c->src, c->dst, _eflags);
6aa8b732
AK		 976 break;
977 case 0x30 ... 0x35:
978 xor: /* xor */
e4e03ded 979 emulate_2op_SrcV("xor", c->src, c->dst, _eflags);
6aa8b732
AK		 980 break;
981 case 0x38 ... 0x3d:
982 cmp: /* cmp */
e4e03ded 983 emulate_2op_SrcV("cmp", c->src, c->dst, _eflags);
6aa8b732
AK		 984 break;
985 case 0x63: /* movsxd */
986 if (mode != X86EMUL_MODE_PROT64)
987 goto cannot_emulate;
e4e03ded 988 c->dst.val = (s32) c->src.val;
6aa8b732
AK		 989 break;
990 case 0x80 ... 0x83: /* Grp1 */
e4e03ded 991 switch (c->modrm_reg) {
6aa8b732
AK		 992 case 0:
993 goto add;
994 case 1:
995 goto or;
996 case 2:
997 goto adc;
998 case 3:
999 goto sbb;
1000 case 4:
1001 goto and;
1002 case 5:
1003 goto sub;
1004 case 6:
1005 goto xor;
1006 case 7:
1007 goto cmp;
1008 }
1009 break;
1010 case 0x84 ... 0x85:
1011 test: /* test */
e4e03ded 1012 emulate_2op_SrcV("test", c->src, c->dst, _eflags);
6aa8b732
AK		 1013 break;
1014 case 0x86 ... 0x87: /* xchg */
1015 /* Write back the register source. */
e4e03ded 1016 switch (c->dst.bytes) {
6aa8b732 1017 case 1:
e4e03ded 1018 *(u8 *) c->src.ptr = (u8) c->dst.val;
6aa8b732
AK		 1019 break;
1020 case 2:
e4e03ded 1021 *(u16 *) c->src.ptr = (u16) c->dst.val;
6aa8b732
AK		 1022 break;
1023 case 4:
e4e03ded 1024 *c->src.ptr = (u32) c->dst.val;
6aa8b732
AK		 1025 break; /* 64b reg: zero-extend */
1026 case 8:
e4e03ded 1027 *c->src.ptr = c->dst.val;
6aa8b732
AK		 1028 break;
1029 }
1030 /*
1031 * Write back the memory destination with implicit LOCK
1032 * prefix.
1033 */
e4e03ded
LV		 1034 c->dst.val = c->src.val;
1035 c->lock_prefix = 1;
6aa8b732 1036 break;
6aa8b732 1037 case 0x88 ... 0x8b: /* mov */
7de75248 1038 goto mov;
7e0b54b1 1039 case 0x8d: /* lea r16/r32, m */
e4e03ded 1040 c->dst.val = c->modrm_val;
7e0b54b1 1041 break;
6aa8b732
AK		 1042 case 0x8f: /* pop (sole member of Grp1a) */
1043 /* 64-bit mode: POP always pops a 64-bit operand. */
1044 if (mode == X86EMUL_MODE_PROT64)
e4e03ded
LV		 1045 c->dst.bytes = 8;
1046 if ((rc = ops->read_std(register_address(
1047 ctxt->ss_base,
1048 c->regs[VCPU_REGS_RSP]),
1049 &c->dst.val,
1050 c->dst.bytes,
1051 ctxt->vcpu)) != 0)
6aa8b732 1052 goto done;
e4e03ded
LV		 1053 register_address_increment(c->regs[VCPU_REGS_RSP],
1054 c->dst.bytes);
6aa8b732 1055 break;
7de75248 1056 case 0xa0 ... 0xa1: /* mov */
e4e03ded
LV		 1057 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1058 c->dst.val = c->src.val;
1059 /* skip src displacement */
1060 c->eip += c->ad_bytes;
7de75248
NK		 1061 break;
1062 case 0xa2 ... 0xa3: /* mov */
e4e03ded
LV		 1063 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1064 /* skip c->dst displacement */
1065 c->eip += c->ad_bytes;
7de75248 1066 break;
6aa8b732
AK		 1067 case 0xc0 ... 0xc1:
1068 grp2: /* Grp2 */
e4e03ded 1069 switch (c->modrm_reg) {
6aa8b732 1070 case 0: /* rol */
e4e03ded 1071 emulate_2op_SrcB("rol", c->src, c->dst, _eflags);
6aa8b732
AK		 1072 break;
1073 case 1: /* ror */
e4e03ded 1074 emulate_2op_SrcB("ror", c->src, c->dst, _eflags);
6aa8b732
AK		 1075 break;
1076 case 2: /* rcl */
e4e03ded 1077 emulate_2op_SrcB("rcl", c->src, c->dst, _eflags);
6aa8b732
AK		 1078 break;
1079 case 3: /* rcr */
e4e03ded 1080 emulate_2op_SrcB("rcr", c->src, c->dst, _eflags);
6aa8b732
AK		 1081 break;
1082 case 4: /* sal/shl */
1083 case 6: /* sal/shl */
e4e03ded 1084 emulate_2op_SrcB("sal", c->src, c->dst, _eflags);
6aa8b732
AK		 1085 break;
1086 case 5: /* shr */
e4e03ded 1087 emulate_2op_SrcB("shr", c->src, c->dst, _eflags);
6aa8b732
AK		 1088 break;
1089 case 7: /* sar */
e4e03ded 1090 emulate_2op_SrcB("sar", c->src, c->dst, _eflags);
6aa8b732
AK		 1091 break;
1092 }
1093 break;
7de75248
NK		 1094 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1095 mov:
e4e03ded 1096 c->dst.val = c->src.val;
7de75248 1097 break;
6aa8b732 1098 case 0xd0 ... 0xd1: /* Grp2 */
e4e03ded 1099 c->src.val = 1;
6aa8b732
AK		 1100 goto grp2;
1101 case 0xd2 ... 0xd3: /* Grp2 */
e4e03ded 1102 c->src.val = c->regs[VCPU_REGS_RCX];
6aa8b732
AK		 1103 goto grp2;
1104 case 0xf6 ... 0xf7: /* Grp3 */
e4e03ded 1105 switch (c->modrm_reg) {
6aa8b732
AK		 1106 case 0 ... 1: /* test */
1107 /*
1108 * Special case in Grp3: test has an immediate
1109 * source operand.
1110 */
e4e03ded
LV		 1111 c->src.type = OP_IMM;
1112 c->src.ptr = (unsigned long *)c->eip;
1113 c->src.bytes = (c->d & ByteOp) ? 1 :
1114 c->op_bytes;
1115 if (c->src.bytes == 8)
1116 c->src.bytes = 4;
1117 switch (c->src.bytes) {
6aa8b732 1118 case 1:
e4e03ded 1119 c->src.val = insn_fetch(s8, 1, c->eip);
6aa8b732
AK		 1120 break;
1121 case 2:
e4e03ded 1122 c->src.val = insn_fetch(s16, 2, c->eip);
6aa8b732
AK		 1123 break;
1124 case 4:
e4e03ded 1125 c->src.val = insn_fetch(s32, 4, c->eip);
6aa8b732
AK		 1126 break;
1127 }
1128 goto test;
1129 case 2: /* not */
e4e03ded 1130 c->dst.val = ~c->dst.val;
6aa8b732
AK		 1131 break;
1132 case 3: /* neg */
e4e03ded 1133 emulate_1op("neg", c->dst, _eflags);
6aa8b732
AK		 1134 break;
1135 default:
1136 goto cannot_emulate;
1137 }
1138 break;
1139 case 0xfe ... 0xff: /* Grp4/Grp5 */
e4e03ded 1140 switch (c->modrm_reg) {
6aa8b732 1141 case 0: /* inc */
e4e03ded 1142 emulate_1op("inc", c->dst, _eflags);
6aa8b732
AK		 1143 break;
1144 case 1: /* dec */
e4e03ded 1145 emulate_1op("dec", c->dst, _eflags);
6aa8b732 1146 break;
26a3e983 1147 case 4: /* jmp abs */
e4e03ded
LV		 1148 if (c->b == 0xff)
1149 c->eip = c->dst.val;
26a3e983
NK		 1150 else
1151 goto cannot_emulate;
1152 break;
6aa8b732
AK		 1153 case 6: /* push */
1154 /* 64-bit mode: PUSH always pushes a 64-bit operand. */
1155 if (mode == X86EMUL_MODE_PROT64) {
e4e03ded
LV		 1156 c->dst.bytes = 8;
1157 if ((rc = ops->read_std(
1158 (unsigned long)c->dst.ptr,
1159 &c->dst.val, 8,
1160 ctxt->vcpu)) != 0)
6aa8b732
AK		 1161 goto done;
1162 }
e4e03ded
LV		 1163 register_address_increment(c->regs[VCPU_REGS_RSP],
1164 -c->dst.bytes);
00b2ef47 1165 if ((rc = ops->write_emulated(
6aa8b732 1166 register_address(ctxt->ss_base,
e4e03ded
LV		 1167 c->regs[VCPU_REGS_RSP]),
1168 &c->dst.val,
1169 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1170 goto done;
02c03a32 1171 no_wb = 1;
6aa8b732
AK		 1172 break;
1173 default:
1174 goto cannot_emulate;
1175 }
1176 break;
1177 }
1178
1179writeback:
02c03a32 1180 if (!no_wb) {
e4e03ded 1181 switch (c->dst.type) {
6aa8b732 1182 case OP_REG:
e4e03ded
LV		 1183 /* The 4-byte case *is* correct:
1184 * in 64-bit mode we zero-extend.
1185 */
1186 switch (c->dst.bytes) {
6aa8b732 1187 case 1:
e4e03ded 1188 *(u8 *)c->dst.ptr = (u8)c->dst.val;
6aa8b732
AK		 1189 break;
1190 case 2:
e4e03ded 1191 *(u16 *)c->dst.ptr = (u16)c->dst.val;
6aa8b732
AK		 1192 break;
1193 case 4:
e4e03ded 1194 *c->dst.ptr = (u32)c->dst.val;
6aa8b732
AK		 1195 break; /* 64b: zero-ext */
1196 case 8:
e4e03ded 1197 *c->dst.ptr = c->dst.val;
6aa8b732
AK		 1198 break;
1199 }
1200 break;
1201 case OP_MEM:
e4e03ded
LV		 1202 if (c->lock_prefix)
1203 rc = ops->cmpxchg_emulated(
1204 (unsigned long)c->dst.ptr,
1205 &c->dst.orig_val,
1206 &c->dst.val,
1207 c->dst.bytes,
1208 ctxt->vcpu);
6aa8b732 1209 else
e4e03ded
LV		 1210 rc = ops->write_emulated(
1211 (unsigned long)c->dst.ptr,
1212 &c->dst.val,
1213 c->dst.bytes,
1214 ctxt->vcpu);
6aa8b732
AK		 1215 if (rc != 0)
1216 goto done;
1217 default:
1218 break;
1219 }
1220 }
1221
1222 /* Commit shadow register state. */
e4e03ded 1223 memcpy(ctxt->vcpu->regs, c->regs, sizeof c->regs);
6aa8b732 1224 ctxt->eflags = _eflags;
e4e03ded 1225 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1226
1227done:
1228 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1229
1230special_insn:
e4e03ded 1231 if (c->twobyte)
6aa8b732 1232 goto twobyte_special_insn;
e4e03ded 1233 switch (c->b) {
7e778161 1234 case 0x50 ... 0x57: /* push reg */
e4e03ded
LV		 1235 if (c->op_bytes == 2)
1236 c->src.val = (u16) c->regs[c->b & 0x7];
7e778161 1237 else
e4e03ded
LV		 1238 c->src.val = (u32) c->regs[c->b & 0x7];
1239 c->dst.type = OP_MEM;
1240 c->dst.bytes = c->op_bytes;
1241 c->dst.val = c->src.val;
1242 register_address_increment(c->regs[VCPU_REGS_RSP],
1243 -c->op_bytes);
1244 c->dst.ptr = (void *) register_address(
1245 ctxt->ss_base, c->regs[VCPU_REGS_RSP]);
7e778161 1246 break;
7de75248 1247 case 0x58 ... 0x5f: /* pop reg */
e4e03ded
LV		 1248 c->dst.ptr =
1249 (unsigned long *)&c->regs[c->b & 0x7];
7de75248
NK		 1250 pop_instruction:
1251 if ((rc = ops->read_std(register_address(ctxt->ss_base,
e4e03ded
LV		 1252 c->regs[VCPU_REGS_RSP]), c->dst.ptr,
1253 c->op_bytes, ctxt->vcpu)) != 0)
7de75248
NK		 1254 goto done;
1255
e4e03ded
LV		 1256 register_address_increment(c->regs[VCPU_REGS_RSP],
1257 c->op_bytes);
7de75248
NK		 1258 no_wb = 1; /* Disable writeback. */
1259 break;
1e35d3c4 1260 case 0x6a: /* push imm8 */
e4e03ded
LV		 1261 c->src.val = 0L;
1262 c->src.val = insn_fetch(s8, 1, c->eip);
1263push:
1264 c->dst.type = OP_MEM;
1265 c->dst.bytes = c->op_bytes;
1266 c->dst.val = c->src.val;
1267 register_address_increment(c->regs[VCPU_REGS_RSP],
1268 -c->op_bytes);
1269 c->dst.ptr = (void *) register_address(ctxt->ss_base,
1270 c->regs[VCPU_REGS_RSP]);
1e35d3c4 1271 break;
e70669ab
LV		 1272 case 0x6c: /* insb */
1273 case 0x6d: /* insw/insd */
3090dd73 1274 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1275 1,
1276 (c->d & ByteOp) ? 1 : c->op_bytes,
1277 c->rep_prefix ?
1278 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1279 (_eflags & EFLG_DF),
e70669ab 1280 register_address(ctxt->es_base,
e4e03ded
LV		 1281 c->regs[VCPU_REGS_RDI]),
1282 c->rep_prefix,
1283 c->regs[VCPU_REGS_RDX]) == 0)
e70669ab
LV		 1284 return -1;
1285 return 0;
1286 case 0x6e: /* outsb */
1287 case 0x6f: /* outsw/outsd */
3090dd73 1288 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
e4e03ded
LV		 1289 0,
1290 (c->d & ByteOp) ? 1 : c->op_bytes,
1291 c->rep_prefix ?
1292 address_mask(c->regs[VCPU_REGS_RCX]) : 1,
1293 (_eflags & EFLG_DF),
1294 register_address(c->override_base ?
1295 *c->override_base :
1296 ctxt->ds_base,
1297 c->regs[VCPU_REGS_RSI]),
1298 c->rep_prefix,
1299 c->regs[VCPU_REGS_RDX]) == 0)
e70669ab
LV		 1300 return -1;
1301 return 0;
55bebde4 1302 case 0x70 ... 0x7f: /* jcc (short) */ {
e4e03ded 1303 int rel = insn_fetch(s8, 1, c->eip);
55bebde4 1304
e4e03ded 1305 if (test_cc(c->b, _eflags))
55bebde4
NK		 1306 JMP_REL(rel);
1307 break;
1308 }
fd2a7608 1309 case 0x9c: /* pushf */
e4e03ded 1310 c->src.val = (unsigned long) _eflags;
fd2a7608 1311 goto push;
535eabcf 1312 case 0x9d: /* popf */
e4e03ded 1313 c->dst.ptr = (unsigned long *) &_eflags;
535eabcf 1314 goto pop_instruction;
7de75248 1315 case 0xc3: /* ret */
e4e03ded 1316 c->dst.ptr = &c->eip;
7de75248
NK		 1317 goto pop_instruction;
1318 case 0xf4: /* hlt */
1319 ctxt->vcpu->halt_request = 1;
1320 goto done;
e70669ab 1321 }
e4e03ded
LV		 1322 if (c->rep_prefix) {
1323 if (c->regs[VCPU_REGS_RCX] == 0) {
1324 ctxt->vcpu->rip = c->eip;
6aa8b732
AK		 1325 goto done;
1326 }
e4e03ded
LV		 1327 c->regs[VCPU_REGS_RCX]--;
1328 c->eip = ctxt->vcpu->rip;
6aa8b732 1329 }
e4e03ded 1330 switch (c->b) {
6aa8b732 1331 case 0xa4 ... 0xa5: /* movs */
e4e03ded
LV		 1332 c->dst.type = OP_MEM;
1333 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1334 c->dst.ptr = (unsigned long *)register_address(
1335 ctxt->es_base,
1336 c->regs[VCPU_REGS_RDI]);
6aa8b732 1337 if ((rc = ops->read_emulated(register_address(
e4e03ded
LV		 1338 c->override_base ? *c->override_base :
1339 ctxt->ds_base,
1340 c->regs[VCPU_REGS_RSI]),
1341 &c->dst.val,
1342 c->dst.bytes, ctxt->vcpu)) != 0)
6aa8b732 1343 goto done;
e4e03ded
LV		 1344 register_address_increment(c->regs[VCPU_REGS_RSI],
1345 (_eflags & EFLG_DF) ? -c->dst.bytes
1346 : c->dst.bytes);
1347 register_address_increment(c->regs[VCPU_REGS_RDI],
1348 (_eflags & EFLG_DF) ? -c->dst.bytes
1349 : c->dst.bytes);
6aa8b732
AK		 1350 break;
1351 case 0xa6 ... 0xa7: /* cmps */
1352 DPRINTF("Urk! I don't handle CMPS.\n");
1353 goto cannot_emulate;
1354 case 0xaa ... 0xab: /* stos */
e4e03ded
LV		 1355 c->dst.type = OP_MEM;
1356 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1357 c->dst.ptr = (unsigned long *)cr2;
1358 c->dst.val = c->regs[VCPU_REGS_RAX];
1359 register_address_increment(c->regs[VCPU_REGS_RDI],
1360 (_eflags & EFLG_DF) ? -c->dst.bytes
1361 : c->dst.bytes);
6aa8b732
AK		 1362 break;
1363 case 0xac ... 0xad: /* lods */
e4e03ded
LV		 1364 c->dst.type = OP_REG;
1365 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1366 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1367 if ((rc = ops->read_emulated(cr2, &c->dst.val,
1368 c->dst.bytes,
cebff02b 1369 ctxt->vcpu)) != 0)
6aa8b732 1370 goto done;
e4e03ded
LV		 1371 register_address_increment(c->regs[VCPU_REGS_RSI],
1372 (_eflags & EFLG_DF) ? -c->dst.bytes
1373 : c->dst.bytes);
6aa8b732
AK		 1374 break;
1375 case 0xae ... 0xaf: /* scas */
1376 DPRINTF("Urk! I don't handle SCAS.\n");
1377 goto cannot_emulate;
1a52e051
NK		 1378 case 0xe8: /* call (near) */ {
1379 long int rel;
e4e03ded 1380 switch (c->op_bytes) {
1a52e051 1381 case 2:
e4e03ded 1382 rel = insn_fetch(s16, 2, c->eip);
1a52e051
NK		 1383 break;
1384 case 4:
e4e03ded 1385 rel = insn_fetch(s32, 4, c->eip);
1a52e051
NK		 1386 break;
1387 case 8:
e4e03ded 1388 rel = insn_fetch(s64, 8, c->eip);
1a52e051
NK		 1389 break;
1390 default:
1391 DPRINTF("Call: Invalid op_bytes\n");
1392 goto cannot_emulate;
1393 }
e4e03ded 1394 c->src.val = (unsigned long) c->eip;
1a52e051 1395 JMP_REL(rel);
e4e03ded 1396 c->op_bytes = c->ad_bytes;
1a52e051
NK		 1397 goto push;
1398 }
1399 case 0xe9: /* jmp rel */
1400 case 0xeb: /* jmp rel short */
e4e03ded 1401 JMP_REL(c->src.val);
1a52e051
NK		 1402 no_wb = 1; /* Disable writeback. */
1403 break;
1404
7f0aaee0 1405
6aa8b732
AK		 1406 }
1407 goto writeback;
1408
1409twobyte_insn:
e4e03ded 1410 switch (c->b) {
6aa8b732 1411 case 0x01: /* lgdt, lidt, lmsw */
d37c8557
AJ		 1412 /* Disable writeback. */
1413 no_wb = 1;
e4e03ded 1414 switch (c->modrm_reg) {
6aa8b732
AK		 1415 u16 size;
1416 unsigned long address;
1417
aca7f966 1418 case 0: /* vmcall */
e4e03ded 1419 if (c->modrm_mod != 3 || c->modrm_rm != 1)
aca7f966
AL		 1420 goto cannot_emulate;
1421
7aa81cc0
AL		 1422 rc = kvm_fix_hypercall(ctxt->vcpu);
1423 if (rc)
1424 goto done;
1425
1426 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1427 break;
6aa8b732 1428 case 2: /* lgdt */
e4e03ded
LV		 1429 rc = read_descriptor(ctxt, ops, c->src.ptr,
1430 &size, &address, c->op_bytes);
6aa8b732
AK		 1431 if (rc)
1432 goto done;
1433 realmode_lgdt(ctxt->vcpu, size, address);
1434 break;
aca7f966 1435 case 3: /* lidt/vmmcall */
e4e03ded 1436 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
7aa81cc0
AL		 1437 rc = kvm_fix_hypercall(ctxt->vcpu);
1438 if (rc)
1439 goto done;
1440 kvm_emulate_hypercall(ctxt->vcpu);
aca7f966 1441 } else {
e4e03ded 1442 rc = read_descriptor(ctxt, ops, c->src.ptr,
aca7f966 1443 &size, &address,
e4e03ded 1444 c->op_bytes);
aca7f966
AL		 1445 if (rc)
1446 goto done;
1447 realmode_lidt(ctxt->vcpu, size, address);
1448 }
6aa8b732
AK		 1449 break;
1450 case 4: /* smsw */
e4e03ded 1451 if (c->modrm_mod != 3)
6aa8b732 1452 goto cannot_emulate;
e4e03ded 1453 *(u16 *)&c->regs[c->modrm_rm]
6aa8b732
AK		 1454 = realmode_get_cr(ctxt->vcpu, 0);
1455 break;
1456 case 6: /* lmsw */
e4e03ded 1457 if (c->modrm_mod != 3)
6aa8b732 1458 goto cannot_emulate;
e4e03ded 1459 realmode_lmsw(ctxt->vcpu, (u16)c->modrm_val, &_eflags);
6aa8b732
AK		 1460 break;
1461 case 7: /* invlpg*/
1462 emulate_invlpg(ctxt->vcpu, cr2);
1463 break;
1464 default:
1465 goto cannot_emulate;
1466 }
1467 break;
1468 case 0x21: /* mov from dr to reg */
bac27d35 1469 no_wb = 1;
e4e03ded 1470 if (c->modrm_mod != 3)
6aa8b732 1471 goto cannot_emulate;
e4e03ded
LV		 1472 rc = emulator_get_dr(ctxt, c->modrm_reg,
1473 &c->regs[c->modrm_rm]);
6aa8b732
AK		 1474 break;
1475 case 0x23: /* mov from reg to dr */
bac27d35 1476 no_wb = 1;
e4e03ded 1477 if (c->modrm_mod != 3)
6aa8b732 1478 goto cannot_emulate;
e4e03ded
LV		 1479 rc = emulator_set_dr(ctxt, c->modrm_reg,
1480 c->regs[c->modrm_rm]);
6aa8b732
AK		 1481 break;
1482 case 0x40 ... 0x4f: /* cmov */
e4e03ded 1483 c->dst.val = c->dst.orig_val = c->src.val;
e3243452 1484 no_wb = 1;
6aa8b732
AK		 1485 /*
1486 * First, assume we're decoding an even cmov opcode
1487 * (lsb == 0).
1488 */
e4e03ded 1489 switch ((c->b & 15) >> 1) {
6aa8b732 1490 case 0: /* cmovo */
e3243452 1491 no_wb = (_eflags & EFLG_OF) ? 0 : 1;
6aa8b732
AK		 1492 break;
1493 case 1: /* cmovb/cmovc/cmovnae */
e3243452 1494 no_wb = (_eflags & EFLG_CF) ? 0 : 1;
6aa8b732
AK		 1495 break;
1496 case 2: /* cmovz/cmove */
e3243452 1497 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
6aa8b732
AK		 1498 break;
1499 case 3: /* cmovbe/cmovna */
e3243452 1500 no_wb = (_eflags & (EFLG_CF | EFLG_ZF)) ? 0 : 1;
6aa8b732
AK		 1501 break;
1502 case 4: /* cmovs */
e3243452 1503 no_wb = (_eflags & EFLG_SF) ? 0 : 1;
6aa8b732
AK		 1504 break;
1505 case 5: /* cmovp/cmovpe */
e3243452 1506 no_wb = (_eflags & EFLG_PF) ? 0 : 1;
6aa8b732
AK		 1507 break;
1508 case 7: /* cmovle/cmovng */
e3243452 1509 no_wb = (_eflags & EFLG_ZF) ? 0 : 1;
6aa8b732
AK		 1510 /* fall through */
1511 case 6: /* cmovl/cmovnge */
e3243452
AK		 1512 no_wb &= (!(_eflags & EFLG_SF) !=
1513 !(_eflags & EFLG_OF)) ? 0 : 1;
6aa8b732
AK		 1514 break;
1515 }
1516 /* Odd cmov opcodes (lsb == 1) have inverted sense. */
e4e03ded 1517 no_wb ^= c->b & 1;
6aa8b732 1518 break;
7de75248
NK		 1519 case 0xa3:
1520 bt: /* bt */
e4e03ded
LV		 1521 /* only subword offset */
1522 c->src.val &= (c->dst.bytes << 3) - 1;
1523 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, _eflags);
7de75248
NK		 1524 break;
1525 case 0xab:
1526 bts: /* bts */
e4e03ded
LV		 1527 /* only subword offset */
1528 c->src.val &= (c->dst.bytes << 3) - 1;
1529 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, _eflags);
7de75248 1530 break;
6aa8b732
AK		 1531 case 0xb0 ... 0xb1: /* cmpxchg */
1532 /*
1533 * Save real source value, then compare EAX against
1534 * destination.
1535 */
e4e03ded
LV		 1536 c->src.orig_val = c->src.val;
1537 c->src.val = c->regs[VCPU_REGS_RAX];
1538 emulate_2op_SrcV("cmp", c->src, c->dst, _eflags);
6aa8b732
AK		 1539 if (_eflags & EFLG_ZF) {
1540 /* Success: write back to memory. */
e4e03ded 1541 c->dst.val = c->src.orig_val;
6aa8b732
AK		 1542 } else {
1543 /* Failure: write the value we saw to EAX. */
e4e03ded
LV		 1544 c->dst.type = OP_REG;
1545 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
6aa8b732
AK		 1546 }
1547 break;
6aa8b732
AK		 1548 case 0xb3:
1549 btr: /* btr */
e4e03ded
LV		 1550 /* only subword offset */
1551 c->src.val &= (c->dst.bytes << 3) - 1;
1552 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, _eflags);
6aa8b732 1553 break;
6aa8b732 1554 case 0xb6 ... 0xb7: /* movzx */
e4e03ded
LV		 1555 c->dst.bytes = c->op_bytes;
1556 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
1557 : (u16) c->src.val;
6aa8b732 1558 break;
6aa8b732 1559 case 0xba: /* Grp8 */
e4e03ded 1560 switch (c->modrm_reg & 3) {
6aa8b732
AK		 1561 case 0:
1562 goto bt;
1563 case 1:
1564 goto bts;
1565 case 2:
1566 goto btr;
1567 case 3:
1568 goto btc;
1569 }
1570 break;
7de75248
NK		 1571 case 0xbb:
1572 btc: /* btc */
e4e03ded
LV		 1573 /* only subword offset */
1574 c->src.val &= (c->dst.bytes << 3) - 1;
1575 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, _eflags);
7de75248 1576 break;
6aa8b732 1577 case 0xbe ... 0xbf: /* movsx */
e4e03ded
LV		 1578 c->dst.bytes = c->op_bytes;
1579 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
1580 (s16) c->src.val;
6aa8b732 1581 break;
a012e65a 1582 case 0xc3: /* movnti */
e4e03ded
LV		 1583 c->dst.bytes = c->op_bytes;
1584 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
1585 (u64) c->src.val;
a012e65a 1586 break;
6aa8b732
AK		 1587 }
1588 goto writeback;
1589
1590twobyte_special_insn:
1591 /* Disable writeback. */
02c03a32 1592 no_wb = 1;
e4e03ded 1593 switch (c->b) {
7de75248
NK		 1594 case 0x06:
1595 emulate_clts(ctxt->vcpu);
1596 break;
651a3e29
AK		 1597 case 0x08: /* invd */
1598 break;
687fdbfe
AK		 1599 case 0x09: /* wbinvd */
1600 break;
6aa8b732
AK		 1601 case 0x0d: /* GrpP (prefetch) */
1602 case 0x18: /* Grp16 (prefetch/nop) */
1603 break;
6aa8b732 1604 case 0x20: /* mov cr, reg */
e4e03ded 1605 if (c->modrm_mod != 3)
6aa8b732 1606 goto cannot_emulate;
e4e03ded
LV		 1607 c->regs[c->modrm_rm] =
1608 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
6aa8b732
AK		 1609 break;
1610 case 0x22: /* mov reg, cr */
e4e03ded 1611 if (c->modrm_mod != 3)
6aa8b732 1612 goto cannot_emulate;
e4e03ded
LV		 1613 realmode_set_cr(ctxt->vcpu,
1614 c->modrm_reg, c->modrm_val, &_eflags);
6aa8b732 1615 break;
35f3f286
AK		 1616 case 0x30:
1617 /* wrmsr */
e4e03ded
LV		 1618 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1619 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1620 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
35f3f286 1621 if (rc) {
cbdd1bea 1622 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1623 c->eip = ctxt->vcpu->rip;
35f3f286
AK		 1624 }
1625 rc = X86EMUL_CONTINUE;
1626 break;
1627 case 0x32:
1628 /* rdmsr */
e4e03ded
LV		 1629 rc = kvm_get_msr(ctxt->vcpu,
1630 c->regs[VCPU_REGS_RCX], &msr_data);
35f3f286 1631 if (rc) {
cbdd1bea 1632 kvm_x86_ops->inject_gp(ctxt->vcpu, 0);
e4e03ded 1633 c->eip = ctxt->vcpu->rip;
35f3f286 1634 } else {
e4e03ded
LV		 1635 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
1636 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
35f3f286
AK		 1637 }
1638 rc = X86EMUL_CONTINUE;
1639 break;
bbe9abbd
NK		 1640 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
1641 long int rel;
1642
e4e03ded 1643 switch (c->op_bytes) {
bbe9abbd 1644 case 2:
e4e03ded 1645 rel = insn_fetch(s16, 2, c->eip);
bbe9abbd
NK		 1646 break;
1647 case 4:
e4e03ded 1648 rel = insn_fetch(s32, 4, c->eip);
bbe9abbd
NK		 1649 break;
1650 case 8:
e4e03ded 1651 rel = insn_fetch(s64, 8, c->eip);
bbe9abbd
NK		 1652 break;
1653 default:
1654 DPRINTF("jnz: Invalid op_bytes\n");
1655 goto cannot_emulate;
1656 }
e4e03ded 1657 if (test_cc(c->b, _eflags))
bbe9abbd
NK		 1658 JMP_REL(rel);
1659 break;
1660 }
6aa8b732 1661 case 0xc7: /* Grp9 (cmpxchg8b) */
6aa8b732 1662 {
4c690a1e 1663 u64 old, new;
cebff02b
LV		 1664 if ((rc = ops->read_emulated(cr2, &old, 8, ctxt->vcpu))
1665 != 0)
6aa8b732 1666 goto done;
e4e03ded
LV		 1667 if (((u32) (old >> 0) !=
1668 (u32) c->regs[VCPU_REGS_RAX]) ||
1669 ((u32) (old >> 32) !=
1670 (u32) c->regs[VCPU_REGS_RDX])) {
1671 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1672 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
6aa8b732
AK		 1673 _eflags &= ~EFLG_ZF;
1674 } else {
e4e03ded
LV		 1675 new = ((u64)c->regs[VCPU_REGS_RCX] << 32)
1676 | (u32) c->regs[VCPU_REGS_RBX];
4c690a1e 1677 if ((rc = ops->cmpxchg_emulated(cr2, &old,
cebff02b 1678 &new, 8, ctxt->vcpu)) != 0)
6aa8b732
AK		 1679 goto done;
1680 _eflags |= EFLG_ZF;
1681 }
1682 break;
1683 }
6aa8b732
AK		 1684 }
1685 goto writeback;
1686
1687cannot_emulate:
e4e03ded 1688 DPRINTF("Cannot emulate %02x\n", c->b);
6aa8b732
AK		 1689 return -1;
1690}
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