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1menuconfig MAILBOX
2 bool "Mailbox Hardware Support"
3 help
4 Mailbox is a framework to control hardware communication between
5 on-chip processors through queued messages and interrupt driven
6 signals. Say Y if your platform supports hardware mailboxes.
7
8if MAILBOX
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9
10config ARM_MHU
11 tristate "ARM MHU Mailbox"
12 depends on ARM_AMBA
13 help
14 Say Y here if you want to build the ARM MHU controller driver.
15 The controller has 3 mailbox channels, the last of which can be
16 used in Secure mode only.
17
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18config PLATFORM_MHU
19 tristate "Platform MHU Mailbox"
20 depends on OF
21 depends on HAS_IOMEM
22 help
23 Say Y here if you want to build a platform specific variant MHU
24 controller driver.
25 The controller has a maximum of 3 mailbox channels, the last of
26 which can be used in Secure mode only.
27
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28config PL320_MBOX
29 bool "ARM PL320 Mailbox"
30 depends on ARM_AMBA
31 help
32 An implementation of the ARM PL320 Interprocessor Communication
33 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to
34 send short messages between Highbank's A9 cores and the EnergyCore
35 Management Engine, primarily for cpufreq. Say Y here if you want
36 to use the PL320 IPCM support.
37
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38config OMAP2PLUS_MBOX
39 tristate "OMAP2+ Mailbox framework support"
40 depends on ARCH_OMAP2PLUS
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41 help
42 Mailbox implementation for OMAP family chips with hardware for
43 interprocessor communication involving DSP, IVA1.0 and IVA2 in
44 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
45 want to use OMAP2+ Mailbox framework support.
46
47config OMAP_MBOX_KFIFO_SIZE
48 int "Mailbox kfifo default buffer size (bytes)"
79859094 49 depends on OMAP2PLUS_MBOX
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50 default 256
51 help
52 Specify the default size of mailbox's kfifo buffers (bytes).
53 This can also be changed at runtime (via the mbox_kfifo_size
54 module parameter).
86c22f8c 55
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56config ROCKCHIP_MBOX
57 bool "Rockchip Soc Intergrated Mailbox Support"
58 depends on ARCH_ROCKCHIP || COMPILE_TEST
59 help
60 This driver provides support for inter-processor communication
61 between CPU cores and MCU processor on Some Rockchip SOCs.
62 Please check it that the Soc you use have Mailbox hardware.
63 Say Y here if you want to use the Rockchip Mailbox support.
64
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65config PCC
66 bool "Platform Communication Channel Driver"
67 depends on ACPI
b6fc6072 68 default n
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69 help
70 ACPI 5.0+ spec defines a generic mode of communication
71 between the OS and a platform such as the BMC. This medium
72 (PCC) is typically used by CPPC (ACPI CPU Performance management),
73 RAS (ACPI reliability protocol) and MPST (ACPI Memory power
74 states). Select this driver if your platform implements the
75 PCC clients mentioned above.
76
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77config ALTERA_MBOX
78 tristate "Altera Mailbox"
59dd3f02 79 depends on HAS_IOMEM
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80 help
81 An implementation of the Altera Mailbox soft core. It is used
82 to send message between processors. Say Y here if you want to use the
83 Altera mailbox support.
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84
85config BCM2835_MBOX
86 tristate "BCM2835 Mailbox"
87 depends on ARCH_BCM2835
88 help
89 An implementation of the BCM2385 Mailbox. It is used to invoke
90 the services of the Videocore. Say Y here if you want to use the
91 BCM2835 Mailbox.
92
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93config STI_MBOX
94 tristate "STI Mailbox framework support"
95 depends on ARCH_STI && OF
96 help
97 Mailbox implementation for STMicroelectonics family chips with
98 hardware for interprocessor communication.
99
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100config TI_MESSAGE_MANAGER
101 tristate "Texas Instruments Message Manager Driver"
102 depends on ARCH_KEYSTONE
103 help
104 An implementation of Message Manager slave driver for Keystone
105 architecture SoCs from Texas Instruments. Message Manager is a
106 communication entity found on few of Texas Instrument's keystone
107 architecture SoCs. These may be used for communication between
108 multiple processors within the SoC. Select this driver if your
109 platform has support for the hardware block.
110
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111config HI6220_MBOX
112 tristate "Hi6220 Mailbox"
113 depends on ARCH_HISI
114 help
115 An implementation of the hi6220 mailbox. It is used to send message
116 between application processors and MCU. Say Y here if you want to
117 build Hi6220 mailbox controller driver.
118
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119config MAILBOX_TEST
120 tristate "Mailbox Test Client"
121 depends on OF
65d3b04a 122 depends on HAS_IOMEM
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123 help
124 Test client to help with testing new Controller driver
125 implementations.
126
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127config QCOM_APCS_IPC
128 tristate "Qualcomm APCS IPC driver"
129 depends on ARCH_QCOM || COMPILE_TEST
130 help
131 Say y here to enable support for the APCS IPC mailbox driver,
132 providing an interface for invoking the inter-process communication
133 signals from the application processor to other masters.
134
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135config TEGRA_HSP_MBOX
136 bool "Tegra HSP (Hardware Synchronization Primitives) Driver"
137 depends on ARCH_TEGRA_186_SOC
138 help
139 The Tegra HSP driver is used for the interprocessor communication
140 between different remote processors and host processors on Tegra186
141 and later SoCs. Say Y here if you want to have this support.
142 If unsure say N.
143
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144config XGENE_SLIMPRO_MBOX
145 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
146 depends on ARCH_XGENE
147 help
148 An implementation of the APM X-Gene Interprocessor Communication
149 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
150 It is used to send short messages between ARM64-bit cores and
151 the SLIMpro Management Engine, primarily for PM. Say Y here if you
152 want to use the APM X-Gene SLIMpro IPCM support.
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153
154config BCM_PDC_MBOX
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155 tristate "Broadcom FlexSparx DMA Mailbox"
156 depends on ARCH_BCM_IPROC || COMPILE_TEST
e0c6fba4 157 depends on HAS_DMA
a24532f8 158 help
fc2041c5 159 Mailbox implementation for the Broadcom FlexSparx DMA ring manager,
a24532f8 160 which provides access to various offload engines on Broadcom
fc2041c5 161 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.
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162
163config BCM_FLEXRM_MBOX
164 tristate "Broadcom FlexRM Mailbox"
73874913 165 depends on ARM64
8f82121d 166 depends on ARCH_BCM_IPROC || COMPILE_TEST
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167 depends on HAS_DMA
168 select GENERIC_MSI_IRQ_DOMAIN
22d28b0f 169 default m if ARCH_BCM_IPROC
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170 help
171 Mailbox implementation of the Broadcom FlexRM ring manager,
172 which provides access to various offload engines on Broadcom
173 SoCs. Say Y here if you want to use the Broadcom FlexRM.
30058677 174endif