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30058677 RH |
1 | menuconfig MAILBOX |
2 | bool "Mailbox Hardware Support" | |
3 | help | |
4 | Mailbox is a framework to control hardware communication between | |
5 | on-chip processors through queued messages and interrupt driven | |
6 | signals. Say Y if your platform supports hardware mailboxes. | |
7 | ||
8 | if MAILBOX | |
ee23d66a JB |
9 | |
10 | config ARM_MHU | |
11 | tristate "ARM MHU Mailbox" | |
12 | depends on ARM_AMBA | |
13 | help | |
14 | Say Y here if you want to build the ARM MHU controller driver. | |
15 | The controller has 3 mailbox channels, the last of which can be | |
16 | used in Secure mode only. | |
17 | ||
2bb70056 OR |
18 | config IMX_MBOX |
19 | tristate "i.MX Mailbox" | |
20 | depends on ARCH_MXC || COMPILE_TEST | |
21 | help | |
22 | Mailbox implementation for i.MX Messaging Unit (MU). | |
23 | ||
ad3a212c NA |
24 | config PLATFORM_MHU |
25 | tristate "Platform MHU Mailbox" | |
26 | depends on OF | |
27 | depends on HAS_IOMEM | |
28 | help | |
29 | Say Y here if you want to build a platform specific variant MHU | |
30 | controller driver. | |
31 | The controller has a maximum of 3 mailbox channels, the last of | |
32 | which can be used in Secure mode only. | |
33 | ||
30058677 RH |
34 | config PL320_MBOX |
35 | bool "ARM PL320 Mailbox" | |
36 | depends on ARM_AMBA | |
37 | help | |
38 | An implementation of the ARM PL320 Interprocessor Communication | |
39 | Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to | |
40 | send short messages between Highbank's A9 cores and the EnergyCore | |
41 | Management Engine, primarily for cpufreq. Say Y here if you want | |
42 | to use the PL320 IPCM support. | |
43 | ||
c869c75c SA |
44 | config OMAP2PLUS_MBOX |
45 | tristate "OMAP2+ Mailbox framework support" | |
46 | depends on ARCH_OMAP2PLUS | |
c869c75c SA |
47 | help |
48 | Mailbox implementation for OMAP family chips with hardware for | |
49 | interprocessor communication involving DSP, IVA1.0 and IVA2 in | |
50 | OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you | |
51 | want to use OMAP2+ Mailbox framework support. | |
52 | ||
53 | config OMAP_MBOX_KFIFO_SIZE | |
54 | int "Mailbox kfifo default buffer size (bytes)" | |
79859094 | 55 | depends on OMAP2PLUS_MBOX |
c869c75c SA |
56 | default 256 |
57 | help | |
58 | Specify the default size of mailbox's kfifo buffers (bytes). | |
59 | This can also be changed at runtime (via the mbox_kfifo_size | |
60 | module parameter). | |
86c22f8c | 61 | |
f70ed3b5 CW |
62 | config ROCKCHIP_MBOX |
63 | bool "Rockchip Soc Intergrated Mailbox Support" | |
64 | depends on ARCH_ROCKCHIP || COMPILE_TEST | |
65 | help | |
66 | This driver provides support for inter-processor communication | |
67 | between CPU cores and MCU processor on Some Rockchip SOCs. | |
68 | Please check it that the Soc you use have Mailbox hardware. | |
69 | Say Y here if you want to use the Rockchip Mailbox support. | |
70 | ||
86c22f8c AC |
71 | config PCC |
72 | bool "Platform Communication Channel Driver" | |
73 | depends on ACPI | |
b6fc6072 | 74 | default n |
86c22f8c AC |
75 | help |
76 | ACPI 5.0+ spec defines a generic mode of communication | |
77 | between the OS and a platform such as the BMC. This medium | |
78 | (PCC) is typically used by CPPC (ACPI CPU Performance management), | |
79 | RAS (ACPI reliability protocol) and MPST (ACPI Memory power | |
80 | states). Select this driver if your platform implements the | |
81 | PCC clients mentioned above. | |
82 | ||
f62092f6 LFT |
83 | config ALTERA_MBOX |
84 | tristate "Altera Mailbox" | |
59dd3f02 | 85 | depends on HAS_IOMEM |
f62092f6 LFT |
86 | help |
87 | An implementation of the Altera Mailbox soft core. It is used | |
88 | to send message between processors. Say Y here if you want to use the | |
89 | Altera mailbox support. | |
0bae6af6 LR |
90 | |
91 | config BCM2835_MBOX | |
92 | tristate "BCM2835 Mailbox" | |
93 | depends on ARCH_BCM2835 | |
94 | help | |
95 | An implementation of the BCM2385 Mailbox. It is used to invoke | |
96 | the services of the Videocore. Say Y here if you want to use the | |
97 | BCM2835 Mailbox. | |
98 | ||
9ef4546c LJ |
99 | config STI_MBOX |
100 | tristate "STI Mailbox framework support" | |
101 | depends on ARCH_STI && OF | |
102 | help | |
103 | Mailbox implementation for STMicroelectonics family chips with | |
104 | hardware for interprocessor communication. | |
105 | ||
aace66b1 NM |
106 | config TI_MESSAGE_MANAGER |
107 | tristate "Texas Instruments Message Manager Driver" | |
cfc0f7a8 | 108 | depends on ARCH_KEYSTONE || ARCH_K3 |
aace66b1 NM |
109 | help |
110 | An implementation of Message Manager slave driver for Keystone | |
cfc0f7a8 NM |
111 | and K3 architecture SoCs from Texas Instruments. Message Manager |
112 | is a communication entity found on few of Texas Instrument's keystone | |
113 | and K3 architecture SoCs. These may be used for communication between | |
aace66b1 NM |
114 | multiple processors within the SoC. Select this driver if your |
115 | platform has support for the hardware block. | |
116 | ||
41c0e939 | 117 | config HI3660_MBOX |
f83d1cfc DL |
118 | tristate "Hi3660 Mailbox" if EXPERT |
119 | depends on (ARCH_HISI || COMPILE_TEST) | |
120 | depends on OF | |
121 | default ARCH_HISI | |
41c0e939 KZ |
122 | help |
123 | An implementation of the hi3660 mailbox. It is used to send message | |
124 | between application processors and other processors/MCU/DSP. Select | |
125 | Y here if you want to use Hi3660 mailbox controller. | |
126 | ||
9c384189 | 127 | config HI6220_MBOX |
f83d1cfc DL |
128 | tristate "Hi6220 Mailbox" if EXPERT |
129 | depends on (ARCH_HISI || COMPILE_TEST) | |
130 | depends on OF | |
131 | default ARCH_HISI | |
9c384189 LY |
132 | help |
133 | An implementation of the hi6220 mailbox. It is used to send message | |
134 | between application processors and MCU. Say Y here if you want to | |
135 | build Hi6220 mailbox controller driver. | |
136 | ||
8ea4484d LJ |
137 | config MAILBOX_TEST |
138 | tristate "Mailbox Test Client" | |
139 | depends on OF | |
65d3b04a | 140 | depends on HAS_IOMEM |
8ea4484d LJ |
141 | help |
142 | Test client to help with testing new Controller driver | |
143 | implementations. | |
144 | ||
25bfee16 BA |
145 | config QCOM_APCS_IPC |
146 | tristate "Qualcomm APCS IPC driver" | |
147 | depends on ARCH_QCOM || COMPILE_TEST | |
148 | help | |
149 | Say y here to enable support for the APCS IPC mailbox driver, | |
150 | providing an interface for invoking the inter-process communication | |
151 | signals from the application processor to other masters. | |
152 | ||
0fe88461 TR |
153 | config TEGRA_HSP_MBOX |
154 | bool "Tegra HSP (Hardware Synchronization Primitives) Driver" | |
85bd2de4 | 155 | depends on ARCH_TEGRA |
0fe88461 TR |
156 | help |
157 | The Tegra HSP driver is used for the interprocessor communication | |
158 | between different remote processors and host processors on Tegra186 | |
159 | and later SoCs. Say Y here if you want to have this support. | |
160 | If unsure say N. | |
161 | ||
f700e84f DD |
162 | config XGENE_SLIMPRO_MBOX |
163 | tristate "APM SoC X-Gene SLIMpro Mailbox Controller" | |
164 | depends on ARCH_XGENE | |
165 | help | |
166 | An implementation of the APM X-Gene Interprocessor Communication | |
167 | Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller. | |
168 | It is used to send short messages between ARM64-bit cores and | |
169 | the SLIMpro Management Engine, primarily for PM. Say Y here if you | |
170 | want to use the APM X-Gene SLIMpro IPCM support. | |
a24532f8 RR |
171 | |
172 | config BCM_PDC_MBOX | |
fc2041c5 SL |
173 | tristate "Broadcom FlexSparx DMA Mailbox" |
174 | depends on ARCH_BCM_IPROC || COMPILE_TEST | |
a24532f8 | 175 | help |
fc2041c5 | 176 | Mailbox implementation for the Broadcom FlexSparx DMA ring manager, |
a24532f8 | 177 | which provides access to various offload engines on Broadcom |
fc2041c5 | 178 | SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2. |
dbc049ee AP |
179 | |
180 | config BCM_FLEXRM_MBOX | |
181 | tristate "Broadcom FlexRM Mailbox" | |
73874913 | 182 | depends on ARM64 |
8f82121d | 183 | depends on ARCH_BCM_IPROC || COMPILE_TEST |
dbc049ee | 184 | select GENERIC_MSI_IRQ_DOMAIN |
22d28b0f | 185 | default m if ARCH_BCM_IPROC |
dbc049ee AP |
186 | help |
187 | Mailbox implementation of the Broadcom FlexRM ring manager, | |
188 | which provides access to various offload engines on Broadcom | |
189 | SoCs. Say Y here if you want to use the Broadcom FlexRM. | |
ffbded7d FD |
190 | |
191 | config STM32_IPCC | |
192 | tristate "STM32 IPCC Mailbox" | |
193 | depends on MACH_STM32MP157 | |
194 | help | |
195 | Mailbox implementation for STMicroelectonics STM32 family chips | |
196 | with hardware for Inter-Processor Communication Controller (IPCC) | |
197 | between processors. Say Y here if you want to have this support. | |
623a6143 HW |
198 | |
199 | config MTK_CMDQ_MBOX | |
200 | tristate "MediaTek CMDQ Mailbox Support" | |
201 | depends on ARCH_MEDIATEK || COMPILE_TEST | |
202 | select MTK_INFRACFG | |
203 | help | |
204 | Say yes here to add support for the MediaTek Command Queue (CMDQ) | |
205 | mailbox driver. The CMDQ is used to help read/write registers with | |
206 | critical time limitation, such as updating display configuration | |
207 | during the vblank. | |
4981b82b WL |
208 | |
209 | config ZYNQMP_IPI_MBOX | |
210 | bool "Xilinx ZynqMP IPI Mailbox" | |
211 | depends on ARCH_ZYNQMP && OF | |
212 | help | |
213 | Say yes here to add support for Xilinx IPI mailbox driver. | |
214 | This mailbox driver is used to send notification or short message | |
215 | between processors with Xilinx ZynqMP IPI. It will place the | |
216 | message to the IPI buffer and will access the IPI control | |
217 | registers to kick the other processor or enquire status. | |
218 | ||
30058677 | 219 | endif |