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a24532f8 RR |
1 | /* |
2 | * Copyright 2016 Broadcom | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License, version 2, as | |
6 | * published by the Free Software Foundation (the "GPL"). | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License version 2 (GPLv2) for more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License | |
14 | * version 2 (GPLv2) along with this source code. | |
15 | */ | |
16 | ||
17 | /* | |
18 | * Broadcom PDC Mailbox Driver | |
19 | * The PDC provides a ring based programming interface to one or more hardware | |
20 | * offload engines. For example, the PDC driver works with both SPU-M and SPU2 | |
21 | * cryptographic offload hardware. In some chips the PDC is referred to as MDE. | |
22 | * | |
23 | * The PDC driver registers with the Linux mailbox framework as a mailbox | |
24 | * controller, once for each PDC instance. Ring 0 for each PDC is registered as | |
25 | * a mailbox channel. The PDC driver uses interrupts to determine when data | |
26 | * transfers to and from an offload engine are complete. The PDC driver uses | |
27 | * threaded IRQs so that response messages are handled outside of interrupt | |
28 | * context. | |
29 | * | |
30 | * The PDC driver allows multiple messages to be pending in the descriptor | |
31 | * rings. The tx_msg_start descriptor index indicates where the last message | |
32 | * starts. The txin_numd value at this index indicates how many descriptor | |
33 | * indexes make up the message. Similar state is kept on the receive side. When | |
34 | * an rx interrupt indicates a response is ready, the PDC driver processes numd | |
35 | * descriptors from the tx and rx ring, thus processing one response at a time. | |
36 | */ | |
37 | ||
38 | #include <linux/errno.h> | |
39 | #include <linux/module.h> | |
40 | #include <linux/init.h> | |
41 | #include <linux/slab.h> | |
42 | #include <linux/debugfs.h> | |
43 | #include <linux/interrupt.h> | |
44 | #include <linux/wait.h> | |
45 | #include <linux/platform_device.h> | |
46 | #include <linux/io.h> | |
47 | #include <linux/of.h> | |
48 | #include <linux/of_device.h> | |
49 | #include <linux/of_address.h> | |
50 | #include <linux/of_irq.h> | |
51 | #include <linux/mailbox_controller.h> | |
52 | #include <linux/mailbox/brcm-message.h> | |
53 | #include <linux/scatterlist.h> | |
54 | #include <linux/dma-direction.h> | |
55 | #include <linux/dma-mapping.h> | |
56 | #include <linux/dmapool.h> | |
57 | ||
58 | #define PDC_SUCCESS 0 | |
59 | ||
60 | #define RING_ENTRY_SIZE sizeof(struct dma64dd) | |
61 | ||
62 | /* # entries in PDC dma ring */ | |
ab8d1b2d RR |
63 | #define PDC_RING_ENTRIES 512 |
64 | /* | |
65 | * Minimum number of ring descriptor entries that must be free to tell mailbox | |
66 | * framework that it can submit another request | |
67 | */ | |
68 | #define PDC_RING_SPACE_MIN 15 | |
69 | ||
a24532f8 RR |
70 | #define PDC_RING_SIZE (PDC_RING_ENTRIES * RING_ENTRY_SIZE) |
71 | /* Rings are 8k aligned */ | |
72 | #define RING_ALIGN_ORDER 13 | |
73 | #define RING_ALIGN BIT(RING_ALIGN_ORDER) | |
74 | ||
75 | #define RX_BUF_ALIGN_ORDER 5 | |
76 | #define RX_BUF_ALIGN BIT(RX_BUF_ALIGN_ORDER) | |
77 | ||
78 | /* descriptor bumping macros */ | |
79 | #define XXD(x, max_mask) ((x) & (max_mask)) | |
80 | #define TXD(x, max_mask) XXD((x), (max_mask)) | |
81 | #define RXD(x, max_mask) XXD((x), (max_mask)) | |
82 | #define NEXTTXD(i, max_mask) TXD((i) + 1, (max_mask)) | |
83 | #define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask)) | |
84 | #define NEXTRXD(i, max_mask) RXD((i) + 1, (max_mask)) | |
85 | #define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask)) | |
86 | #define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask)) | |
87 | #define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask)) | |
88 | ||
89 | /* Length of BCM header at start of SPU msg, in bytes */ | |
90 | #define BCM_HDR_LEN 8 | |
91 | ||
92 | /* | |
93 | * PDC driver reserves ringset 0 on each SPU for its own use. The driver does | |
94 | * not currently support use of multiple ringsets on a single PDC engine. | |
95 | */ | |
96 | #define PDC_RINGSET 0 | |
97 | ||
98 | /* | |
99 | * Interrupt mask and status definitions. Enable interrupts for tx and rx on | |
100 | * ring 0 | |
101 | */ | |
a24532f8 | 102 | #define PDC_RCVINT_0 (16 + PDC_RINGSET) |
a24532f8 | 103 | #define PDC_RCVINTEN_0 BIT(PDC_RCVINT_0) |
ab8d1b2d | 104 | #define PDC_INTMASK (PDC_RCVINTEN_0) |
a24532f8 RR |
105 | #define PDC_LAZY_FRAMECOUNT 1 |
106 | #define PDC_LAZY_TIMEOUT 10000 | |
107 | #define PDC_LAZY_INT (PDC_LAZY_TIMEOUT | (PDC_LAZY_FRAMECOUNT << 24)) | |
108 | #define PDC_INTMASK_OFFSET 0x24 | |
109 | #define PDC_INTSTATUS_OFFSET 0x20 | |
110 | #define PDC_RCVLAZY0_OFFSET (0x30 + 4 * PDC_RINGSET) | |
111 | ||
112 | /* | |
113 | * For SPU2, configure MDE_CKSUM_CONTROL to write 17 bytes of metadata | |
114 | * before frame | |
115 | */ | |
116 | #define PDC_SPU2_RESP_HDR_LEN 17 | |
117 | #define PDC_CKSUM_CTRL BIT(27) | |
118 | #define PDC_CKSUM_CTRL_OFFSET 0x400 | |
119 | ||
120 | #define PDC_SPUM_RESP_HDR_LEN 32 | |
121 | ||
122 | /* | |
123 | * Sets the following bits for write to transmit control reg: | |
a24532f8 RR |
124 | * 11 - PtyChkDisable - parity check is disabled |
125 | * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory | |
126 | */ | |
9fb0f9ac SL |
127 | #define PDC_TX_CTL 0x000C0800 |
128 | ||
129 | /* Bit in tx control reg to enable tx channel */ | |
130 | #define PDC_TX_ENABLE 0x1 | |
a24532f8 RR |
131 | |
132 | /* | |
133 | * Sets the following bits for write to receive control reg: | |
a24532f8 RR |
134 | * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf |
135 | * 9 - SepRxHdrDescEn - place start of new frames only in descriptors | |
136 | * that have StartOfFrame set | |
137 | * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all | |
138 | * remaining bytes in current frame, report error | |
139 | * in rx frame status for current frame | |
140 | * 11 - PtyChkDisable - parity check is disabled | |
141 | * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory | |
142 | */ | |
9fb0f9ac SL |
143 | #define PDC_RX_CTL 0x000C0E00 |
144 | ||
145 | /* Bit in rx control reg to enable rx channel */ | |
146 | #define PDC_RX_ENABLE 0x1 | |
a24532f8 RR |
147 | |
148 | #define CRYPTO_D64_RS0_CD_MASK ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1) | |
149 | ||
150 | /* descriptor flags */ | |
151 | #define D64_CTRL1_EOT BIT(28) /* end of descriptor table */ | |
152 | #define D64_CTRL1_IOC BIT(29) /* interrupt on complete */ | |
153 | #define D64_CTRL1_EOF BIT(30) /* end of frame */ | |
154 | #define D64_CTRL1_SOF BIT(31) /* start of frame */ | |
155 | ||
156 | #define RX_STATUS_OVERFLOW 0x00800000 | |
157 | #define RX_STATUS_LEN 0x0000FFFF | |
158 | ||
159 | #define PDC_TXREGS_OFFSET 0x200 | |
160 | #define PDC_RXREGS_OFFSET 0x220 | |
161 | ||
162 | /* Maximum size buffer the DMA engine can handle */ | |
163 | #define PDC_DMA_BUF_MAX 16384 | |
164 | ||
165 | struct pdc_dma_map { | |
166 | void *ctx; /* opaque context associated with frame */ | |
167 | }; | |
168 | ||
169 | /* dma descriptor */ | |
170 | struct dma64dd { | |
171 | u32 ctrl1; /* misc control bits */ | |
172 | u32 ctrl2; /* buffer count and address extension */ | |
173 | u32 addrlow; /* memory address of the date buffer, bits 31:0 */ | |
174 | u32 addrhigh; /* memory address of the date buffer, bits 63:32 */ | |
175 | }; | |
176 | ||
177 | /* dma registers per channel(xmt or rcv) */ | |
178 | struct dma64_regs { | |
179 | u32 control; /* enable, et al */ | |
180 | u32 ptr; /* last descriptor posted to chip */ | |
181 | u32 addrlow; /* descriptor ring base address low 32-bits */ | |
182 | u32 addrhigh; /* descriptor ring base address bits 63:32 */ | |
183 | u32 status0; /* last rx descriptor written by hw */ | |
184 | u32 status1; /* driver does not use */ | |
185 | }; | |
186 | ||
187 | /* cpp contortions to concatenate w/arg prescan */ | |
188 | #ifndef PAD | |
189 | #define _PADLINE(line) pad ## line | |
190 | #define _XSTR(line) _PADLINE(line) | |
191 | #define PAD _XSTR(__LINE__) | |
192 | #endif /* PAD */ | |
193 | ||
194 | /* dma registers. matches hw layout. */ | |
195 | struct dma64 { | |
196 | struct dma64_regs dmaxmt; /* dma tx */ | |
197 | u32 PAD[2]; | |
198 | struct dma64_regs dmarcv; /* dma rx */ | |
199 | u32 PAD[2]; | |
200 | }; | |
201 | ||
202 | /* PDC registers */ | |
203 | struct pdc_regs { | |
204 | u32 devcontrol; /* 0x000 */ | |
205 | u32 devstatus; /* 0x004 */ | |
206 | u32 PAD; | |
207 | u32 biststatus; /* 0x00c */ | |
208 | u32 PAD[4]; | |
209 | u32 intstatus; /* 0x020 */ | |
210 | u32 intmask; /* 0x024 */ | |
211 | u32 gptimer; /* 0x028 */ | |
212 | ||
213 | u32 PAD; | |
214 | u32 intrcvlazy_0; /* 0x030 */ | |
215 | u32 intrcvlazy_1; /* 0x034 */ | |
216 | u32 intrcvlazy_2; /* 0x038 */ | |
217 | u32 intrcvlazy_3; /* 0x03c */ | |
218 | ||
219 | u32 PAD[48]; | |
220 | u32 removed_intrecvlazy; /* 0x100 */ | |
221 | u32 flowctlthresh; /* 0x104 */ | |
222 | u32 wrrthresh; /* 0x108 */ | |
223 | u32 gmac_idle_cnt_thresh; /* 0x10c */ | |
224 | ||
225 | u32 PAD[4]; | |
226 | u32 ifioaccessaddr; /* 0x120 */ | |
227 | u32 ifioaccessbyte; /* 0x124 */ | |
228 | u32 ifioaccessdata; /* 0x128 */ | |
229 | ||
230 | u32 PAD[21]; | |
231 | u32 phyaccess; /* 0x180 */ | |
232 | u32 PAD; | |
233 | u32 phycontrol; /* 0x188 */ | |
234 | u32 txqctl; /* 0x18c */ | |
235 | u32 rxqctl; /* 0x190 */ | |
236 | u32 gpioselect; /* 0x194 */ | |
237 | u32 gpio_output_en; /* 0x198 */ | |
238 | u32 PAD; /* 0x19c */ | |
239 | u32 txq_rxq_mem_ctl; /* 0x1a0 */ | |
240 | u32 memory_ecc_status; /* 0x1a4 */ | |
241 | u32 serdes_ctl; /* 0x1a8 */ | |
242 | u32 serdes_status0; /* 0x1ac */ | |
243 | u32 serdes_status1; /* 0x1b0 */ | |
244 | u32 PAD[11]; /* 0x1b4-1dc */ | |
245 | u32 clk_ctl_st; /* 0x1e0 */ | |
246 | u32 hw_war; /* 0x1e4 */ | |
247 | u32 pwrctl; /* 0x1e8 */ | |
248 | u32 PAD[5]; | |
249 | ||
250 | #define PDC_NUM_DMA_RINGS 4 | |
251 | struct dma64 dmaregs[PDC_NUM_DMA_RINGS]; /* 0x0200 - 0x2fc */ | |
252 | ||
253 | /* more registers follow, but we don't use them */ | |
254 | }; | |
255 | ||
256 | /* structure for allocating/freeing DMA rings */ | |
257 | struct pdc_ring_alloc { | |
258 | dma_addr_t dmabase; /* DMA address of start of ring */ | |
259 | void *vbase; /* base kernel virtual address of ring */ | |
260 | u32 size; /* ring allocation size in bytes */ | |
261 | }; | |
262 | ||
263 | /* PDC state structure */ | |
264 | struct pdc_state { | |
a24532f8 RR |
265 | /* Index of the PDC whose state is in this structure instance */ |
266 | u8 pdc_idx; | |
267 | ||
268 | /* Platform device for this PDC instance */ | |
269 | struct platform_device *pdev; | |
270 | ||
271 | /* | |
272 | * Each PDC instance has a mailbox controller. PDC receives request | |
273 | * messages through mailboxes, and sends response messages through the | |
274 | * mailbox framework. | |
275 | */ | |
276 | struct mbox_controller mbc; | |
277 | ||
278 | unsigned int pdc_irq; | |
279 | ||
280 | /* | |
281 | * Last interrupt status read from PDC device. Saved in interrupt | |
282 | * handler so the handler can clear the interrupt in the device, | |
283 | * and the interrupt thread called later can know which interrupt | |
284 | * bits are active. | |
285 | */ | |
286 | unsigned long intstatus; | |
287 | ||
288 | /* Number of bytes of receive status prior to each rx frame */ | |
289 | u32 rx_status_len; | |
290 | /* Whether a BCM header is prepended to each frame */ | |
291 | bool use_bcm_hdr; | |
292 | /* Sum of length of BCM header and rx status header */ | |
293 | u32 pdc_resp_hdr_len; | |
294 | ||
295 | /* The base virtual address of DMA hw registers */ | |
296 | void __iomem *pdc_reg_vbase; | |
297 | ||
298 | /* Pool for allocation of DMA rings */ | |
299 | struct dma_pool *ring_pool; | |
300 | ||
301 | /* Pool for allocation of metadata buffers for response messages */ | |
302 | struct dma_pool *rx_buf_pool; | |
303 | ||
304 | /* | |
305 | * The base virtual address of DMA tx/rx descriptor rings. Corresponding | |
306 | * DMA address and size of ring allocation. | |
307 | */ | |
308 | struct pdc_ring_alloc tx_ring_alloc; | |
309 | struct pdc_ring_alloc rx_ring_alloc; | |
310 | ||
311 | struct pdc_regs *regs; /* start of PDC registers */ | |
312 | ||
313 | struct dma64_regs *txregs_64; /* dma tx engine registers */ | |
314 | struct dma64_regs *rxregs_64; /* dma rx engine registers */ | |
315 | ||
316 | /* | |
317 | * Arrays of PDC_RING_ENTRIES descriptors | |
318 | * To use multiple ringsets, this needs to be extended | |
319 | */ | |
320 | struct dma64dd *txd_64; /* tx descriptor ring */ | |
321 | struct dma64dd *rxd_64; /* rx descriptor ring */ | |
322 | ||
323 | /* descriptor ring sizes */ | |
324 | u32 ntxd; /* # tx descriptors */ | |
325 | u32 nrxd; /* # rx descriptors */ | |
326 | u32 nrxpost; /* # rx buffers to keep posted */ | |
327 | u32 ntxpost; /* max number of tx buffers that can be posted */ | |
328 | ||
329 | /* | |
330 | * Index of next tx descriptor to reclaim. That is, the descriptor | |
331 | * index of the oldest tx buffer for which the host has yet to process | |
332 | * the corresponding response. | |
333 | */ | |
334 | u32 txin; | |
335 | ||
336 | /* | |
337 | * Index of the first receive descriptor for the sequence of | |
338 | * message fragments currently under construction. Used to build up | |
339 | * the rxin_numd count for a message. Updated to rxout when the host | |
340 | * starts a new sequence of rx buffers for a new message. | |
341 | */ | |
342 | u32 tx_msg_start; | |
343 | ||
344 | /* Index of next tx descriptor to post. */ | |
345 | u32 txout; | |
346 | ||
347 | /* | |
348 | * Number of tx descriptors associated with the message that starts | |
349 | * at this tx descriptor index. | |
350 | */ | |
351 | u32 txin_numd[PDC_RING_ENTRIES]; | |
352 | ||
353 | /* | |
354 | * Index of next rx descriptor to reclaim. This is the index of | |
355 | * the next descriptor whose data has yet to be processed by the host. | |
356 | */ | |
357 | u32 rxin; | |
358 | ||
359 | /* | |
360 | * Index of the first receive descriptor for the sequence of | |
361 | * message fragments currently under construction. Used to build up | |
362 | * the rxin_numd count for a message. Updated to rxout when the host | |
363 | * starts a new sequence of rx buffers for a new message. | |
364 | */ | |
365 | u32 rx_msg_start; | |
366 | ||
367 | /* | |
368 | * Saved value of current hardware rx descriptor index. | |
369 | * The last rx buffer written by the hw is the index previous to | |
370 | * this one. | |
371 | */ | |
372 | u32 last_rx_curr; | |
373 | ||
374 | /* Index of next rx descriptor to post. */ | |
375 | u32 rxout; | |
376 | ||
377 | /* | |
378 | * opaque context associated with frame that starts at each | |
379 | * rx ring index. | |
380 | */ | |
381 | void *rxp_ctx[PDC_RING_ENTRIES]; | |
382 | ||
383 | /* | |
384 | * Scatterlists used to form request and reply frames beginning at a | |
385 | * given ring index. Retained in order to unmap each sg after reply | |
386 | * is processed | |
387 | */ | |
388 | struct scatterlist *src_sg[PDC_RING_ENTRIES]; | |
389 | struct scatterlist *dst_sg[PDC_RING_ENTRIES]; | |
390 | ||
391 | /* | |
392 | * Number of rx descriptors associated with the message that starts | |
393 | * at this descriptor index. Not set for every index. For example, | |
394 | * if descriptor index i points to a scatterlist with 4 entries, then | |
395 | * the next three descriptor indexes don't have a value set. | |
396 | */ | |
397 | u32 rxin_numd[PDC_RING_ENTRIES]; | |
398 | ||
399 | void *resp_hdr[PDC_RING_ENTRIES]; | |
400 | dma_addr_t resp_hdr_daddr[PDC_RING_ENTRIES]; | |
401 | ||
402 | struct dentry *debugfs_stats; /* debug FS stats file for this PDC */ | |
403 | ||
404 | /* counters */ | |
ab8d1b2d RR |
405 | u32 pdc_requests; /* number of request messages submitted */ |
406 | u32 pdc_replies; /* number of reply messages received */ | |
407 | u32 last_tx_not_done; /* too few tx descriptors to indicate done */ | |
408 | u32 tx_ring_full; /* unable to accept msg because tx ring full */ | |
409 | u32 rx_ring_full; /* unable to accept msg because rx ring full */ | |
410 | u32 txnobuf; /* unable to create tx descriptor */ | |
411 | u32 rxnobuf; /* unable to create rx descriptor */ | |
412 | u32 rx_oflow; /* count of rx overflows */ | |
a24532f8 RR |
413 | }; |
414 | ||
415 | /* Global variables */ | |
416 | ||
417 | struct pdc_globals { | |
418 | /* Actual number of SPUs in hardware, as reported by device tree */ | |
419 | u32 num_spu; | |
420 | }; | |
421 | ||
422 | static struct pdc_globals pdcg; | |
423 | ||
424 | /* top level debug FS directory for PDC driver */ | |
425 | static struct dentry *debugfs_dir; | |
426 | ||
427 | static ssize_t pdc_debugfs_read(struct file *filp, char __user *ubuf, | |
428 | size_t count, loff_t *offp) | |
429 | { | |
430 | struct pdc_state *pdcs; | |
431 | char *buf; | |
432 | ssize_t ret, out_offset, out_count; | |
433 | ||
434 | out_count = 512; | |
435 | ||
436 | buf = kmalloc(out_count, GFP_KERNEL); | |
437 | if (!buf) | |
438 | return -ENOMEM; | |
439 | ||
440 | pdcs = filp->private_data; | |
441 | out_offset = 0; | |
442 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
443 | "SPU %u stats:\n", pdcs->pdc_idx); | |
444 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
ab8d1b2d | 445 | "PDC requests....................%u\n", |
a24532f8 RR |
446 | pdcs->pdc_requests); |
447 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
ab8d1b2d | 448 | "PDC responses...................%u\n", |
a24532f8 RR |
449 | pdcs->pdc_replies); |
450 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
ab8d1b2d RR |
451 | "Tx not done.....................%u\n", |
452 | pdcs->last_tx_not_done); | |
453 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
454 | "Tx ring full....................%u\n", | |
455 | pdcs->tx_ring_full); | |
456 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
457 | "Rx ring full....................%u\n", | |
458 | pdcs->rx_ring_full); | |
459 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
460 | "Tx desc write fail. Ring full...%u\n", | |
a24532f8 RR |
461 | pdcs->txnobuf); |
462 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
ab8d1b2d | 463 | "Rx desc write fail. Ring full...%u\n", |
a24532f8 RR |
464 | pdcs->rxnobuf); |
465 | out_offset += snprintf(buf + out_offset, out_count - out_offset, | |
ab8d1b2d | 466 | "Receive overflow................%u\n", |
a24532f8 | 467 | pdcs->rx_oflow); |
ab8d1b2d RR |
468 | out_offset += snprintf(buf + out_offset, out_count - out_offset, |
469 | "Num frags in rx ring............%u\n", | |
470 | NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, | |
471 | pdcs->nrxpost)); | |
a24532f8 RR |
472 | |
473 | if (out_offset > out_count) | |
474 | out_offset = out_count; | |
475 | ||
476 | ret = simple_read_from_buffer(ubuf, count, offp, buf, out_offset); | |
477 | kfree(buf); | |
478 | return ret; | |
479 | } | |
480 | ||
481 | static const struct file_operations pdc_debugfs_stats = { | |
482 | .owner = THIS_MODULE, | |
483 | .open = simple_open, | |
484 | .read = pdc_debugfs_read, | |
485 | }; | |
486 | ||
487 | /** | |
488 | * pdc_setup_debugfs() - Create the debug FS directories. If the top-level | |
489 | * directory has not yet been created, create it now. Create a stats file in | |
490 | * this directory for a SPU. | |
491 | * @pdcs: PDC state structure | |
492 | */ | |
a75e4a85 | 493 | static void pdc_setup_debugfs(struct pdc_state *pdcs) |
a24532f8 RR |
494 | { |
495 | char spu_stats_name[16]; | |
496 | ||
497 | if (!debugfs_initialized()) | |
498 | return; | |
499 | ||
500 | snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx); | |
501 | if (!debugfs_dir) | |
502 | debugfs_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); | |
503 | ||
9b1b2b3a RR |
504 | /* S_IRUSR == 0400 */ |
505 | pdcs->debugfs_stats = debugfs_create_file(spu_stats_name, 0400, | |
a24532f8 RR |
506 | debugfs_dir, pdcs, |
507 | &pdc_debugfs_stats); | |
508 | } | |
509 | ||
a75e4a85 | 510 | static void pdc_free_debugfs(void) |
a24532f8 | 511 | { |
9310f1de SL |
512 | debugfs_remove_recursive(debugfs_dir); |
513 | debugfs_dir = NULL; | |
a24532f8 RR |
514 | } |
515 | ||
516 | /** | |
517 | * pdc_build_rxd() - Build DMA descriptor to receive SPU result. | |
518 | * @pdcs: PDC state for SPU that will generate result | |
519 | * @dma_addr: DMA address of buffer that descriptor is being built for | |
520 | * @buf_len: Length of the receive buffer, in bytes | |
521 | * @flags: Flags to be stored in descriptor | |
522 | */ | |
523 | static inline void | |
524 | pdc_build_rxd(struct pdc_state *pdcs, dma_addr_t dma_addr, | |
525 | u32 buf_len, u32 flags) | |
526 | { | |
527 | struct device *dev = &pdcs->pdev->dev; | |
528 | ||
529 | dev_dbg(dev, | |
530 | "Writing rx descriptor for PDC %u at index %u with length %u. flags %#x\n", | |
531 | pdcs->pdc_idx, pdcs->rxout, buf_len, flags); | |
532 | ||
533 | iowrite32(lower_32_bits(dma_addr), | |
534 | (void *)&pdcs->rxd_64[pdcs->rxout].addrlow); | |
535 | iowrite32(upper_32_bits(dma_addr), | |
536 | (void *)&pdcs->rxd_64[pdcs->rxout].addrhigh); | |
537 | iowrite32(flags, (void *)&pdcs->rxd_64[pdcs->rxout].ctrl1); | |
538 | iowrite32(buf_len, (void *)&pdcs->rxd_64[pdcs->rxout].ctrl2); | |
539 | /* bump ring index and return */ | |
540 | pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost); | |
541 | } | |
542 | ||
543 | /** | |
544 | * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to | |
545 | * hardware. | |
546 | * @pdcs: PDC state for the SPU that will process this request | |
547 | * @dma_addr: DMA address of packet to be transmitted | |
548 | * @buf_len: Length of tx buffer, in bytes | |
549 | * @flags: Flags to be stored in descriptor | |
550 | */ | |
551 | static inline void | |
552 | pdc_build_txd(struct pdc_state *pdcs, dma_addr_t dma_addr, u32 buf_len, | |
553 | u32 flags) | |
554 | { | |
555 | struct device *dev = &pdcs->pdev->dev; | |
556 | ||
557 | dev_dbg(dev, | |
558 | "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n", | |
559 | pdcs->pdc_idx, pdcs->txout, buf_len, flags); | |
560 | ||
561 | iowrite32(lower_32_bits(dma_addr), | |
562 | (void *)&pdcs->txd_64[pdcs->txout].addrlow); | |
563 | iowrite32(upper_32_bits(dma_addr), | |
564 | (void *)&pdcs->txd_64[pdcs->txout].addrhigh); | |
565 | iowrite32(flags, (void *)&pdcs->txd_64[pdcs->txout].ctrl1); | |
566 | iowrite32(buf_len, (void *)&pdcs->txd_64[pdcs->txout].ctrl2); | |
567 | ||
568 | /* bump ring index and return */ | |
569 | pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost); | |
570 | } | |
571 | ||
572 | /** | |
573 | * pdc_receive() - Receive a response message from a given SPU. | |
574 | * @pdcs: PDC state for the SPU to receive from | |
575 | * @mssg: mailbox message to be returned to client | |
576 | * | |
577 | * When the return code indicates success, the response message is available in | |
578 | * the receive buffers provided prior to submission of the request. | |
579 | * | |
580 | * Input: | |
581 | * pdcs - PDC state structure for the SPU to be polled | |
582 | * mssg - mailbox message to be returned to client. This function sets the | |
583 | * context pointer on the message to help the client associate the | |
584 | * response with a request. | |
585 | * | |
586 | * Return: PDC_SUCCESS if one or more receive descriptors was processed | |
587 | * -EAGAIN indicates that no response message is available | |
588 | * -EIO an error occurred | |
589 | */ | |
590 | static int | |
591 | pdc_receive(struct pdc_state *pdcs, struct brcm_message *mssg) | |
592 | { | |
593 | struct device *dev = &pdcs->pdev->dev; | |
594 | u32 len, rx_status; | |
595 | u32 num_frags; | |
596 | int i; | |
597 | u8 *resp_hdr; /* virtual addr of start of resp message DMA header */ | |
598 | u32 frags_rdy; /* number of fragments ready to read */ | |
599 | u32 rx_idx; /* ring index of start of receive frame */ | |
600 | dma_addr_t resp_hdr_daddr; | |
601 | ||
a24532f8 RR |
602 | /* |
603 | * return if a complete response message is not yet ready. | |
604 | * rxin_numd[rxin] is the number of fragments in the next msg | |
605 | * to read. | |
606 | */ | |
607 | frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost); | |
608 | if ((frags_rdy == 0) || (frags_rdy < pdcs->rxin_numd[pdcs->rxin])) { | |
609 | /* See if the hw has written more fragments than we know */ | |
610 | pdcs->last_rx_curr = | |
611 | (ioread32((void *)&pdcs->rxregs_64->status0) & | |
612 | CRYPTO_D64_RS0_CD_MASK) / RING_ENTRY_SIZE; | |
613 | frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, | |
614 | pdcs->nrxpost); | |
615 | if ((frags_rdy == 0) || | |
616 | (frags_rdy < pdcs->rxin_numd[pdcs->rxin])) { | |
617 | /* No response ready */ | |
a24532f8 RR |
618 | return -EAGAIN; |
619 | } | |
620 | /* can't read descriptors/data until write index is read */ | |
621 | rmb(); | |
622 | } | |
623 | ||
624 | num_frags = pdcs->txin_numd[pdcs->txin]; | |
625 | dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin], | |
626 | sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE); | |
627 | ||
628 | for (i = 0; i < num_frags; i++) | |
629 | pdcs->txin = NEXTTXD(pdcs->txin, pdcs->ntxpost); | |
630 | ||
631 | dev_dbg(dev, "PDC %u reclaimed %d tx descriptors", | |
632 | pdcs->pdc_idx, num_frags); | |
633 | ||
634 | rx_idx = pdcs->rxin; | |
635 | num_frags = pdcs->rxin_numd[rx_idx]; | |
636 | /* Return opaque context with result */ | |
637 | mssg->ctx = pdcs->rxp_ctx[rx_idx]; | |
638 | pdcs->rxp_ctx[rx_idx] = NULL; | |
639 | resp_hdr = pdcs->resp_hdr[rx_idx]; | |
640 | resp_hdr_daddr = pdcs->resp_hdr_daddr[rx_idx]; | |
641 | dma_unmap_sg(dev, pdcs->dst_sg[rx_idx], | |
642 | sg_nents(pdcs->dst_sg[rx_idx]), DMA_FROM_DEVICE); | |
643 | ||
644 | for (i = 0; i < num_frags; i++) | |
645 | pdcs->rxin = NEXTRXD(pdcs->rxin, pdcs->nrxpost); | |
646 | ||
a24532f8 RR |
647 | dev_dbg(dev, "PDC %u reclaimed %d rx descriptors", |
648 | pdcs->pdc_idx, num_frags); | |
649 | ||
650 | dev_dbg(dev, | |
651 | "PDC %u txin %u, txout %u, rxin %u, rxout %u, last_rx_curr %u\n", | |
652 | pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin, | |
653 | pdcs->rxout, pdcs->last_rx_curr); | |
654 | ||
655 | if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) { | |
656 | /* | |
657 | * For SPU-M, get length of response msg and rx overflow status. | |
658 | */ | |
659 | rx_status = *((u32 *)resp_hdr); | |
660 | len = rx_status & RX_STATUS_LEN; | |
661 | dev_dbg(dev, | |
662 | "SPU response length %u bytes", len); | |
663 | if (unlikely(((rx_status & RX_STATUS_OVERFLOW) || (!len)))) { | |
664 | if (rx_status & RX_STATUS_OVERFLOW) { | |
665 | dev_err_ratelimited(dev, | |
666 | "crypto receive overflow"); | |
667 | pdcs->rx_oflow++; | |
668 | } else { | |
669 | dev_info_ratelimited(dev, "crypto rx len = 0"); | |
670 | } | |
671 | return -EIO; | |
672 | } | |
673 | } | |
674 | ||
675 | dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr); | |
676 | ||
677 | pdcs->pdc_replies++; | |
678 | /* if we read one or more rx descriptors, claim success */ | |
679 | if (num_frags > 0) | |
680 | return PDC_SUCCESS; | |
681 | else | |
682 | return -EIO; | |
683 | } | |
684 | ||
685 | /** | |
686 | * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit | |
687 | * descriptors for a given SPU. The scatterlist buffers contain the data for a | |
688 | * SPU request message. | |
689 | * @spu_idx: The index of the SPU to submit the request to, [0, max_spu) | |
690 | * @sg: Scatterlist whose buffers contain part of the SPU request | |
691 | * | |
692 | * If a scatterlist buffer is larger than PDC_DMA_BUF_MAX, multiple descriptors | |
693 | * are written for that buffer, each <= PDC_DMA_BUF_MAX byte in length. | |
694 | * | |
695 | * Return: PDC_SUCCESS if successful | |
696 | * < 0 otherwise | |
697 | */ | |
698 | static int pdc_tx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg) | |
699 | { | |
700 | u32 flags = 0; | |
701 | u32 eot; | |
702 | u32 tx_avail; | |
703 | ||
704 | /* | |
705 | * Num descriptors needed. Conservatively assume we need a descriptor | |
706 | * for every entry in sg. | |
707 | */ | |
708 | u32 num_desc; | |
709 | u32 desc_w = 0; /* Number of tx descriptors written */ | |
710 | u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */ | |
711 | dma_addr_t databufptr; /* DMA address to put in descriptor */ | |
712 | ||
713 | num_desc = (u32)sg_nents(sg); | |
714 | ||
715 | /* check whether enough tx descriptors are available */ | |
716 | tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, | |
717 | pdcs->ntxpost); | |
718 | if (unlikely(num_desc > tx_avail)) { | |
719 | pdcs->txnobuf++; | |
720 | return -ENOSPC; | |
721 | } | |
722 | ||
723 | /* build tx descriptors */ | |
724 | if (pdcs->tx_msg_start == pdcs->txout) { | |
725 | /* Start of frame */ | |
726 | pdcs->txin_numd[pdcs->tx_msg_start] = 0; | |
727 | pdcs->src_sg[pdcs->txout] = sg; | |
728 | flags = D64_CTRL1_SOF; | |
729 | } | |
730 | ||
731 | while (sg) { | |
732 | if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) | |
733 | eot = D64_CTRL1_EOT; | |
734 | else | |
735 | eot = 0; | |
736 | ||
737 | /* | |
738 | * If sg buffer larger than PDC limit, split across | |
739 | * multiple descriptors | |
740 | */ | |
741 | bufcnt = sg_dma_len(sg); | |
742 | databufptr = sg_dma_address(sg); | |
743 | while (bufcnt > PDC_DMA_BUF_MAX) { | |
744 | pdc_build_txd(pdcs, databufptr, PDC_DMA_BUF_MAX, | |
745 | flags | eot); | |
746 | desc_w++; | |
747 | bufcnt -= PDC_DMA_BUF_MAX; | |
748 | databufptr += PDC_DMA_BUF_MAX; | |
749 | if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) | |
750 | eot = D64_CTRL1_EOT; | |
751 | else | |
752 | eot = 0; | |
753 | } | |
754 | sg = sg_next(sg); | |
755 | if (!sg) | |
756 | /* Writing last descriptor for frame */ | |
757 | flags |= (D64_CTRL1_EOF | D64_CTRL1_IOC); | |
758 | pdc_build_txd(pdcs, databufptr, bufcnt, flags | eot); | |
759 | desc_w++; | |
760 | /* Clear start of frame after first descriptor */ | |
761 | flags &= ~D64_CTRL1_SOF; | |
762 | } | |
763 | pdcs->txin_numd[pdcs->tx_msg_start] += desc_w; | |
764 | ||
765 | return PDC_SUCCESS; | |
766 | } | |
767 | ||
768 | /** | |
769 | * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx | |
770 | * ring. | |
771 | * @pdcs: PDC state for SPU to process the request | |
772 | * | |
773 | * Sets the index of the last descriptor written in both the rx and tx ring. | |
774 | * | |
775 | * Return: PDC_SUCCESS | |
776 | */ | |
777 | static int pdc_tx_list_final(struct pdc_state *pdcs) | |
778 | { | |
779 | /* | |
780 | * write barrier to ensure all register writes are complete | |
781 | * before chip starts to process new request | |
782 | */ | |
783 | wmb(); | |
784 | iowrite32(pdcs->rxout << 4, (void *)&pdcs->rxregs_64->ptr); | |
785 | iowrite32(pdcs->txout << 4, (void *)&pdcs->txregs_64->ptr); | |
786 | pdcs->pdc_requests++; | |
787 | ||
788 | return PDC_SUCCESS; | |
789 | } | |
790 | ||
791 | /** | |
792 | * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC. | |
793 | * @pdcs: PDC state for SPU handling request | |
794 | * @dst_sg: scatterlist providing rx buffers for response to be returned to | |
795 | * mailbox client | |
796 | * @ctx: Opaque context for this request | |
797 | * | |
798 | * Posts a single receive descriptor to hold the metadata that precedes a | |
799 | * response. For example, with SPU-M, the metadata is a 32-byte DMA header and | |
800 | * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and | |
801 | * rx to indicate the start of a new message. | |
802 | * | |
803 | * Return: PDC_SUCCESS if successful | |
804 | * < 0 if an error (e.g., rx ring is full) | |
805 | */ | |
806 | static int pdc_rx_list_init(struct pdc_state *pdcs, struct scatterlist *dst_sg, | |
807 | void *ctx) | |
808 | { | |
809 | u32 flags = 0; | |
810 | u32 rx_avail; | |
811 | u32 rx_pkt_cnt = 1; /* Adding a single rx buffer */ | |
812 | dma_addr_t daddr; | |
813 | void *vaddr; | |
814 | ||
815 | rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, | |
816 | pdcs->nrxpost); | |
817 | if (unlikely(rx_pkt_cnt > rx_avail)) { | |
818 | pdcs->rxnobuf++; | |
819 | return -ENOSPC; | |
820 | } | |
821 | ||
822 | /* allocate a buffer for the dma rx status */ | |
823 | vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr); | |
824 | if (!vaddr) | |
825 | return -ENOMEM; | |
826 | ||
827 | /* | |
828 | * Update msg_start indexes for both tx and rx to indicate the start | |
829 | * of a new sequence of descriptor indexes that contain the fragments | |
830 | * of the same message. | |
831 | */ | |
832 | pdcs->rx_msg_start = pdcs->rxout; | |
833 | pdcs->tx_msg_start = pdcs->txout; | |
834 | ||
835 | /* This is always the first descriptor in the receive sequence */ | |
836 | flags = D64_CTRL1_SOF; | |
837 | pdcs->rxin_numd[pdcs->rx_msg_start] = 1; | |
838 | ||
839 | if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) | |
840 | flags |= D64_CTRL1_EOT; | |
841 | ||
842 | pdcs->rxp_ctx[pdcs->rxout] = ctx; | |
843 | pdcs->dst_sg[pdcs->rxout] = dst_sg; | |
844 | pdcs->resp_hdr[pdcs->rxout] = vaddr; | |
845 | pdcs->resp_hdr_daddr[pdcs->rxout] = daddr; | |
846 | pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags); | |
847 | return PDC_SUCCESS; | |
848 | } | |
849 | ||
850 | /** | |
851 | * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive | |
852 | * descriptors for a given SPU. The caller must have already DMA mapped the | |
853 | * scatterlist. | |
854 | * @spu_idx: Indicates which SPU the buffers are for | |
855 | * @sg: Scatterlist whose buffers are added to the receive ring | |
856 | * | |
857 | * If a receive buffer in the scatterlist is larger than PDC_DMA_BUF_MAX, | |
858 | * multiple receive descriptors are written, each with a buffer <= | |
859 | * PDC_DMA_BUF_MAX. | |
860 | * | |
861 | * Return: PDC_SUCCESS if successful | |
862 | * < 0 otherwise (e.g., receive ring is full) | |
863 | */ | |
864 | static int pdc_rx_list_sg_add(struct pdc_state *pdcs, struct scatterlist *sg) | |
865 | { | |
866 | u32 flags = 0; | |
867 | u32 rx_avail; | |
868 | ||
869 | /* | |
870 | * Num descriptors needed. Conservatively assume we need a descriptor | |
871 | * for every entry from our starting point in the scatterlist. | |
872 | */ | |
873 | u32 num_desc; | |
874 | u32 desc_w = 0; /* Number of tx descriptors written */ | |
875 | u32 bufcnt; /* Number of bytes of buffer pointed to by descriptor */ | |
876 | dma_addr_t databufptr; /* DMA address to put in descriptor */ | |
877 | ||
878 | num_desc = (u32)sg_nents(sg); | |
879 | ||
880 | rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, | |
881 | pdcs->nrxpost); | |
882 | if (unlikely(num_desc > rx_avail)) { | |
883 | pdcs->rxnobuf++; | |
884 | return -ENOSPC; | |
885 | } | |
886 | ||
887 | while (sg) { | |
888 | if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) | |
889 | flags = D64_CTRL1_EOT; | |
890 | else | |
891 | flags = 0; | |
892 | ||
893 | /* | |
894 | * If sg buffer larger than PDC limit, split across | |
895 | * multiple descriptors | |
896 | */ | |
897 | bufcnt = sg_dma_len(sg); | |
898 | databufptr = sg_dma_address(sg); | |
899 | while (bufcnt > PDC_DMA_BUF_MAX) { | |
900 | pdc_build_rxd(pdcs, databufptr, PDC_DMA_BUF_MAX, flags); | |
901 | desc_w++; | |
902 | bufcnt -= PDC_DMA_BUF_MAX; | |
903 | databufptr += PDC_DMA_BUF_MAX; | |
904 | if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) | |
905 | flags = D64_CTRL1_EOT; | |
906 | else | |
907 | flags = 0; | |
908 | } | |
909 | pdc_build_rxd(pdcs, databufptr, bufcnt, flags); | |
910 | desc_w++; | |
911 | sg = sg_next(sg); | |
912 | } | |
913 | pdcs->rxin_numd[pdcs->rx_msg_start] += desc_w; | |
914 | ||
915 | return PDC_SUCCESS; | |
916 | } | |
917 | ||
918 | /** | |
919 | * pdc_irq_handler() - Interrupt handler called in interrupt context. | |
920 | * @irq: Interrupt number that has fired | |
921 | * @cookie: PDC state for DMA engine that generated the interrupt | |
922 | * | |
923 | * We have to clear the device interrupt status flags here. So cache the | |
924 | * status for later use in the thread function. Other than that, just return | |
925 | * WAKE_THREAD to invoke the thread function. | |
926 | * | |
927 | * Return: IRQ_WAKE_THREAD if interrupt is ours | |
928 | * IRQ_NONE otherwise | |
929 | */ | |
930 | static irqreturn_t pdc_irq_handler(int irq, void *cookie) | |
931 | { | |
932 | struct pdc_state *pdcs = cookie; | |
933 | u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); | |
934 | ||
a24532f8 RR |
935 | if (intstatus & PDC_RCVINTEN_0) |
936 | set_bit(PDC_RCVINT_0, &pdcs->intstatus); | |
937 | ||
938 | /* Clear interrupt flags in device */ | |
939 | iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); | |
940 | ||
941 | /* Wakeup IRQ thread */ | |
942 | if (pdcs && (irq == pdcs->pdc_irq) && (intstatus & PDC_INTMASK)) | |
943 | return IRQ_WAKE_THREAD; | |
944 | ||
945 | return IRQ_NONE; | |
946 | } | |
947 | ||
948 | /** | |
949 | * pdc_irq_thread() - Function invoked on deferred thread when a DMA tx has | |
950 | * completed or data is available to receive. | |
951 | * @irq: Interrupt number | |
952 | * @cookie: PDC state for PDC that generated the interrupt | |
953 | * | |
954 | * On DMA tx complete, notify the mailbox client. On DMA rx complete, process | |
955 | * as many SPU response messages as are available and send each to the mailbox | |
956 | * client. | |
957 | * | |
958 | * Return: IRQ_HANDLED if we recognized and handled the interrupt | |
959 | * IRQ_NONE otherwise | |
960 | */ | |
961 | static irqreturn_t pdc_irq_thread(int irq, void *cookie) | |
962 | { | |
963 | struct pdc_state *pdcs = cookie; | |
964 | struct mbox_controller *mbc; | |
965 | struct mbox_chan *chan; | |
a24532f8 RR |
966 | bool rx_int; |
967 | int rx_status; | |
968 | struct brcm_message mssg; | |
969 | ||
a24532f8 RR |
970 | rx_int = test_and_clear_bit(PDC_RCVINT_0, &pdcs->intstatus); |
971 | ||
ab8d1b2d | 972 | if (pdcs && rx_int) { |
a24532f8 | 973 | dev_dbg(&pdcs->pdev->dev, |
ab8d1b2d RR |
974 | "%s() got irq %d with rx_int %s", |
975 | __func__, irq, rx_int ? "set" : "clear"); | |
a24532f8 RR |
976 | |
977 | mbc = &pdcs->mbc; | |
978 | chan = &mbc->chans[0]; | |
979 | ||
ab8d1b2d RR |
980 | while (1) { |
981 | /* Could be many frames ready */ | |
982 | memset(&mssg, 0, sizeof(mssg)); | |
983 | mssg.type = BRCM_MESSAGE_SPU; | |
984 | rx_status = pdc_receive(pdcs, &mssg); | |
985 | if (rx_status >= 0) { | |
986 | dev_dbg(&pdcs->pdev->dev, | |
987 | "%s(): invoking client rx cb", | |
988 | __func__); | |
989 | mbox_chan_received_data(chan, &mssg); | |
990 | } else { | |
991 | dev_dbg(&pdcs->pdev->dev, | |
992 | "%s(): no SPU response available", | |
993 | __func__); | |
994 | break; | |
a24532f8 RR |
995 | } |
996 | } | |
997 | return IRQ_HANDLED; | |
998 | } | |
999 | return IRQ_NONE; | |
1000 | } | |
1001 | ||
1002 | /** | |
1003 | * pdc_ring_init() - Allocate DMA rings and initialize constant fields of | |
1004 | * descriptors in one ringset. | |
1005 | * @pdcs: PDC instance state | |
1006 | * @ringset: index of ringset being used | |
1007 | * | |
1008 | * Return: PDC_SUCCESS if ring initialized | |
1009 | * < 0 otherwise | |
1010 | */ | |
1011 | static int pdc_ring_init(struct pdc_state *pdcs, int ringset) | |
1012 | { | |
1013 | int i; | |
1014 | int err = PDC_SUCCESS; | |
1015 | struct dma64 *dma_reg; | |
1016 | struct device *dev = &pdcs->pdev->dev; | |
1017 | struct pdc_ring_alloc tx; | |
1018 | struct pdc_ring_alloc rx; | |
1019 | ||
1020 | /* Allocate tx ring */ | |
1021 | tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase); | |
1022 | if (!tx.vbase) { | |
1023 | err = -ENOMEM; | |
1024 | goto done; | |
1025 | } | |
1026 | ||
1027 | /* Allocate rx ring */ | |
1028 | rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase); | |
1029 | if (!rx.vbase) { | |
1030 | err = -ENOMEM; | |
1031 | goto fail_dealloc; | |
1032 | } | |
1033 | ||
a68b2166 | 1034 | dev_dbg(dev, " - base DMA addr of tx ring %pad", &tx.dmabase); |
a24532f8 | 1035 | dev_dbg(dev, " - base virtual addr of tx ring %p", tx.vbase); |
a68b2166 | 1036 | dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase); |
a24532f8 RR |
1037 | dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase); |
1038 | ||
a24532f8 RR |
1039 | memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx)); |
1040 | memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx)); | |
1041 | ||
1042 | pdcs->rxin = 0; | |
1043 | pdcs->rx_msg_start = 0; | |
1044 | pdcs->last_rx_curr = 0; | |
1045 | pdcs->rxout = 0; | |
1046 | pdcs->txin = 0; | |
1047 | pdcs->tx_msg_start = 0; | |
1048 | pdcs->txout = 0; | |
1049 | ||
1050 | /* Set descriptor array base addresses */ | |
1051 | pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase; | |
1052 | pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase; | |
1053 | ||
1054 | /* Tell device the base DMA address of each ring */ | |
1055 | dma_reg = &pdcs->regs->dmaregs[ringset]; | |
9fb0f9ac SL |
1056 | |
1057 | /* But first disable DMA and set curptr to 0 for both TX & RX */ | |
1058 | iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); | |
1059 | iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)), | |
1060 | (void *)&dma_reg->dmarcv.control); | |
1061 | iowrite32(0, (void *)&dma_reg->dmaxmt.ptr); | |
1062 | iowrite32(0, (void *)&dma_reg->dmarcv.ptr); | |
1063 | ||
1064 | /* Set base DMA addresses */ | |
a24532f8 RR |
1065 | iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase), |
1066 | (void *)&dma_reg->dmaxmt.addrlow); | |
1067 | iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase), | |
1068 | (void *)&dma_reg->dmaxmt.addrhigh); | |
1069 | ||
1070 | iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase), | |
1071 | (void *)&dma_reg->dmarcv.addrlow); | |
1072 | iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase), | |
1073 | (void *)&dma_reg->dmarcv.addrhigh); | |
1074 | ||
9fb0f9ac SL |
1075 | /* Re-enable DMA */ |
1076 | iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control); | |
1077 | iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)), | |
1078 | (void *)&dma_reg->dmarcv.control); | |
1079 | ||
a24532f8 RR |
1080 | /* Initialize descriptors */ |
1081 | for (i = 0; i < PDC_RING_ENTRIES; i++) { | |
1082 | /* Every tx descriptor can be used for start of frame. */ | |
1083 | if (i != pdcs->ntxpost) { | |
1084 | iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF, | |
1085 | (void *)&pdcs->txd_64[i].ctrl1); | |
1086 | } else { | |
1087 | /* Last descriptor in ringset. Set End of Table. */ | |
1088 | iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOF | | |
1089 | D64_CTRL1_EOT, | |
1090 | (void *)&pdcs->txd_64[i].ctrl1); | |
1091 | } | |
1092 | ||
1093 | /* Every rx descriptor can be used for start of frame */ | |
1094 | if (i != pdcs->nrxpost) { | |
1095 | iowrite32(D64_CTRL1_SOF, | |
1096 | (void *)&pdcs->rxd_64[i].ctrl1); | |
1097 | } else { | |
1098 | /* Last descriptor in ringset. Set End of Table. */ | |
1099 | iowrite32(D64_CTRL1_SOF | D64_CTRL1_EOT, | |
1100 | (void *)&pdcs->rxd_64[i].ctrl1); | |
1101 | } | |
1102 | } | |
a24532f8 RR |
1103 | return PDC_SUCCESS; |
1104 | ||
1105 | fail_dealloc: | |
1106 | dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase); | |
1107 | done: | |
1108 | return err; | |
1109 | } | |
1110 | ||
1111 | static void pdc_ring_free(struct pdc_state *pdcs) | |
1112 | { | |
1113 | if (pdcs->tx_ring_alloc.vbase) { | |
1114 | dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase, | |
1115 | pdcs->tx_ring_alloc.dmabase); | |
1116 | pdcs->tx_ring_alloc.vbase = NULL; | |
1117 | } | |
1118 | ||
1119 | if (pdcs->rx_ring_alloc.vbase) { | |
1120 | dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase, | |
1121 | pdcs->rx_ring_alloc.dmabase); | |
1122 | pdcs->rx_ring_alloc.vbase = NULL; | |
1123 | } | |
1124 | } | |
1125 | ||
ab8d1b2d RR |
1126 | /** |
1127 | * pdc_desc_count() - Count the number of DMA descriptors that will be required | |
1128 | * for a given scatterlist. Account for the max length of a DMA buffer. | |
1129 | * @sg: Scatterlist to be DMA'd | |
1130 | * Return: Number of descriptors required | |
1131 | */ | |
1132 | static u32 pdc_desc_count(struct scatterlist *sg) | |
1133 | { | |
1134 | u32 cnt = 0; | |
1135 | ||
1136 | while (sg) { | |
1137 | cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1); | |
1138 | sg = sg_next(sg); | |
1139 | } | |
1140 | return cnt; | |
1141 | } | |
1142 | ||
1143 | /** | |
1144 | * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors | |
1145 | * and the rx ring has room for rx_cnt descriptors. | |
1146 | * @pdcs: PDC state | |
1147 | * @tx_cnt: The number of descriptors required in the tx ring | |
1148 | * @rx_cnt: The number of descriptors required i the rx ring | |
1149 | * | |
1150 | * Return: true if one of the rings does not have enough space | |
1151 | * false if sufficient space is available in both rings | |
1152 | */ | |
1153 | static bool pdc_rings_full(struct pdc_state *pdcs, int tx_cnt, int rx_cnt) | |
1154 | { | |
1155 | u32 rx_avail; | |
1156 | u32 tx_avail; | |
1157 | bool full = false; | |
1158 | ||
1159 | /* Check if the tx and rx rings are likely to have enough space */ | |
1160 | rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, | |
1161 | pdcs->nrxpost); | |
1162 | if (unlikely(rx_cnt > rx_avail)) { | |
1163 | pdcs->rx_ring_full++; | |
1164 | full = true; | |
1165 | } | |
1166 | ||
1167 | if (likely(!full)) { | |
1168 | tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, | |
1169 | pdcs->ntxpost); | |
1170 | if (unlikely(tx_cnt > tx_avail)) { | |
1171 | pdcs->tx_ring_full++; | |
1172 | full = true; | |
1173 | } | |
1174 | } | |
1175 | return full; | |
1176 | } | |
1177 | ||
1178 | /** | |
1179 | * pdc_last_tx_done() - If both the tx and rx rings have at least | |
1180 | * PDC_RING_SPACE_MIN descriptors available, then indicate that the mailbox | |
1181 | * framework can submit another message. | |
1182 | * @chan: mailbox channel to check | |
1183 | * Return: true if PDC can accept another message on this channel | |
1184 | */ | |
1185 | static bool pdc_last_tx_done(struct mbox_chan *chan) | |
1186 | { | |
1187 | struct pdc_state *pdcs = chan->con_priv; | |
1188 | bool ret; | |
1189 | ||
1190 | if (unlikely(pdc_rings_full(pdcs, PDC_RING_SPACE_MIN, | |
1191 | PDC_RING_SPACE_MIN))) { | |
1192 | pdcs->last_tx_not_done++; | |
1193 | ret = false; | |
1194 | } else { | |
1195 | ret = true; | |
1196 | } | |
1197 | return ret; | |
1198 | } | |
1199 | ||
a24532f8 RR |
1200 | /** |
1201 | * pdc_send_data() - mailbox send_data function | |
1202 | * @chan: The mailbox channel on which the data is sent. The channel | |
1203 | * corresponds to a DMA ringset. | |
1204 | * @data: The mailbox message to be sent. The message must be a | |
1205 | * brcm_message structure. | |
1206 | * | |
1207 | * This function is registered as the send_data function for the mailbox | |
1208 | * controller. From the destination scatterlist in the mailbox message, it | |
1209 | * creates a sequence of receive descriptors in the rx ring. From the source | |
1210 | * scatterlist, it creates a sequence of transmit descriptors in the tx ring. | |
1211 | * After creating the descriptors, it writes the rx ptr and tx ptr registers to | |
1212 | * initiate the DMA transfer. | |
1213 | * | |
1214 | * This function does the DMA map and unmap of the src and dst scatterlists in | |
1215 | * the mailbox message. | |
1216 | * | |
1217 | * Return: 0 if successful | |
1218 | * -ENOTSUPP if the mailbox message is a type this driver does not | |
1219 | * support | |
1220 | * < 0 if an error | |
1221 | */ | |
1222 | static int pdc_send_data(struct mbox_chan *chan, void *data) | |
1223 | { | |
1224 | struct pdc_state *pdcs = chan->con_priv; | |
1225 | struct device *dev = &pdcs->pdev->dev; | |
1226 | struct brcm_message *mssg = data; | |
1227 | int err = PDC_SUCCESS; | |
1228 | int src_nent; | |
1229 | int dst_nent; | |
1230 | int nent; | |
ab8d1b2d RR |
1231 | u32 tx_desc_req; |
1232 | u32 rx_desc_req; | |
a24532f8 RR |
1233 | |
1234 | if (mssg->type != BRCM_MESSAGE_SPU) | |
1235 | return -ENOTSUPP; | |
1236 | ||
1237 | src_nent = sg_nents(mssg->spu.src); | |
1238 | if (src_nent) { | |
1239 | nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE); | |
1240 | if (nent == 0) | |
1241 | return -EIO; | |
1242 | } | |
1243 | ||
1244 | dst_nent = sg_nents(mssg->spu.dst); | |
1245 | if (dst_nent) { | |
1246 | nent = dma_map_sg(dev, mssg->spu.dst, dst_nent, | |
1247 | DMA_FROM_DEVICE); | |
1248 | if (nent == 0) { | |
1249 | dma_unmap_sg(dev, mssg->spu.src, src_nent, | |
1250 | DMA_TO_DEVICE); | |
1251 | return -EIO; | |
1252 | } | |
1253 | } | |
1254 | ||
ab8d1b2d RR |
1255 | /* |
1256 | * Check if the tx and rx rings have enough space. Do this prior to | |
1257 | * writing any tx or rx descriptors. Need to ensure that we do not write | |
1258 | * a partial set of descriptors, or write just rx descriptors but | |
1259 | * corresponding tx descriptors don't fit. Note that we want this check | |
1260 | * and the entire sequence of descriptor to happen without another | |
1261 | * thread getting in. The channel spin lock in the mailbox framework | |
1262 | * ensures this. | |
1263 | */ | |
1264 | tx_desc_req = pdc_desc_count(mssg->spu.src); | |
1265 | rx_desc_req = pdc_desc_count(mssg->spu.dst); | |
1266 | if (pdc_rings_full(pdcs, tx_desc_req, rx_desc_req + 1)) | |
1267 | return -ENOSPC; | |
a24532f8 RR |
1268 | |
1269 | /* Create rx descriptors to SPU catch response */ | |
1270 | err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx); | |
1271 | err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst); | |
1272 | ||
1273 | /* Create tx descriptors to submit SPU request */ | |
1274 | err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src); | |
1275 | err |= pdc_tx_list_final(pdcs); /* initiate transfer */ | |
1276 | ||
a24532f8 RR |
1277 | if (err) |
1278 | dev_err(&pdcs->pdev->dev, | |
1279 | "%s failed with error %d", __func__, err); | |
1280 | ||
1281 | return err; | |
1282 | } | |
1283 | ||
1284 | static int pdc_startup(struct mbox_chan *chan) | |
1285 | { | |
1286 | return pdc_ring_init(chan->con_priv, PDC_RINGSET); | |
1287 | } | |
1288 | ||
1289 | static void pdc_shutdown(struct mbox_chan *chan) | |
1290 | { | |
1291 | struct pdc_state *pdcs = chan->con_priv; | |
1292 | ||
068cf29e DC |
1293 | if (!pdcs) |
1294 | return; | |
a24532f8 | 1295 | |
068cf29e DC |
1296 | dev_dbg(&pdcs->pdev->dev, |
1297 | "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx); | |
a24532f8 RR |
1298 | pdc_ring_free(pdcs); |
1299 | } | |
1300 | ||
1301 | /** | |
1302 | * pdc_hw_init() - Use the given initialization parameters to initialize the | |
1303 | * state for one of the PDCs. | |
1304 | * @pdcs: state of the PDC | |
1305 | */ | |
1306 | static | |
1307 | void pdc_hw_init(struct pdc_state *pdcs) | |
1308 | { | |
1309 | struct platform_device *pdev; | |
1310 | struct device *dev; | |
1311 | struct dma64 *dma_reg; | |
1312 | int ringset = PDC_RINGSET; | |
1313 | ||
1314 | pdev = pdcs->pdev; | |
1315 | dev = &pdev->dev; | |
1316 | ||
1317 | dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx); | |
1318 | dev_dbg(dev, "state structure: %p", | |
1319 | pdcs); | |
1320 | dev_dbg(dev, " - base virtual addr of hw regs %p", | |
1321 | pdcs->pdc_reg_vbase); | |
1322 | ||
1323 | /* initialize data structures */ | |
1324 | pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase; | |
1325 | pdcs->txregs_64 = (struct dma64_regs *) | |
1326 | (void *)(((u8 *)pdcs->pdc_reg_vbase) + | |
1327 | PDC_TXREGS_OFFSET + (sizeof(struct dma64) * ringset)); | |
1328 | pdcs->rxregs_64 = (struct dma64_regs *) | |
1329 | (void *)(((u8 *)pdcs->pdc_reg_vbase) + | |
1330 | PDC_RXREGS_OFFSET + (sizeof(struct dma64) * ringset)); | |
1331 | ||
1332 | pdcs->ntxd = PDC_RING_ENTRIES; | |
1333 | pdcs->nrxd = PDC_RING_ENTRIES; | |
1334 | pdcs->ntxpost = PDC_RING_ENTRIES - 1; | |
1335 | pdcs->nrxpost = PDC_RING_ENTRIES - 1; | |
9fb0f9ac | 1336 | iowrite32(0, &pdcs->regs->intmask); |
a24532f8 RR |
1337 | |
1338 | dma_reg = &pdcs->regs->dmaregs[ringset]; | |
a24532f8 | 1339 | |
9fb0f9ac SL |
1340 | /* Configure DMA but will enable later in pdc_ring_init() */ |
1341 | iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); | |
a24532f8 RR |
1342 | |
1343 | iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), | |
1344 | (void *)&dma_reg->dmarcv.control); | |
1345 | ||
9fb0f9ac SL |
1346 | /* Reset current index pointers after making sure DMA is disabled */ |
1347 | iowrite32(0, &dma_reg->dmaxmt.ptr); | |
1348 | iowrite32(0, &dma_reg->dmarcv.ptr); | |
1349 | ||
a24532f8 RR |
1350 | if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN) |
1351 | iowrite32(PDC_CKSUM_CTRL, | |
1352 | pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET); | |
1353 | } | |
1354 | ||
9fb0f9ac SL |
1355 | /** |
1356 | * pdc_hw_disable() - Disable the tx and rx control in the hw. | |
1357 | * @pdcs: PDC state structure | |
1358 | * | |
1359 | */ | |
1360 | static void pdc_hw_disable(struct pdc_state *pdcs) | |
1361 | { | |
1362 | struct dma64 *dma_reg; | |
1363 | ||
1364 | dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET]; | |
1365 | iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); | |
1366 | iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), | |
1367 | &dma_reg->dmarcv.control); | |
1368 | } | |
1369 | ||
a24532f8 RR |
1370 | /** |
1371 | * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata | |
1372 | * header returned with each response message. | |
1373 | * @pdcs: PDC state structure | |
1374 | * | |
1375 | * The metadata is not returned to the mailbox client. So the PDC driver | |
1376 | * manages these buffers. | |
1377 | * | |
1378 | * Return: PDC_SUCCESS | |
1379 | * -ENOMEM if pool creation fails | |
1380 | */ | |
1381 | static int pdc_rx_buf_pool_create(struct pdc_state *pdcs) | |
1382 | { | |
1383 | struct platform_device *pdev; | |
1384 | struct device *dev; | |
1385 | ||
1386 | pdev = pdcs->pdev; | |
1387 | dev = &pdev->dev; | |
1388 | ||
1389 | pdcs->pdc_resp_hdr_len = pdcs->rx_status_len; | |
1390 | if (pdcs->use_bcm_hdr) | |
1391 | pdcs->pdc_resp_hdr_len += BCM_HDR_LEN; | |
1392 | ||
1393 | pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev, | |
1394 | pdcs->pdc_resp_hdr_len, | |
1395 | RX_BUF_ALIGN, 0); | |
1396 | if (!pdcs->rx_buf_pool) | |
1397 | return -ENOMEM; | |
1398 | ||
1399 | return PDC_SUCCESS; | |
1400 | } | |
1401 | ||
1402 | /** | |
1403 | * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and | |
1404 | * specify a threaded IRQ handler for deferred handling of interrupts outside of | |
1405 | * interrupt context. | |
1406 | * @pdcs: PDC state | |
1407 | * | |
1408 | * Set the interrupt mask for transmit and receive done. | |
1409 | * Set the lazy interrupt frame count to generate an interrupt for just one pkt. | |
1410 | * | |
1411 | * Return: PDC_SUCCESS | |
1412 | * <0 if threaded irq request fails | |
1413 | */ | |
1414 | static int pdc_interrupts_init(struct pdc_state *pdcs) | |
1415 | { | |
1416 | struct platform_device *pdev = pdcs->pdev; | |
1417 | struct device *dev = &pdev->dev; | |
1418 | struct device_node *dn = pdev->dev.of_node; | |
1419 | int err; | |
1420 | ||
1421 | pdcs->intstatus = 0; | |
1422 | ||
1423 | /* interrupt configuration */ | |
1424 | iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); | |
1425 | iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + PDC_RCVLAZY0_OFFSET); | |
1426 | ||
1427 | /* read irq from device tree */ | |
1428 | pdcs->pdc_irq = irq_of_parse_and_map(dn, 0); | |
1429 | dev_dbg(dev, "pdc device %s irq %u for pdcs %p", | |
1430 | dev_name(dev), pdcs->pdc_irq, pdcs); | |
1431 | err = devm_request_threaded_irq(dev, pdcs->pdc_irq, | |
1432 | pdc_irq_handler, | |
1433 | pdc_irq_thread, 0, dev_name(dev), pdcs); | |
1434 | if (err) { | |
1435 | dev_err(dev, "threaded tx IRQ %u request failed with err %d\n", | |
1436 | pdcs->pdc_irq, err); | |
1437 | return err; | |
1438 | } | |
1439 | return PDC_SUCCESS; | |
1440 | } | |
1441 | ||
1442 | static const struct mbox_chan_ops pdc_mbox_chan_ops = { | |
1443 | .send_data = pdc_send_data, | |
ab8d1b2d | 1444 | .last_tx_done = pdc_last_tx_done, |
a24532f8 RR |
1445 | .startup = pdc_startup, |
1446 | .shutdown = pdc_shutdown | |
1447 | }; | |
1448 | ||
1449 | /** | |
1450 | * pdc_mb_init() - Initialize the mailbox controller. | |
1451 | * @pdcs: PDC state | |
1452 | * | |
1453 | * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel | |
1454 | * driver only uses one ringset and thus one mb channel. PDC uses the transmit | |
1455 | * complete interrupt to determine when a mailbox message has successfully been | |
1456 | * transmitted. | |
1457 | * | |
1458 | * Return: 0 on success | |
1459 | * < 0 if there is an allocation or registration failure | |
1460 | */ | |
1461 | static int pdc_mb_init(struct pdc_state *pdcs) | |
1462 | { | |
1463 | struct device *dev = &pdcs->pdev->dev; | |
1464 | struct mbox_controller *mbc; | |
1465 | int chan_index; | |
1466 | int err; | |
1467 | ||
1468 | mbc = &pdcs->mbc; | |
1469 | mbc->dev = dev; | |
1470 | mbc->ops = &pdc_mbox_chan_ops; | |
1471 | mbc->num_chans = 1; | |
1472 | mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans), | |
1473 | GFP_KERNEL); | |
1474 | if (!mbc->chans) | |
1475 | return -ENOMEM; | |
1476 | ||
ab8d1b2d RR |
1477 | mbc->txdone_irq = false; |
1478 | mbc->txdone_poll = true; | |
1479 | mbc->txpoll_period = 1; | |
a24532f8 RR |
1480 | for (chan_index = 0; chan_index < mbc->num_chans; chan_index++) |
1481 | mbc->chans[chan_index].con_priv = pdcs; | |
1482 | ||
1483 | /* Register mailbox controller */ | |
1484 | err = mbox_controller_register(mbc); | |
1485 | if (err) { | |
1486 | dev_crit(dev, | |
1487 | "Failed to register PDC mailbox controller. Error %d.", | |
1488 | err); | |
1489 | return err; | |
1490 | } | |
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | /** | |
1495 | * pdc_dt_read() - Read application-specific data from device tree. | |
1496 | * @pdev: Platform device | |
1497 | * @pdcs: PDC state | |
1498 | * | |
1499 | * Reads the number of bytes of receive status that precede each received frame. | |
1500 | * Reads whether transmit and received frames should be preceded by an 8-byte | |
1501 | * BCM header. | |
1502 | * | |
1503 | * Return: 0 if successful | |
1504 | * -ENODEV if device not available | |
1505 | */ | |
1506 | static int pdc_dt_read(struct platform_device *pdev, struct pdc_state *pdcs) | |
1507 | { | |
1508 | struct device *dev = &pdev->dev; | |
1509 | struct device_node *dn = pdev->dev.of_node; | |
1510 | int err; | |
1511 | ||
1512 | err = of_property_read_u32(dn, "brcm,rx-status-len", | |
1513 | &pdcs->rx_status_len); | |
1514 | if (err < 0) | |
1515 | dev_err(dev, | |
1516 | "%s failed to get DMA receive status length from device tree", | |
1517 | __func__); | |
1518 | ||
1519 | pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr"); | |
1520 | ||
1521 | return 0; | |
1522 | } | |
1523 | ||
1524 | /** | |
1525 | * pdc_probe() - Probe function for PDC driver. | |
1526 | * @pdev: PDC platform device | |
1527 | * | |
1528 | * Reserve and map register regions defined in device tree. | |
1529 | * Allocate and initialize tx and rx DMA rings. | |
1530 | * Initialize a mailbox controller for each PDC. | |
1531 | * | |
1532 | * Return: 0 if successful | |
1533 | * < 0 if an error | |
1534 | */ | |
1535 | static int pdc_probe(struct platform_device *pdev) | |
1536 | { | |
1537 | int err = 0; | |
1538 | struct device *dev = &pdev->dev; | |
1539 | struct resource *pdc_regs; | |
1540 | struct pdc_state *pdcs; | |
1541 | ||
1542 | /* PDC state for one SPU */ | |
1543 | pdcs = devm_kzalloc(dev, sizeof(*pdcs), GFP_KERNEL); | |
1544 | if (!pdcs) { | |
1545 | err = -ENOMEM; | |
1546 | goto cleanup; | |
1547 | } | |
1548 | ||
a24532f8 RR |
1549 | pdcs->pdev = pdev; |
1550 | platform_set_drvdata(pdev, pdcs); | |
1551 | pdcs->pdc_idx = pdcg.num_spu; | |
1552 | pdcg.num_spu++; | |
1553 | ||
1554 | err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); | |
1555 | if (err) { | |
1556 | dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err); | |
1557 | goto cleanup; | |
1558 | } | |
1559 | ||
1560 | /* Create DMA pool for tx ring */ | |
1561 | pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE, | |
1562 | RING_ALIGN, 0); | |
1563 | if (!pdcs->ring_pool) { | |
1564 | err = -ENOMEM; | |
1565 | goto cleanup; | |
1566 | } | |
1567 | ||
1568 | err = pdc_dt_read(pdev, pdcs); | |
1569 | if (err) | |
1570 | goto cleanup_ring_pool; | |
1571 | ||
1572 | pdc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1573 | if (!pdc_regs) { | |
1574 | err = -ENODEV; | |
1575 | goto cleanup_ring_pool; | |
1576 | } | |
a68b2166 RR |
1577 | dev_dbg(dev, "PDC register region res.start = %pa, res.end = %pa", |
1578 | &pdc_regs->start, &pdc_regs->end); | |
a24532f8 RR |
1579 | |
1580 | pdcs->pdc_reg_vbase = devm_ioremap_resource(&pdev->dev, pdc_regs); | |
1581 | if (IS_ERR(pdcs->pdc_reg_vbase)) { | |
1582 | err = PTR_ERR(pdcs->pdc_reg_vbase); | |
1583 | dev_err(&pdev->dev, "Failed to map registers: %d\n", err); | |
1584 | goto cleanup_ring_pool; | |
1585 | } | |
1586 | ||
1587 | /* create rx buffer pool after dt read to know how big buffers are */ | |
1588 | err = pdc_rx_buf_pool_create(pdcs); | |
1589 | if (err) | |
1590 | goto cleanup_ring_pool; | |
1591 | ||
1592 | pdc_hw_init(pdcs); | |
1593 | ||
1594 | err = pdc_interrupts_init(pdcs); | |
1595 | if (err) | |
1596 | goto cleanup_buf_pool; | |
1597 | ||
1598 | /* Initialize mailbox controller */ | |
1599 | err = pdc_mb_init(pdcs); | |
1600 | if (err) | |
1601 | goto cleanup_buf_pool; | |
1602 | ||
1603 | pdcs->debugfs_stats = NULL; | |
1604 | pdc_setup_debugfs(pdcs); | |
1605 | ||
1606 | dev_dbg(dev, "pdc_probe() successful"); | |
1607 | return PDC_SUCCESS; | |
1608 | ||
1609 | cleanup_buf_pool: | |
1610 | dma_pool_destroy(pdcs->rx_buf_pool); | |
1611 | ||
1612 | cleanup_ring_pool: | |
1613 | dma_pool_destroy(pdcs->ring_pool); | |
1614 | ||
1615 | cleanup: | |
1616 | return err; | |
1617 | } | |
1618 | ||
1619 | static int pdc_remove(struct platform_device *pdev) | |
1620 | { | |
1621 | struct pdc_state *pdcs = platform_get_drvdata(pdev); | |
1622 | ||
1623 | pdc_free_debugfs(); | |
1624 | ||
9fb0f9ac SL |
1625 | pdc_hw_disable(pdcs); |
1626 | ||
a24532f8 RR |
1627 | mbox_controller_unregister(&pdcs->mbc); |
1628 | ||
1629 | dma_pool_destroy(pdcs->rx_buf_pool); | |
1630 | dma_pool_destroy(pdcs->ring_pool); | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | static const struct of_device_id pdc_mbox_of_match[] = { | |
1635 | {.compatible = "brcm,iproc-pdc-mbox"}, | |
1636 | { /* sentinel */ } | |
1637 | }; | |
1638 | MODULE_DEVICE_TABLE(of, pdc_mbox_of_match); | |
1639 | ||
1640 | static struct platform_driver pdc_mbox_driver = { | |
1641 | .probe = pdc_probe, | |
1642 | .remove = pdc_remove, | |
1643 | .driver = { | |
1644 | .name = "brcm-iproc-pdc-mbox", | |
1645 | .of_match_table = of_match_ptr(pdc_mbox_of_match), | |
1646 | }, | |
1647 | }; | |
1648 | module_platform_driver(pdc_mbox_driver); | |
1649 | ||
1650 | MODULE_AUTHOR("Rob Rice <rob.rice@broadcom.com>"); | |
1651 | MODULE_DESCRIPTION("Broadcom PDC mailbox driver"); | |
1652 | MODULE_LICENSE("GPL v2"); |