[mirror_ubuntu-bionic-kernel.git] / drivers / mailbox / mailbox-omap2.c

/*
 * Mailbox reservation modules for OMAP2/3
 *
 * Copyright (C) 2006-2009 Nokia Corporation
 * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
 *        and  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#include <linux/module.h>
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/mailbox-omap.h>

#include "omap-mbox.h"

#define MAILBOX_REVISION		0x000
#define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
#define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
#define MAILBOX_MSGSTATUS(m)		(0x0c0 + 4 * (m))
#define MAILBOX_IRQSTATUS(u)		(0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u)		(0x104 + 8 * (u))

#define OMAP4_MAILBOX_IRQSTATUS(u)	(0x104 + 0x10 * (u))
#define OMAP4_MAILBOX_IRQENABLE(u)	(0x108 + 0x10 * (u))
#define OMAP4_MAILBOX_IRQENABLE_CLR(u)	(0x10c + 0x10 * (u))

#define MAILBOX_IRQ_NEWMSG(m)		(1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m)		(1 << (2 * (m) + 1))

#define MBOX_REG_SIZE			0x120

#define OMAP4_MBOX_REG_SIZE		0x130

#define MBOX_NR_REGS			(MBOX_REG_SIZE / sizeof(u32))
#define OMAP4_MBOX_NR_REGS		(OMAP4_MBOX_REG_SIZE / sizeof(u32))

static void __iomem *mbox_base;

struct omap_mbox2_fifo {
	unsigned long msg;
	unsigned long fifo_stat;
	unsigned long msg_stat;
};

struct omap_mbox2_priv {
	struct omap_mbox2_fifo tx_fifo;
	struct omap_mbox2_fifo rx_fifo;
	unsigned long irqenable;
	unsigned long irqstatus;
	u32 newmsg_bit;
	u32 notfull_bit;
	u32 ctx[OMAP4_MBOX_NR_REGS];
	unsigned long irqdisable;
	u32 intr_type;
};

static inline unsigned int mbox_read_reg(size_t ofs)
{
	return __raw_readl(mbox_base + ofs);
}

static inline void mbox_write_reg(u32 val, size_t ofs)
{
	__raw_writel(val, mbox_base + ofs);
}

/* Mailbox H/W preparations */
static int omap2_mbox_startup(struct omap_mbox *mbox)
{
	u32 l;

	pm_runtime_enable(mbox->dev->parent);
	pm_runtime_get_sync(mbox->dev->parent);

	l = mbox_read_reg(MAILBOX_REVISION);
	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));

	return 0;
}

static void omap2_mbox_shutdown(struct omap_mbox *mbox)
{
	pm_runtime_put_sync(mbox->dev->parent);
	pm_runtime_disable(mbox->dev->parent);
}

/* Mailbox FIFO handle functions */
static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_msg_t) mbox_read_reg(fifo->msg);
}

static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	mbox_write_reg(msg, fifo->msg);
}

static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	return (mbox_read_reg(fifo->msg_stat) == 0);
}

static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
{
	struct omap_mbox2_fifo *fifo =
		&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	return mbox_read_reg(fifo->fifo_stat);
}

/* Mailbox IRQ handle functions */
static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	l = mbox_read_reg(p->irqenable);
	l |= bit;
	mbox_write_reg(l, p->irqenable);
}

static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	/*
	 * Read and update the interrupt configuration register for pre-OMAP4.
	 * OMAP4 and later SoCs have a dedicated interrupt disabling register.
	 */
	if (!p->intr_type)
		bit = mbox_read_reg(p->irqdisable) & ~bit;

	mbox_write_reg(bit, p->irqdisable);
}

static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;

	mbox_write_reg(bit, p->irqstatus);

	/* Flush posted write for irq status to avoid spurious interrupts */
	mbox_read_reg(p->irqstatus);
}

static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
{
	struct omap_mbox2_priv *p = mbox->priv;
	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	u32 enable = mbox_read_reg(p->irqenable);
	u32 status = mbox_read_reg(p->irqstatus);

	return (int)(enable & status & bit);
}

static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;

	if (p->intr_type)
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		p->ctx[i] = mbox_read_reg(i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
{
	int i;
	struct omap_mbox2_priv *p = mbox->priv;
	int nr_regs;

	if (p->intr_type)
		nr_regs = OMAP4_MBOX_NR_REGS;
	else
		nr_regs = MBOX_NR_REGS;
	for (i = 0; i < nr_regs; i++) {
		mbox_write_reg(p->ctx[i], i * sizeof(u32));

		dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
			i, p->ctx[i]);
	}
}

static struct omap_mbox_ops omap2_mbox_ops = {
	.type		= OMAP_MBOX_TYPE2,
	.startup	= omap2_mbox_startup,
	.shutdown	= omap2_mbox_shutdown,
	.fifo_read	= omap2_mbox_fifo_read,
	.fifo_write	= omap2_mbox_fifo_write,
	.fifo_empty	= omap2_mbox_fifo_empty,
	.fifo_full	= omap2_mbox_fifo_full,
	.enable_irq	= omap2_mbox_enable_irq,
	.disable_irq	= omap2_mbox_disable_irq,
	.ack_irq	= omap2_mbox_ack_irq,
	.is_irq		= omap2_mbox_is_irq,
	.save_ctx	= omap2_mbox_save_ctx,
	.restore_ctx	= omap2_mbox_restore_ctx,
};

static int omap2_mbox_probe(struct platform_device *pdev)
{
	struct resource *mem;
	int ret;
	struct omap_mbox **list, *mbox, *mboxblk;
	struct omap_mbox2_priv *priv, *privblk;
	struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
	struct omap_mbox_dev_info *info;
	int i;

	if (!pdata || !pdata->info_cnt || !pdata->info) {
		pr_err("%s: platform not supported\n", __func__);
		return -ENODEV;
	}

	/* allocate one extra for marking end of list */
	list = kzalloc((pdata->info_cnt + 1) * sizeof(*list), GFP_KERNEL);
	if (!list)
		return -ENOMEM;

	mboxblk = mbox = kzalloc(pdata->info_cnt * sizeof(*mbox), GFP_KERNEL);
	if (!mboxblk) {
		ret = -ENOMEM;
		goto free_list;
	}

	privblk = priv = kzalloc(pdata->info_cnt * sizeof(*priv), GFP_KERNEL);
	if (!privblk) {
		ret = -ENOMEM;
		goto free_mboxblk;
	}

	info = pdata->info;
	for (i = 0; i < pdata->info_cnt; i++, info++, priv++) {
		priv->tx_fifo.msg = MAILBOX_MESSAGE(info->tx_id);
		priv->tx_fifo.fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id);
		priv->rx_fifo.msg =  MAILBOX_MESSAGE(info->rx_id);
		priv->rx_fifo.msg_stat =  MAILBOX_MSGSTATUS(info->rx_id);
		priv->notfull_bit = MAILBOX_IRQ_NOTFULL(info->tx_id);
		priv->newmsg_bit = MAILBOX_IRQ_NEWMSG(info->rx_id);
		if (pdata->intr_type) {
			priv->irqenable = OMAP4_MAILBOX_IRQENABLE(info->usr_id);
			priv->irqstatus = OMAP4_MAILBOX_IRQSTATUS(info->usr_id);
			priv->irqdisable =
				OMAP4_MAILBOX_IRQENABLE_CLR(info->usr_id);
		} else {
			priv->irqenable = MAILBOX_IRQENABLE(info->usr_id);
			priv->irqstatus = MAILBOX_IRQSTATUS(info->usr_id);
			priv->irqdisable = MAILBOX_IRQENABLE(info->usr_id);
		}
		priv->intr_type = pdata->intr_type;

		mbox->priv = priv;
		mbox->name = info->name;
		mbox->ops = &omap2_mbox_ops;
		mbox->irq = platform_get_irq(pdev, info->irq_id);
		if (mbox->irq < 0) {
			ret = mbox->irq;
			goto free_privblk;
		}
		list[i] = mbox++;
	}

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		ret = -ENOENT;
		goto free_privblk;
	}

	mbox_base = ioremap(mem->start, resource_size(mem));
	if (!mbox_base) {
		ret = -ENOMEM;
		goto free_privblk;
	}

	ret = omap_mbox_register(&pdev->dev, list);
	if (ret)
		goto unmap_mbox;
	platform_set_drvdata(pdev, list);

	return 0;

unmap_mbox:
	iounmap(mbox_base);
free_privblk:
	kfree(privblk);
free_mboxblk:
	kfree(mboxblk);
free_list:
	kfree(list);
	return ret;
}

static int omap2_mbox_remove(struct platform_device *pdev)
{
	struct omap_mbox2_priv *privblk;
	struct omap_mbox **list = platform_get_drvdata(pdev);
	struct omap_mbox *mboxblk = list[0];

	privblk = mboxblk->priv;
	omap_mbox_unregister();
	iounmap(mbox_base);
	kfree(privblk);
	kfree(mboxblk);
	kfree(list);

	return 0;
}

static struct platform_driver omap2_mbox_driver = {
	.probe	= omap2_mbox_probe,
	.remove	= omap2_mbox_remove,
	.driver	= {
		.name = "omap-mailbox",
	},
};

static int __init omap2_mbox_init(void)
{
	return platform_driver_register(&omap2_mbox_driver);
}

static void __exit omap2_mbox_exit(void)
{
	platform_driver_unregister(&omap2_mbox_driver);
}

module_init(omap2_mbox_init);
module_exit(omap2_mbox_exit);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
MODULE_AUTHOR("Paul Mundt");
MODULE_ALIAS("platform:omap2-mailbox");
Commit	Line	Data
340a614a	1	/*
733ecc5c	2	* Mailbox reservation modules for OMAP2/3
340a614a	3	*
733ecc5c	4	* Copyright (C) 2006-2009 Nokia Corporation
340a614a	5	* Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
733ecc5c	6	* and Paul Mundt
340a614a HD	7	*
	8	* This file is subject to the terms and conditions of the GNU General Public
	9	* License. See the file "COPYING" in the main directory of this archive
	10	* for more details.
	11	*/
	12
a1bcc1dc	13	#include <linux/module.h>
b8a7cf8e	14	#include <linux/slab.h>
340a614a HD	15	#include <linux/clk.h>
	16	#include <linux/err.h>
	17	#include <linux/platform_device.h>
fced80c7	18	#include <linux/io.h>
82d2a5db	19	#include <linux/pm_runtime.h>
b8a7cf8e	20	#include <linux/platform_data/mailbox-omap.h>
7d7e1eba	21
c869c75c	22	#include "omap-mbox.h"
340a614a	23
733ecc5c	24	#define MAILBOX_REVISION 0x000
733ecc5c HD	25	#define MAILBOX_MESSAGE(m) (0x040 + 4 * (m))
	26	#define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m))
	27	#define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m))
	28	#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
	29	#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
340a614a	30
256a4bd7 TL	31	#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
	32	#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
	33	#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
5f00ec64 S	34
	35	#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
	36	#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
340a614a	37
c75ee752	38	#define MBOX_REG_SIZE 0x120
5f00ec64 S	39
	40	#define OMAP4_MBOX_REG_SIZE 0x130
	41
c75ee752	42	#define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32))
5f00ec64	43	#define OMAP4_MBOX_NR_REGS (OMAP4_MBOX_REG_SIZE / sizeof(u32))
c75ee752	44
6c20a683	45	static void __iomem *mbox_base;
340a614a HD	46
	47	struct omap_mbox2_fifo {
	48	unsigned long msg;
	49	unsigned long fifo_stat;
	50	unsigned long msg_stat;
	51	};
	52
	53	struct omap_mbox2_priv {
	54	struct omap_mbox2_fifo tx_fifo;
	55	struct omap_mbox2_fifo rx_fifo;
	56	unsigned long irqenable;
	57	unsigned long irqstatus;
	58	u32 newmsg_bit;
	59	u32 notfull_bit;
5f00ec64 S	60	u32 ctx[OMAP4_MBOX_NR_REGS];
5f00ec64 S	61	unsigned long irqdisable;
b8a7cf8e	62	u32 intr_type;
340a614a HD	63	};
340a614a HD	64
6c20a683	65	static inline unsigned int mbox_read_reg(size_t ofs)
340a614a	66	{
6c20a683	67	return __raw_readl(mbox_base + ofs);
340a614a HD	68	}
340a614a HD	69
6c20a683	70	static inline void mbox_write_reg(u32 val, size_t ofs)
340a614a	71	{
6c20a683	72	__raw_writel(val, mbox_base + ofs);
340a614a HD	73	}
	74
	75	/* Mailbox H/W preparations */
bfbdcf8a	76	static int omap2_mbox_startup(struct omap_mbox *mbox)
340a614a	77	{
1ffe627d	78	u32 l;
340a614a	79
82d2a5db ORL	80	pm_runtime_enable(mbox->dev->parent);
82d2a5db ORL	81	pm_runtime_get_sync(mbox->dev->parent);
1ffe627d	82
94fc58c6	83	l = mbox_read_reg(MAILBOX_REVISION);
909f9dc7	84	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
94fc58c6	85
340a614a HD	86	return 0;
	87	}
	88
bfbdcf8a	89	static void omap2_mbox_shutdown(struct omap_mbox *mbox)
340a614a	90	{
82d2a5db ORL	91	pm_runtime_put_sync(mbox->dev->parent);
82d2a5db ORL	92	pm_runtime_disable(mbox->dev->parent);
340a614a HD	93	}
	94
	95	/* Mailbox FIFO handle functions */
bfbdcf8a	96	static mbox_msg_t omap2_mbox_fifo_read(struct omap_mbox *mbox)
340a614a HD	97	{
	98	struct omap_mbox2_fifo *fifo =
	99	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	100	return (mbox_msg_t) mbox_read_reg(fifo->msg);
	101	}
	102
bfbdcf8a	103	static void omap2_mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg)
340a614a HD	104	{
	105	struct omap_mbox2_fifo *fifo =
	106	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
	107	mbox_write_reg(msg, fifo->msg);
	108	}
	109
bfbdcf8a	110	static int omap2_mbox_fifo_empty(struct omap_mbox *mbox)
340a614a HD	111	{
	112	struct omap_mbox2_fifo *fifo =
	113	&((struct omap_mbox2_priv *)mbox->priv)->rx_fifo;
	114	return (mbox_read_reg(fifo->msg_stat) == 0);
	115	}
	116
bfbdcf8a	117	static int omap2_mbox_fifo_full(struct omap_mbox *mbox)
340a614a HD	118	{
	119	struct omap_mbox2_fifo *fifo =
	120	&((struct omap_mbox2_priv *)mbox->priv)->tx_fifo;
5f00ec64	121	return mbox_read_reg(fifo->fifo_stat);
340a614a HD	122	}
	123
	124	/* Mailbox IRQ handle functions */
f91ca05f	125	static void omap2_mbox_enable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	126	{
b45b501c	127	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	128	u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	129
	130	l = mbox_read_reg(p->irqenable);
	131	l \|= bit;
	132	mbox_write_reg(l, p->irqenable);
	133	}
	134
f91ca05f	135	static void omap2_mbox_disable_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	136	{
b45b501c	137	struct omap_mbox2_priv *p = mbox->priv;
525a1138 HK	138	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
525a1138 HK	139
b8a7cf8e SA	140	/*
	141	* Read and update the interrupt configuration register for pre-OMAP4.
	142	* OMAP4 and later SoCs have a dedicated interrupt disabling register.
	143	*/
	144	if (!p->intr_type)
525a1138 HK	145	bit = mbox_read_reg(p->irqdisable) & ~bit;
	146
	147	mbox_write_reg(bit, p->irqdisable);
340a614a HD	148	}
340a614a HD	149
f91ca05f	150	static void omap2_mbox_ack_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	151	{
b45b501c	152	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	153	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	154
	155	mbox_write_reg(bit, p->irqstatus);
8828880d HD	156
	157	/* Flush posted write for irq status to avoid spurious interrupts */
	158	mbox_read_reg(p->irqstatus);
340a614a HD	159	}
340a614a HD	160
f91ca05f	161	static int omap2_mbox_is_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
340a614a	162	{
b45b501c	163	struct omap_mbox2_priv *p = mbox->priv;
340a614a HD	164	u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
	165	u32 enable = mbox_read_reg(p->irqenable);
	166	u32 status = mbox_read_reg(p->irqstatus);
	167
5f00ec64	168	return (int)(enable & status & bit);
340a614a HD	169	}
340a614a HD	170
c75ee752 HD	171	static void omap2_mbox_save_ctx(struct omap_mbox *mbox)
	172	{
	173	int i;
	174	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64	175	int nr_regs;
b8a7cf8e SA	176
b8a7cf8e SA	177	if (p->intr_type)
5f00ec64 S	178	nr_regs = OMAP4_MBOX_NR_REGS;
	179	else
	180	nr_regs = MBOX_NR_REGS;
	181	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	182	p->ctx[i] = mbox_read_reg(i * sizeof(u32));
	183
	184	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	185	i, p->ctx[i]);
	186	}
	187	}
	188
	189	static void omap2_mbox_restore_ctx(struct omap_mbox *mbox)
	190	{
	191	int i;
	192	struct omap_mbox2_priv *p = mbox->priv;
5f00ec64	193	int nr_regs;
b8a7cf8e SA	194
b8a7cf8e SA	195	if (p->intr_type)
5f00ec64 S	196	nr_regs = OMAP4_MBOX_NR_REGS;
	197	else
	198	nr_regs = MBOX_NR_REGS;
	199	for (i = 0; i < nr_regs; i++) {
c75ee752 HD	200	mbox_write_reg(p->ctx[i], i * sizeof(u32));
	201
	202	dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__,
	203	i, p->ctx[i]);
	204	}
	205	}
	206
340a614a HD	207	static struct omap_mbox_ops omap2_mbox_ops = {
	208	.type = OMAP_MBOX_TYPE2,
	209	.startup = omap2_mbox_startup,
	210	.shutdown = omap2_mbox_shutdown,
	211	.fifo_read = omap2_mbox_fifo_read,
	212	.fifo_write = omap2_mbox_fifo_write,
	213	.fifo_empty = omap2_mbox_fifo_empty,
	214	.fifo_full = omap2_mbox_fifo_full,
	215	.enable_irq = omap2_mbox_enable_irq,
	216	.disable_irq = omap2_mbox_disable_irq,
	217	.ack_irq = omap2_mbox_ack_irq,
	218	.is_irq = omap2_mbox_is_irq,
c75ee752 HD	219	.save_ctx = omap2_mbox_save_ctx,
c75ee752 HD	220	.restore_ctx = omap2_mbox_restore_ctx,
340a614a HD	221	};
340a614a HD	222
351a102d	223	static int omap2_mbox_probe(struct platform_device *pdev)
340a614a	224	{
898ee756	225	struct resource *mem;
6c20a683	226	int ret;
b8a7cf8e SA	227	struct omap_mbox *list, mbox, *mboxblk;
	228	struct omap_mbox2_priv priv, privblk;
	229	struct omap_mbox_pdata *pdata = pdev->dev.platform_data;
	230	struct omap_mbox_dev_info *info;
	231	int i;
898ee756	232
b8a7cf8e SA	233	if (!pdata \|\| !pdata->info_cnt \|\| !pdata->info) {
	234	pr_err("%s: platform not supported\n", __func__);
	235	return -ENODEV;
340a614a	236	}
ff0fba0b	237
b8a7cf8e SA	238	/* allocate one extra for marking end of list */
	239	list = kzalloc((pdata->info_cnt + 1) * sizeof(*list), GFP_KERNEL);
	240	if (!list)
	241	return -ENOMEM;
340a614a	242
b8a7cf8e SA	243	mboxblk = mbox = kzalloc(pdata->info_cnt * sizeof(*mbox), GFP_KERNEL);
	244	if (!mboxblk) {
	245	ret = -ENOMEM;
	246	goto free_list;
898ee756	247	}
5f00ec64	248
b8a7cf8e SA	249	privblk = priv = kzalloc(pdata->info_cnt * sizeof(*priv), GFP_KERNEL);
	250	if (!privblk) {
	251	ret = -ENOMEM;
	252	goto free_mboxblk;
340a614a	253	}
b8a7cf8e SA	254
	255	info = pdata->info;
	256	for (i = 0; i < pdata->info_cnt; i++, info++, priv++) {
	257	priv->tx_fifo.msg = MAILBOX_MESSAGE(info->tx_id);
	258	priv->tx_fifo.fifo_stat = MAILBOX_FIFOSTATUS(info->tx_id);
	259	priv->rx_fifo.msg = MAILBOX_MESSAGE(info->rx_id);
	260	priv->rx_fifo.msg_stat = MAILBOX_MSGSTATUS(info->rx_id);
	261	priv->notfull_bit = MAILBOX_IRQ_NOTFULL(info->tx_id);
	262	priv->newmsg_bit = MAILBOX_IRQ_NEWMSG(info->rx_id);
	263	if (pdata->intr_type) {
	264	priv->irqenable = OMAP4_MAILBOX_IRQENABLE(info->usr_id);
	265	priv->irqstatus = OMAP4_MAILBOX_IRQSTATUS(info->usr_id);
	266	priv->irqdisable =
	267	OMAP4_MAILBOX_IRQENABLE_CLR(info->usr_id);
	268	} else {
	269	priv->irqenable = MAILBOX_IRQENABLE(info->usr_id);
	270	priv->irqstatus = MAILBOX_IRQSTATUS(info->usr_id);
	271	priv->irqdisable = MAILBOX_IRQENABLE(info->usr_id);
	272	}
	273	priv->intr_type = pdata->intr_type;
	274
	275	mbox->priv = priv;
	276	mbox->name = info->name;
	277	mbox->ops = &omap2_mbox_ops;
	278	mbox->irq = platform_get_irq(pdev, info->irq_id);
	279	if (mbox->irq < 0) {
	280	ret = mbox->irq;
	281	goto free_privblk;
	282	}
	283	list[i] = mbox++;
5f00ec64	284	}
6c20a683	285
898ee756	286	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b8a7cf8e SA	287	if (!mem) {
	288	ret = -ENOENT;
	289	goto free_privblk;
	290	}
a41677c6	291
898ee756	292	mbox_base = ioremap(mem->start, resource_size(mem));
b8a7cf8e SA	293	if (!mbox_base) {
	294	ret = -ENOMEM;
	295	goto free_privblk;
	296	}
898ee756	297
9c80c8cd	298	ret = omap_mbox_register(&pdev->dev, list);
b8a7cf8e SA	299	if (ret)
	300	goto unmap_mbox;
	301	platform_set_drvdata(pdev, list);
340a614a	302
5d783731	303	return 0;
b8a7cf8e SA	304
	305	unmap_mbox:
	306	iounmap(mbox_base);
	307	free_privblk:
	308	kfree(privblk);
	309	free_mboxblk:
	310	kfree(mboxblk);
	311	free_list:
	312	kfree(list);
	313	return ret;
340a614a HD	314	}
340a614a HD	315
351a102d	316	static int omap2_mbox_remove(struct platform_device *pdev)
340a614a	317	{
b8a7cf8e SA	318	struct omap_mbox2_priv *privblk;
	319	struct omap_mbox **list = platform_get_drvdata(pdev);
	320	struct omap_mbox *mboxblk = list[0];
	321
	322	privblk = mboxblk->priv;
9c80c8cd	323	omap_mbox_unregister();
6c20a683	324	iounmap(mbox_base);
b8a7cf8e SA	325	kfree(privblk);
	326	kfree(mboxblk);
	327	kfree(list);
b8a7cf8e	328
340a614a HD	329	return 0;
	330	}
	331
	332	static struct platform_driver omap2_mbox_driver = {
c869c75c SA	333	.probe = omap2_mbox_probe,
	334	.remove = omap2_mbox_remove,
	335	.driver = {
d742709e	336	.name = "omap-mailbox",
340a614a HD	337	},
	338	};
	339
	340	static int __init omap2_mbox_init(void)
	341	{
	342	return platform_driver_register(&omap2_mbox_driver);
	343	}
	344
	345	static void __exit omap2_mbox_exit(void)
	346	{
	347	platform_driver_unregister(&omap2_mbox_driver);
	348	}
	349
134d12fa	350	module_init(omap2_mbox_init);
340a614a HD	351	module_exit(omap2_mbox_exit);
340a614a HD	352
733ecc5c	353	MODULE_LICENSE("GPL v2");
5f00ec64	354	MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
f375325a OBC	355	MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>");
f375325a OBC	356	MODULE_AUTHOR("Paul Mundt");
d742709e	357	MODULE_ALIAS("platform:omap2-mailbox");