[mirror_ubuntu-hirsute-kernel.git] / drivers / mailbox / rockchip-mailbox.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
 */

#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#define MAILBOX_A2B_INTEN		0x00
#define MAILBOX_A2B_STATUS		0x04
#define MAILBOX_A2B_CMD(x)		(0x08 + (x) * 8)
#define MAILBOX_A2B_DAT(x)		(0x0c + (x) * 8)

#define MAILBOX_B2A_INTEN		0x28
#define MAILBOX_B2A_STATUS		0x2C
#define MAILBOX_B2A_CMD(x)		(0x30 + (x) * 8)
#define MAILBOX_B2A_DAT(x)		(0x34 + (x) * 8)

struct rockchip_mbox_msg {
	u32 cmd;
	int rx_size;
};

struct rockchip_mbox_data {
	int num_chans;
};

struct rockchip_mbox_chan {
	int idx;
	int irq;
	struct rockchip_mbox_msg *msg;
	struct rockchip_mbox *mb;
};

struct rockchip_mbox {
	struct mbox_controller mbox;
	struct clk *pclk;
	void __iomem *mbox_base;

	/* The maximum size of buf for each channel */
	u32 buf_size;

	struct rockchip_mbox_chan *chans;
};

static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
{
	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
	struct rockchip_mbox_msg *msg = data;
	struct rockchip_mbox_chan *chans = mb->chans;

	if (!msg)
		return -EINVAL;

	if (msg->rx_size > mb->buf_size) {
		dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
			mb->buf_size);
		return -EINVAL;
	}

	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
		chans->idx, msg->cmd);

	mb->chans[chans->idx].msg = msg;

	writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
	writel_relaxed(msg->rx_size, mb->mbox_base +
		       MAILBOX_A2B_DAT(chans->idx));

	return 0;
}

static int rockchip_mbox_startup(struct mbox_chan *chan)
{
	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);

	/* Enable all B2A interrupts */
	writel_relaxed((1 << mb->mbox.num_chans) - 1,
		       mb->mbox_base + MAILBOX_B2A_INTEN);

	return 0;
}

static void rockchip_mbox_shutdown(struct mbox_chan *chan)
{
	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
	struct rockchip_mbox_chan *chans = mb->chans;

	/* Disable all B2A interrupts */
	writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);

	mb->chans[chans->idx].msg = NULL;
}

static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
	.send_data	= rockchip_mbox_send_data,
	.startup	= rockchip_mbox_startup,
	.shutdown	= rockchip_mbox_shutdown,
};

static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
{
	int idx;
	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;
	u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);

	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
		if ((status & (1 << idx)) && (irq == mb->chans[idx].irq)) {
			/* Clear mbox interrupt */
			writel_relaxed(1 << idx,
				       mb->mbox_base + MAILBOX_B2A_STATUS);
			return IRQ_WAKE_THREAD;
		}
	}

	return IRQ_NONE;
}

static irqreturn_t rockchip_mbox_isr(int irq, void *dev_id)
{
	int idx;
	struct rockchip_mbox_msg *msg = NULL;
	struct rockchip_mbox *mb = (struct rockchip_mbox *)dev_id;

	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
		if (irq != mb->chans[idx].irq)
			continue;

		msg = mb->chans[idx].msg;
		if (!msg) {
			dev_err(mb->mbox.dev,
				"Chan[%d]: B2A message is NULL\n", idx);
			break; /* spurious */
		}

		mbox_chan_received_data(&mb->mbox.chans[idx], msg);
		mb->chans[idx].msg = NULL;

		dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
			idx, msg->cmd);

		break;
	}

	return IRQ_HANDLED;
}

static const struct rockchip_mbox_data rk3368_drv_data = {
	.num_chans = 4,
};

static const struct of_device_id rockchip_mbox_of_match[] = {
	{ .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
	{ },
};
MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match);

static int rockchip_mbox_probe(struct platform_device *pdev)
{
	struct rockchip_mbox *mb;
	const struct of_device_id *match;
	const struct rockchip_mbox_data *drv_data;
	struct resource *res;
	int ret, irq, i;

	if (!pdev->dev.of_node)
		return -ENODEV;

	match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
	drv_data = (const struct rockchip_mbox_data *)match->data;

	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
	if (!mb)
		return -ENOMEM;

	mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
				 sizeof(*mb->chans), GFP_KERNEL);
	if (!mb->chans)
		return -ENOMEM;

	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
				      sizeof(*mb->mbox.chans), GFP_KERNEL);
	if (!mb->mbox.chans)
		return -ENOMEM;

	platform_set_drvdata(pdev, mb);

	mb->mbox.dev = &pdev->dev;
	mb->mbox.num_chans = drv_data->num_chans;
	mb->mbox.ops = &rockchip_mbox_chan_ops;
	mb->mbox.txdone_irq = true;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mb->mbox_base))
		return PTR_ERR(mb->mbox_base);

	/* Each channel has two buffers for A2B and B2A */
	mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2);

	mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
	if (IS_ERR(mb->pclk)) {
		ret = PTR_ERR(mb->pclk);
		dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
			ret);
		return ret;
	}

	ret = clk_prepare_enable(mb->pclk);
	if (ret) {
		dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
		return ret;
	}

	for (i = 0; i < mb->mbox.num_chans; i++) {
		irq = platform_get_irq(pdev, i);
		if (irq < 0)
			return irq;

		ret = devm_request_threaded_irq(&pdev->dev, irq,
						rockchip_mbox_irq,
						rockchip_mbox_isr, IRQF_ONESHOT,
						dev_name(&pdev->dev), mb);
		if (ret < 0)
			return ret;

		mb->chans[i].idx = i;
		mb->chans[i].irq = irq;
		mb->chans[i].mb = mb;
		mb->chans[i].msg = NULL;
	}

	ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
	if (ret < 0)
		dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);

	return ret;
}

static struct platform_driver rockchip_mbox_driver = {
	.probe	= rockchip_mbox_probe,
	.driver = {
		.name = "rockchip-mailbox",
		.of_match_table = of_match_ptr(rockchip_mbox_of_match),
	},
};

module_platform_driver(rockchip_mbox_driver);

MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");
Commit	Line	Data
2025cf9e	1	// SPDX-License-Identifier: GPL-2.0-only
f70ed3b5 CW	2	/*
f70ed3b5 CW	3	* Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
f70ed3b5 CW	4	*/
	5
	6	#include <linux/clk.h>
	7	#include <linux/interrupt.h>
	8	#include <linux/io.h>
	9	#include <linux/kernel.h>
	10	#include <linux/mailbox_controller.h>
	11	#include <linux/module.h>
	12	#include <linux/of_device.h>
	13	#include <linux/platform_device.h>
	14
	15	#define MAILBOX_A2B_INTEN 0x00
	16	#define MAILBOX_A2B_STATUS 0x04
	17	#define MAILBOX_A2B_CMD(x) (0x08 + (x) * 8)
	18	#define MAILBOX_A2B_DAT(x) (0x0c + (x) * 8)
	19
	20	#define MAILBOX_B2A_INTEN 0x28
	21	#define MAILBOX_B2A_STATUS 0x2C
	22	#define MAILBOX_B2A_CMD(x) (0x30 + (x) * 8)
	23	#define MAILBOX_B2A_DAT(x) (0x34 + (x) * 8)
	24
	25	struct rockchip_mbox_msg {
	26	u32 cmd;
	27	int rx_size;
	28	};
	29
	30	struct rockchip_mbox_data {
	31	int num_chans;
	32	};
	33
	34	struct rockchip_mbox_chan {
	35	int idx;
	36	int irq;
	37	struct rockchip_mbox_msg *msg;
	38	struct rockchip_mbox *mb;
	39	};
	40
	41	struct rockchip_mbox {
	42	struct mbox_controller mbox;
	43	struct clk *pclk;
	44	void __iomem *mbox_base;
	45
	46	/* The maximum size of buf for each channel */
	47	u32 buf_size;
	48
	49	struct rockchip_mbox_chan *chans;
	50	};
	51
	52	static int rockchip_mbox_send_data(struct mbox_chan chan, void data)
	53	{
	54	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
	55	struct rockchip_mbox_msg *msg = data;
	56	struct rockchip_mbox_chan *chans = mb->chans;
	57
	58	if (!msg)
	59	return -EINVAL;
	60
	61	if (msg->rx_size > mb->buf_size) {
	62	dev_err(mb->mbox.dev, "Transmit size over buf size(%d)\n",
	63	mb->buf_size);
	64	return -EINVAL;
	65	}
	66
	67	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
68	chans->idx, msg->cmd);
69
70	mb->chans[chans->idx].msg = msg;
71
72	writel_relaxed(msg->cmd, mb->mbox_base + MAILBOX_A2B_CMD(chans->idx));
73	writel_relaxed(msg->rx_size, mb->mbox_base +
74	MAILBOX_A2B_DAT(chans->idx));
75
76	return 0;
77	}
78
79	static int rockchip_mbox_startup(struct mbox_chan *chan)
80	{
81	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
82
83	/* Enable all B2A interrupts */
84	writel_relaxed((1 << mb->mbox.num_chans) - 1,
85	mb->mbox_base + MAILBOX_B2A_INTEN);
86
87	return 0;
88	}
89
90	static void rockchip_mbox_shutdown(struct mbox_chan *chan)
91	{
92	struct rockchip_mbox *mb = dev_get_drvdata(chan->mbox->dev);
93	struct rockchip_mbox_chan *chans = mb->chans;
94
95	/* Disable all B2A interrupts */
96	writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);
97
98	mb->chans[chans->idx].msg = NULL;
99	}
100
101	static const struct mbox_chan_ops rockchip_mbox_chan_ops = {
102	.send_data = rockchip_mbox_send_data,
103	.startup = rockchip_mbox_startup,
104	.shutdown = rockchip_mbox_shutdown,
105	};
106
107	static irqreturn_t rockchip_mbox_irq(int irq, void *dev_id)
108	{
109	int idx;
110	struct rockchip_mbox mb = (struct rockchip_mbox )dev_id;
111	u32 status = readl_relaxed(mb->mbox_base + MAILBOX_B2A_STATUS);
112
113	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
114	if ((status & (1 << idx)) && (irq == mb->chans[idx].irq)) {
115	/* Clear mbox interrupt */
116	writel_relaxed(1 << idx,
117	mb->mbox_base + MAILBOX_B2A_STATUS);
118	return IRQ_WAKE_THREAD;
119	}
120	}
121
122	return IRQ_NONE;
123	}
124
125	static irqreturn_t rockchip_mbox_isr(int irq, void *dev_id)
126	{
127	int idx;
128	struct rockchip_mbox_msg *msg = NULL;
129	struct rockchip_mbox mb = (struct rockchip_mbox )dev_id;
130
131	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
132	if (irq != mb->chans[idx].irq)
133	continue;
134
135	msg = mb->chans[idx].msg;
136	if (!msg) {
137	dev_err(mb->mbox.dev,
138	"Chan[%d]: B2A message is NULL\n", idx);
139	break; /* spurious */
140	}
141
142	mbox_chan_received_data(&mb->mbox.chans[idx], msg);
143	mb->chans[idx].msg = NULL;
144
145	dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
146	idx, msg->cmd);
147
148	break;
149	}
150
151	return IRQ_HANDLED;
152	}
153
154	static const struct rockchip_mbox_data rk3368_drv_data = {
155	.num_chans = 4,
156	};
157
158	static const struct of_device_id rockchip_mbox_of_match[] = {
159	{ .compatible = "rockchip,rk3368-mailbox", .data = &rk3368_drv_data},
160	{ },
161	};
162	MODULE_DEVICE_TABLE(of, rockchp_mbox_of_match);
163
164	static int rockchip_mbox_probe(struct platform_device *pdev)
165	{
166	struct rockchip_mbox *mb;
167	const struct of_device_id *match;
168	const struct rockchip_mbox_data *drv_data;
169	struct resource *res;
170	int ret, irq, i;
171
172	if (!pdev->dev.of_node)
173	return -ENODEV;
174
175	match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
176	drv_data = (const struct rockchip_mbox_data *)match->data;
177
178	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
179	if (!mb)
180	return -ENOMEM;
181
182	mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
183	sizeof(*mb->chans), GFP_KERNEL);
184	if (!mb->chans)
185	return -ENOMEM;
186
187	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
188	sizeof(*mb->mbox.chans), GFP_KERNEL);
189	if (!mb->mbox.chans)
190	return -ENOMEM;
191
192	platform_set_drvdata(pdev, mb);
193
194	mb->mbox.dev = &pdev->dev;
195	mb->mbox.num_chans = drv_data->num_chans;
196	mb->mbox.ops = &rockchip_mbox_chan_ops;
197	mb->mbox.txdone_irq = true;
198
199	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
200	if (!res)
201	return -ENODEV;
202
203	mb->mbox_base = devm_ioremap_resource(&pdev->dev, res);
204	if (IS_ERR(mb->mbox_base))
205	return PTR_ERR(mb->mbox_base);
206
207	/* Each channel has two buffers for A2B and B2A */
c5a9d1f3	208	mb->buf_size = (size_t)resource_size(res) / (drv_data->num_chans * 2);
f70ed3b5 CW	209
	210	mb->pclk = devm_clk_get(&pdev->dev, "pclk_mailbox");
	211	if (IS_ERR(mb->pclk)) {
	212	ret = PTR_ERR(mb->pclk);
	213	dev_err(&pdev->dev, "failed to get pclk_mailbox clock: %d\n",
	214	ret);
	215	return ret;
	216	}
	217
	218	ret = clk_prepare_enable(mb->pclk);
	219	if (ret) {
	220	dev_err(&pdev->dev, "failed to enable pclk: %d\n", ret);
	221	return ret;
	222	}
	223
	224	for (i = 0; i < mb->mbox.num_chans; i++) {
	225	irq = platform_get_irq(pdev, i);
	226	if (irq < 0)
	227	return irq;
	228
	229	ret = devm_request_threaded_irq(&pdev->dev, irq,
	230	rockchip_mbox_irq,
	231	rockchip_mbox_isr, IRQF_ONESHOT,
	232	dev_name(&pdev->dev), mb);
	233	if (ret < 0)
	234	return ret;
	235
	236	mb->chans[i].idx = i;
	237	mb->chans[i].irq = irq;
	238	mb->chans[i].mb = mb;
	239	mb->chans[i].msg = NULL;
	240	}
	241
08f2f88a	242	ret = devm_mbox_controller_register(&pdev->dev, &mb->mbox);
f70ed3b5 CW	243	if (ret < 0)
	244	dev_err(&pdev->dev, "Failed to register mailbox: %d\n", ret);
	245
	246	return ret;
	247	}
	248
f70ed3b5 CW	249	static struct platform_driver rockchip_mbox_driver = {
f70ed3b5 CW	250	.probe = rockchip_mbox_probe,
f70ed3b5 CW	251	.driver = {
	252	.name = "rockchip-mailbox",
	253	.of_match_table = of_match_ptr(rockchip_mbox_of_match),
	254	},
	255	};
	256
	257	module_platform_driver(rockchip_mbox_driver);
	258
	259	MODULE_LICENSE("GPL v2");
	260	MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
	261	MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
	262	MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");