[mirror_ubuntu-hirsute-kernel.git] / drivers / mailbox / stm32-ipcc.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
 * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 *          Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
 */

#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/mailbox_controller.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_wakeirq.h>

#define IPCC_XCR		0x000
#define XCR_RXOIE		BIT(0)
#define XCR_TXOIE		BIT(16)

#define IPCC_XMR		0x004
#define IPCC_XSCR		0x008
#define IPCC_XTOYSR		0x00c

#define IPCC_PROC_OFFST		0x010

#define IPCC_HWCFGR		0x3f0
#define IPCFGR_CHAN_MASK	GENMASK(7, 0)

#define IPCC_VER		0x3f4
#define VER_MINREV_MASK		GENMASK(3, 0)
#define VER_MAJREV_MASK		GENMASK(7, 4)

#define RX_BIT_MASK		GENMASK(15, 0)
#define RX_BIT_CHAN(chan)	BIT(chan)
#define TX_BIT_SHIFT		16
#define TX_BIT_MASK		GENMASK(31, 16)
#define TX_BIT_CHAN(chan)	BIT(TX_BIT_SHIFT + (chan))

#define STM32_MAX_PROCS		2

enum {
	IPCC_IRQ_RX,
	IPCC_IRQ_TX,
	IPCC_IRQ_NUM,
};

struct stm32_ipcc {
	struct mbox_controller controller;
	void __iomem *reg_base;
	void __iomem *reg_proc;
	struct clk *clk;
	int irqs[IPCC_IRQ_NUM];
	int wkp;
	u32 proc_id;
	u32 n_chans;
	u32 xcr;
	u32 xmr;
};

static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
{
	writel_relaxed(readl_relaxed(reg) | mask, reg);
}

static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
{
	writel_relaxed(readl_relaxed(reg) & ~mask, reg);
}

static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
{
	struct stm32_ipcc *ipcc = data;
	struct device *dev = ipcc->controller.dev;
	u32 status, mr, tosr, chan;
	irqreturn_t ret = IRQ_NONE;
	int proc_offset;

	/* read 'channel occupied' status from other proc */
	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
	tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);

	/* search for unmasked 'channel occupied' */
	status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);

	for (chan = 0; chan < ipcc->n_chans; chan++) {
		if (!(status & (1 << chan)))
			continue;

		dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);

		mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);

		stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
				    RX_BIT_CHAN(chan));

		ret = IRQ_HANDLED;
	}

	return ret;
}

static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
{
	struct stm32_ipcc *ipcc = data;
	struct device *dev = ipcc->controller.dev;
	u32 status, mr, tosr, chan;
	irqreturn_t ret = IRQ_NONE;

	tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);

	/* search for unmasked 'channel free' */
	status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);

	for (chan = 0; chan < ipcc->n_chans ; chan++) {
		if (!(status & (1 << chan)))
			continue;

		dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);

		/* mask 'tx channel free' interrupt */
		stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
				    TX_BIT_CHAN(chan));

		mbox_chan_txdone(&ipcc->controller.chans[chan], 0);

		ret = IRQ_HANDLED;
	}

	return ret;
}

static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
{
	unsigned int chan = (unsigned int)link->con_priv;
	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
					       controller);

	dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);

	/* set channel n occupied */
	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));

	/* unmask 'tx channel free' interrupt */
	stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));

	return 0;
}

static int stm32_ipcc_startup(struct mbox_chan *link)
{
	unsigned int chan = (unsigned int)link->con_priv;
	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
					       controller);
	int ret;

	ret = clk_prepare_enable(ipcc->clk);
	if (ret) {
		dev_err(ipcc->controller.dev, "can not enable the clock\n");
		return ret;
	}

	/* unmask 'rx channel occupied' interrupt */
	stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));

	return 0;
}

static void stm32_ipcc_shutdown(struct mbox_chan *link)
{
	unsigned int chan = (unsigned int)link->con_priv;
	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
					       controller);

	/* mask rx/tx interrupt */
	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
			    RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));

	clk_disable_unprepare(ipcc->clk);
}

static const struct mbox_chan_ops stm32_ipcc_ops = {
	.send_data	= stm32_ipcc_send_data,
	.startup	= stm32_ipcc_startup,
	.shutdown	= stm32_ipcc_shutdown,
};

static int stm32_ipcc_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct stm32_ipcc *ipcc;
	struct resource *res;
	unsigned int i;
	int ret;
	u32 ip_ver;
	static const char * const irq_name[] = {"rx", "tx"};
	irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};

	if (!np) {
		dev_err(dev, "No DT found\n");
		return -ENODEV;
	}

	ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
	if (!ipcc)
		return -ENOMEM;

	/* proc_id */
	if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
		dev_err(dev, "Missing st,proc-id\n");
		return -ENODEV;
	}

	if (ipcc->proc_id >= STM32_MAX_PROCS) {
		dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
		return -EINVAL;
	}

	/* regs */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	ipcc->reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(ipcc->reg_base))
		return PTR_ERR(ipcc->reg_base);

	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;

	/* clock */
	ipcc->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(ipcc->clk))
		return PTR_ERR(ipcc->clk);

	ret = clk_prepare_enable(ipcc->clk);
	if (ret) {
		dev_err(dev, "can not enable the clock\n");
		return ret;
	}

	/* irq */
	for (i = 0; i < IPCC_IRQ_NUM; i++) {
		ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
		if (ipcc->irqs[i] < 0) {
			if (ipcc->irqs[i] != -EPROBE_DEFER)
				dev_err(dev, "no IRQ specified %s\n",
					irq_name[i]);
			ret = ipcc->irqs[i];
			goto err_clk;
		}

		ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
						irq_thread[i], IRQF_ONESHOT,
						dev_name(dev), ipcc);
		if (ret) {
			dev_err(dev, "failed to request irq %d (%d)\n", i, ret);
			goto err_clk;
		}
	}

	/* mask and enable rx/tx irq */
	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
			    RX_BIT_MASK | TX_BIT_MASK);
	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);

	/* wakeup */
	if (of_property_read_bool(np, "wakeup-source")) {
		ipcc->wkp = platform_get_irq_byname(pdev, "wakeup");
		if (ipcc->wkp < 0) {
			if (ipcc->wkp != -EPROBE_DEFER)
				dev_err(dev, "could not get wakeup IRQ\n");
			ret = ipcc->wkp;
			goto err_clk;
		}

		device_set_wakeup_capable(dev, true);
		ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
		if (ret) {
			dev_err(dev, "Failed to set wake up irq\n");
			goto err_init_wkp;
		}
	}

	/* mailbox controller */
	ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
	ipcc->n_chans &= IPCFGR_CHAN_MASK;

	ipcc->controller.dev = dev;
	ipcc->controller.txdone_irq = true;
	ipcc->controller.ops = &stm32_ipcc_ops;
	ipcc->controller.num_chans = ipcc->n_chans;
	ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
					      sizeof(*ipcc->controller.chans),
					      GFP_KERNEL);
	if (!ipcc->controller.chans) {
		ret = -ENOMEM;
		goto err_irq_wkp;
	}

	for (i = 0; i < ipcc->controller.num_chans; i++)
		ipcc->controller.chans[i].con_priv = (void *)i;

	ret = devm_mbox_controller_register(dev, &ipcc->controller);
	if (ret)
		goto err_irq_wkp;

	platform_set_drvdata(pdev, ipcc);

	ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);

	dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
		 FIELD_GET(VER_MAJREV_MASK, ip_ver),
		 FIELD_GET(VER_MINREV_MASK, ip_ver),
		 ipcc->controller.num_chans, ipcc->proc_id);

	clk_disable_unprepare(ipcc->clk);
	return 0;

err_irq_wkp:
	if (ipcc->wkp)
		dev_pm_clear_wake_irq(dev);
err_init_wkp:
	device_init_wakeup(dev, false);
err_clk:
	clk_disable_unprepare(ipcc->clk);
	return ret;
}

static int stm32_ipcc_remove(struct platform_device *pdev)
{
	struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);

	if (ipcc->wkp)
		dev_pm_clear_wake_irq(&pdev->dev);

	device_init_wakeup(&pdev->dev, false);

	return 0;
}

#ifdef CONFIG_PM_SLEEP
static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable)
{
	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
	unsigned int i;

	if (device_may_wakeup(dev))
		for (i = 0; i < IPCC_IRQ_NUM; i++)
			irq_set_irq_wake(ipcc->irqs[i], enable);
}

static int stm32_ipcc_suspend(struct device *dev)
{
	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);

	ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
	ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);

	stm32_ipcc_set_irq_wake(dev, true);

	return 0;
}

static int stm32_ipcc_resume(struct device *dev)
{
	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);

	stm32_ipcc_set_irq_wake(dev, false);

	writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
	writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
			 stm32_ipcc_suspend, stm32_ipcc_resume);

static const struct of_device_id stm32_ipcc_of_match[] = {
	{ .compatible = "st,stm32mp1-ipcc" },
	{},
};
MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);

static struct platform_driver stm32_ipcc_driver = {
	.driver = {
		.name = "stm32-ipcc",
		.pm = &stm32_ipcc_pm_ops,
		.of_match_table = stm32_ipcc_of_match,
	},
	.probe		= stm32_ipcc_probe,
	.remove		= stm32_ipcc_remove,
};

module_platform_driver(stm32_ipcc_driver);

MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
MODULE_DESCRIPTION("STM32 IPCC driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
ffbded7d FD	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
	4	* Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	5	* Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
	6	*/
	7
	8	#include <linux/bitfield.h>
	9	#include <linux/clk.h>
	10	#include <linux/interrupt.h>
68a1c848	11	#include <linux/io.h>
ffbded7d FD	12	#include <linux/mailbox_controller.h>
ffbded7d FD	13	#include <linux/module.h>
ffbded7d FD	14	#include <linux/platform_device.h>
	15	#include <linux/pm_wakeirq.h>
	16
	17	#define IPCC_XCR 0x000
	18	#define XCR_RXOIE BIT(0)
	19	#define XCR_TXOIE BIT(16)
	20
	21	#define IPCC_XMR 0x004
	22	#define IPCC_XSCR 0x008
	23	#define IPCC_XTOYSR 0x00c
	24
	25	#define IPCC_PROC_OFFST 0x010
	26
	27	#define IPCC_HWCFGR 0x3f0
	28	#define IPCFGR_CHAN_MASK GENMASK(7, 0)
	29
	30	#define IPCC_VER 0x3f4
	31	#define VER_MINREV_MASK GENMASK(3, 0)
	32	#define VER_MAJREV_MASK GENMASK(7, 4)
	33
	34	#define RX_BIT_MASK GENMASK(15, 0)
	35	#define RX_BIT_CHAN(chan) BIT(chan)
	36	#define TX_BIT_SHIFT 16
	37	#define TX_BIT_MASK GENMASK(31, 16)
	38	#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
	39
	40	#define STM32_MAX_PROCS 2
	41
	42	enum {
	43	IPCC_IRQ_RX,
	44	IPCC_IRQ_TX,
	45	IPCC_IRQ_NUM,
	46	};
	47
	48	struct stm32_ipcc {
	49	struct mbox_controller controller;
	50	void __iomem *reg_base;
	51	void __iomem *reg_proc;
	52	struct clk *clk;
	53	int irqs[IPCC_IRQ_NUM];
	54	int wkp;
	55	u32 proc_id;
	56	u32 n_chans;
	57	u32 xcr;
	58	u32 xmr;
	59	};
	60
	61	static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
	62	{
	63	writel_relaxed(readl_relaxed(reg) \| mask, reg);
	64	}
	65
	66	static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
	67	{
	68	writel_relaxed(readl_relaxed(reg) & ~mask, reg);
	69	}
	70
	71	static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
	72	{
	73	struct stm32_ipcc *ipcc = data;
	74	struct device *dev = ipcc->controller.dev;
	75	u32 status, mr, tosr, chan;
	76	irqreturn_t ret = IRQ_NONE;
	77	int proc_offset;
78
79	/* read 'channel occupied' status from other proc */
80	proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
81	tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
82	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
83
84	/* search for unmasked 'channel occupied' */
85	status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
86
87	for (chan = 0; chan < ipcc->n_chans; chan++) {
88	if (!(status & (1 << chan)))
89	continue;
90
91	dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
92
93	mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
94
95	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
96	RX_BIT_CHAN(chan));
97
98	ret = IRQ_HANDLED;
99	}
100
101	return ret;
102	}
103
104	static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
105	{
106	struct stm32_ipcc *ipcc = data;
107	struct device *dev = ipcc->controller.dev;
108	u32 status, mr, tosr, chan;
109	irqreturn_t ret = IRQ_NONE;
110
111	tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
112	mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
113
114	/* search for unmasked 'channel free' */
115	status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
116
117	for (chan = 0; chan < ipcc->n_chans ; chan++) {
118	if (!(status & (1 << chan)))
119	continue;
120
121	dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
122
123	/* mask 'tx channel free' interrupt */
124	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
125	TX_BIT_CHAN(chan));
126
127	mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
128
129	ret = IRQ_HANDLED;
130	}
131
132	return ret;
133	}
134
135	static int stm32_ipcc_send_data(struct mbox_chan link, void data)
136	{
137	unsigned int chan = (unsigned int)link->con_priv;
138	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
139	controller);
140
141	dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
142
143	/* set channel n occupied */
144	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));
145
146	/* unmask 'tx channel free' interrupt */
147	stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));
148
149	return 0;
150	}
151
152	static int stm32_ipcc_startup(struct mbox_chan *link)
153	{
154	unsigned int chan = (unsigned int)link->con_priv;
155	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
156	controller);
157	int ret;
158
159	ret = clk_prepare_enable(ipcc->clk);
160	if (ret) {
161	dev_err(ipcc->controller.dev, "can not enable the clock\n");
162	return ret;
163	}
164
165	/* unmask 'rx channel occupied' interrupt */
166	stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));
167
168	return 0;
169	}
170
171	static void stm32_ipcc_shutdown(struct mbox_chan *link)
172	{
173	unsigned int chan = (unsigned int)link->con_priv;
174	struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
175	controller);
176
177	/* mask rx/tx interrupt */
178	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
179	RX_BIT_CHAN(chan) \| TX_BIT_CHAN(chan));
180
181	clk_disable_unprepare(ipcc->clk);
182	}
183
184	static const struct mbox_chan_ops stm32_ipcc_ops = {
185	.send_data = stm32_ipcc_send_data,
186	.startup = stm32_ipcc_startup,
187	.shutdown = stm32_ipcc_shutdown,
188	};
189
190	static int stm32_ipcc_probe(struct platform_device *pdev)
191	{
192	struct device *dev = &pdev->dev;
193	struct device_node *np = dev->of_node;
194	struct stm32_ipcc *ipcc;
195	struct resource *res;
196	unsigned int i;
197	int ret;
198	u32 ip_ver;
199	static const char * const irq_name[] = {"rx", "tx"};
200	irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};
201
202	if (!np) {
203	dev_err(dev, "No DT found\n");
204	return -ENODEV;
205	}
206
207	ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
208	if (!ipcc)
209	return -ENOMEM;
210
211	/* proc_id */
212	if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
213	dev_err(dev, "Missing st,proc-id\n");
214	return -ENODEV;
215	}
216
217	if (ipcc->proc_id >= STM32_MAX_PROCS) {
218	dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
219	return -EINVAL;
220	}
221
222	/* regs */
223	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224	ipcc->reg_base = devm_ioremap_resource(dev, res);
225	if (IS_ERR(ipcc->reg_base))
226	return PTR_ERR(ipcc->reg_base);
227
228	ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
229
230	/* clock */
231	ipcc->clk = devm_clk_get(dev, NULL);
232	if (IS_ERR(ipcc->clk))
233	return PTR_ERR(ipcc->clk);
234
235	ret = clk_prepare_enable(ipcc->clk);
236	if (ret) {
237	dev_err(dev, "can not enable the clock\n");
238	return ret;
239	}
240
241	/* irq */
242	for (i = 0; i < IPCC_IRQ_NUM; i++) {
68a1c848	243	ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
ffbded7d	244	if (ipcc->irqs[i] < 0) {
68a1c848 FD	245	if (ipcc->irqs[i] != -EPROBE_DEFER)
	246	dev_err(dev, "no IRQ specified %s\n",
	247	irq_name[i]);
ffbded7d FD	248	ret = ipcc->irqs[i];
	249	goto err_clk;
	250	}
	251
	252	ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
	253	irq_thread[i], IRQF_ONESHOT,
	254	dev_name(dev), ipcc);
	255	if (ret) {
	256	dev_err(dev, "failed to request irq %d (%d)\n", i, ret);
	257	goto err_clk;
	258	}
	259	}
	260
	261	/* mask and enable rx/tx irq */
	262	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
	263	RX_BIT_MASK \| TX_BIT_MASK);
	264	stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE \| XCR_TXOIE);
	265
	266	/* wakeup */
	267	if (of_property_read_bool(np, "wakeup-source")) {
68a1c848	268	ipcc->wkp = platform_get_irq_byname(pdev, "wakeup");
ffbded7d	269	if (ipcc->wkp < 0) {
68a1c848 FD	270	if (ipcc->wkp != -EPROBE_DEFER)
68a1c848 FD	271	dev_err(dev, "could not get wakeup IRQ\n");
ffbded7d FD	272	ret = ipcc->wkp;
	273	goto err_clk;
	274	}
	275
eac36c86	276	device_set_wakeup_capable(dev, true);
ffbded7d FD	277	ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
	278	if (ret) {
	279	dev_err(dev, "Failed to set wake up irq\n");
	280	goto err_init_wkp;
	281	}
ffbded7d FD	282	}
	283
	284	/* mailbox controller */
	285	ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
	286	ipcc->n_chans &= IPCFGR_CHAN_MASK;
	287
	288	ipcc->controller.dev = dev;
	289	ipcc->controller.txdone_irq = true;
	290	ipcc->controller.ops = &stm32_ipcc_ops;
	291	ipcc->controller.num_chans = ipcc->n_chans;
	292	ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
	293	sizeof(*ipcc->controller.chans),
	294	GFP_KERNEL);
	295	if (!ipcc->controller.chans) {
	296	ret = -ENOMEM;
	297	goto err_irq_wkp;
	298	}
	299
	300	for (i = 0; i < ipcc->controller.num_chans; i++)
	301	ipcc->controller.chans[i].con_priv = (void *)i;
	302
368d7767	303	ret = devm_mbox_controller_register(dev, &ipcc->controller);
ffbded7d FD	304	if (ret)
	305	goto err_irq_wkp;
	306
	307	platform_set_drvdata(pdev, ipcc);
	308
	309	ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
	310
	311	dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
	312	FIELD_GET(VER_MAJREV_MASK, ip_ver),
	313	FIELD_GET(VER_MINREV_MASK, ip_ver),
	314	ipcc->controller.num_chans, ipcc->proc_id);
	315
	316	clk_disable_unprepare(ipcc->clk);
	317	return 0;
	318
	319	err_irq_wkp:
	320	if (ipcc->wkp)
	321	dev_pm_clear_wake_irq(dev);
	322	err_init_wkp:
	323	device_init_wakeup(dev, false);
	324	err_clk:
	325	clk_disable_unprepare(ipcc->clk);
	326	return ret;
	327	}
	328
	329	static int stm32_ipcc_remove(struct platform_device *pdev)
	330	{
	331	struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);
	332
ffbded7d FD	333	if (ipcc->wkp)
	334	dev_pm_clear_wake_irq(&pdev->dev);
	335
	336	device_init_wakeup(&pdev->dev, false);
	337
	338	return 0;
	339	}
	340
	341	#ifdef CONFIG_PM_SLEEP
	342	static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable)
	343	{
	344	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
	345	unsigned int i;
	346
	347	if (device_may_wakeup(dev))
	348	for (i = 0; i < IPCC_IRQ_NUM; i++)
	349	irq_set_irq_wake(ipcc->irqs[i], enable);
	350	}
	351
	352	static int stm32_ipcc_suspend(struct device *dev)
	353	{
	354	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
	355
	356	ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
	357	ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
	358
	359	stm32_ipcc_set_irq_wake(dev, true);
	360
	361	return 0;
	362	}
	363
	364	static int stm32_ipcc_resume(struct device *dev)
	365	{
	366	struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
	367
	368	stm32_ipcc_set_irq_wake(dev, false);
	369
	370	writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
	371	writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
	372
	373	return 0;
	374	}
	375	#endif
	376
	377	static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
	378	stm32_ipcc_suspend, stm32_ipcc_resume);
	379
	380	static const struct of_device_id stm32_ipcc_of_match[] = {
	381	{ .compatible = "st,stm32mp1-ipcc" },
	382	{},
	383	};
	384	MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);
	385
	386	static struct platform_driver stm32_ipcc_driver = {
	387	.driver = {
	388	.name = "stm32-ipcc",
	389	.pm = &stm32_ipcc_pm_ops,
	390	.of_match_table = stm32_ipcc_of_match,
	391	},
	392	.probe = stm32_ipcc_probe,
	393	.remove = stm32_ipcc_remove,
	394	};
	395
	396	module_platform_driver(stm32_ipcc_driver);
397
398	MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
399	MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
400	MODULE_DESCRIPTION("STM32 IPCC driver");
401	MODULE_LICENSE("GPL v2");