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ffbded7d FD |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) STMicroelectronics 2018 - All Rights Reserved | |
4 | * Authors: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. | |
5 | * Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics. | |
6 | */ | |
7 | ||
8 | #include <linux/bitfield.h> | |
9 | #include <linux/clk.h> | |
10 | #include <linux/interrupt.h> | |
68a1c848 | 11 | #include <linux/io.h> |
ffbded7d FD |
12 | #include <linux/mailbox_controller.h> |
13 | #include <linux/module.h> | |
ffbded7d FD |
14 | #include <linux/platform_device.h> |
15 | #include <linux/pm_wakeirq.h> | |
16 | ||
17 | #define IPCC_XCR 0x000 | |
18 | #define XCR_RXOIE BIT(0) | |
19 | #define XCR_TXOIE BIT(16) | |
20 | ||
21 | #define IPCC_XMR 0x004 | |
22 | #define IPCC_XSCR 0x008 | |
23 | #define IPCC_XTOYSR 0x00c | |
24 | ||
25 | #define IPCC_PROC_OFFST 0x010 | |
26 | ||
27 | #define IPCC_HWCFGR 0x3f0 | |
28 | #define IPCFGR_CHAN_MASK GENMASK(7, 0) | |
29 | ||
30 | #define IPCC_VER 0x3f4 | |
31 | #define VER_MINREV_MASK GENMASK(3, 0) | |
32 | #define VER_MAJREV_MASK GENMASK(7, 4) | |
33 | ||
34 | #define RX_BIT_MASK GENMASK(15, 0) | |
35 | #define RX_BIT_CHAN(chan) BIT(chan) | |
36 | #define TX_BIT_SHIFT 16 | |
37 | #define TX_BIT_MASK GENMASK(31, 16) | |
38 | #define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan)) | |
39 | ||
40 | #define STM32_MAX_PROCS 2 | |
41 | ||
42 | enum { | |
43 | IPCC_IRQ_RX, | |
44 | IPCC_IRQ_TX, | |
45 | IPCC_IRQ_NUM, | |
46 | }; | |
47 | ||
48 | struct stm32_ipcc { | |
49 | struct mbox_controller controller; | |
50 | void __iomem *reg_base; | |
51 | void __iomem *reg_proc; | |
52 | struct clk *clk; | |
dba9a3df | 53 | spinlock_t lock; /* protect access to IPCC registers */ |
ffbded7d FD |
54 | int irqs[IPCC_IRQ_NUM]; |
55 | int wkp; | |
56 | u32 proc_id; | |
57 | u32 n_chans; | |
58 | u32 xcr; | |
59 | u32 xmr; | |
60 | }; | |
61 | ||
dba9a3df AP |
62 | static inline void stm32_ipcc_set_bits(spinlock_t *lock, void __iomem *reg, |
63 | u32 mask) | |
ffbded7d | 64 | { |
dba9a3df AP |
65 | unsigned long flags; |
66 | ||
67 | spin_lock_irqsave(lock, flags); | |
ffbded7d | 68 | writel_relaxed(readl_relaxed(reg) | mask, reg); |
dba9a3df | 69 | spin_unlock_irqrestore(lock, flags); |
ffbded7d FD |
70 | } |
71 | ||
dba9a3df AP |
72 | static inline void stm32_ipcc_clr_bits(spinlock_t *lock, void __iomem *reg, |
73 | u32 mask) | |
ffbded7d | 74 | { |
dba9a3df AP |
75 | unsigned long flags; |
76 | ||
77 | spin_lock_irqsave(lock, flags); | |
ffbded7d | 78 | writel_relaxed(readl_relaxed(reg) & ~mask, reg); |
dba9a3df | 79 | spin_unlock_irqrestore(lock, flags); |
ffbded7d FD |
80 | } |
81 | ||
82 | static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data) | |
83 | { | |
84 | struct stm32_ipcc *ipcc = data; | |
85 | struct device *dev = ipcc->controller.dev; | |
86 | u32 status, mr, tosr, chan; | |
87 | irqreturn_t ret = IRQ_NONE; | |
88 | int proc_offset; | |
89 | ||
90 | /* read 'channel occupied' status from other proc */ | |
91 | proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST; | |
92 | tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR); | |
93 | mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); | |
94 | ||
95 | /* search for unmasked 'channel occupied' */ | |
96 | status = tosr & FIELD_GET(RX_BIT_MASK, ~mr); | |
97 | ||
98 | for (chan = 0; chan < ipcc->n_chans; chan++) { | |
99 | if (!(status & (1 << chan))) | |
100 | continue; | |
101 | ||
102 | dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan); | |
103 | ||
104 | mbox_chan_received_data(&ipcc->controller.chans[chan], NULL); | |
105 | ||
dba9a3df | 106 | stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, |
ffbded7d FD |
107 | RX_BIT_CHAN(chan)); |
108 | ||
109 | ret = IRQ_HANDLED; | |
110 | } | |
111 | ||
112 | return ret; | |
113 | } | |
114 | ||
115 | static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data) | |
116 | { | |
117 | struct stm32_ipcc *ipcc = data; | |
118 | struct device *dev = ipcc->controller.dev; | |
119 | u32 status, mr, tosr, chan; | |
120 | irqreturn_t ret = IRQ_NONE; | |
121 | ||
122 | tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR); | |
123 | mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); | |
124 | ||
125 | /* search for unmasked 'channel free' */ | |
126 | status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr); | |
127 | ||
128 | for (chan = 0; chan < ipcc->n_chans ; chan++) { | |
129 | if (!(status & (1 << chan))) | |
130 | continue; | |
131 | ||
132 | dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan); | |
133 | ||
134 | /* mask 'tx channel free' interrupt */ | |
dba9a3df | 135 | stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
ffbded7d FD |
136 | TX_BIT_CHAN(chan)); |
137 | ||
138 | mbox_chan_txdone(&ipcc->controller.chans[chan], 0); | |
139 | ||
140 | ret = IRQ_HANDLED; | |
141 | } | |
142 | ||
143 | return ret; | |
144 | } | |
145 | ||
146 | static int stm32_ipcc_send_data(struct mbox_chan *link, void *data) | |
147 | { | |
148 | unsigned int chan = (unsigned int)link->con_priv; | |
149 | struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, | |
150 | controller); | |
151 | ||
152 | dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan); | |
153 | ||
154 | /* set channel n occupied */ | |
dba9a3df AP |
155 | stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XSCR, |
156 | TX_BIT_CHAN(chan)); | |
ffbded7d FD |
157 | |
158 | /* unmask 'tx channel free' interrupt */ | |
dba9a3df AP |
159 | stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
160 | TX_BIT_CHAN(chan)); | |
ffbded7d FD |
161 | |
162 | return 0; | |
163 | } | |
164 | ||
165 | static int stm32_ipcc_startup(struct mbox_chan *link) | |
166 | { | |
167 | unsigned int chan = (unsigned int)link->con_priv; | |
168 | struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, | |
169 | controller); | |
170 | int ret; | |
171 | ||
172 | ret = clk_prepare_enable(ipcc->clk); | |
173 | if (ret) { | |
174 | dev_err(ipcc->controller.dev, "can not enable the clock\n"); | |
175 | return ret; | |
176 | } | |
177 | ||
178 | /* unmask 'rx channel occupied' interrupt */ | |
dba9a3df AP |
179 | stm32_ipcc_clr_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
180 | RX_BIT_CHAN(chan)); | |
ffbded7d FD |
181 | |
182 | return 0; | |
183 | } | |
184 | ||
185 | static void stm32_ipcc_shutdown(struct mbox_chan *link) | |
186 | { | |
187 | unsigned int chan = (unsigned int)link->con_priv; | |
188 | struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc, | |
189 | controller); | |
190 | ||
191 | /* mask rx/tx interrupt */ | |
dba9a3df | 192 | stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
ffbded7d FD |
193 | RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan)); |
194 | ||
195 | clk_disable_unprepare(ipcc->clk); | |
196 | } | |
197 | ||
198 | static const struct mbox_chan_ops stm32_ipcc_ops = { | |
199 | .send_data = stm32_ipcc_send_data, | |
200 | .startup = stm32_ipcc_startup, | |
201 | .shutdown = stm32_ipcc_shutdown, | |
202 | }; | |
203 | ||
204 | static int stm32_ipcc_probe(struct platform_device *pdev) | |
205 | { | |
206 | struct device *dev = &pdev->dev; | |
207 | struct device_node *np = dev->of_node; | |
208 | struct stm32_ipcc *ipcc; | |
209 | struct resource *res; | |
210 | unsigned int i; | |
211 | int ret; | |
212 | u32 ip_ver; | |
213 | static const char * const irq_name[] = {"rx", "tx"}; | |
214 | irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq}; | |
215 | ||
216 | if (!np) { | |
217 | dev_err(dev, "No DT found\n"); | |
218 | return -ENODEV; | |
219 | } | |
220 | ||
221 | ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL); | |
222 | if (!ipcc) | |
223 | return -ENOMEM; | |
224 | ||
dba9a3df AP |
225 | spin_lock_init(&ipcc->lock); |
226 | ||
ffbded7d FD |
227 | /* proc_id */ |
228 | if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) { | |
229 | dev_err(dev, "Missing st,proc-id\n"); | |
230 | return -ENODEV; | |
231 | } | |
232 | ||
233 | if (ipcc->proc_id >= STM32_MAX_PROCS) { | |
234 | dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id); | |
235 | return -EINVAL; | |
236 | } | |
237 | ||
238 | /* regs */ | |
239 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
240 | ipcc->reg_base = devm_ioremap_resource(dev, res); | |
241 | if (IS_ERR(ipcc->reg_base)) | |
242 | return PTR_ERR(ipcc->reg_base); | |
243 | ||
244 | ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST; | |
245 | ||
246 | /* clock */ | |
247 | ipcc->clk = devm_clk_get(dev, NULL); | |
248 | if (IS_ERR(ipcc->clk)) | |
249 | return PTR_ERR(ipcc->clk); | |
250 | ||
251 | ret = clk_prepare_enable(ipcc->clk); | |
252 | if (ret) { | |
253 | dev_err(dev, "can not enable the clock\n"); | |
254 | return ret; | |
255 | } | |
256 | ||
257 | /* irq */ | |
258 | for (i = 0; i < IPCC_IRQ_NUM; i++) { | |
68a1c848 | 259 | ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]); |
ffbded7d | 260 | if (ipcc->irqs[i] < 0) { |
68a1c848 FD |
261 | if (ipcc->irqs[i] != -EPROBE_DEFER) |
262 | dev_err(dev, "no IRQ specified %s\n", | |
263 | irq_name[i]); | |
ffbded7d FD |
264 | ret = ipcc->irqs[i]; |
265 | goto err_clk; | |
266 | } | |
267 | ||
268 | ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL, | |
269 | irq_thread[i], IRQF_ONESHOT, | |
270 | dev_name(dev), ipcc); | |
271 | if (ret) { | |
272 | dev_err(dev, "failed to request irq %d (%d)\n", i, ret); | |
273 | goto err_clk; | |
274 | } | |
275 | } | |
276 | ||
277 | /* mask and enable rx/tx irq */ | |
dba9a3df | 278 | stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XMR, |
ffbded7d | 279 | RX_BIT_MASK | TX_BIT_MASK); |
dba9a3df AP |
280 | stm32_ipcc_set_bits(&ipcc->lock, ipcc->reg_proc + IPCC_XCR, |
281 | XCR_RXOIE | XCR_TXOIE); | |
ffbded7d FD |
282 | |
283 | /* wakeup */ | |
284 | if (of_property_read_bool(np, "wakeup-source")) { | |
68a1c848 | 285 | ipcc->wkp = platform_get_irq_byname(pdev, "wakeup"); |
ffbded7d | 286 | if (ipcc->wkp < 0) { |
68a1c848 FD |
287 | if (ipcc->wkp != -EPROBE_DEFER) |
288 | dev_err(dev, "could not get wakeup IRQ\n"); | |
ffbded7d FD |
289 | ret = ipcc->wkp; |
290 | goto err_clk; | |
291 | } | |
292 | ||
eac36c86 | 293 | device_set_wakeup_capable(dev, true); |
ffbded7d FD |
294 | ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp); |
295 | if (ret) { | |
296 | dev_err(dev, "Failed to set wake up irq\n"); | |
297 | goto err_init_wkp; | |
298 | } | |
ffbded7d FD |
299 | } |
300 | ||
301 | /* mailbox controller */ | |
302 | ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR); | |
303 | ipcc->n_chans &= IPCFGR_CHAN_MASK; | |
304 | ||
305 | ipcc->controller.dev = dev; | |
306 | ipcc->controller.txdone_irq = true; | |
307 | ipcc->controller.ops = &stm32_ipcc_ops; | |
308 | ipcc->controller.num_chans = ipcc->n_chans; | |
309 | ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans, | |
310 | sizeof(*ipcc->controller.chans), | |
311 | GFP_KERNEL); | |
312 | if (!ipcc->controller.chans) { | |
313 | ret = -ENOMEM; | |
314 | goto err_irq_wkp; | |
315 | } | |
316 | ||
317 | for (i = 0; i < ipcc->controller.num_chans; i++) | |
318 | ipcc->controller.chans[i].con_priv = (void *)i; | |
319 | ||
368d7767 | 320 | ret = devm_mbox_controller_register(dev, &ipcc->controller); |
ffbded7d FD |
321 | if (ret) |
322 | goto err_irq_wkp; | |
323 | ||
324 | platform_set_drvdata(pdev, ipcc); | |
325 | ||
326 | ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER); | |
327 | ||
328 | dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n", | |
329 | FIELD_GET(VER_MAJREV_MASK, ip_ver), | |
330 | FIELD_GET(VER_MINREV_MASK, ip_ver), | |
331 | ipcc->controller.num_chans, ipcc->proc_id); | |
332 | ||
333 | clk_disable_unprepare(ipcc->clk); | |
334 | return 0; | |
335 | ||
336 | err_irq_wkp: | |
337 | if (ipcc->wkp) | |
338 | dev_pm_clear_wake_irq(dev); | |
339 | err_init_wkp: | |
340 | device_init_wakeup(dev, false); | |
341 | err_clk: | |
342 | clk_disable_unprepare(ipcc->clk); | |
343 | return ret; | |
344 | } | |
345 | ||
346 | static int stm32_ipcc_remove(struct platform_device *pdev) | |
347 | { | |
348 | struct stm32_ipcc *ipcc = platform_get_drvdata(pdev); | |
349 | ||
ffbded7d FD |
350 | if (ipcc->wkp) |
351 | dev_pm_clear_wake_irq(&pdev->dev); | |
352 | ||
353 | device_init_wakeup(&pdev->dev, false); | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | #ifdef CONFIG_PM_SLEEP | |
359 | static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable) | |
360 | { | |
361 | struct stm32_ipcc *ipcc = dev_get_drvdata(dev); | |
362 | unsigned int i; | |
363 | ||
364 | if (device_may_wakeup(dev)) | |
365 | for (i = 0; i < IPCC_IRQ_NUM; i++) | |
366 | irq_set_irq_wake(ipcc->irqs[i], enable); | |
367 | } | |
368 | ||
369 | static int stm32_ipcc_suspend(struct device *dev) | |
370 | { | |
371 | struct stm32_ipcc *ipcc = dev_get_drvdata(dev); | |
372 | ||
373 | ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR); | |
374 | ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR); | |
375 | ||
376 | stm32_ipcc_set_irq_wake(dev, true); | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | static int stm32_ipcc_resume(struct device *dev) | |
382 | { | |
383 | struct stm32_ipcc *ipcc = dev_get_drvdata(dev); | |
384 | ||
385 | stm32_ipcc_set_irq_wake(dev, false); | |
386 | ||
387 | writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR); | |
388 | writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | #endif | |
393 | ||
394 | static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops, | |
395 | stm32_ipcc_suspend, stm32_ipcc_resume); | |
396 | ||
397 | static const struct of_device_id stm32_ipcc_of_match[] = { | |
398 | { .compatible = "st,stm32mp1-ipcc" }, | |
399 | {}, | |
400 | }; | |
401 | MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match); | |
402 | ||
403 | static struct platform_driver stm32_ipcc_driver = { | |
404 | .driver = { | |
405 | .name = "stm32-ipcc", | |
406 | .pm = &stm32_ipcc_pm_ops, | |
407 | .of_match_table = stm32_ipcc_of_match, | |
408 | }, | |
409 | .probe = stm32_ipcc_probe, | |
410 | .remove = stm32_ipcc_remove, | |
411 | }; | |
412 | ||
413 | module_platform_driver(stm32_ipcc_driver); | |
414 | ||
415 | MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>"); | |
416 | MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); | |
417 | MODULE_DESCRIPTION("STM32 IPCC driver"); | |
418 | MODULE_LICENSE("GPL v2"); |