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9ea53b74 | 1 | /* |
11b64d31 | 2 | * driver for ENE KB3926 B/C/D/E/F CIR (pnp id: ENE0XXX) |
9ea53b74 ML |
3 | * |
4 | * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License as | |
8 | * published by the Free Software Foundation; either version 2 of the | |
9 | * License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 | |
19 | * USA | |
11b64d31 ML |
20 | * |
21 | * Special thanks to: | |
22 | * Sami R. <maesesami@gmail.com> for lot of help in debugging and therefore | |
23 | * bringing to life support for transmission & learning mode. | |
24 | * | |
25 | * Charlie Andrews <charliethepilot@googlemail.com> for lots of help in | |
26 | * bringing up the support of new firmware buffer that is popular | |
27 | * on latest notebooks | |
28 | * | |
29 | * ENE for partial device documentation | |
30 | * | |
9ea53b74 ML |
31 | */ |
32 | ||
33 | #include <linux/kernel.h> | |
34 | #include <linux/module.h> | |
35 | #include <linux/pnp.h> | |
36 | #include <linux/io.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/sched.h> | |
931e39a1 ML |
39 | #include <linux/slab.h> |
40 | #include <linux/input.h> | |
41 | #include <media/ir-core.h> | |
42 | #include <media/ir-common.h> | |
43 | #include "ene_ir.h" | |
9ea53b74 | 44 | |
11b64d31 ML |
45 | static int sample_period; |
46 | static bool learning_mode; | |
9ea53b74 | 47 | static int debug; |
11b64d31 | 48 | static bool txsim; |
9ea53b74 | 49 | |
11b64d31 ML |
50 | static void ene_set_reg_addr(struct ene_device *dev, u16 reg) |
51 | { | |
52 | outb(reg >> 8, dev->hw_io + ENE_ADDR_HI); | |
53 | outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO); | |
54 | } | |
9ea53b74 ML |
55 | |
56 | /* read a hardware register */ | |
11b64d31 | 57 | static u8 ene_read_reg(struct ene_device *dev, u16 reg) |
9ea53b74 ML |
58 | { |
59 | u8 retval; | |
11b64d31 | 60 | ene_set_reg_addr(dev, reg); |
9ea53b74 | 61 | retval = inb(dev->hw_io + ENE_IO); |
11b64d31 | 62 | dbg_regs("reg %04x == %02x", reg, retval); |
9ea53b74 ML |
63 | return retval; |
64 | } | |
65 | ||
66 | /* write a hardware register */ | |
11b64d31 | 67 | static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value) |
9ea53b74 | 68 | { |
11b64d31 ML |
69 | dbg_regs("reg %04x <- %02x", reg, value); |
70 | ene_set_reg_addr(dev, reg); | |
9ea53b74 | 71 | outb(value, dev->hw_io + ENE_IO); |
9ea53b74 ML |
72 | } |
73 | ||
11b64d31 ML |
74 | /* Set bits in hardware register */ |
75 | static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask) | |
9ea53b74 | 76 | { |
11b64d31 ML |
77 | dbg_regs("reg %04x |= %02x", reg, mask); |
78 | ene_set_reg_addr(dev, reg); | |
79 | outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO); | |
80 | } | |
9ea53b74 | 81 | |
11b64d31 ML |
82 | /* Clear bits in hardware register */ |
83 | static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask) | |
84 | { | |
85 | dbg_regs("reg %04x &= ~%02x ", reg, mask); | |
86 | ene_set_reg_addr(dev, reg); | |
87 | outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO); | |
88 | } | |
9ea53b74 | 89 | |
11b64d31 ML |
90 | /* A helper to set/clear a bit in register according to boolean variable */ |
91 | static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask, | |
92 | bool set) | |
93 | { | |
94 | if (set) | |
95 | ene_set_reg_mask(dev, reg, mask); | |
96 | else | |
97 | ene_clear_reg_mask(dev, reg, mask); | |
9ea53b74 ML |
98 | } |
99 | ||
100 | /* detect hardware features */ | |
101 | static int ene_hw_detect(struct ene_device *dev) | |
102 | { | |
103 | u8 chip_major, chip_minor; | |
104 | u8 hw_revision, old_ver; | |
11b64d31 | 105 | u8 fw_reg2, fw_reg1; |
9ea53b74 | 106 | |
11b64d31 ML |
107 | ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD); |
108 | chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR); | |
109 | chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR); | |
110 | ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD); | |
9ea53b74 | 111 | |
11b64d31 ML |
112 | hw_revision = ene_read_reg(dev, ENE_ECHV); |
113 | old_ver = ene_read_reg(dev, ENE_HW_VER_OLD); | |
9ea53b74 | 114 | |
11b64d31 ML |
115 | dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) + |
116 | (ene_read_reg(dev, ENE_PLLFRL) >> 4); | |
931e39a1 | 117 | |
11b64d31 ML |
118 | if (sample_period != ENE_DEFAULT_SAMPLE_PERIOD) |
119 | dev->rx_period_adjust = | |
120 | dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4; | |
931e39a1 | 121 | |
9ea53b74 | 122 | if (hw_revision == 0xFF) { |
11b64d31 ML |
123 | ene_warn("device seems to be disabled"); |
124 | ene_warn("send a mail to lirc-list@lists.sourceforge.net"); | |
125 | ene_warn("please attach output of acpidump and dmidecode"); | |
9ea53b74 ML |
126 | return -ENODEV; |
127 | } | |
128 | ||
11b64d31 ML |
129 | ene_notice("chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x", |
130 | chip_major, chip_minor, old_ver, hw_revision); | |
131 | ||
132 | ene_notice("PLL freq = %d", dev->pll_freq); | |
133 | ||
9ea53b74 | 134 | if (chip_major == 0x33) { |
11b64d31 | 135 | ene_warn("chips 0x33xx aren't supported"); |
9ea53b74 ML |
136 | return -ENODEV; |
137 | } | |
138 | ||
139 | if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) { | |
140 | dev->hw_revision = ENE_HW_C; | |
11b64d31 | 141 | ene_notice("KB3926C detected"); |
9ea53b74 ML |
142 | } else if (old_ver == 0x24 && hw_revision == 0xC0) { |
143 | dev->hw_revision = ENE_HW_B; | |
11b64d31 | 144 | ene_notice("KB3926B detected"); |
9ea53b74 ML |
145 | } else { |
146 | dev->hw_revision = ENE_HW_D; | |
11b64d31 | 147 | ene_notice("KB3926D or higher detected"); |
9ea53b74 ML |
148 | } |
149 | ||
9ea53b74 ML |
150 | /* detect features hardware supports */ |
151 | if (dev->hw_revision < ENE_HW_C) | |
152 | return 0; | |
153 | ||
11b64d31 ML |
154 | fw_reg1 = ene_read_reg(dev, ENE_FW1); |
155 | fw_reg2 = ene_read_reg(dev, ENE_FW2); | |
9ea53b74 | 156 | |
11b64d31 | 157 | ene_notice("Firmware regs: %02x %02x", fw_reg1, fw_reg2); |
9ea53b74 | 158 | |
11b64d31 ML |
159 | dev->hw_use_gpio_0a = fw_reg2 & ENE_FW2_GP0A; |
160 | dev->hw_learning_and_tx_capable = fw_reg2 & ENE_FW2_LEARNING; | |
161 | dev->hw_extra_buffer = fw_reg1 & ENE_FW1_HAS_EXTRA_BUF; | |
162 | dev->hw_fan_input = dev->hw_learning_and_tx_capable && | |
163 | (fw_reg2 & ENE_FW2_FAN_INPUT); | |
9ea53b74 | 164 | |
11b64d31 | 165 | ene_notice("Hardware features:"); |
9ea53b74 ML |
166 | |
167 | if (dev->hw_learning_and_tx_capable) { | |
11b64d31 ML |
168 | ene_notice("* Supports transmitting & learning mode"); |
169 | ene_notice(" This feature is rare and therefore,"); | |
170 | ene_notice(" you are welcome to test it,"); | |
171 | ene_notice(" and/or contact the author via:"); | |
172 | ene_notice(" lirc-list@lists.sourceforge.net"); | |
173 | ene_notice(" or maximlevitsky@gmail.com"); | |
174 | ||
175 | ene_notice("* Uses GPIO %s for IR raw input", | |
176 | dev->hw_use_gpio_0a ? "40" : "0A"); | |
177 | ||
178 | if (dev->hw_fan_input) | |
179 | ene_notice("* Uses unused fan feedback input as source" | |
180 | " of demodulated IR data"); | |
9ea53b74 | 181 | } |
11b64d31 ML |
182 | |
183 | if (!dev->hw_fan_input) | |
184 | ene_notice("* Uses GPIO %s for IR demodulated input", | |
185 | dev->hw_use_gpio_0a ? "0A" : "40"); | |
186 | ||
187 | if (dev->hw_extra_buffer) | |
188 | ene_notice("* Uses new style input buffer"); | |
9ea53b74 ML |
189 | return 0; |
190 | } | |
191 | ||
11b64d31 ML |
192 | /* Sense current received carrier */ |
193 | void ene_rx_sense_carrier(struct ene_device *dev) | |
9ea53b74 | 194 | { |
11b64d31 ML |
195 | int period = ene_read_reg(dev, ENE_CIRCAR_PRD); |
196 | int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD); | |
197 | int carrier, duty_cycle; | |
198 | ||
199 | ||
200 | if (!(period & ENE_CIRCAR_PRD_VALID)) | |
201 | return; | |
202 | ||
203 | period &= ~ENE_CIRCAR_PRD_VALID; | |
204 | ||
205 | if (!period) | |
206 | return; | |
207 | ||
208 | dbg("RX: hardware carrier period = %02x", period); | |
209 | dbg("RX: hardware carrier pulse period = %02x", hperiod); | |
210 | ||
211 | ||
212 | carrier = 2000000 / period; | |
213 | duty_cycle = (hperiod * 100) / period; | |
214 | dbg("RX: sensed carrier = %d Hz, duty cycle %d%%", | |
215 | carrier, duty_cycle); | |
216 | ||
217 | /* TODO: Send carrier & duty cycle to IR layer */ | |
9ea53b74 ML |
218 | } |
219 | ||
11b64d31 ML |
220 | /* this enables/disables the CIR RX engine */ |
221 | static void ene_enable_cir_engine(struct ene_device *dev, bool enable) | |
9ea53b74 | 222 | { |
11b64d31 ML |
223 | ene_set_clear_reg_mask(dev, ENE_CIRCFG, |
224 | ENE_CIRCFG_RX_EN | ENE_CIRCFG_RX_IRQ, enable); | |
9ea53b74 ML |
225 | } |
226 | ||
11b64d31 ML |
227 | /* this selects input for CIR engine. Ether GPIO 0A or GPIO40*/ |
228 | static void ene_select_rx_input(struct ene_device *dev, bool gpio_0a) | |
9ea53b74 | 229 | { |
11b64d31 | 230 | ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a); |
9ea53b74 ML |
231 | } |
232 | ||
11b64d31 ML |
233 | /* |
234 | * this enables alternative input via fan tachometer sensor and bypasses | |
235 | * the hw CIR engine | |
236 | */ | |
237 | static void ene_enable_fan_input(struct ene_device *dev, bool enable) | |
9ea53b74 | 238 | { |
11b64d31 ML |
239 | if (!dev->hw_fan_input) |
240 | return; | |
9ea53b74 | 241 | |
11b64d31 ML |
242 | if (!enable) |
243 | ene_write_reg(dev, ENE_FAN_AS_IN1, 0); | |
244 | else { | |
245 | ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN); | |
246 | ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN); | |
247 | } | |
248 | dev->rx_fan_input_inuse = enable; | |
9ea53b74 ML |
249 | } |
250 | ||
11b64d31 ML |
251 | /* setup the receiver for RX*/ |
252 | static void ene_rx_setup(struct ene_device *dev) | |
9ea53b74 | 253 | { |
11b64d31 ML |
254 | bool learning_mode = dev->learning_enabled || |
255 | dev->carrier_detect_enabled; | |
256 | int sample_period_adjust = 0; | |
9ea53b74 | 257 | |
9ea53b74 | 258 | |
11b64d31 ML |
259 | /* set sample period*/ |
260 | if (sample_period == ENE_DEFAULT_SAMPLE_PERIOD) | |
261 | sample_period_adjust = | |
262 | dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2; | |
9ea53b74 | 263 | |
11b64d31 ML |
264 | ene_write_reg(dev, ENE_CIRRLC_CFG, |
265 | (sample_period + sample_period_adjust) | | |
266 | ENE_CIRRLC_CFG_OVERFLOW); | |
267 | /* revB doesn't support inputs */ | |
268 | if (dev->hw_revision < ENE_HW_C) | |
269 | goto select_timeout; | |
9ea53b74 | 270 | |
11b64d31 | 271 | if (learning_mode && dev->hw_learning_and_tx_capable) { |
9ea53b74 | 272 | |
11b64d31 ML |
273 | /* Enable the opposite of the normal input |
274 | That means that if GPIO40 is normally used, use GPIO0A | |
275 | and vice versa. | |
276 | This input will carry non demodulated | |
277 | signal, and we will tell the hw to demodulate it itself */ | |
278 | ene_select_rx_input(dev, !dev->hw_use_gpio_0a); | |
279 | dev->rx_fan_input_inuse = false; | |
9ea53b74 | 280 | |
11b64d31 ML |
281 | /* Enable carrier demodulation */ |
282 | ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD); | |
9ea53b74 | 283 | |
11b64d31 ML |
284 | /* Enable carrier detection */ |
285 | ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT, | |
286 | dev->carrier_detect_enabled || debug); | |
9ea53b74 | 287 | } else { |
11b64d31 ML |
288 | if (dev->hw_fan_input) |
289 | dev->rx_fan_input_inuse = true; | |
290 | else | |
291 | ene_select_rx_input(dev, dev->hw_use_gpio_0a); | |
292 | ||
293 | /* Disable carrier detection & demodulation */ | |
294 | ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD); | |
295 | ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT); | |
9ea53b74 ML |
296 | } |
297 | ||
11b64d31 | 298 | select_timeout: |
931e39a1 | 299 | if (dev->rx_fan_input_inuse) { |
11b64d31 | 300 | dev->props->rx_resolution = MS_TO_NS(ENE_FW_SAMPLE_PERIOD_FAN); |
931e39a1 | 301 | |
11b64d31 ML |
302 | /* Fan input doesn't support timeouts, it just ends the |
303 | input with a maximum sample */ | |
304 | dev->props->min_timeout = dev->props->max_timeout = | |
305 | MS_TO_NS(ENE_FW_SMPL_BUF_FAN_MSK * | |
306 | ENE_FW_SAMPLE_PERIOD_FAN); | |
931e39a1 | 307 | } else { |
11b64d31 ML |
308 | dev->props->rx_resolution = MS_TO_NS(sample_period); |
309 | ||
310 | /* Theoreticly timeout is unlimited, but we cap it | |
311 | * because it was seen that on one device, it | |
312 | * would stop sending spaces after around 250 msec. | |
313 | * Besides, this is close to 2^32 anyway and timeout is u32. | |
314 | */ | |
315 | dev->props->min_timeout = MS_TO_NS(127 * sample_period); | |
316 | dev->props->max_timeout = MS_TO_NS(200000); | |
931e39a1 | 317 | } |
11b64d31 ML |
318 | |
319 | if (dev->hw_learning_and_tx_capable) | |
320 | dev->props->tx_resolution = MS_TO_NS(sample_period); | |
321 | ||
322 | if (dev->props->timeout > dev->props->max_timeout) | |
323 | dev->props->timeout = dev->props->max_timeout; | |
324 | if (dev->props->timeout < dev->props->min_timeout) | |
325 | dev->props->timeout = dev->props->min_timeout; | |
9ea53b74 ML |
326 | } |
327 | ||
328 | /* Enable the device for receive */ | |
329 | static void ene_rx_enable(struct ene_device *dev) | |
330 | { | |
331 | u8 reg_value; | |
11b64d31 | 332 | dbg("RX: setup receiver, learning mode = %d", learning_mode); |
9ea53b74 | 333 | |
11b64d31 | 334 | /* Enable system interrupt */ |
9ea53b74 | 335 | if (dev->hw_revision < ENE_HW_C) { |
11b64d31 ML |
336 | ene_write_reg(dev, ENEB_IRQ, dev->irq << 1); |
337 | ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01); | |
9ea53b74 | 338 | } else { |
11b64d31 ML |
339 | reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0; |
340 | reg_value |= ENE_IRQ_UNK_EN; | |
341 | reg_value &= ~ENE_IRQ_STATUS; | |
342 | reg_value |= (dev->irq & ENE_IRQ_MASK); | |
343 | ene_write_reg(dev, ENE_IRQ, reg_value); | |
9ea53b74 ML |
344 | } |
345 | ||
11b64d31 ML |
346 | if (dev->hw_revision >= ENE_HW_C) |
347 | ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63); | |
348 | ||
349 | /* Enable the inputs */ | |
350 | ene_write_reg(dev, ENE_CIRCFG2, 0x00); | |
9ea53b74 | 351 | |
11b64d31 ML |
352 | if (dev->rx_fan_input_inuse) { |
353 | ene_enable_cir_engine(dev, false); | |
354 | ene_enable_fan_input(dev, true); | |
355 | } else { | |
356 | ene_enable_cir_engine(dev, true); | |
357 | ene_enable_fan_input(dev, false); | |
358 | } | |
9ea53b74 ML |
359 | |
360 | /* ack any pending irqs - just in case */ | |
361 | ene_irq_status(dev); | |
362 | ||
9ea53b74 | 363 | /* enable firmware bits */ |
11b64d31 | 364 | ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ); |
931e39a1 ML |
365 | |
366 | /* enter idle mode */ | |
11b64d31 ML |
367 | ir_raw_event_set_idle(dev->idev, true); |
368 | dev->rx_enabled = true; | |
9ea53b74 ML |
369 | } |
370 | ||
931e39a1 | 371 | /* Disable the device receiver */ |
9ea53b74 ML |
372 | static void ene_rx_disable(struct ene_device *dev) |
373 | { | |
374 | /* disable inputs */ | |
11b64d31 ML |
375 | ene_enable_cir_engine(dev, false); |
376 | ene_enable_fan_input(dev, false); | |
9ea53b74 ML |
377 | |
378 | /* disable hardware IRQ and firmware flag */ | |
11b64d31 | 379 | ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ); |
9ea53b74 | 380 | |
11b64d31 ML |
381 | ir_raw_event_set_idle(dev->idev, true); |
382 | dev->rx_enabled = false; | |
9ea53b74 ML |
383 | } |
384 | ||
9ea53b74 ML |
385 | /* prepare transmission */ |
386 | static void ene_tx_prepare(struct ene_device *dev) | |
387 | { | |
11b64d31 ML |
388 | u8 conf1 = ene_read_reg(dev, ENE_CIRCFG); |
389 | u8 fwreg2 = ene_read_reg(dev, ENE_FW2); | |
9ea53b74 | 390 | |
9ea53b74 ML |
391 | dev->saved_conf1 = conf1; |
392 | ||
11b64d31 ML |
393 | /* Show information about currently connected transmitter jacks */ |
394 | if (fwreg2 & ENE_FW2_EMMITER1_CONN) | |
395 | dbg("TX: Transmitter #1 is connected"); | |
9ea53b74 | 396 | |
11b64d31 ML |
397 | if (fwreg2 & ENE_FW2_EMMITER2_CONN) |
398 | dbg("TX: Transmitter #2 is connected"); | |
9ea53b74 | 399 | |
11b64d31 ML |
400 | if (!(fwreg2 & (ENE_FW2_EMMITER1_CONN | ENE_FW2_EMMITER2_CONN))) |
401 | ene_warn("TX: transmitter cable isn't connected!"); | |
402 | ||
403 | /* Set transmitter mask */ | |
404 | ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41, | |
405 | !!(dev->transmitter_mask & 0x01)); | |
406 | ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D, | |
407 | !!(dev->transmitter_mask & 0x02)); | |
9ea53b74 | 408 | |
11b64d31 ML |
409 | /* Set the carrier period && duty cycle */ |
410 | if (dev->tx_period) { | |
9ea53b74 | 411 | |
11b64d31 | 412 | int tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle); |
9ea53b74 | 413 | |
11b64d31 ML |
414 | if (!tx_puls_width) |
415 | tx_puls_width = 1; | |
9ea53b74 | 416 | |
11b64d31 ML |
417 | dbg("TX: pulse distance = %d * 500 ns", dev->tx_period); |
418 | dbg("TX: pulse width = %d * 500 ns", tx_puls_width); | |
9ea53b74 | 419 | |
11b64d31 ML |
420 | ene_write_reg(dev, ENE_CIRMOD_PRD, ENE_CIRMOD_PRD_POL | |
421 | dev->tx_period); | |
9ea53b74 | 422 | |
11b64d31 | 423 | ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width); |
9ea53b74 | 424 | |
11b64d31 | 425 | conf1 |= ENE_CIRCFG_TX_CARR; |
9ea53b74 | 426 | } else |
11b64d31 | 427 | conf1 &= ~ENE_CIRCFG_TX_CARR; |
9ea53b74 | 428 | |
11b64d31 ML |
429 | /* disable receive on revc */ |
430 | if (dev->hw_revision == ENE_HW_C) | |
431 | conf1 &= ~ENE_CIRCFG_RX_EN; | |
9ea53b74 | 432 | |
11b64d31 ML |
433 | /* Enable TX engine */ |
434 | conf1 |= ENE_CIRCFG_TX_EN | ENE_CIRCFG_TX_IRQ; | |
435 | ene_write_reg(dev, ENE_CIRCFG, conf1); | |
9ea53b74 ML |
436 | } |
437 | ||
438 | /* end transmission */ | |
439 | static void ene_tx_complete(struct ene_device *dev) | |
440 | { | |
11b64d31 | 441 | ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1); |
931e39a1 | 442 | dev->tx_buffer = NULL; |
9ea53b74 ML |
443 | } |
444 | ||
9ea53b74 ML |
445 | |
446 | /* TX one sample - must be called with dev->hw_lock*/ | |
447 | static void ene_tx_sample(struct ene_device *dev) | |
448 | { | |
449 | u8 raw_tx; | |
450 | u32 sample; | |
11b64d31 | 451 | bool pulse = dev->tx_sample_pulse; |
9ea53b74 | 452 | |
931e39a1 | 453 | if (!dev->tx_buffer) { |
11b64d31 | 454 | ene_warn("TX: BUG: attempt to transmit NULL buffer"); |
9ea53b74 ML |
455 | return; |
456 | } | |
457 | ||
458 | /* Grab next TX sample */ | |
459 | if (!dev->tx_sample) { | |
11b64d31 ML |
460 | |
461 | if (dev->tx_pos == dev->tx_len) { | |
9ea53b74 | 462 | if (!dev->tx_done) { |
11b64d31 ML |
463 | dbg("TX: no more data to send"); |
464 | dev->tx_done = true; | |
9ea53b74 ML |
465 | goto exit; |
466 | } else { | |
11b64d31 | 467 | dbg("TX: last sample sent by hardware"); |
9ea53b74 ML |
468 | ene_tx_complete(dev); |
469 | complete(&dev->tx_complete); | |
470 | return; | |
471 | } | |
472 | } | |
473 | ||
474 | sample = dev->tx_buffer[dev->tx_pos++]; | |
475 | dev->tx_sample_pulse = !dev->tx_sample_pulse; | |
476 | ||
11b64d31 | 477 | dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period); |
9ea53b74 | 478 | |
9ea53b74 | 479 | if (!dev->tx_sample) |
11b64d31 | 480 | dev->tx_sample = 1; |
9ea53b74 ML |
481 | } |
482 | ||
11b64d31 | 483 | raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK); |
9ea53b74 ML |
484 | dev->tx_sample -= raw_tx; |
485 | ||
11b64d31 ML |
486 | dbg("TX: sample %8d (%s)", raw_tx * sample_period, |
487 | pulse ? "pulse" : "space"); | |
488 | if (pulse) | |
489 | raw_tx |= ENE_CIRRLC_OUT_PULSE; | |
490 | ||
491 | ene_write_reg(dev, | |
492 | dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx); | |
9ea53b74 | 493 | |
9ea53b74 ML |
494 | dev->tx_reg = !dev->tx_reg; |
495 | exit: | |
496 | /* simulate TX done interrupt */ | |
497 | if (txsim) | |
498 | mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500); | |
499 | } | |
500 | ||
501 | /* timer to simulate tx done interrupt */ | |
502 | static void ene_tx_irqsim(unsigned long data) | |
503 | { | |
504 | struct ene_device *dev = (struct ene_device *)data; | |
505 | unsigned long flags; | |
506 | ||
507 | spin_lock_irqsave(&dev->hw_lock, flags); | |
508 | ene_tx_sample(dev); | |
509 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
510 | } | |
511 | ||
11b64d31 ML |
512 | /* Read properities of hw sample buffer */ |
513 | static void ene_setup_hw_buffer(struct ene_device *dev) | |
514 | { | |
515 | u16 tmp; | |
516 | ||
517 | ene_read_hw_pointer(dev); | |
518 | dev->r_pointer = dev->w_pointer; | |
519 | ||
520 | if (!dev->hw_extra_buffer) { | |
521 | dev->buffer_len = ENE_FW_PACKET_SIZE * 2; | |
522 | return; | |
523 | } | |
524 | ||
525 | tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER); | |
526 | tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8; | |
527 | dev->extra_buf1_address = tmp; | |
528 | ||
529 | dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2); | |
530 | ||
531 | tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3); | |
532 | tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8; | |
533 | dev->extra_buf2_address = tmp; | |
534 | ||
535 | dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5); | |
536 | ||
537 | dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8; | |
538 | ||
539 | ene_notice("Hardware uses 2 extended buffers:"); | |
540 | ene_notice(" 0x%04x - len : %d", dev->extra_buf1_address, | |
541 | dev->extra_buf1_len); | |
542 | ene_notice(" 0x%04x - len : %d", dev->extra_buf2_address, | |
543 | dev->extra_buf2_len); | |
544 | ||
545 | ene_notice("Total buffer len = %d", dev->buffer_len); | |
546 | ||
547 | if (dev->buffer_len > 64 || dev->buffer_len < 16) | |
548 | goto error; | |
549 | ||
550 | if (dev->extra_buf1_address > 0xFBFC || | |
551 | dev->extra_buf1_address < 0xEC00) | |
552 | goto error; | |
553 | ||
554 | if (dev->extra_buf2_address > 0xFBFC || | |
555 | dev->extra_buf2_address < 0xEC00) | |
556 | goto error; | |
557 | ||
558 | if (dev->r_pointer > dev->buffer_len) | |
559 | goto error; | |
560 | ||
561 | ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND); | |
562 | return; | |
563 | error: | |
564 | ene_warn("Error validating extra buffers, device probably won't work"); | |
565 | dev->hw_extra_buffer = false; | |
566 | ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND); | |
567 | } | |
568 | ||
569 | ||
570 | /* Restore the pointers to extra buffers - to make module reload work*/ | |
571 | static void ene_restore_extra_buffer(struct ene_device *dev) | |
572 | { | |
573 | if (!dev->hw_extra_buffer) | |
574 | return; | |
575 | ||
576 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0, | |
577 | dev->extra_buf1_address & 0xFF); | |
578 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1, | |
579 | dev->extra_buf1_address >> 8); | |
580 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len); | |
581 | ||
582 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3, | |
583 | dev->extra_buf2_address & 0xFF); | |
584 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4, | |
585 | dev->extra_buf2_address >> 8); | |
586 | ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5, | |
587 | dev->extra_buf2_len); | |
588 | ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND); | |
589 | } | |
590 | ||
9ea53b74 ML |
591 | |
592 | /* read irq status and ack it */ | |
593 | static int ene_irq_status(struct ene_device *dev) | |
594 | { | |
595 | u8 irq_status; | |
596 | u8 fw_flags1, fw_flags2; | |
9ea53b74 ML |
597 | int retval = 0; |
598 | ||
11b64d31 | 599 | fw_flags2 = ene_read_reg(dev, ENE_FW2); |
9ea53b74 ML |
600 | |
601 | if (dev->hw_revision < ENE_HW_C) { | |
11b64d31 | 602 | irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS); |
9ea53b74 ML |
603 | |
604 | if (!(irq_status & ENEB_IRQ_STATUS_IR)) | |
605 | return 0; | |
606 | ||
11b64d31 | 607 | ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR); |
9ea53b74 ML |
608 | return ENE_IRQ_RX; |
609 | } | |
610 | ||
11b64d31 ML |
611 | irq_status = ene_read_reg(dev, ENE_IRQ); |
612 | if (!(irq_status & ENE_IRQ_STATUS)) | |
9ea53b74 ML |
613 | return 0; |
614 | ||
615 | /* original driver does that twice - a workaround ? */ | |
11b64d31 ML |
616 | ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS); |
617 | ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS); | |
9ea53b74 | 618 | |
11b64d31 ML |
619 | /* check RX interrupt */ |
620 | if (fw_flags2 & ENE_FW2_RXIRQ) { | |
621 | retval |= ENE_IRQ_RX; | |
622 | ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ); | |
623 | } | |
9ea53b74 | 624 | |
11b64d31 ML |
625 | /* check TX interrupt */ |
626 | fw_flags1 = ene_read_reg(dev, ENE_FW1); | |
9ea53b74 | 627 | if (fw_flags1 & ENE_FW1_TXIRQ) { |
11b64d31 | 628 | ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ); |
9ea53b74 ML |
629 | retval |= ENE_IRQ_TX; |
630 | } | |
631 | ||
11b64d31 ML |
632 | return retval; |
633 | } | |
9ea53b74 | 634 | |
11b64d31 ML |
635 | /* Read hardware write pointer */ |
636 | static void ene_read_hw_pointer(struct ene_device *dev) | |
637 | { | |
638 | if (dev->hw_extra_buffer) | |
639 | dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER); | |
640 | else | |
641 | dev->w_pointer = ene_read_reg(dev, ENE_FW2) | |
642 | & ENE_FW2_BUF_WPTR ? 0 : ENE_FW_PACKET_SIZE; | |
643 | ||
644 | dbg_verbose("RB: HW write pointer: %02x, driver read pointer: %02x", | |
645 | dev->w_pointer, dev->r_pointer); | |
646 | } | |
647 | ||
648 | /* Gets address of next sample from HW ring buffer */ | |
649 | static int ene_get_sample_reg(struct ene_device *dev) | |
650 | { | |
651 | int r_pointer; | |
652 | ||
653 | if (dev->r_pointer == dev->w_pointer) { | |
654 | dbg_verbose("RB: hit end, try update w_pointer"); | |
655 | ene_read_hw_pointer(dev); | |
9ea53b74 ML |
656 | } |
657 | ||
11b64d31 ML |
658 | if (dev->r_pointer == dev->w_pointer) { |
659 | dbg_verbose("RB: end of data at %d", dev->r_pointer); | |
660 | return 0; | |
661 | } | |
9ea53b74 | 662 | |
11b64d31 ML |
663 | dbg_verbose("RB: reading at offset %d", dev->r_pointer); |
664 | r_pointer = dev->r_pointer; | |
665 | ||
666 | dev->r_pointer++; | |
667 | if (dev->r_pointer == dev->buffer_len) | |
668 | dev->r_pointer = 0; | |
669 | ||
670 | dbg_verbose("RB: next read will be from offset %d", dev->r_pointer); | |
671 | ||
672 | if (r_pointer < 8) { | |
673 | dbg_verbose("RB: read at main buffer at %d", r_pointer); | |
674 | return ENE_FW_SAMPLE_BUFFER + r_pointer; | |
675 | } | |
676 | ||
677 | r_pointer -= 8; | |
678 | ||
679 | if (r_pointer < dev->extra_buf1_len) { | |
680 | dbg_verbose("RB: read at 1st extra buffer at %d", r_pointer); | |
681 | return dev->extra_buf1_address + r_pointer; | |
682 | } | |
683 | ||
684 | r_pointer -= dev->extra_buf1_len; | |
685 | ||
686 | if (r_pointer < dev->extra_buf2_len) { | |
687 | dbg_verbose("RB: read at 2nd extra buffer at %d", r_pointer); | |
688 | return dev->extra_buf2_address + r_pointer; | |
689 | } | |
690 | ||
691 | dbg("attempt to read beyong ring bufer end"); | |
692 | return 0; | |
9ea53b74 ML |
693 | } |
694 | ||
695 | /* interrupt handler */ | |
696 | static irqreturn_t ene_isr(int irq, void *data) | |
697 | { | |
11b64d31 ML |
698 | u16 hw_value, reg; |
699 | int hw_sample, irq_status; | |
700 | bool pulse; | |
9ea53b74 | 701 | unsigned long flags; |
9ea53b74 ML |
702 | irqreturn_t retval = IRQ_NONE; |
703 | struct ene_device *dev = (struct ene_device *)data; | |
931e39a1 | 704 | struct ir_raw_event ev; |
9ea53b74 | 705 | |
9ea53b74 | 706 | spin_lock_irqsave(&dev->hw_lock, flags); |
11b64d31 ML |
707 | |
708 | dbg_verbose("ISR called"); | |
709 | ene_read_hw_pointer(dev); | |
9ea53b74 ML |
710 | irq_status = ene_irq_status(dev); |
711 | ||
712 | if (!irq_status) | |
713 | goto unlock; | |
714 | ||
715 | retval = IRQ_HANDLED; | |
716 | ||
717 | if (irq_status & ENE_IRQ_TX) { | |
11b64d31 | 718 | dbg_verbose("TX interrupt"); |
9ea53b74 | 719 | if (!dev->hw_learning_and_tx_capable) { |
11b64d31 | 720 | dbg("TX interrupt on unsupported device!"); |
9ea53b74 ML |
721 | goto unlock; |
722 | } | |
723 | ene_tx_sample(dev); | |
724 | } | |
725 | ||
726 | if (!(irq_status & ENE_IRQ_RX)) | |
727 | goto unlock; | |
728 | ||
11b64d31 | 729 | dbg_verbose("RX interrupt"); |
9ea53b74 | 730 | |
931e39a1 | 731 | if (dev->carrier_detect_enabled || debug) |
11b64d31 ML |
732 | ene_rx_sense_carrier(dev); |
733 | ||
734 | /* On hardware that don't support extra buffer we need to trust | |
735 | the interrupt and not track the read pointer */ | |
736 | if (!dev->hw_extra_buffer) | |
737 | dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0; | |
738 | ||
739 | while (1) { | |
9ea53b74 | 740 | |
11b64d31 ML |
741 | reg = ene_get_sample_reg(dev); |
742 | ||
743 | dbg_verbose("next sample to read at: %04x", reg); | |
744 | if (!reg) | |
745 | break; | |
746 | ||
747 | hw_value = ene_read_reg(dev, reg); | |
9ea53b74 ML |
748 | |
749 | if (dev->rx_fan_input_inuse) { | |
11b64d31 ML |
750 | |
751 | int offset = ENE_FW_SMPL_BUF_FAN - ENE_FW_SAMPLE_BUFFER; | |
752 | ||
9ea53b74 | 753 | /* read high part of the sample */ |
11b64d31 ML |
754 | hw_value |= ene_read_reg(dev, reg + offset) << 8; |
755 | pulse = hw_value & ENE_FW_SMPL_BUF_FAN_PLS; | |
9ea53b74 ML |
756 | |
757 | /* clear space bit, and other unused bits */ | |
11b64d31 ML |
758 | hw_value &= ENE_FW_SMPL_BUF_FAN_MSK; |
759 | hw_sample = hw_value * ENE_FW_SAMPLE_PERIOD_FAN; | |
9ea53b74 ML |
760 | |
761 | } else { | |
11b64d31 ML |
762 | pulse = !(hw_value & ENE_FW_SAMPLE_SPACE); |
763 | hw_value &= ~ENE_FW_SAMPLE_SPACE; | |
9ea53b74 | 764 | hw_sample = hw_value * sample_period; |
931e39a1 ML |
765 | |
766 | if (dev->rx_period_adjust) { | |
11b64d31 ML |
767 | hw_sample *= 100; |
768 | hw_sample /= (100 + dev->rx_period_adjust); | |
931e39a1 | 769 | } |
9ea53b74 | 770 | } |
9ea53b74 | 771 | |
11b64d31 ML |
772 | if (!dev->hw_extra_buffer && !hw_sample) { |
773 | dev->r_pointer = dev->w_pointer; | |
774 | continue; | |
775 | } | |
931e39a1 | 776 | |
11b64d31 | 777 | dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space"); |
931e39a1 | 778 | |
11b64d31 | 779 | ev.duration = MS_TO_NS(hw_sample); |
931e39a1 ML |
780 | ev.pulse = pulse; |
781 | ir_raw_event_store_with_filter(dev->idev, &ev); | |
9ea53b74 | 782 | } |
931e39a1 ML |
783 | |
784 | ir_raw_event_handle(dev->idev); | |
9ea53b74 ML |
785 | unlock: |
786 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
787 | return retval; | |
788 | } | |
789 | ||
790 | /* Initialize default settings */ | |
791 | static void ene_setup_settings(struct ene_device *dev) | |
792 | { | |
9ea53b74 | 793 | dev->tx_period = 32; |
11b64d31 ML |
794 | dev->tx_duty_cycle = 50; /*%*/ |
795 | dev->transmitter_mask = 0x03; | |
9ea53b74 | 796 | |
9ea53b74 | 797 | dev->learning_enabled = |
11b64d31 | 798 | (learning_mode && dev->hw_learning_and_tx_capable); |
9ea53b74 | 799 | |
11b64d31 ML |
800 | /* Set reasonable default timeout */ |
801 | dev->props->timeout = MS_TO_NS(15000); | |
9ea53b74 ML |
802 | } |
803 | ||
804 | /* outside interface: called on first open*/ | |
805 | static int ene_open(void *data) | |
806 | { | |
807 | struct ene_device *dev = (struct ene_device *)data; | |
808 | unsigned long flags; | |
809 | ||
810 | spin_lock_irqsave(&dev->hw_lock, flags); | |
9ea53b74 ML |
811 | ene_rx_enable(dev); |
812 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
813 | return 0; | |
814 | } | |
815 | ||
816 | /* outside interface: called on device close*/ | |
817 | static void ene_close(void *data) | |
818 | { | |
819 | struct ene_device *dev = (struct ene_device *)data; | |
820 | unsigned long flags; | |
821 | spin_lock_irqsave(&dev->hw_lock, flags); | |
822 | ||
823 | ene_rx_disable(dev); | |
9ea53b74 ML |
824 | spin_unlock_irqrestore(&dev->hw_lock, flags); |
825 | } | |
826 | ||
931e39a1 ML |
827 | /* outside interface: set transmitter mask */ |
828 | static int ene_set_tx_mask(void *data, u32 tx_mask) | |
9ea53b74 | 829 | { |
931e39a1 | 830 | struct ene_device *dev = (struct ene_device *)data; |
9ea53b74 | 831 | unsigned long flags; |
11b64d31 | 832 | dbg("TX: attempt to set transmitter mask %02x", tx_mask); |
931e39a1 ML |
833 | |
834 | /* invalid txmask */ | |
11b64d31 ML |
835 | if (!tx_mask || tx_mask & ~0x03) { |
836 | dbg("TX: invalid mask"); | |
931e39a1 ML |
837 | /* return count of transmitters */ |
838 | return 2; | |
9ea53b74 ML |
839 | } |
840 | ||
931e39a1 ML |
841 | spin_lock_irqsave(&dev->hw_lock, flags); |
842 | dev->transmitter_mask = tx_mask; | |
843 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
844 | return 0; | |
845 | } | |
9ea53b74 | 846 | |
931e39a1 ML |
847 | /* outside interface : set tx carrier */ |
848 | static int ene_set_tx_carrier(void *data, u32 carrier) | |
849 | { | |
850 | struct ene_device *dev = (struct ene_device *)data; | |
851 | unsigned long flags; | |
11b64d31 | 852 | u32 period = 2000000 / carrier; |
9ea53b74 | 853 | |
11b64d31 | 854 | dbg("TX: attempt to set tx carrier to %d kHz", carrier); |
9ea53b74 | 855 | |
11b64d31 ML |
856 | if (period && (period > ENE_CIRMOD_PRD_MAX || |
857 | period < ENE_CIRMOD_PRD_MIN)) { | |
9ea53b74 | 858 | |
11b64d31 ML |
859 | dbg("TX: out of range %d-%d kHz carrier", |
860 | 2000 / ENE_CIRMOD_PRD_MIN, | |
861 | 2000 / ENE_CIRMOD_PRD_MAX); | |
9ea53b74 | 862 | |
11b64d31 | 863 | return -1; |
9ea53b74 ML |
864 | } |
865 | ||
11b64d31 | 866 | dbg("TX: set carrier to %d kHz", carrier); |
931e39a1 ML |
867 | spin_lock_irqsave(&dev->hw_lock, flags); |
868 | dev->tx_period = period; | |
869 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
870 | return 0; | |
9ea53b74 ML |
871 | } |
872 | ||
11b64d31 ML |
873 | /*outside interface : set tx duty cycle */ |
874 | static int ene_set_tx_duty_cycle(void *data, u32 duty_cycle) | |
875 | { | |
876 | struct ene_device *dev = (struct ene_device *)data; | |
877 | unsigned long flags; | |
878 | ||
879 | dbg("TX: setting duty cycle to %d%%", duty_cycle); | |
880 | ||
881 | BUG_ON(!duty_cycle || duty_cycle >= 100); | |
882 | ||
883 | spin_lock_irqsave(&dev->hw_lock, flags); | |
884 | dev->tx_duty_cycle = duty_cycle; | |
885 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
886 | return 0; | |
887 | } | |
931e39a1 ML |
888 | |
889 | /* outside interface: enable learning mode */ | |
890 | static int ene_set_learning_mode(void *data, int enable) | |
9ea53b74 | 891 | { |
931e39a1 | 892 | struct ene_device *dev = (struct ene_device *)data; |
9ea53b74 | 893 | unsigned long flags; |
931e39a1 ML |
894 | if (enable == dev->learning_enabled) |
895 | return 0; | |
9ea53b74 | 896 | |
931e39a1 ML |
897 | spin_lock_irqsave(&dev->hw_lock, flags); |
898 | dev->learning_enabled = enable; | |
11b64d31 ML |
899 | ene_rx_disable(dev); |
900 | ene_rx_setup(dev); | |
901 | ene_rx_enable(dev); | |
931e39a1 ML |
902 | spin_unlock_irqrestore(&dev->hw_lock, flags); |
903 | return 0; | |
904 | } | |
9ea53b74 | 905 | |
931e39a1 ML |
906 | /* outside interface: enable or disable idle mode */ |
907 | static void ene_rx_set_idle(void *data, int idle) | |
908 | { | |
909 | struct ene_device *dev = (struct ene_device *)data; | |
9ea53b74 | 910 | |
11b64d31 ML |
911 | if (!idle) |
912 | return; | |
9ea53b74 | 913 | |
11b64d31 ML |
914 | dbg("RX: stopping the receiver"); |
915 | ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN); | |
916 | ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN); | |
917 | } | |
9ea53b74 | 918 | |
931e39a1 ML |
919 | /* outside interface: transmit */ |
920 | static int ene_transmit(void *data, int *buf, u32 n) | |
921 | { | |
922 | struct ene_device *dev = (struct ene_device *)data; | |
923 | unsigned long flags; | |
924 | ||
925 | dev->tx_buffer = buf; | |
9ea53b74 ML |
926 | dev->tx_len = n / sizeof(int); |
927 | dev->tx_pos = 0; | |
928 | dev->tx_reg = 0; | |
929 | dev->tx_done = 0; | |
930 | dev->tx_sample = 0; | |
931 | dev->tx_sample_pulse = 0; | |
932 | ||
11b64d31 | 933 | dbg("TX: %d samples", dev->tx_len); |
9ea53b74 ML |
934 | |
935 | spin_lock_irqsave(&dev->hw_lock, flags); | |
936 | ||
9ea53b74 ML |
937 | ene_tx_prepare(dev); |
938 | ||
939 | /* Transmit first two samples */ | |
940 | ene_tx_sample(dev); | |
941 | ene_tx_sample(dev); | |
942 | ||
943 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
944 | ||
945 | if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) { | |
11b64d31 | 946 | dbg("TX: timeout"); |
9ea53b74 ML |
947 | spin_lock_irqsave(&dev->hw_lock, flags); |
948 | ene_tx_complete(dev); | |
949 | spin_unlock_irqrestore(&dev->hw_lock, flags); | |
950 | } else | |
11b64d31 | 951 | dbg("TX: done"); |
9ea53b74 ML |
952 | return n; |
953 | } | |
954 | ||
931e39a1 ML |
955 | /* probe entry */ |
956 | static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id) | |
9ea53b74 | 957 | { |
9ea53b74 | 958 | int error = -ENOMEM; |
931e39a1 ML |
959 | struct ir_dev_props *ir_props; |
960 | struct input_dev *input_dev; | |
961 | struct ene_device *dev; | |
9ea53b74 | 962 | |
931e39a1 ML |
963 | /* allocate memory */ |
964 | input_dev = input_allocate_device(); | |
965 | ir_props = kzalloc(sizeof(struct ir_dev_props), GFP_KERNEL); | |
9ea53b74 ML |
966 | dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL); |
967 | ||
931e39a1 ML |
968 | if (!input_dev || !ir_props || !dev) |
969 | goto error; | |
9ea53b74 ML |
970 | |
971 | /* validate resources */ | |
931e39a1 ML |
972 | error = -ENODEV; |
973 | ||
9ea53b74 | 974 | if (!pnp_port_valid(pnp_dev, 0) || |
11b64d31 | 975 | pnp_port_len(pnp_dev, 0) < ENE_IO_SIZE) |
931e39a1 | 976 | goto error; |
9ea53b74 ML |
977 | |
978 | if (!pnp_irq_valid(pnp_dev, 0)) | |
931e39a1 | 979 | goto error; |
9ea53b74 | 980 | |
9ea53b74 ML |
981 | spin_lock_init(&dev->hw_lock); |
982 | ||
983 | /* claim the resources */ | |
984 | error = -EBUSY; | |
11b64d31 ML |
985 | dev->hw_io = pnp_port_start(pnp_dev, 0); |
986 | if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) { | |
987 | dev->hw_io = -1; | |
988 | dev->irq = -1; | |
931e39a1 | 989 | goto error; |
11b64d31 | 990 | } |
9ea53b74 | 991 | |
11b64d31 | 992 | dev->irq = pnp_irq(pnp_dev, 0); |
9ea53b74 | 993 | if (request_irq(dev->irq, ene_isr, |
11b64d31 ML |
994 | IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) { |
995 | dev->irq = -1; | |
931e39a1 | 996 | goto error; |
11b64d31 | 997 | } |
931e39a1 ML |
998 | |
999 | pnp_set_drvdata(pnp_dev, dev); | |
1000 | dev->pnp_dev = pnp_dev; | |
9ea53b74 | 1001 | |
11b64d31 ML |
1002 | /* don't allow too short/long sample periods */ |
1003 | if (sample_period < 5 || sample_period > 0x7F) | |
1004 | sample_period = ENE_DEFAULT_SAMPLE_PERIOD; | |
1005 | ||
9ea53b74 ML |
1006 | /* detect hardware version and features */ |
1007 | error = ene_hw_detect(dev); | |
1008 | if (error) | |
931e39a1 | 1009 | goto error; |
9ea53b74 | 1010 | |
9ea53b74 | 1011 | if (!dev->hw_learning_and_tx_capable && txsim) { |
11b64d31 | 1012 | dev->hw_learning_and_tx_capable = true; |
9ea53b74 ML |
1013 | setup_timer(&dev->tx_sim_timer, ene_tx_irqsim, |
1014 | (long unsigned int)dev); | |
11b64d31 | 1015 | ene_warn("Simulation of TX activated"); |
9ea53b74 ML |
1016 | } |
1017 | ||
931e39a1 ML |
1018 | ir_props->driver_type = RC_DRIVER_IR_RAW; |
1019 | ir_props->allowed_protos = IR_TYPE_ALL; | |
1020 | ir_props->priv = dev; | |
1021 | ir_props->open = ene_open; | |
1022 | ir_props->close = ene_close; | |
11b64d31 | 1023 | ir_props->s_idle = ene_rx_set_idle; |
9ea53b74 | 1024 | |
931e39a1 ML |
1025 | dev->props = ir_props; |
1026 | dev->idev = input_dev; | |
9ea53b74 | 1027 | |
931e39a1 | 1028 | if (dev->hw_learning_and_tx_capable) { |
931e39a1 | 1029 | ir_props->s_learning_mode = ene_set_learning_mode; |
931e39a1 ML |
1030 | init_completion(&dev->tx_complete); |
1031 | ir_props->tx_ir = ene_transmit; | |
1032 | ir_props->s_tx_mask = ene_set_tx_mask; | |
1033 | ir_props->s_tx_carrier = ene_set_tx_carrier; | |
11b64d31 | 1034 | ir_props->s_tx_duty_cycle = ene_set_tx_duty_cycle; |
931e39a1 ML |
1035 | /* ir_props->s_carrier_report = ene_set_carrier_report; */ |
1036 | } | |
1037 | ||
11b64d31 ML |
1038 | ene_setup_hw_buffer(dev); |
1039 | ene_setup_settings(dev); | |
1040 | ene_rx_setup(dev); | |
931e39a1 | 1041 | |
11b64d31 ML |
1042 | device_set_wakeup_capable(&pnp_dev->dev, true); |
1043 | device_set_wakeup_enable(&pnp_dev->dev, true); | |
9ea53b74 | 1044 | |
931e39a1 ML |
1045 | if (dev->hw_learning_and_tx_capable) |
1046 | input_dev->name = "ENE eHome Infrared Remote Transceiver"; | |
1047 | else | |
1048 | input_dev->name = "ENE eHome Infrared Remote Receiver"; | |
1049 | ||
9ea53b74 | 1050 | error = -ENODEV; |
931e39a1 ML |
1051 | if (ir_input_register(input_dev, RC_MAP_RC6_MCE, ir_props, |
1052 | ENE_DRIVER_NAME)) | |
1053 | goto error; | |
1054 | ||
11b64d31 | 1055 | ene_notice("driver has been succesfully loaded"); |
9ea53b74 | 1056 | return 0; |
931e39a1 | 1057 | error: |
11b64d31 | 1058 | if (dev && dev->irq >= 0) |
931e39a1 | 1059 | free_irq(dev->irq, dev); |
11b64d31 ML |
1060 | if (dev && dev->hw_io >= 0) |
1061 | release_region(dev->hw_io, ENE_IO_SIZE); | |
931e39a1 ML |
1062 | |
1063 | input_free_device(input_dev); | |
1064 | kfree(ir_props); | |
9ea53b74 | 1065 | kfree(dev); |
9ea53b74 ML |
1066 | return error; |
1067 | } | |
1068 | ||
1069 | /* main unload function */ | |
1070 | static void ene_remove(struct pnp_dev *pnp_dev) | |
1071 | { | |
1072 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
1073 | unsigned long flags; | |
1074 | ||
1075 | spin_lock_irqsave(&dev->hw_lock, flags); | |
1076 | ene_rx_disable(dev); | |
11b64d31 | 1077 | ene_restore_extra_buffer(dev); |
9ea53b74 ML |
1078 | spin_unlock_irqrestore(&dev->hw_lock, flags); |
1079 | ||
1080 | free_irq(dev->irq, dev); | |
11b64d31 | 1081 | release_region(dev->hw_io, ENE_IO_SIZE); |
931e39a1 ML |
1082 | ir_input_unregister(dev->idev); |
1083 | kfree(dev->props); | |
9ea53b74 ML |
1084 | kfree(dev); |
1085 | } | |
1086 | ||
1087 | /* enable wake on IR (wakes on specific button on original remote) */ | |
1088 | static void ene_enable_wake(struct ene_device *dev, int enable) | |
1089 | { | |
1090 | enable = enable && device_may_wakeup(&dev->pnp_dev->dev); | |
11b64d31 ML |
1091 | dbg("wake on IR %s", enable ? "enabled" : "disabled"); |
1092 | ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable); | |
9ea53b74 ML |
1093 | } |
1094 | ||
1095 | #ifdef CONFIG_PM | |
1096 | static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state) | |
1097 | { | |
1098 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
11b64d31 ML |
1099 | ene_enable_wake(dev, true); |
1100 | ||
1101 | /* TODO: add support for wake pattern */ | |
9ea53b74 ML |
1102 | return 0; |
1103 | } | |
1104 | ||
1105 | static int ene_resume(struct pnp_dev *pnp_dev) | |
1106 | { | |
1107 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
11b64d31 ML |
1108 | if (dev->rx_enabled) { |
1109 | ene_rx_setup(dev); | |
9ea53b74 | 1110 | ene_rx_enable(dev); |
11b64d31 ML |
1111 | } |
1112 | ene_enable_wake(dev, false); | |
9ea53b74 ML |
1113 | return 0; |
1114 | } | |
1115 | #endif | |
1116 | ||
1117 | static void ene_shutdown(struct pnp_dev *pnp_dev) | |
1118 | { | |
1119 | struct ene_device *dev = pnp_get_drvdata(pnp_dev); | |
11b64d31 | 1120 | ene_enable_wake(dev, true); |
9ea53b74 ML |
1121 | } |
1122 | ||
1123 | static const struct pnp_device_id ene_ids[] = { | |
1124 | {.id = "ENE0100",}, | |
1125 | {.id = "ENE0200",}, | |
1126 | {.id = "ENE0201",}, | |
931e39a1 | 1127 | {.id = "ENE0202",}, |
9ea53b74 ML |
1128 | {}, |
1129 | }; | |
1130 | ||
1131 | static struct pnp_driver ene_driver = { | |
1132 | .name = ENE_DRIVER_NAME, | |
1133 | .id_table = ene_ids, | |
1134 | .flags = PNP_DRIVER_RES_DO_NOT_CHANGE, | |
1135 | ||
1136 | .probe = ene_probe, | |
1137 | .remove = __devexit_p(ene_remove), | |
1138 | #ifdef CONFIG_PM | |
1139 | .suspend = ene_suspend, | |
1140 | .resume = ene_resume, | |
1141 | #endif | |
1142 | .shutdown = ene_shutdown, | |
1143 | }; | |
1144 | ||
1145 | static int __init ene_init(void) | |
1146 | { | |
1147 | return pnp_register_driver(&ene_driver); | |
1148 | } | |
1149 | ||
1150 | static void ene_exit(void) | |
1151 | { | |
1152 | pnp_unregister_driver(&ene_driver); | |
1153 | } | |
1154 | ||
1155 | module_param(sample_period, int, S_IRUGO); | |
1156 | MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)"); | |
1157 | ||
11b64d31 ML |
1158 | module_param(learning_mode, bool, S_IRUGO); |
1159 | MODULE_PARM_DESC(learning_mode, "Enable learning mode by default"); | |
9ea53b74 ML |
1160 | |
1161 | module_param(debug, int, S_IRUGO | S_IWUSR); | |
11b64d31 | 1162 | MODULE_PARM_DESC(debug, "Debug level"); |
9ea53b74 ML |
1163 | |
1164 | module_param(txsim, bool, S_IRUGO); | |
1165 | MODULE_PARM_DESC(txsim, | |
1166 | "Simulate TX features on unsupported hardware (dangerous)"); | |
1167 | ||
9ea53b74 ML |
1168 | MODULE_DEVICE_TABLE(pnp, ene_ids); |
1169 | MODULE_DESCRIPTION | |
11b64d31 ML |
1170 | ("Infrared input driver for KB3926B/C/D/E/F " |
1171 | "(aka ENE0100/ENE0200/ENE0201/ENE0202) CIR port"); | |
9ea53b74 ML |
1172 | |
1173 | MODULE_AUTHOR("Maxim Levitsky"); | |
1174 | MODULE_LICENSE("GPL"); | |
1175 | ||
1176 | module_init(ene_init); | |
1177 | module_exit(ene_exit); |