[mirror_ubuntu-bionic-kernel.git] / drivers / media / IR / ene_ir.h

/*
 * driver for ENE KB3926 B/C/D CIR (also known as ENE0100/ENE0200/ENE0201)
 *
 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of the
 * License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
 * USA
 */
#include <linux/spinlock.h>
#include <media/lirc.h>
#include <media/lirc_dev.h>

/* hardware address */
#define ENE_STATUS		0	/* hardware status - unused */
#define ENE_ADDR_HI		1	/* hi byte of register address */
#define ENE_ADDR_LO		2	/* low byte of register address */
#define ENE_IO			3	/* read/write window */
#define ENE_MAX_IO		4

/* 8 bytes of samples, divided in 2 halfs*/
#define ENE_SAMPLE_BUFFER	0xF8F0	/* regular sample buffer */
#define ENE_SAMPLE_SPC_MASK	0x80	/* sample is space */
#define ENE_SAMPLE_VALUE_MASK	0x7F
#define ENE_SAMPLE_OVERFLOW	0x7F
#define ENE_SAMPLES_SIZE	4

/* fan input sample buffer */
#define ENE_SAMPLE_BUFFER_FAN	0xF8FB	/* this buffer holds high byte of */
					/* each sample of normal buffer */
#define ENE_FAN_SMPL_PULS_MSK	0x8000	/* this bit of combined sample */
					/* if set, says that sample is pulse */
#define ENE_FAN_VALUE_MASK	0x0FFF  /* mask for valid bits of the value */

/* first firmware register */
#define ENE_FW1			0xF8F8
#define	ENE_FW1_ENABLE		0x01	/* enable fw processing */
#define ENE_FW1_TXIRQ		0x02	/* TX interrupt pending */
#define ENE_FW1_WAKE		0x40	/* enable wake from S3 */
#define ENE_FW1_IRQ		0x80	/* enable interrupt */

/* second firmware register */
#define ENE_FW2			0xF8F9
#define ENE_FW2_BUF_HIGH	0x01	/* which half of the buffer to read */
#define ENE_FW2_IRQ_CLR		0x04	/* clear this on IRQ */
#define ENE_FW2_GP40_AS_LEARN	0x08	/* normal input is used as */
					/* learning input */
#define ENE_FW2_FAN_AS_NRML_IN	0x40	/* fan is used as normal input */
#define ENE_FW2_LEARNING	0x80	/* hardware supports learning and TX */

/* transmitter ports */
#define ENE_TX_PORT2		0xFC01	/* this enables one or both */
#define ENE_TX_PORT2_EN		0x20	/* TX ports */
#define ENE_TX_PORT1		0xFC08
#define ENE_TX_PORT1_EN		0x02

/* IRQ registers block (for revision B) */
#define ENEB_IRQ		0xFD09	/* IRQ number */
#define ENEB_IRQ_UNK1		0xFD17	/* unknown setting = 1 */
#define ENEB_IRQ_STATUS		0xFD80	/* irq status */
#define ENEB_IRQ_STATUS_IR	0x20	/* IR irq */

/* fan as input settings - only if learning capable */
#define ENE_FAN_AS_IN1		0xFE30  /* fan init reg 1 */
#define ENE_FAN_AS_IN1_EN	0xCD
#define ENE_FAN_AS_IN2		0xFE31  /* fan init reg 2 */
#define ENE_FAN_AS_IN2_EN	0x03
#define ENE_SAMPLE_PERIOD_FAN   61	/* fan input has fixed sample period */

/* IRQ registers block (for revision C,D) */
#define ENEC_IRQ		0xFE9B	/* new irq settings register */
#define ENEC_IRQ_MASK		0x0F	/* irq number mask */
#define ENEC_IRQ_UNK_EN		0x10	/* always enabled */
#define ENEC_IRQ_STATUS		0x20	/* irq status and ACK */

/* CIR block settings */
#define ENE_CIR_CONF1		0xFEC0
#define ENE_CIR_CONF1_TX_CLEAR	0x01	/* clear that on revC */
					/* while transmitting */
#define ENE_CIR_CONF1_RX_ON	0x07	/* normal reciever enabled */
#define ENE_CIR_CONF1_LEARN1	0x08	/* enabled on learning mode */
#define ENE_CIR_CONF1_TX_ON	0x30	/* enabled on transmit */
#define ENE_CIR_CONF1_TX_CARR	0x80	/* send TX carrier or not */

#define ENE_CIR_CONF2		0xFEC1	/* unknown setting = 0 */
#define ENE_CIR_CONF2_LEARN2	0x10	/* set on enable learning */
#define ENE_CIR_CONF2_GPIO40DIS	0x20	/* disable input via gpio40 */

#define ENE_CIR_SAMPLE_PERIOD	0xFEC8	/* sample period in us */
#define ENE_CIR_SAMPLE_OVERFLOW	0x80	/* interrupt on overflows if set */


/* Two byte tx buffer */
#define ENE_TX_INPUT1		0xFEC9
#define ENE_TX_INPUT2		0xFECA
#define ENE_TX_PULSE_MASK	0x80	/* Transmitted sample is pulse */
#define ENE_TX_SMLP_MASK	0x7F
#define ENE_TX_SMPL_PERIOD	50	/* transmit sample period - fixed */


/* Unknown TX setting - TX sample period ??? */
#define ENE_TX_UNK1		0xFECB	/* set to 0x63 */

/* Current recieved carrier period */
#define ENE_RX_CARRIER		0xFECC	/* RX period (500 ns) */
#define ENE_RX_CARRIER_VALID	0x80	/* Register content valid */


/* TX period (1/carrier) */
#define ENE_TX_PERIOD		0xFECE	/* TX period (500 ns) */
#define ENE_TX_PERIOD_UNKBIT	0x80	/* This bit set on transmit*/
#define ENE_TX_PERIOD_PULSE	0xFECF	/* TX pulse period (500 ns)*/

/* Hardware versions */
#define ENE_HW_VERSION		0xFF00	/* hardware revision */
#define ENE_HW_UNK		0xFF1D
#define ENE_HW_UNK_CLR		0x04
#define ENE_HW_VER_MAJOR	0xFF1E	/* chip version */
#define ENE_HW_VER_MINOR	0xFF1F
#define ENE_HW_VER_OLD		0xFD00

/* Normal/Learning carrier ranges - only valid if we have learning input*/
/* TODO: test */
#define ENE_NORMAL_RX_LOW	34
#define ENE_NORMAL_RX_HI	38

/* Tx carrier range */
/* Hardware might be able to do more, but this range is enough for
   all purposes */
#define ENE_TX_PERIOD_MAX	32	/* corresponds to 29.4 kHz */
#define ENE_TX_PERIOD_MIN	16	/* corrsponds to 62.5 kHz */


/* Minimal and maximal gaps */

/* Normal case:
	Minimal gap is 0x7F * sample period
	Maximum gap depends on hardware.
	For KB3926B, it is unlimited, for newer models its around
	250000, after which HW stops sending samples, and that is
	not possible to change */

/* Fan case:
	Both minimal and maximal gaps are same, and equal to 0xFFF * 0x61
	And there is nothing to change this setting
*/

#define ENE_MAXGAP		250000
#define ENE_MINGAP		(127 * sample_period)

/******************************************************************************/

#define ENE_DRIVER_NAME		"enecir"
#define ENE_TXBUF_SIZE (500 * sizeof(int))	/* 500 samples (arbitary) */

#define ENE_IRQ_RX		1
#define ENE_IRQ_TX		2

#define  ENE_HW_B		1	/* 3926B */
#define  ENE_HW_C		2	/* 3926C */
#define  ENE_HW_D		3	/* 3926D */

#define ene_printk(level, text, ...) \
	printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__)

#define ene_dbg(text, ...) \
	if (debug) \
		printk(KERN_DEBUG \
			ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)

#define ene_dbg_verbose(text, ...) \
	if (debug > 1) \
		printk(KERN_DEBUG \
			ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)


struct ene_device {
	struct pnp_dev *pnp_dev;
	struct lirc_driver *lirc_driver;
	int in_use;

	/* hw IO settings */
	unsigned long hw_io;
	int irq;
	spinlock_t hw_lock;

	/* HW features */
	int hw_revision;			/* hardware revision */
	int hw_learning_and_tx_capable;		/* learning capable */
	int hw_gpio40_learning;			/* gpio40 is learning */
	int hw_fan_as_normal_input;		/* fan input is used as */
						/* regular input */
	/* HW state*/
	int rx_pointer;				/* hw pointer to rx buffer */
	int rx_fan_input_inuse;			/* is fan input in use for rx*/
	int tx_reg;				/* current reg used for TX */
	u8  saved_conf1;			/* saved FEC0 reg */
	int learning_enabled;			/* learning input enabled */

	/* RX sample handling */
	int rx_sample;				/* current recieved sample */
	int rx_sample_pulse;			/* recieved sample is pulse */
	int rx_idle;				/* idle mode for RX activated */
	struct timeval rx_gap_start;		/* time of start of idle */
	int rx_timeout;				/* time in ms of RX timeout */
	int rx_send_timeout_packet;		/* do we send RX timeout */
	int rx_timeout_sent;			/* we sent the timeout packet */
	int rx_carrier_sense;			/* sense carrier */

	/* TX sample handling */
	unsigned int tx_sample;			/* current sample for TX */
	int tx_sample_pulse;			/* current sample is pulse */

	/* TX buffer */
	int tx_buffer[ENE_TXBUF_SIZE];		/* input samples buffer*/
	int tx_pos;				/* position in that bufer */
	int tx_len;				/* current len of tx buffer */
	int tx_underway;			/* TX is under way*/
	int tx_done;				/* done transmitting */
						/* one more sample pending*/
	struct completion tx_complete;		/* TX completion */
	struct timer_list tx_sim_timer;

	/*TX settings */
	int tx_period;
	int tx_duty_cycle;
	int transmitter_mask;
};
Commit	Line	Data
9ea53b74 ML	1	/*
	2	* driver for ENE KB3926 B/C/D CIR (also known as ENE0100/ENE0200/ENE0201)
	3	*
	4	* Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation; either version 2 of the
	9	* License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful, but
	12	* WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
	19	* USA
	20	*/
	21	#include <linux/spinlock.h>
	22	#include <media/lirc.h>
	23	#include <media/lirc_dev.h>
	24
	25	/* hardware address */
	26	#define ENE_STATUS 0 /* hardware status - unused */
	27	#define ENE_ADDR_HI 1 /* hi byte of register address */
	28	#define ENE_ADDR_LO 2 /* low byte of register address */
	29	#define ENE_IO 3 /* read/write window */
	30	#define ENE_MAX_IO 4
	31
	32	/* 8 bytes of samples, divided in 2 halfs*/
	33	#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */
	34	#define ENE_SAMPLE_SPC_MASK 0x80 /* sample is space */
	35	#define ENE_SAMPLE_VALUE_MASK 0x7F
	36	#define ENE_SAMPLE_OVERFLOW 0x7F
	37	#define ENE_SAMPLES_SIZE 4
	38
	39	/* fan input sample buffer */
	40	#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */
	41	/* each sample of normal buffer */
	42	#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */
	43	/* if set, says that sample is pulse */
	44	#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */
	45
	46	/* first firmware register */
	47	#define ENE_FW1 0xF8F8
	48	#define ENE_FW1_ENABLE 0x01 /* enable fw processing */
	49	#define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
	50	#define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
	51	#define ENE_FW1_IRQ 0x80 /* enable interrupt */
	52
	53	/* second firmware register */
	54	#define ENE_FW2 0xF8F9
	55	#define ENE_FW2_BUF_HIGH 0x01 /* which half of the buffer to read */
	56	#define ENE_FW2_IRQ_CLR 0x04 /* clear this on IRQ */
	57	#define ENE_FW2_GP40_AS_LEARN 0x08 /* normal input is used as */
	58	/* learning input */
	59	#define ENE_FW2_FAN_AS_NRML_IN 0x40 /* fan is used as normal input */
	60	#define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
	61
	62	/* transmitter ports */
	63	#define ENE_TX_PORT2 0xFC01 /* this enables one or both */
	64	#define ENE_TX_PORT2_EN 0x20 /* TX ports */
65	#define ENE_TX_PORT1 0xFC08
66	#define ENE_TX_PORT1_EN 0x02
67
68	/* IRQ registers block (for revision B) */
69	#define ENEB_IRQ 0xFD09 /* IRQ number */
70	#define ENEB_IRQ_UNK1 0xFD17 /* unknown setting = 1 */
71	#define ENEB_IRQ_STATUS 0xFD80 /* irq status */
72	#define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
73
74	/* fan as input settings - only if learning capable */
75	#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
76	#define ENE_FAN_AS_IN1_EN 0xCD
77	#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
78	#define ENE_FAN_AS_IN2_EN 0x03
79	#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
80
81	/* IRQ registers block (for revision C,D) */
82	#define ENEC_IRQ 0xFE9B /* new irq settings register */
83	#define ENEC_IRQ_MASK 0x0F /* irq number mask */
84	#define ENEC_IRQ_UNK_EN 0x10 /* always enabled */
85	#define ENEC_IRQ_STATUS 0x20 /* irq status and ACK */
86
87	/* CIR block settings */
88	#define ENE_CIR_CONF1 0xFEC0
89	#define ENE_CIR_CONF1_TX_CLEAR 0x01 /* clear that on revC */
90	/* while transmitting */
91	#define ENE_CIR_CONF1_RX_ON 0x07 /* normal reciever enabled */
92	#define ENE_CIR_CONF1_LEARN1 0x08 /* enabled on learning mode */
93	#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */
94	#define ENE_CIR_CONF1_TX_CARR 0x80 /* send TX carrier or not */
95
96	#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */
97	#define ENE_CIR_CONF2_LEARN2 0x10 /* set on enable learning */
98	#define ENE_CIR_CONF2_GPIO40DIS 0x20 /* disable input via gpio40 */
99
100	#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */
101	#define ENE_CIR_SAMPLE_OVERFLOW 0x80 /* interrupt on overflows if set */
102
103
104	/* Two byte tx buffer */
105	#define ENE_TX_INPUT1 0xFEC9
106	#define ENE_TX_INPUT2 0xFECA
107	#define ENE_TX_PULSE_MASK 0x80 /* Transmitted sample is pulse */
108	#define ENE_TX_SMLP_MASK 0x7F
109	#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period - fixed */
110
111
112	/* Unknown TX setting - TX sample period ??? */
113	#define ENE_TX_UNK1 0xFECB /* set to 0x63 */
114
115	/* Current recieved carrier period */
116	#define ENE_RX_CARRIER 0xFECC /* RX period (500 ns) */
117	#define ENE_RX_CARRIER_VALID 0x80 /* Register content valid */
118
119
120	/* TX period (1/carrier) */
121	#define ENE_TX_PERIOD 0xFECE /* TX period (500 ns) */
122	#define ENE_TX_PERIOD_UNKBIT 0x80 /* This bit set on transmit*/
123	#define ENE_TX_PERIOD_PULSE 0xFECF /* TX pulse period (500 ns)*/
124
125	/* Hardware versions */
126	#define ENE_HW_VERSION 0xFF00 /* hardware revision */
127	#define ENE_HW_UNK 0xFF1D
128	#define ENE_HW_UNK_CLR 0x04
129	#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */
130	#define ENE_HW_VER_MINOR 0xFF1F
131	#define ENE_HW_VER_OLD 0xFD00
132
133	/* Normal/Learning carrier ranges - only valid if we have learning input*/
134	/* TODO: test */
135	#define ENE_NORMAL_RX_LOW 34
136	#define ENE_NORMAL_RX_HI 38
137
138	/* Tx carrier range */
139	/* Hardware might be able to do more, but this range is enough for
140	all purposes */
141	#define ENE_TX_PERIOD_MAX 32 /* corresponds to 29.4 kHz */
142	#define ENE_TX_PERIOD_MIN 16 /* corrsponds to 62.5 kHz */
143
144
145
146	/* Minimal and maximal gaps */
147
148	/* Normal case:
149	Minimal gap is 0x7F * sample period
150	Maximum gap depends on hardware.
151	For KB3926B, it is unlimited, for newer models its around
152	250000, after which HW stops sending samples, and that is
153	not possible to change */
154
155	/* Fan case:
156	Both minimal and maximal gaps are same, and equal to 0xFFF * 0x61
157	And there is nothing to change this setting
158	*/
159
160	#define ENE_MAXGAP 250000
161	#define ENE_MINGAP (127 * sample_period)
162
163	/******************************************************************************/
164
165	#define ENE_DRIVER_NAME "enecir"
166	#define ENE_TXBUF_SIZE (500 * sizeof(int)) /* 500 samples (arbitary) */
167
168	#define ENE_IRQ_RX 1
169	#define ENE_IRQ_TX 2
170
171	#define ENE_HW_B 1 /* 3926B */
172	#define ENE_HW_C 2 /* 3926C */
173	#define ENE_HW_D 3 /* 3926D */
174
175	#define ene_printk(level, text, ...) \
176	printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__)
177
178	#define ene_dbg(text, ...) \
179	if (debug) \
180	printk(KERN_DEBUG \
181	ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
182
183	#define ene_dbg_verbose(text, ...) \
184	if (debug > 1) \
185	printk(KERN_DEBUG \
186	ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
187
188
189	struct ene_device {
190	struct pnp_dev *pnp_dev;
191	struct lirc_driver *lirc_driver;
192	int in_use;
193
194	/* hw IO settings */
195	unsigned long hw_io;
196	int irq;
197	spinlock_t hw_lock;
198
199	/* HW features */
200	int hw_revision; /* hardware revision */
201	int hw_learning_and_tx_capable; /* learning capable */
202	int hw_gpio40_learning; /* gpio40 is learning */
203	int hw_fan_as_normal_input; /* fan input is used as */
204	/* regular input */
205	/* HW state*/
206	int rx_pointer; /* hw pointer to rx buffer */
207	int rx_fan_input_inuse; /* is fan input in use for rx*/
208	int tx_reg; /* current reg used for TX */
209	u8 saved_conf1; /* saved FEC0 reg */
210	int learning_enabled; /* learning input enabled */
211
212	/* RX sample handling */
213	int rx_sample; /* current recieved sample */
214	int rx_sample_pulse; /* recieved sample is pulse */
215	int rx_idle; /* idle mode for RX activated */
216	struct timeval rx_gap_start; /* time of start of idle */
217	int rx_timeout; /* time in ms of RX timeout */
218	int rx_send_timeout_packet; /* do we send RX timeout */
219	int rx_timeout_sent; /* we sent the timeout packet */
220	int rx_carrier_sense; /* sense carrier */
221
222	/* TX sample handling */
223	unsigned int tx_sample; /* current sample for TX */
224	int tx_sample_pulse; /* current sample is pulse */
225
226	/* TX buffer */
227	int tx_buffer[ENE_TXBUF_SIZE]; /* input samples buffer*/
228	int tx_pos; /* position in that bufer */
229	int tx_len; /* current len of tx buffer */
230	int tx_underway; /* TX is under way*/
231	int tx_done; /* done transmitting */
232	/* one more sample pending*/
233	struct completion tx_complete; /* TX completion */
234	struct timer_list tx_sim_timer;
235
236	/TX settings /
237	int tx_period;
238	int tx_duty_cycle;
239	int transmitter_mask;
240	};