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V4L/DVB(7871): mxl5005s: Re-org code and update copyrights
[mirror_ubuntu-artful-kernel.git] / drivers / media / common / tuners / mxl5005s.c
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52c99bda 1/*
48937295
ST		 2 MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
3
4 Copyright (C) 2008 MaxLinear
5 Copyright (C) 2006 Steven Toth <stoth@hauppauge.com>
6 Functions:
7 mxl5005s_reset()
8 mxl5005s_writereg()
9 mxl5005s_writeregs()
10 mxl5005s_init()
11 mxl5005s_reconfigure()
12 mxl5005s_AssignTunerMode()
13 mxl5005s_set_params()
14 mxl5005s_get_frequency()
15 mxl5005s_get_bandwidth()
16 mxl5005s_release()
17 mxl5005s_attach()
18
19 Copyright (c) 2008 Realtek
20 Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
21 Functions:
22 mxl5005s_SetRfFreqHz()
23
24 This program is free software; you can redistribute it and/or modify
25 it under the terms of the GNU General Public License as published by
26 the Free Software Foundation; either version 2 of the License, or
27 (at your option) any later version.
28
29 This program is distributed in the hope that it will be useful,
30 but WITHOUT ANY WARRANTY; without even the implied warranty of
31 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 GNU General Public License for more details.
33
34 You should have received a copy of the GNU General Public License
35 along with this program; if not, write to the Free Software
36 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
37
38*/
39
40/*
41 History of this driver (Steven Toth):
42 I was given a public release of a linux driver that included
43 support for the MaxLinear MXL5005S silicon tuner. Analysis of
44 the tuner driver showed clearly three things.
52c99bda 45
48937295
ST		 46 1. The tuner driver didn't support the LinuxTV tuner API
47 so the code Realtek added had to be removed.
48
49 2. A significant amount of the driver is reference driver code
50 from MaxLinear, I felt it was important to identify and
51 preserve this.
52
53 3. New code has to be added to interface correctly with the
54 LinuxTV API, as a regular kernel module.
55
56 Other than the reference driver enum's, I've clearly marked
57 sections of the code and retained the copyright of the
58 respective owners.
59*/
5c1b2051
ST		 60#include <linux/kernel.h>
61#include <linux/init.h>
62#include <linux/module.h>
63#include <linux/string.h>
64#include <linux/slab.h>
65#include <linux/delay.h>
66#include "dvb_frontend.h"
2637d5b4 67#include "mxl5005s.h"
52c99bda 68
48937295 69static int debug = 2;
85d220d0
ST		 70
71#define dprintk(level, arg...) do { \
48937295 72 if (level <= debug) \
85d220d0
ST		 73 printk(arg); \
74 } while (0)
75
76#define TUNER_REGS_NUM 104
77#define INITCTRL_NUM 40
78
79#ifdef _MXL_PRODUCTION
80#define CHCTRL_NUM 39
81#else
82#define CHCTRL_NUM 36
83#endif
84
85#define MXLCTRL_NUM 189
86#define MASTER_CONTROL_ADDR 9
87
85d220d0
ST		 88/* Enumeration of Master Control Register State */
89typedef enum
90{
91 MC_LOAD_START = 1,
92 MC_POWER_DOWN,
93 MC_SYNTH_RESET,
94 MC_SEQ_OFF
95} Master_Control_State;
96
85d220d0
ST		 97/* Enumeration of MXL5005 Tuner Modulation Type */
98typedef enum
99{
100 MXL_DEFAULT_MODULATION = 0,
101 MXL_DVBT,
102 MXL_ATSC,
103 MXL_QAM,
104 MXL_ANALOG_CABLE,
105 MXL_ANALOG_OTA
106} Tuner_Modu_Type;
107
85d220d0
ST		 108/* MXL5005 Tuner Register Struct */
109typedef struct _TunerReg_struct
110{
111 u16 Reg_Num; /* Tuner Register Address */
112 u16 Reg_Val; /* Current sofware programmed value waiting to be writen */
113} TunerReg_struct;
114
115typedef enum
116{
117 /* Initialization Control Names */
118 DN_IQTN_AMP_CUT = 1, /* 1 */
119 BB_MODE, /* 2 */
120 BB_BUF, /* 3 */
121 BB_BUF_OA, /* 4 */
122 BB_ALPF_BANDSELECT, /* 5 */
123 BB_IQSWAP, /* 6 */
124 BB_DLPF_BANDSEL, /* 7 */
125 RFSYN_CHP_GAIN, /* 8 */
126 RFSYN_EN_CHP_HIGAIN, /* 9 */
127 AGC_IF, /* 10 */
128 AGC_RF, /* 11 */
129 IF_DIVVAL, /* 12 */
130 IF_VCO_BIAS, /* 13 */
131 CHCAL_INT_MOD_IF, /* 14 */
132 CHCAL_FRAC_MOD_IF, /* 15 */
133 DRV_RES_SEL, /* 16 */
134 I_DRIVER, /* 17 */
135 EN_AAF, /* 18 */
136 EN_3P, /* 19 */
137 EN_AUX_3P, /* 20 */
138 SEL_AAF_BAND, /* 21 */
139 SEQ_ENCLK16_CLK_OUT, /* 22 */
140 SEQ_SEL4_16B, /* 23 */
141 XTAL_CAPSELECT, /* 24 */
142 IF_SEL_DBL, /* 25 */
143 RFSYN_R_DIV, /* 26 */
144 SEQ_EXTSYNTHCALIF, /* 27 */
145 SEQ_EXTDCCAL, /* 28 */
146 AGC_EN_RSSI, /* 29 */
147 RFA_ENCLKRFAGC, /* 30 */
148 RFA_RSSI_REFH, /* 31 */
149 RFA_RSSI_REF, /* 32 */
150 RFA_RSSI_REFL, /* 33 */
151 RFA_FLR, /* 34 */
152 RFA_CEIL, /* 35 */
153 SEQ_EXTIQFSMPULSE, /* 36 */
154 OVERRIDE_1, /* 37 */
155 BB_INITSTATE_DLPF_TUNE, /* 38 */
156 TG_R_DIV, /* 39 */
157 EN_CHP_LIN_B, /* 40 */
158
159 /* Channel Change Control Names */
160 DN_POLY = 51, /* 51 */
161 DN_RFGAIN, /* 52 */
162 DN_CAP_RFLPF, /* 53 */
163 DN_EN_VHFUHFBAR, /* 54 */
164 DN_GAIN_ADJUST, /* 55 */
165 DN_IQTNBUF_AMP, /* 56 */
166 DN_IQTNGNBFBIAS_BST, /* 57 */
167 RFSYN_EN_OUTMUX, /* 58 */
168 RFSYN_SEL_VCO_OUT, /* 59 */
169 RFSYN_SEL_VCO_HI, /* 60 */
170 RFSYN_SEL_DIVM, /* 61 */
171 RFSYN_RF_DIV_BIAS, /* 62 */
172 DN_SEL_FREQ, /* 63 */
173 RFSYN_VCO_BIAS, /* 64 */
174 CHCAL_INT_MOD_RF, /* 65 */
175 CHCAL_FRAC_MOD_RF, /* 66 */
176 RFSYN_LPF_R, /* 67 */
177 CHCAL_EN_INT_RF, /* 68 */
178 TG_LO_DIVVAL, /* 69 */
179 TG_LO_SELVAL, /* 70 */
180 TG_DIV_VAL, /* 71 */
181 TG_VCO_BIAS, /* 72 */
182 SEQ_EXTPOWERUP, /* 73 */
183 OVERRIDE_2, /* 74 */
184 OVERRIDE_3, /* 75 */
185 OVERRIDE_4, /* 76 */
186 SEQ_FSM_PULSE, /* 77 */
187 GPIO_4B, /* 78 */
188 GPIO_3B, /* 79 */
189 GPIO_4, /* 80 */
190 GPIO_3, /* 81 */
191 GPIO_1B, /* 82 */
192 DAC_A_ENABLE, /* 83 */
193 DAC_B_ENABLE, /* 84 */
194 DAC_DIN_A, /* 85 */
195 DAC_DIN_B, /* 86 */
196#ifdef _MXL_PRODUCTION
197 RFSYN_EN_DIV, /* 87 */
198 RFSYN_DIVM, /* 88 */
199 DN_BYPASS_AGC_I2C /* 89 */
200#endif
201} MXL5005_ControlName;
202
203/*
204 * The following context is source code provided by MaxLinear.
205 * MaxLinear source code - Common_MXL.h (?)
206 */
207
208/* Constants */
209#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
210#define MXL5005S_LATCH_BYTE 0xfe
211
212/* Register address, MSB, and LSB */
213#define MXL5005S_BB_IQSWAP_ADDR 59
214#define MXL5005S_BB_IQSWAP_MSB 0
215#define MXL5005S_BB_IQSWAP_LSB 0
216
217#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
218#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
219#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
220
221/* Standard modes */
222enum
223{
224 MXL5005S_STANDARD_DVBT,
225 MXL5005S_STANDARD_ATSC,
226};
227#define MXL5005S_STANDARD_MODE_NUM 2
228
229/* Bandwidth modes */
230enum
231{
232 MXL5005S_BANDWIDTH_6MHZ = 6000000,
233 MXL5005S_BANDWIDTH_7MHZ = 7000000,
234 MXL5005S_BANDWIDTH_8MHZ = 8000000,
235};
236#define MXL5005S_BANDWIDTH_MODE_NUM 3
237
3935c254
ST		 238/* MXL5005 Tuner Control Struct */
239typedef struct _TunerControl_struct {
240 u16 Ctrl_Num; /* Control Number */
241 u16 size; /* Number of bits to represent Value */
242 u16 addr[25]; /* Array of Tuner Register Address for each bit position */
243 u16 bit[25]; /* Array of bit position in Register Address for each bit position */
244 u16 val[25]; /* Binary representation of Value */
245} TunerControl_struct;
246
247/* MXL5005 Tuner Struct */
248struct mxl5005s_state
52c99bda 249{
3935c254
ST		 250 u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
251 u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
252 u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
253 u32 IF_OUT; /* Desired IF Out Frequency */
254 u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
255 u32 RF_IN; /* RF Input Frequency */
256 u32 Fxtal; /* XTAL Frequency */
257 u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
258 u16 TOP; /* Value: take over point */
259 u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */
260 u8 DIV_OUT; /* 4MHz or 16MHz */
261 u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
262 u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
263 u8 Mod_Type; /* Modulation Type; */
264 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
265 u8 TF_Type; /* Tracking Filter Type */
266 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
267
268 /* Calculated Settings */
269 u32 RF_LO; /* Synth RF LO Frequency */
270 u32 IF_LO; /* Synth IF LO Frequency */
271 u32 TG_LO; /* Synth TG_LO Frequency */
272
273 /* Pointers to ControlName Arrays */
274 u16 Init_Ctrl_Num; /* Number of INIT Control Names */
275 TunerControl_struct
276 Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
277
278 u16 CH_Ctrl_Num; /* Number of CH Control Names */
279 TunerControl_struct
280 CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
281
282 u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
283 TunerControl_struct
284 MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
285
286 /* Pointer to Tuner Register Array */
287 u16 TunerRegs_Num; /* Number of Tuner Registers */
288 TunerReg_struct
289 TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
52c99bda 290
85d220d0 291 /* Linux driver framework specific */
48937295 292 struct mxl5005s_config *config;
85d220d0
ST		 293 struct dvb_frontend *frontend;
294 struct i2c_adapter *i2c;
48937295
ST		 295
296 /* Cache values */
297 u32 current_mode;
298
85d220d0 299};
52c99bda 300
85d220d0
ST		 301u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value);
302u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value);
303u16 MXL_GetMasterControl(u8 *MasterReg, int state);
304void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal);
305u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
306u32 MXL_Ceiling(u32 value, u32 resolution);
307u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal);
308u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal);
309u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup);
310u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val);
311u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count);
312u32 MXL_GetXtalInt(u32 Xtal_Freq);
313u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq);
314void MXL_SynthIFLO_Calc(struct dvb_frontend *fe);
315void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe);
316u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count);
48937295 317int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len);
85d220d0 318u16 MXL_IFSynthInit(struct dvb_frontend *fe);
48937295
ST		 319int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth);
320int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth);
321
322/* ----------------------------------------------------------------
323 * Begin: Custom code salvaged from the Realtek driver.
324 * Copyright (c) 2008 Realtek
325 * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
326 * This code is placed under the terms of the GNU General Public License
327 *
328 * Released by Realtek under GPLv2.
329 * Thanks to Realtek for a lot of support we received !
330 *
331 * Revision: 080314 - original version
332 */
85d220d0
ST		 333
334int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz)
52c99bda 335{
85d220d0 336 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda
ST		 337 unsigned char AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
338 unsigned char ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
339 int TableLen;
340
85d220d0 341 u32 IfDivval;
52c99bda
ST		 342 unsigned char MasterControlByte;
343
85d220d0 344 dprintk(1, "%s() freq=%ld\n", __func__, RfFreqHz);
52c99bda
ST		 345
346 // Set MxL5005S tuner RF frequency according to MxL5005S tuner example code.
347
348 // Tuner RF frequency setting stage 0
349 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET) ;
350 AddrTable[0] = MASTER_CONTROL_ADDR;
85d220d0 351 ByteTable[0] |= state->config->AgcMasterByte;
52c99bda 352
48937295 353 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
52c99bda
ST		 354
355 // Tuner RF frequency setting stage 1
85d220d0 356 MXL_TuneRF(fe, RfFreqHz);
52c99bda 357
85d220d0 358 MXL_ControlRead(fe, IF_DIVVAL, &IfDivval);
52c99bda 359
85d220d0
ST		 360 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 0);
361 MXL_ControlWrite(fe, SEQ_EXTPOWERUP, 1);
362 MXL_ControlWrite(fe, IF_DIVVAL, 8);
363 MXL_GetCHRegister(fe, AddrTable, ByteTable, &TableLen) ;
52c99bda
ST		 364
365 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
366 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
48937295 367 ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte;
52c99bda
ST		 368 TableLen += 1;
369
48937295 370 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
52c99bda
ST		 371
372 // Wait 30 ms.
48937295 373 msleep(150);
52c99bda
ST		 374
375 // Tuner RF frequency setting stage 2
85d220d0
ST		 376 MXL_ControlWrite(fe, SEQ_FSM_PULSE, 1) ;
377 MXL_ControlWrite(fe, IF_DIVVAL, IfDivval) ;
378 MXL_GetCHRegister_ZeroIF(fe, AddrTable, ByteTable, &TableLen) ;
52c99bda
ST		 379
380 MXL_GetMasterControl(&MasterControlByte, MC_LOAD_START) ;
381 AddrTable[TableLen] = MASTER_CONTROL_ADDR ;
48937295 382 ByteTable[TableLen] = MasterControlByte | state->config->AgcMasterByte ;
52c99bda
ST		 383 TableLen += 1;
384
48937295 385 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
52c99bda 386
48937295 387 msleep(100);
8c66a19d 388
85d220d0 389 return 0;
52c99bda 390}
48937295 391/* End: Custom code taken from the Realtek driver */
52c99bda 392
48937295
ST		 393/* ----------------------------------------------------------------
394 * Begin: Reference driver code found in the Realtek driver.
395 * Copyright (c) 2008 MaxLinear
396 */
3935c254 397u16 MXL5005_RegisterInit(struct dvb_frontend *fe)
52c99bda 398{
85d220d0 399 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 400 state->TunerRegs_Num = TUNER_REGS_NUM ;
401// state->TunerRegs = (TunerReg_struct *) calloc( TUNER_REGS_NUM, sizeof(TunerReg_struct) ) ;
52c99bda 402
3935c254
ST		 403 state->TunerRegs[0].Reg_Num = 9 ;
404 state->TunerRegs[0].Reg_Val = 0x40 ;
52c99bda 405
3935c254
ST		 406 state->TunerRegs[1].Reg_Num = 11 ;
407 state->TunerRegs[1].Reg_Val = 0x19 ;
52c99bda 408
3935c254
ST		 409 state->TunerRegs[2].Reg_Num = 12 ;
410 state->TunerRegs[2].Reg_Val = 0x60 ;
52c99bda 411
3935c254
ST		 412 state->TunerRegs[3].Reg_Num = 13 ;
413 state->TunerRegs[3].Reg_Val = 0x00 ;
52c99bda 414
3935c254
ST		 415 state->TunerRegs[4].Reg_Num = 14 ;
416 state->TunerRegs[4].Reg_Val = 0x00 ;
52c99bda 417
3935c254
ST		 418 state->TunerRegs[5].Reg_Num = 15 ;
419 state->TunerRegs[5].Reg_Val = 0xC0 ;
52c99bda 420
3935c254
ST		 421 state->TunerRegs[6].Reg_Num = 16 ;
422 state->TunerRegs[6].Reg_Val = 0x00 ;
52c99bda 423
3935c254
ST		 424 state->TunerRegs[7].Reg_Num = 17 ;
425 state->TunerRegs[7].Reg_Val = 0x00 ;
52c99bda 426
3935c254
ST		 427 state->TunerRegs[8].Reg_Num = 18 ;
428 state->TunerRegs[8].Reg_Val = 0x00 ;
52c99bda 429
3935c254
ST		 430 state->TunerRegs[9].Reg_Num = 19 ;
431 state->TunerRegs[9].Reg_Val = 0x34 ;
52c99bda 432
3935c254
ST		 433 state->TunerRegs[10].Reg_Num = 21 ;
434 state->TunerRegs[10].Reg_Val = 0x00 ;
52c99bda 435
3935c254
ST		 436 state->TunerRegs[11].Reg_Num = 22 ;
437 state->TunerRegs[11].Reg_Val = 0x6B ;
52c99bda 438
3935c254
ST		 439 state->TunerRegs[12].Reg_Num = 23 ;
440 state->TunerRegs[12].Reg_Val = 0x35 ;
52c99bda 441
3935c254
ST		 442 state->TunerRegs[13].Reg_Num = 24 ;
443 state->TunerRegs[13].Reg_Val = 0x70 ;
52c99bda 444
3935c254
ST		 445 state->TunerRegs[14].Reg_Num = 25 ;
446 state->TunerRegs[14].Reg_Val = 0x3E ;
52c99bda 447
3935c254
ST		 448 state->TunerRegs[15].Reg_Num = 26 ;
449 state->TunerRegs[15].Reg_Val = 0x82 ;
52c99bda 450
3935c254
ST		 451 state->TunerRegs[16].Reg_Num = 31 ;
452 state->TunerRegs[16].Reg_Val = 0x00 ;
52c99bda 453
3935c254
ST		 454 state->TunerRegs[17].Reg_Num = 32 ;
455 state->TunerRegs[17].Reg_Val = 0x40 ;
52c99bda 456
3935c254
ST		 457 state->TunerRegs[18].Reg_Num = 33 ;
458 state->TunerRegs[18].Reg_Val = 0x53 ;
52c99bda 459
3935c254
ST		 460 state->TunerRegs[19].Reg_Num = 34 ;
461 state->TunerRegs[19].Reg_Val = 0x81 ;
52c99bda 462
3935c254
ST		 463 state->TunerRegs[20].Reg_Num = 35 ;
464 state->TunerRegs[20].Reg_Val = 0xC9 ;
52c99bda 465
3935c254
ST		 466 state->TunerRegs[21].Reg_Num = 36 ;
467 state->TunerRegs[21].Reg_Val = 0x01 ;
52c99bda 468
3935c254
ST		 469 state->TunerRegs[22].Reg_Num = 37 ;
470 state->TunerRegs[22].Reg_Val = 0x00 ;
52c99bda 471
3935c254
ST		 472 state->TunerRegs[23].Reg_Num = 41 ;
473 state->TunerRegs[23].Reg_Val = 0x00 ;
52c99bda 474
3935c254
ST		 475 state->TunerRegs[24].Reg_Num = 42 ;
476 state->TunerRegs[24].Reg_Val = 0xF8 ;
52c99bda 477
3935c254
ST		 478 state->TunerRegs[25].Reg_Num = 43 ;
479 state->TunerRegs[25].Reg_Val = 0x43 ;
52c99bda 480
3935c254
ST		 481 state->TunerRegs[26].Reg_Num = 44 ;
482 state->TunerRegs[26].Reg_Val = 0x20 ;
52c99bda 483
3935c254
ST		 484 state->TunerRegs[27].Reg_Num = 45 ;
485 state->TunerRegs[27].Reg_Val = 0x80 ;
52c99bda 486
3935c254
ST		 487 state->TunerRegs[28].Reg_Num = 46 ;
488 state->TunerRegs[28].Reg_Val = 0x88 ;
52c99bda 489
3935c254
ST		 490 state->TunerRegs[29].Reg_Num = 47 ;
491 state->TunerRegs[29].Reg_Val = 0x86 ;
52c99bda 492
3935c254
ST		 493 state->TunerRegs[30].Reg_Num = 48 ;
494 state->TunerRegs[30].Reg_Val = 0x00 ;
52c99bda 495
3935c254
ST		 496 state->TunerRegs[31].Reg_Num = 49 ;
497 state->TunerRegs[31].Reg_Val = 0x00 ;
52c99bda 498
3935c254
ST		 499 state->TunerRegs[32].Reg_Num = 53 ;
500 state->TunerRegs[32].Reg_Val = 0x94 ;
52c99bda 501
3935c254
ST		 502 state->TunerRegs[33].Reg_Num = 54 ;
503 state->TunerRegs[33].Reg_Val = 0xFA ;
52c99bda 504
3935c254
ST		 505 state->TunerRegs[34].Reg_Num = 55 ;
506 state->TunerRegs[34].Reg_Val = 0x92 ;
52c99bda 507
3935c254
ST		 508 state->TunerRegs[35].Reg_Num = 56 ;
509 state->TunerRegs[35].Reg_Val = 0x80 ;
52c99bda 510
3935c254
ST		 511 state->TunerRegs[36].Reg_Num = 57 ;
512 state->TunerRegs[36].Reg_Val = 0x41 ;
52c99bda 513
3935c254
ST		 514 state->TunerRegs[37].Reg_Num = 58 ;
515 state->TunerRegs[37].Reg_Val = 0xDB ;
52c99bda 516
3935c254
ST		 517 state->TunerRegs[38].Reg_Num = 59 ;
518 state->TunerRegs[38].Reg_Val = 0x00 ;
52c99bda 519
3935c254
ST		 520 state->TunerRegs[39].Reg_Num = 60 ;
521 state->TunerRegs[39].Reg_Val = 0x00 ;
52c99bda 522
3935c254
ST		 523 state->TunerRegs[40].Reg_Num = 61 ;
524 state->TunerRegs[40].Reg_Val = 0x00 ;
52c99bda 525
3935c254
ST		 526 state->TunerRegs[41].Reg_Num = 62 ;
527 state->TunerRegs[41].Reg_Val = 0x00 ;
52c99bda 528
3935c254
ST		 529 state->TunerRegs[42].Reg_Num = 65 ;
530 state->TunerRegs[42].Reg_Val = 0xF8 ;
52c99bda 531
3935c254
ST		 532 state->TunerRegs[43].Reg_Num = 66 ;
533 state->TunerRegs[43].Reg_Val = 0xE4 ;
52c99bda 534
3935c254
ST		 535 state->TunerRegs[44].Reg_Num = 67 ;
536 state->TunerRegs[44].Reg_Val = 0x90 ;
52c99bda 537
3935c254
ST		 538 state->TunerRegs[45].Reg_Num = 68 ;
539 state->TunerRegs[45].Reg_Val = 0xC0 ;
52c99bda 540
3935c254
ST		 541 state->TunerRegs[46].Reg_Num = 69 ;
542 state->TunerRegs[46].Reg_Val = 0x01 ;
52c99bda 543
3935c254
ST		 544 state->TunerRegs[47].Reg_Num = 70 ;
545 state->TunerRegs[47].Reg_Val = 0x50 ;
52c99bda 546
3935c254
ST		 547 state->TunerRegs[48].Reg_Num = 71 ;
548 state->TunerRegs[48].Reg_Val = 0x06 ;
52c99bda 549
3935c254
ST		 550 state->TunerRegs[49].Reg_Num = 72 ;
551 state->TunerRegs[49].Reg_Val = 0x00 ;
52c99bda 552
3935c254
ST		 553 state->TunerRegs[50].Reg_Num = 73 ;
554 state->TunerRegs[50].Reg_Val = 0x20 ;
52c99bda 555
3935c254
ST		 556 state->TunerRegs[51].Reg_Num = 76 ;
557 state->TunerRegs[51].Reg_Val = 0xBB ;
52c99bda 558
3935c254
ST		 559 state->TunerRegs[52].Reg_Num = 77 ;
560 state->TunerRegs[52].Reg_Val = 0x13 ;
52c99bda 561
3935c254
ST		 562 state->TunerRegs[53].Reg_Num = 81 ;
563 state->TunerRegs[53].Reg_Val = 0x04 ;
52c99bda 564
3935c254
ST		 565 state->TunerRegs[54].Reg_Num = 82 ;
566 state->TunerRegs[54].Reg_Val = 0x75 ;
52c99bda 567
3935c254
ST		 568 state->TunerRegs[55].Reg_Num = 83 ;
569 state->TunerRegs[55].Reg_Val = 0x00 ;
52c99bda 570
3935c254
ST		 571 state->TunerRegs[56].Reg_Num = 84 ;
572 state->TunerRegs[56].Reg_Val = 0x00 ;
52c99bda 573
3935c254
ST		 574 state->TunerRegs[57].Reg_Num = 85 ;
575 state->TunerRegs[57].Reg_Val = 0x00 ;
52c99bda 576
3935c254
ST		 577 state->TunerRegs[58].Reg_Num = 91 ;
578 state->TunerRegs[58].Reg_Val = 0x70 ;
52c99bda 579
3935c254
ST		 580 state->TunerRegs[59].Reg_Num = 92 ;
581 state->TunerRegs[59].Reg_Val = 0x00 ;
52c99bda 582
3935c254
ST		 583 state->TunerRegs[60].Reg_Num = 93 ;
584 state->TunerRegs[60].Reg_Val = 0x00 ;
52c99bda 585
3935c254
ST		 586 state->TunerRegs[61].Reg_Num = 94 ;
587 state->TunerRegs[61].Reg_Val = 0x00 ;
52c99bda 588
3935c254
ST		 589 state->TunerRegs[62].Reg_Num = 95 ;
590 state->TunerRegs[62].Reg_Val = 0x0C ;
52c99bda 591
3935c254
ST		 592 state->TunerRegs[63].Reg_Num = 96 ;
593 state->TunerRegs[63].Reg_Val = 0x00 ;
52c99bda 594
3935c254
ST		 595 state->TunerRegs[64].Reg_Num = 97 ;
596 state->TunerRegs[64].Reg_Val = 0x00 ;
52c99bda 597
3935c254
ST		 598 state->TunerRegs[65].Reg_Num = 98 ;
599 state->TunerRegs[65].Reg_Val = 0xE2 ;
52c99bda 600
3935c254
ST		 601 state->TunerRegs[66].Reg_Num = 99 ;
602 state->TunerRegs[66].Reg_Val = 0x00 ;
52c99bda 603
3935c254
ST		 604 state->TunerRegs[67].Reg_Num = 100 ;
605 state->TunerRegs[67].Reg_Val = 0x00 ;
52c99bda 606
3935c254
ST		 607 state->TunerRegs[68].Reg_Num = 101 ;
608 state->TunerRegs[68].Reg_Val = 0x12 ;
52c99bda 609
3935c254
ST		 610 state->TunerRegs[69].Reg_Num = 102 ;
611 state->TunerRegs[69].Reg_Val = 0x80 ;
52c99bda 612
3935c254
ST		 613 state->TunerRegs[70].Reg_Num = 103 ;
614 state->TunerRegs[70].Reg_Val = 0x32 ;
52c99bda 615
3935c254
ST		 616 state->TunerRegs[71].Reg_Num = 104 ;
617 state->TunerRegs[71].Reg_Val = 0xB4 ;
52c99bda 618
3935c254
ST		 619 state->TunerRegs[72].Reg_Num = 105 ;
620 state->TunerRegs[72].Reg_Val = 0x60 ;
52c99bda 621
3935c254
ST		 622 state->TunerRegs[73].Reg_Num = 106 ;
623 state->TunerRegs[73].Reg_Val = 0x83 ;
52c99bda 624
3935c254
ST		 625 state->TunerRegs[74].Reg_Num = 107 ;
626 state->TunerRegs[74].Reg_Val = 0x84 ;
52c99bda 627
3935c254
ST		 628 state->TunerRegs[75].Reg_Num = 108 ;
629 state->TunerRegs[75].Reg_Val = 0x9C ;
52c99bda 630
3935c254
ST		 631 state->TunerRegs[76].Reg_Num = 109 ;
632 state->TunerRegs[76].Reg_Val = 0x02 ;
52c99bda 633
3935c254
ST		 634 state->TunerRegs[77].Reg_Num = 110 ;
635 state->TunerRegs[77].Reg_Val = 0x81 ;
52c99bda 636
3935c254
ST		 637 state->TunerRegs[78].Reg_Num = 111 ;
638 state->TunerRegs[78].Reg_Val = 0xC0 ;
52c99bda 639
3935c254
ST		 640 state->TunerRegs[79].Reg_Num = 112 ;
641 state->TunerRegs[79].Reg_Val = 0x10 ;
52c99bda 642
3935c254
ST		 643 state->TunerRegs[80].Reg_Num = 131 ;
644 state->TunerRegs[80].Reg_Val = 0x8A ;
52c99bda 645
3935c254
ST		 646 state->TunerRegs[81].Reg_Num = 132 ;
647 state->TunerRegs[81].Reg_Val = 0x10 ;
52c99bda 648
3935c254
ST		 649 state->TunerRegs[82].Reg_Num = 133 ;
650 state->TunerRegs[82].Reg_Val = 0x24 ;
52c99bda 651
3935c254
ST		 652 state->TunerRegs[83].Reg_Num = 134 ;
653 state->TunerRegs[83].Reg_Val = 0x00 ;
52c99bda 654
3935c254
ST		 655 state->TunerRegs[84].Reg_Num = 135 ;
656 state->TunerRegs[84].Reg_Val = 0x00 ;
52c99bda 657
3935c254
ST		 658 state->TunerRegs[85].Reg_Num = 136 ;
659 state->TunerRegs[85].Reg_Val = 0x7E ;
52c99bda 660
3935c254
ST		 661 state->TunerRegs[86].Reg_Num = 137 ;
662 state->TunerRegs[86].Reg_Val = 0x40 ;
52c99bda 663
3935c254
ST		 664 state->TunerRegs[87].Reg_Num = 138 ;
665 state->TunerRegs[87].Reg_Val = 0x38 ;
52c99bda 666
3935c254
ST		 667 state->TunerRegs[88].Reg_Num = 146 ;
668 state->TunerRegs[88].Reg_Val = 0xF6 ;
52c99bda 669
3935c254
ST		 670 state->TunerRegs[89].Reg_Num = 147 ;
671 state->TunerRegs[89].Reg_Val = 0x1A ;
52c99bda 672
3935c254
ST		 673 state->TunerRegs[90].Reg_Num = 148 ;
674 state->TunerRegs[90].Reg_Val = 0x62 ;
52c99bda 675
3935c254
ST		 676 state->TunerRegs[91].Reg_Num = 149 ;
677 state->TunerRegs[91].Reg_Val = 0x33 ;
52c99bda 678
3935c254
ST		 679 state->TunerRegs[92].Reg_Num = 150 ;
680 state->TunerRegs[92].Reg_Val = 0x80 ;
52c99bda 681
3935c254
ST		 682 state->TunerRegs[93].Reg_Num = 156 ;
683 state->TunerRegs[93].Reg_Val = 0x56 ;
52c99bda 684
3935c254
ST		 685 state->TunerRegs[94].Reg_Num = 157 ;
686 state->TunerRegs[94].Reg_Val = 0x17 ;
52c99bda 687
3935c254
ST		 688 state->TunerRegs[95].Reg_Num = 158 ;
689 state->TunerRegs[95].Reg_Val = 0xA9 ;
52c99bda 690
3935c254
ST		 691 state->TunerRegs[96].Reg_Num = 159 ;
692 state->TunerRegs[96].Reg_Val = 0x00 ;
52c99bda 693
3935c254
ST		 694 state->TunerRegs[97].Reg_Num = 160 ;
695 state->TunerRegs[97].Reg_Val = 0x00 ;
52c99bda 696
3935c254
ST		 697 state->TunerRegs[98].Reg_Num = 161 ;
698 state->TunerRegs[98].Reg_Val = 0x00 ;
52c99bda 699
3935c254
ST		 700 state->TunerRegs[99].Reg_Num = 162 ;
701 state->TunerRegs[99].Reg_Val = 0x40 ;
52c99bda 702
3935c254
ST		 703 state->TunerRegs[100].Reg_Num = 166 ;
704 state->TunerRegs[100].Reg_Val = 0xAE ;
52c99bda 705
3935c254
ST		 706 state->TunerRegs[101].Reg_Num = 167 ;
707 state->TunerRegs[101].Reg_Val = 0x1B ;
52c99bda 708
3935c254
ST		 709 state->TunerRegs[102].Reg_Num = 168 ;
710 state->TunerRegs[102].Reg_Val = 0xF2 ;
52c99bda 711
3935c254
ST		 712 state->TunerRegs[103].Reg_Num = 195 ;
713 state->TunerRegs[103].Reg_Val = 0x00 ;
52c99bda
ST		 714
715 return 0 ;
716}
717
3935c254 718u16 MXL5005_ControlInit(struct dvb_frontend *fe)
52c99bda 719{
85d220d0 720 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 721 state->Init_Ctrl_Num = INITCTRL_NUM;
722
723 state->Init_Ctrl[0].Ctrl_Num = DN_IQTN_AMP_CUT ;
724 state->Init_Ctrl[0].size = 1 ;
725 state->Init_Ctrl[0].addr[0] = 73;
726 state->Init_Ctrl[0].bit[0] = 7;
727 state->Init_Ctrl[0].val[0] = 0;
728
729 state->Init_Ctrl[1].Ctrl_Num = BB_MODE ;
730 state->Init_Ctrl[1].size = 1 ;
731 state->Init_Ctrl[1].addr[0] = 53;
732 state->Init_Ctrl[1].bit[0] = 2;
733 state->Init_Ctrl[1].val[0] = 1;
734
735 state->Init_Ctrl[2].Ctrl_Num = BB_BUF ;
736 state->Init_Ctrl[2].size = 2 ;
737 state->Init_Ctrl[2].addr[0] = 53;
738 state->Init_Ctrl[2].bit[0] = 1;
739 state->Init_Ctrl[2].val[0] = 0;
740 state->Init_Ctrl[2].addr[1] = 57;
741 state->Init_Ctrl[2].bit[1] = 0;
742 state->Init_Ctrl[2].val[1] = 1;
743
744 state->Init_Ctrl[3].Ctrl_Num = BB_BUF_OA ;
745 state->Init_Ctrl[3].size = 1 ;
746 state->Init_Ctrl[3].addr[0] = 53;
747 state->Init_Ctrl[3].bit[0] = 0;
748 state->Init_Ctrl[3].val[0] = 0;
749
750 state->Init_Ctrl[4].Ctrl_Num = BB_ALPF_BANDSELECT ;
751 state->Init_Ctrl[4].size = 3 ;
752 state->Init_Ctrl[4].addr[0] = 53;
753 state->Init_Ctrl[4].bit[0] = 5;
754 state->Init_Ctrl[4].val[0] = 0;
755 state->Init_Ctrl[4].addr[1] = 53;
756 state->Init_Ctrl[4].bit[1] = 6;
757 state->Init_Ctrl[4].val[1] = 0;
758 state->Init_Ctrl[4].addr[2] = 53;
759 state->Init_Ctrl[4].bit[2] = 7;
760 state->Init_Ctrl[4].val[2] = 1;
761
762 state->Init_Ctrl[5].Ctrl_Num = BB_IQSWAP ;
763 state->Init_Ctrl[5].size = 1 ;
764 state->Init_Ctrl[5].addr[0] = 59;
765 state->Init_Ctrl[5].bit[0] = 0;
766 state->Init_Ctrl[5].val[0] = 0;
767
768 state->Init_Ctrl[6].Ctrl_Num = BB_DLPF_BANDSEL ;
769 state->Init_Ctrl[6].size = 2 ;
770 state->Init_Ctrl[6].addr[0] = 53;
771 state->Init_Ctrl[6].bit[0] = 3;
772 state->Init_Ctrl[6].val[0] = 0;
773 state->Init_Ctrl[6].addr[1] = 53;
774 state->Init_Ctrl[6].bit[1] = 4;
775 state->Init_Ctrl[6].val[1] = 1;
776
777 state->Init_Ctrl[7].Ctrl_Num = RFSYN_CHP_GAIN ;
778 state->Init_Ctrl[7].size = 4 ;
779 state->Init_Ctrl[7].addr[0] = 22;
780 state->Init_Ctrl[7].bit[0] = 4;
781 state->Init_Ctrl[7].val[0] = 0;
782 state->Init_Ctrl[7].addr[1] = 22;
783 state->Init_Ctrl[7].bit[1] = 5;
784 state->Init_Ctrl[7].val[1] = 1;
785 state->Init_Ctrl[7].addr[2] = 22;
786 state->Init_Ctrl[7].bit[2] = 6;
787 state->Init_Ctrl[7].val[2] = 1;
788 state->Init_Ctrl[7].addr[3] = 22;
789 state->Init_Ctrl[7].bit[3] = 7;
790 state->Init_Ctrl[7].val[3] = 0;
791
792 state->Init_Ctrl[8].Ctrl_Num = RFSYN_EN_CHP_HIGAIN ;
793 state->Init_Ctrl[8].size = 1 ;
794 state->Init_Ctrl[8].addr[0] = 22;
795 state->Init_Ctrl[8].bit[0] = 2;
796 state->Init_Ctrl[8].val[0] = 0;
797
798 state->Init_Ctrl[9].Ctrl_Num = AGC_IF ;
799 state->Init_Ctrl[9].size = 4 ;
800 state->Init_Ctrl[9].addr[0] = 76;
801 state->Init_Ctrl[9].bit[0] = 0;
802 state->Init_Ctrl[9].val[0] = 1;
803 state->Init_Ctrl[9].addr[1] = 76;
804 state->Init_Ctrl[9].bit[1] = 1;
805 state->Init_Ctrl[9].val[1] = 1;
806 state->Init_Ctrl[9].addr[2] = 76;
807 state->Init_Ctrl[9].bit[2] = 2;
808 state->Init_Ctrl[9].val[2] = 0;
809 state->Init_Ctrl[9].addr[3] = 76;
810 state->Init_Ctrl[9].bit[3] = 3;
811 state->Init_Ctrl[9].val[3] = 1;
812
813 state->Init_Ctrl[10].Ctrl_Num = AGC_RF ;
814 state->Init_Ctrl[10].size = 4 ;
815 state->Init_Ctrl[10].addr[0] = 76;
816 state->Init_Ctrl[10].bit[0] = 4;
817 state->Init_Ctrl[10].val[0] = 1;
818 state->Init_Ctrl[10].addr[1] = 76;
819 state->Init_Ctrl[10].bit[1] = 5;
820 state->Init_Ctrl[10].val[1] = 1;
821 state->Init_Ctrl[10].addr[2] = 76;
822 state->Init_Ctrl[10].bit[2] = 6;
823 state->Init_Ctrl[10].val[2] = 0;
824 state->Init_Ctrl[10].addr[3] = 76;
825 state->Init_Ctrl[10].bit[3] = 7;
826 state->Init_Ctrl[10].val[3] = 1;
827
828 state->Init_Ctrl[11].Ctrl_Num = IF_DIVVAL ;
829 state->Init_Ctrl[11].size = 5 ;
830 state->Init_Ctrl[11].addr[0] = 43;
831 state->Init_Ctrl[11].bit[0] = 3;
832 state->Init_Ctrl[11].val[0] = 0;
833 state->Init_Ctrl[11].addr[1] = 43;
834 state->Init_Ctrl[11].bit[1] = 4;
835 state->Init_Ctrl[11].val[1] = 0;
836 state->Init_Ctrl[11].addr[2] = 43;
837 state->Init_Ctrl[11].bit[2] = 5;
838 state->Init_Ctrl[11].val[2] = 0;
839 state->Init_Ctrl[11].addr[3] = 43;
840 state->Init_Ctrl[11].bit[3] = 6;
841 state->Init_Ctrl[11].val[3] = 1;
842 state->Init_Ctrl[11].addr[4] = 43;
843 state->Init_Ctrl[11].bit[4] = 7;
844 state->Init_Ctrl[11].val[4] = 0;
845
846 state->Init_Ctrl[12].Ctrl_Num = IF_VCO_BIAS ;
847 state->Init_Ctrl[12].size = 6 ;
848 state->Init_Ctrl[12].addr[0] = 44;
849 state->Init_Ctrl[12].bit[0] = 2;
850 state->Init_Ctrl[12].val[0] = 0;
851 state->Init_Ctrl[12].addr[1] = 44;
852 state->Init_Ctrl[12].bit[1] = 3;
853 state->Init_Ctrl[12].val[1] = 0;
854 state->Init_Ctrl[12].addr[2] = 44;
855 state->Init_Ctrl[12].bit[2] = 4;
856 state->Init_Ctrl[12].val[2] = 0;
857 state->Init_Ctrl[12].addr[3] = 44;
858 state->Init_Ctrl[12].bit[3] = 5;
859 state->Init_Ctrl[12].val[3] = 1;
860 state->Init_Ctrl[12].addr[4] = 44;
861 state->Init_Ctrl[12].bit[4] = 6;
862 state->Init_Ctrl[12].val[4] = 0;
863 state->Init_Ctrl[12].addr[5] = 44;
864 state->Init_Ctrl[12].bit[5] = 7;
865 state->Init_Ctrl[12].val[5] = 0;
866
867 state->Init_Ctrl[13].Ctrl_Num = CHCAL_INT_MOD_IF ;
868 state->Init_Ctrl[13].size = 7 ;
869 state->Init_Ctrl[13].addr[0] = 11;
870 state->Init_Ctrl[13].bit[0] = 0;
871 state->Init_Ctrl[13].val[0] = 1;
872 state->Init_Ctrl[13].addr[1] = 11;
873 state->Init_Ctrl[13].bit[1] = 1;
874 state->Init_Ctrl[13].val[1] = 0;
875 state->Init_Ctrl[13].addr[2] = 11;
876 state->Init_Ctrl[13].bit[2] = 2;
877 state->Init_Ctrl[13].val[2] = 0;
878 state->Init_Ctrl[13].addr[3] = 11;
879 state->Init_Ctrl[13].bit[3] = 3;
880 state->Init_Ctrl[13].val[3] = 1;
881 state->Init_Ctrl[13].addr[4] = 11;
882 state->Init_Ctrl[13].bit[4] = 4;
883 state->Init_Ctrl[13].val[4] = 1;
884 state->Init_Ctrl[13].addr[5] = 11;
885 state->Init_Ctrl[13].bit[5] = 5;
886 state->Init_Ctrl[13].val[5] = 0;
887 state->Init_Ctrl[13].addr[6] = 11;
888 state->Init_Ctrl[13].bit[6] = 6;
889 state->Init_Ctrl[13].val[6] = 0;
890
891 state->Init_Ctrl[14].Ctrl_Num = CHCAL_FRAC_MOD_IF ;
892 state->Init_Ctrl[14].size = 16 ;
893 state->Init_Ctrl[14].addr[0] = 13;
894 state->Init_Ctrl[14].bit[0] = 0;
895 state->Init_Ctrl[14].val[0] = 0;
896 state->Init_Ctrl[14].addr[1] = 13;
897 state->Init_Ctrl[14].bit[1] = 1;
898 state->Init_Ctrl[14].val[1] = 0;
899 state->Init_Ctrl[14].addr[2] = 13;
900 state->Init_Ctrl[14].bit[2] = 2;
901 state->Init_Ctrl[14].val[2] = 0;
902 state->Init_Ctrl[14].addr[3] = 13;
903 state->Init_Ctrl[14].bit[3] = 3;
904 state->Init_Ctrl[14].val[3] = 0;
905 state->Init_Ctrl[14].addr[4] = 13;
906 state->Init_Ctrl[14].bit[4] = 4;
907 state->Init_Ctrl[14].val[4] = 0;
908 state->Init_Ctrl[14].addr[5] = 13;
909 state->Init_Ctrl[14].bit[5] = 5;
910 state->Init_Ctrl[14].val[5] = 0;
911 state->Init_Ctrl[14].addr[6] = 13;
912 state->Init_Ctrl[14].bit[6] = 6;
913 state->Init_Ctrl[14].val[6] = 0;
914 state->Init_Ctrl[14].addr[7] = 13;
915 state->Init_Ctrl[14].bit[7] = 7;
916 state->Init_Ctrl[14].val[7] = 0;
917 state->Init_Ctrl[14].addr[8] = 12;
918 state->Init_Ctrl[14].bit[8] = 0;
919 state->Init_Ctrl[14].val[8] = 0;
920 state->Init_Ctrl[14].addr[9] = 12;
921 state->Init_Ctrl[14].bit[9] = 1;
922 state->Init_Ctrl[14].val[9] = 0;
923 state->Init_Ctrl[14].addr[10] = 12;
924 state->Init_Ctrl[14].bit[10] = 2;
925 state->Init_Ctrl[14].val[10] = 0;
926 state->Init_Ctrl[14].addr[11] = 12;
927 state->Init_Ctrl[14].bit[11] = 3;
928 state->Init_Ctrl[14].val[11] = 0;
929 state->Init_Ctrl[14].addr[12] = 12;
930 state->Init_Ctrl[14].bit[12] = 4;
931 state->Init_Ctrl[14].val[12] = 0;
932 state->Init_Ctrl[14].addr[13] = 12;
933 state->Init_Ctrl[14].bit[13] = 5;
934 state->Init_Ctrl[14].val[13] = 1;
935 state->Init_Ctrl[14].addr[14] = 12;
936 state->Init_Ctrl[14].bit[14] = 6;
937 state->Init_Ctrl[14].val[14] = 1;
938 state->Init_Ctrl[14].addr[15] = 12;
939 state->Init_Ctrl[14].bit[15] = 7;
940 state->Init_Ctrl[14].val[15] = 0;
941
942 state->Init_Ctrl[15].Ctrl_Num = DRV_RES_SEL ;
943 state->Init_Ctrl[15].size = 3 ;
944 state->Init_Ctrl[15].addr[0] = 147;
945 state->Init_Ctrl[15].bit[0] = 2;
946 state->Init_Ctrl[15].val[0] = 0;
947 state->Init_Ctrl[15].addr[1] = 147;
948 state->Init_Ctrl[15].bit[1] = 3;
949 state->Init_Ctrl[15].val[1] = 1;
950 state->Init_Ctrl[15].addr[2] = 147;
951 state->Init_Ctrl[15].bit[2] = 4;
952 state->Init_Ctrl[15].val[2] = 1;
953
954 state->Init_Ctrl[16].Ctrl_Num = I_DRIVER ;
955 state->Init_Ctrl[16].size = 2 ;
956 state->Init_Ctrl[16].addr[0] = 147;
957 state->Init_Ctrl[16].bit[0] = 0;
958 state->Init_Ctrl[16].val[0] = 0;
959 state->Init_Ctrl[16].addr[1] = 147;
960 state->Init_Ctrl[16].bit[1] = 1;
961 state->Init_Ctrl[16].val[1] = 1;
962
963 state->Init_Ctrl[17].Ctrl_Num = EN_AAF ;
964 state->Init_Ctrl[17].size = 1 ;
965 state->Init_Ctrl[17].addr[0] = 147;
966 state->Init_Ctrl[17].bit[0] = 7;
967 state->Init_Ctrl[17].val[0] = 0;
968
969 state->Init_Ctrl[18].Ctrl_Num = EN_3P ;
970 state->Init_Ctrl[18].size = 1 ;
971 state->Init_Ctrl[18].addr[0] = 147;
972 state->Init_Ctrl[18].bit[0] = 6;
973 state->Init_Ctrl[18].val[0] = 0;
974
975 state->Init_Ctrl[19].Ctrl_Num = EN_AUX_3P ;
976 state->Init_Ctrl[19].size = 1 ;
977 state->Init_Ctrl[19].addr[0] = 156;
978 state->Init_Ctrl[19].bit[0] = 0;
979 state->Init_Ctrl[19].val[0] = 0;
980
981 state->Init_Ctrl[20].Ctrl_Num = SEL_AAF_BAND ;
982 state->Init_Ctrl[20].size = 1 ;
983 state->Init_Ctrl[20].addr[0] = 147;
984 state->Init_Ctrl[20].bit[0] = 5;
985 state->Init_Ctrl[20].val[0] = 0;
986
987 state->Init_Ctrl[21].Ctrl_Num = SEQ_ENCLK16_CLK_OUT ;
988 state->Init_Ctrl[21].size = 1 ;
989 state->Init_Ctrl[21].addr[0] = 137;
990 state->Init_Ctrl[21].bit[0] = 4;
991 state->Init_Ctrl[21].val[0] = 0;
992
993 state->Init_Ctrl[22].Ctrl_Num = SEQ_SEL4_16B ;
994 state->Init_Ctrl[22].size = 1 ;
995 state->Init_Ctrl[22].addr[0] = 137;
996 state->Init_Ctrl[22].bit[0] = 7;
997 state->Init_Ctrl[22].val[0] = 0;
998
999 state->Init_Ctrl[23].Ctrl_Num = XTAL_CAPSELECT ;
1000 state->Init_Ctrl[23].size = 1 ;
1001 state->Init_Ctrl[23].addr[0] = 91;
1002 state->Init_Ctrl[23].bit[0] = 5;
1003 state->Init_Ctrl[23].val[0] = 1;
1004
1005 state->Init_Ctrl[24].Ctrl_Num = IF_SEL_DBL ;
1006 state->Init_Ctrl[24].size = 1 ;
1007 state->Init_Ctrl[24].addr[0] = 43;
1008 state->Init_Ctrl[24].bit[0] = 0;
1009 state->Init_Ctrl[24].val[0] = 1;
1010
1011 state->Init_Ctrl[25].Ctrl_Num = RFSYN_R_DIV ;
1012 state->Init_Ctrl[25].size = 2 ;
1013 state->Init_Ctrl[25].addr[0] = 22;
1014 state->Init_Ctrl[25].bit[0] = 0;
1015 state->Init_Ctrl[25].val[0] = 1;
1016 state->Init_Ctrl[25].addr[1] = 22;
1017 state->Init_Ctrl[25].bit[1] = 1;
1018 state->Init_Ctrl[25].val[1] = 1;
1019
1020 state->Init_Ctrl[26].Ctrl_Num = SEQ_EXTSYNTHCALIF ;
1021 state->Init_Ctrl[26].size = 1 ;
1022 state->Init_Ctrl[26].addr[0] = 134;
1023 state->Init_Ctrl[26].bit[0] = 2;
1024 state->Init_Ctrl[26].val[0] = 0;
1025
1026 state->Init_Ctrl[27].Ctrl_Num = SEQ_EXTDCCAL ;
1027 state->Init_Ctrl[27].size = 1 ;
1028 state->Init_Ctrl[27].addr[0] = 137;
1029 state->Init_Ctrl[27].bit[0] = 3;
1030 state->Init_Ctrl[27].val[0] = 0;
1031
1032 state->Init_Ctrl[28].Ctrl_Num = AGC_EN_RSSI ;
1033 state->Init_Ctrl[28].size = 1 ;
1034 state->Init_Ctrl[28].addr[0] = 77;
1035 state->Init_Ctrl[28].bit[0] = 7;
1036 state->Init_Ctrl[28].val[0] = 0;
1037
1038 state->Init_Ctrl[29].Ctrl_Num = RFA_ENCLKRFAGC ;
1039 state->Init_Ctrl[29].size = 1 ;
1040 state->Init_Ctrl[29].addr[0] = 166;
1041 state->Init_Ctrl[29].bit[0] = 7;
1042 state->Init_Ctrl[29].val[0] = 1;
1043
1044 state->Init_Ctrl[30].Ctrl_Num = RFA_RSSI_REFH ;
1045 state->Init_Ctrl[30].size = 3 ;
1046 state->Init_Ctrl[30].addr[0] = 166;
1047 state->Init_Ctrl[30].bit[0] = 0;
1048 state->Init_Ctrl[30].val[0] = 0;
1049 state->Init_Ctrl[30].addr[1] = 166;
1050 state->Init_Ctrl[30].bit[1] = 1;
1051 state->Init_Ctrl[30].val[1] = 1;
1052 state->Init_Ctrl[30].addr[2] = 166;
1053 state->Init_Ctrl[30].bit[2] = 2;
1054 state->Init_Ctrl[30].val[2] = 1;
1055
1056 state->Init_Ctrl[31].Ctrl_Num = RFA_RSSI_REF ;
1057 state->Init_Ctrl[31].size = 3 ;
1058 state->Init_Ctrl[31].addr[0] = 166;
1059 state->Init_Ctrl[31].bit[0] = 3;
1060 state->Init_Ctrl[31].val[0] = 1;
1061 state->Init_Ctrl[31].addr[1] = 166;
1062 state->Init_Ctrl[31].bit[1] = 4;
1063 state->Init_Ctrl[31].val[1] = 0;
1064 state->Init_Ctrl[31].addr[2] = 166;
1065 state->Init_Ctrl[31].bit[2] = 5;
1066 state->Init_Ctrl[31].val[2] = 1;
1067
1068 state->Init_Ctrl[32].Ctrl_Num = RFA_RSSI_REFL ;
1069 state->Init_Ctrl[32].size = 3 ;
1070 state->Init_Ctrl[32].addr[0] = 167;
1071 state->Init_Ctrl[32].bit[0] = 0;
1072 state->Init_Ctrl[32].val[0] = 1;
1073 state->Init_Ctrl[32].addr[1] = 167;
1074 state->Init_Ctrl[32].bit[1] = 1;
1075 state->Init_Ctrl[32].val[1] = 1;
1076 state->Init_Ctrl[32].addr[2] = 167;
1077 state->Init_Ctrl[32].bit[2] = 2;
1078 state->Init_Ctrl[32].val[2] = 0;
1079
1080 state->Init_Ctrl[33].Ctrl_Num = RFA_FLR ;
1081 state->Init_Ctrl[33].size = 4 ;
1082 state->Init_Ctrl[33].addr[0] = 168;
1083 state->Init_Ctrl[33].bit[0] = 0;
1084 state->Init_Ctrl[33].val[0] = 0;
1085 state->Init_Ctrl[33].addr[1] = 168;
1086 state->Init_Ctrl[33].bit[1] = 1;
1087 state->Init_Ctrl[33].val[1] = 1;
1088 state->Init_Ctrl[33].addr[2] = 168;
1089 state->Init_Ctrl[33].bit[2] = 2;
1090 state->Init_Ctrl[33].val[2] = 0;
1091 state->Init_Ctrl[33].addr[3] = 168;
1092 state->Init_Ctrl[33].bit[3] = 3;
1093 state->Init_Ctrl[33].val[3] = 0;
1094
1095 state->Init_Ctrl[34].Ctrl_Num = RFA_CEIL ;
1096 state->Init_Ctrl[34].size = 4 ;
1097 state->Init_Ctrl[34].addr[0] = 168;
1098 state->Init_Ctrl[34].bit[0] = 4;
1099 state->Init_Ctrl[34].val[0] = 1;
1100 state->Init_Ctrl[34].addr[1] = 168;
1101 state->Init_Ctrl[34].bit[1] = 5;
1102 state->Init_Ctrl[34].val[1] = 1;
1103 state->Init_Ctrl[34].addr[2] = 168;
1104 state->Init_Ctrl[34].bit[2] = 6;
1105 state->Init_Ctrl[34].val[2] = 1;
1106 state->Init_Ctrl[34].addr[3] = 168;
1107 state->Init_Ctrl[34].bit[3] = 7;
1108 state->Init_Ctrl[34].val[3] = 1;
1109
1110 state->Init_Ctrl[35].Ctrl_Num = SEQ_EXTIQFSMPULSE ;
1111 state->Init_Ctrl[35].size = 1 ;
1112 state->Init_Ctrl[35].addr[0] = 135;
1113 state->Init_Ctrl[35].bit[0] = 0;
1114 state->Init_Ctrl[35].val[0] = 0;
1115
1116 state->Init_Ctrl[36].Ctrl_Num = OVERRIDE_1 ;
1117 state->Init_Ctrl[36].size = 1 ;
1118 state->Init_Ctrl[36].addr[0] = 56;
1119 state->Init_Ctrl[36].bit[0] = 3;
1120 state->Init_Ctrl[36].val[0] = 0;
1121
1122 state->Init_Ctrl[37].Ctrl_Num = BB_INITSTATE_DLPF_TUNE ;
1123 state->Init_Ctrl[37].size = 7 ;
1124 state->Init_Ctrl[37].addr[0] = 59;
1125 state->Init_Ctrl[37].bit[0] = 1;
1126 state->Init_Ctrl[37].val[0] = 0;
1127 state->Init_Ctrl[37].addr[1] = 59;
1128 state->Init_Ctrl[37].bit[1] = 2;
1129 state->Init_Ctrl[37].val[1] = 0;
1130 state->Init_Ctrl[37].addr[2] = 59;
1131 state->Init_Ctrl[37].bit[2] = 3;
1132 state->Init_Ctrl[37].val[2] = 0;
1133 state->Init_Ctrl[37].addr[3] = 59;
1134 state->Init_Ctrl[37].bit[3] = 4;
1135 state->Init_Ctrl[37].val[3] = 0;
1136 state->Init_Ctrl[37].addr[4] = 59;
1137 state->Init_Ctrl[37].bit[4] = 5;
1138 state->Init_Ctrl[37].val[4] = 0;
1139 state->Init_Ctrl[37].addr[5] = 59;
1140 state->Init_Ctrl[37].bit[5] = 6;
1141 state->Init_Ctrl[37].val[5] = 0;
1142 state->Init_Ctrl[37].addr[6] = 59;
1143 state->Init_Ctrl[37].bit[6] = 7;
1144 state->Init_Ctrl[37].val[6] = 0;
1145
1146 state->Init_Ctrl[38].Ctrl_Num = TG_R_DIV ;
1147 state->Init_Ctrl[38].size = 6 ;
1148 state->Init_Ctrl[38].addr[0] = 32;
1149 state->Init_Ctrl[38].bit[0] = 2;
1150 state->Init_Ctrl[38].val[0] = 0;
1151 state->Init_Ctrl[38].addr[1] = 32;
1152 state->Init_Ctrl[38].bit[1] = 3;
1153 state->Init_Ctrl[38].val[1] = 0;
1154 state->Init_Ctrl[38].addr[2] = 32;
1155 state->Init_Ctrl[38].bit[2] = 4;
1156 state->Init_Ctrl[38].val[2] = 0;
1157 state->Init_Ctrl[38].addr[3] = 32;
1158 state->Init_Ctrl[38].bit[3] = 5;
1159 state->Init_Ctrl[38].val[3] = 0;
1160 state->Init_Ctrl[38].addr[4] = 32;
1161 state->Init_Ctrl[38].bit[4] = 6;
1162 state->Init_Ctrl[38].val[4] = 1;
1163 state->Init_Ctrl[38].addr[5] = 32;
1164 state->Init_Ctrl[38].bit[5] = 7;
1165 state->Init_Ctrl[38].val[5] = 0;
1166
1167 state->Init_Ctrl[39].Ctrl_Num = EN_CHP_LIN_B ;
1168 state->Init_Ctrl[39].size = 1 ;
1169 state->Init_Ctrl[39].addr[0] = 25;
1170 state->Init_Ctrl[39].bit[0] = 3;
1171 state->Init_Ctrl[39].val[0] = 1;
1172
1173
1174 state->CH_Ctrl_Num = CHCTRL_NUM ;
1175
1176 state->CH_Ctrl[0].Ctrl_Num = DN_POLY ;
1177 state->CH_Ctrl[0].size = 2 ;
1178 state->CH_Ctrl[0].addr[0] = 68;
1179 state->CH_Ctrl[0].bit[0] = 6;
1180 state->CH_Ctrl[0].val[0] = 1;
1181 state->CH_Ctrl[0].addr[1] = 68;
1182 state->CH_Ctrl[0].bit[1] = 7;
1183 state->CH_Ctrl[0].val[1] = 1;
1184
1185 state->CH_Ctrl[1].Ctrl_Num = DN_RFGAIN ;
1186 state->CH_Ctrl[1].size = 2 ;
1187 state->CH_Ctrl[1].addr[0] = 70;
1188 state->CH_Ctrl[1].bit[0] = 6;
1189 state->CH_Ctrl[1].val[0] = 1;
1190 state->CH_Ctrl[1].addr[1] = 70;
1191 state->CH_Ctrl[1].bit[1] = 7;
1192 state->CH_Ctrl[1].val[1] = 0;
1193
1194 state->CH_Ctrl[2].Ctrl_Num = DN_CAP_RFLPF ;
1195 state->CH_Ctrl[2].size = 9 ;
1196 state->CH_Ctrl[2].addr[0] = 69;
1197 state->CH_Ctrl[2].bit[0] = 5;
1198 state->CH_Ctrl[2].val[0] = 0;
1199 state->CH_Ctrl[2].addr[1] = 69;
1200 state->CH_Ctrl[2].bit[1] = 6;
1201 state->CH_Ctrl[2].val[1] = 0;
1202 state->CH_Ctrl[2].addr[2] = 69;
1203 state->CH_Ctrl[2].bit[2] = 7;
1204 state->CH_Ctrl[2].val[2] = 0;
1205 state->CH_Ctrl[2].addr[3] = 68;
1206 state->CH_Ctrl[2].bit[3] = 0;
1207 state->CH_Ctrl[2].val[3] = 0;
1208 state->CH_Ctrl[2].addr[4] = 68;
1209 state->CH_Ctrl[2].bit[4] = 1;
1210 state->CH_Ctrl[2].val[4] = 0;
1211 state->CH_Ctrl[2].addr[5] = 68;
1212 state->CH_Ctrl[2].bit[5] = 2;
1213 state->CH_Ctrl[2].val[5] = 0;
1214 state->CH_Ctrl[2].addr[6] = 68;
1215 state->CH_Ctrl[2].bit[6] = 3;
1216 state->CH_Ctrl[2].val[6] = 0;
1217 state->CH_Ctrl[2].addr[7] = 68;
1218 state->CH_Ctrl[2].bit[7] = 4;
1219 state->CH_Ctrl[2].val[7] = 0;
1220 state->CH_Ctrl[2].addr[8] = 68;
1221 state->CH_Ctrl[2].bit[8] = 5;
1222 state->CH_Ctrl[2].val[8] = 0;
1223
1224 state->CH_Ctrl[3].Ctrl_Num = DN_EN_VHFUHFBAR ;
1225 state->CH_Ctrl[3].size = 1 ;
1226 state->CH_Ctrl[3].addr[0] = 70;
1227 state->CH_Ctrl[3].bit[0] = 5;
1228 state->CH_Ctrl[3].val[0] = 0;
1229
1230 state->CH_Ctrl[4].Ctrl_Num = DN_GAIN_ADJUST ;
1231 state->CH_Ctrl[4].size = 3 ;
1232 state->CH_Ctrl[4].addr[0] = 73;
1233 state->CH_Ctrl[4].bit[0] = 4;
1234 state->CH_Ctrl[4].val[0] = 0;
1235 state->CH_Ctrl[4].addr[1] = 73;
1236 state->CH_Ctrl[4].bit[1] = 5;
1237 state->CH_Ctrl[4].val[1] = 1;
1238 state->CH_Ctrl[4].addr[2] = 73;
1239 state->CH_Ctrl[4].bit[2] = 6;
1240 state->CH_Ctrl[4].val[2] = 0;
1241
1242 state->CH_Ctrl[5].Ctrl_Num = DN_IQTNBUF_AMP ;
1243 state->CH_Ctrl[5].size = 4 ;
1244 state->CH_Ctrl[5].addr[0] = 70;
1245 state->CH_Ctrl[5].bit[0] = 0;
1246 state->CH_Ctrl[5].val[0] = 0;
1247 state->CH_Ctrl[5].addr[1] = 70;
1248 state->CH_Ctrl[5].bit[1] = 1;
1249 state->CH_Ctrl[5].val[1] = 0;
1250 state->CH_Ctrl[5].addr[2] = 70;
1251 state->CH_Ctrl[5].bit[2] = 2;
1252 state->CH_Ctrl[5].val[2] = 0;
1253 state->CH_Ctrl[5].addr[3] = 70;
1254 state->CH_Ctrl[5].bit[3] = 3;
1255 state->CH_Ctrl[5].val[3] = 0;
1256
1257 state->CH_Ctrl[6].Ctrl_Num = DN_IQTNGNBFBIAS_BST ;
1258 state->CH_Ctrl[6].size = 1 ;
1259 state->CH_Ctrl[6].addr[0] = 70;
1260 state->CH_Ctrl[6].bit[0] = 4;
1261 state->CH_Ctrl[6].val[0] = 1;
1262
1263 state->CH_Ctrl[7].Ctrl_Num = RFSYN_EN_OUTMUX ;
1264 state->CH_Ctrl[7].size = 1 ;
1265 state->CH_Ctrl[7].addr[0] = 111;
1266 state->CH_Ctrl[7].bit[0] = 4;
1267 state->CH_Ctrl[7].val[0] = 0;
1268
1269 state->CH_Ctrl[8].Ctrl_Num = RFSYN_SEL_VCO_OUT ;
1270 state->CH_Ctrl[8].size = 1 ;
1271 state->CH_Ctrl[8].addr[0] = 111;
1272 state->CH_Ctrl[8].bit[0] = 7;
1273 state->CH_Ctrl[8].val[0] = 1;
1274
1275 state->CH_Ctrl[9].Ctrl_Num = RFSYN_SEL_VCO_HI ;
1276 state->CH_Ctrl[9].size = 1 ;
1277 state->CH_Ctrl[9].addr[0] = 111;
1278 state->CH_Ctrl[9].bit[0] = 6;
1279 state->CH_Ctrl[9].val[0] = 1;
1280
1281 state->CH_Ctrl[10].Ctrl_Num = RFSYN_SEL_DIVM ;
1282 state->CH_Ctrl[10].size = 1 ;
1283 state->CH_Ctrl[10].addr[0] = 111;
1284 state->CH_Ctrl[10].bit[0] = 5;
1285 state->CH_Ctrl[10].val[0] = 0;
1286
1287 state->CH_Ctrl[11].Ctrl_Num = RFSYN_RF_DIV_BIAS ;
1288 state->CH_Ctrl[11].size = 2 ;
1289 state->CH_Ctrl[11].addr[0] = 110;
1290 state->CH_Ctrl[11].bit[0] = 0;
1291 state->CH_Ctrl[11].val[0] = 1;
1292 state->CH_Ctrl[11].addr[1] = 110;
1293 state->CH_Ctrl[11].bit[1] = 1;
1294 state->CH_Ctrl[11].val[1] = 0;
1295
1296 state->CH_Ctrl[12].Ctrl_Num = DN_SEL_FREQ ;
1297 state->CH_Ctrl[12].size = 3 ;
1298 state->CH_Ctrl[12].addr[0] = 69;
1299 state->CH_Ctrl[12].bit[0] = 2;
1300 state->CH_Ctrl[12].val[0] = 0;
1301 state->CH_Ctrl[12].addr[1] = 69;
1302 state->CH_Ctrl[12].bit[1] = 3;
1303 state->CH_Ctrl[12].val[1] = 0;
1304 state->CH_Ctrl[12].addr[2] = 69;
1305 state->CH_Ctrl[12].bit[2] = 4;
1306 state->CH_Ctrl[12].val[2] = 0;
1307
1308 state->CH_Ctrl[13].Ctrl_Num = RFSYN_VCO_BIAS ;
1309 state->CH_Ctrl[13].size = 6 ;
1310 state->CH_Ctrl[13].addr[0] = 110;
1311 state->CH_Ctrl[13].bit[0] = 2;
1312 state->CH_Ctrl[13].val[0] = 0;
1313 state->CH_Ctrl[13].addr[1] = 110;
1314 state->CH_Ctrl[13].bit[1] = 3;
1315 state->CH_Ctrl[13].val[1] = 0;
1316 state->CH_Ctrl[13].addr[2] = 110;
1317 state->CH_Ctrl[13].bit[2] = 4;
1318 state->CH_Ctrl[13].val[2] = 0;
1319 state->CH_Ctrl[13].addr[3] = 110;
1320 state->CH_Ctrl[13].bit[3] = 5;
1321 state->CH_Ctrl[13].val[3] = 0;
1322 state->CH_Ctrl[13].addr[4] = 110;
1323 state->CH_Ctrl[13].bit[4] = 6;
1324 state->CH_Ctrl[13].val[4] = 0;
1325 state->CH_Ctrl[13].addr[5] = 110;
1326 state->CH_Ctrl[13].bit[5] = 7;
1327 state->CH_Ctrl[13].val[5] = 1;
1328
1329 state->CH_Ctrl[14].Ctrl_Num = CHCAL_INT_MOD_RF ;
1330 state->CH_Ctrl[14].size = 7 ;
1331 state->CH_Ctrl[14].addr[0] = 14;
1332 state->CH_Ctrl[14].bit[0] = 0;
1333 state->CH_Ctrl[14].val[0] = 0;
1334 state->CH_Ctrl[14].addr[1] = 14;
1335 state->CH_Ctrl[14].bit[1] = 1;
1336 state->CH_Ctrl[14].val[1] = 0;
1337 state->CH_Ctrl[14].addr[2] = 14;
1338 state->CH_Ctrl[14].bit[2] = 2;
1339 state->CH_Ctrl[14].val[2] = 0;
1340 state->CH_Ctrl[14].addr[3] = 14;
1341 state->CH_Ctrl[14].bit[3] = 3;
1342 state->CH_Ctrl[14].val[3] = 0;
1343 state->CH_Ctrl[14].addr[4] = 14;
1344 state->CH_Ctrl[14].bit[4] = 4;
1345 state->CH_Ctrl[14].val[4] = 0;
1346 state->CH_Ctrl[14].addr[5] = 14;
1347 state->CH_Ctrl[14].bit[5] = 5;
1348 state->CH_Ctrl[14].val[5] = 0;
1349 state->CH_Ctrl[14].addr[6] = 14;
1350 state->CH_Ctrl[14].bit[6] = 6;
1351 state->CH_Ctrl[14].val[6] = 0;
1352
1353 state->CH_Ctrl[15].Ctrl_Num = CHCAL_FRAC_MOD_RF ;
1354 state->CH_Ctrl[15].size = 18 ;
1355 state->CH_Ctrl[15].addr[0] = 17;
1356 state->CH_Ctrl[15].bit[0] = 6;
1357 state->CH_Ctrl[15].val[0] = 0;
1358 state->CH_Ctrl[15].addr[1] = 17;
1359 state->CH_Ctrl[15].bit[1] = 7;
1360 state->CH_Ctrl[15].val[1] = 0;
1361 state->CH_Ctrl[15].addr[2] = 16;
1362 state->CH_Ctrl[15].bit[2] = 0;
1363 state->CH_Ctrl[15].val[2] = 0;
1364 state->CH_Ctrl[15].addr[3] = 16;
1365 state->CH_Ctrl[15].bit[3] = 1;
1366 state->CH_Ctrl[15].val[3] = 0;
1367 state->CH_Ctrl[15].addr[4] = 16;
1368 state->CH_Ctrl[15].bit[4] = 2;
1369 state->CH_Ctrl[15].val[4] = 0;
1370 state->CH_Ctrl[15].addr[5] = 16;
1371 state->CH_Ctrl[15].bit[5] = 3;
1372 state->CH_Ctrl[15].val[5] = 0;
1373 state->CH_Ctrl[15].addr[6] = 16;
1374 state->CH_Ctrl[15].bit[6] = 4;
1375 state->CH_Ctrl[15].val[6] = 0;
1376 state->CH_Ctrl[15].addr[7] = 16;
1377 state->CH_Ctrl[15].bit[7] = 5;
1378 state->CH_Ctrl[15].val[7] = 0;
1379 state->CH_Ctrl[15].addr[8] = 16;
1380 state->CH_Ctrl[15].bit[8] = 6;
1381 state->CH_Ctrl[15].val[8] = 0;
1382 state->CH_Ctrl[15].addr[9] = 16;
1383 state->CH_Ctrl[15].bit[9] = 7;
1384 state->CH_Ctrl[15].val[9] = 0;
1385 state->CH_Ctrl[15].addr[10] = 15;
1386 state->CH_Ctrl[15].bit[10] = 0;
1387 state->CH_Ctrl[15].val[10] = 0;
1388 state->CH_Ctrl[15].addr[11] = 15;
1389 state->CH_Ctrl[15].bit[11] = 1;
1390 state->CH_Ctrl[15].val[11] = 0;
1391 state->CH_Ctrl[15].addr[12] = 15;
1392 state->CH_Ctrl[15].bit[12] = 2;
1393 state->CH_Ctrl[15].val[12] = 0;
1394 state->CH_Ctrl[15].addr[13] = 15;
1395 state->CH_Ctrl[15].bit[13] = 3;
1396 state->CH_Ctrl[15].val[13] = 0;
1397 state->CH_Ctrl[15].addr[14] = 15;
1398 state->CH_Ctrl[15].bit[14] = 4;
1399 state->CH_Ctrl[15].val[14] = 0;
1400 state->CH_Ctrl[15].addr[15] = 15;
1401 state->CH_Ctrl[15].bit[15] = 5;
1402 state->CH_Ctrl[15].val[15] = 0;
1403 state->CH_Ctrl[15].addr[16] = 15;
1404 state->CH_Ctrl[15].bit[16] = 6;
1405 state->CH_Ctrl[15].val[16] = 1;
1406 state->CH_Ctrl[15].addr[17] = 15;
1407 state->CH_Ctrl[15].bit[17] = 7;
1408 state->CH_Ctrl[15].val[17] = 1;
1409
1410 state->CH_Ctrl[16].Ctrl_Num = RFSYN_LPF_R ;
1411 state->CH_Ctrl[16].size = 5 ;
1412 state->CH_Ctrl[16].addr[0] = 112;
1413 state->CH_Ctrl[16].bit[0] = 0;
1414 state->CH_Ctrl[16].val[0] = 0;
1415 state->CH_Ctrl[16].addr[1] = 112;
1416 state->CH_Ctrl[16].bit[1] = 1;
1417 state->CH_Ctrl[16].val[1] = 0;
1418 state->CH_Ctrl[16].addr[2] = 112;
1419 state->CH_Ctrl[16].bit[2] = 2;
1420 state->CH_Ctrl[16].val[2] = 0;
1421 state->CH_Ctrl[16].addr[3] = 112;
1422 state->CH_Ctrl[16].bit[3] = 3;
1423 state->CH_Ctrl[16].val[3] = 0;
1424 state->CH_Ctrl[16].addr[4] = 112;
1425 state->CH_Ctrl[16].bit[4] = 4;
1426 state->CH_Ctrl[16].val[4] = 1;
1427
1428 state->CH_Ctrl[17].Ctrl_Num = CHCAL_EN_INT_RF ;
1429 state->CH_Ctrl[17].size = 1 ;
1430 state->CH_Ctrl[17].addr[0] = 14;
1431 state->CH_Ctrl[17].bit[0] = 7;
1432 state->CH_Ctrl[17].val[0] = 0;
1433
1434 state->CH_Ctrl[18].Ctrl_Num = TG_LO_DIVVAL ;
1435 state->CH_Ctrl[18].size = 4 ;
1436 state->CH_Ctrl[18].addr[0] = 107;
1437 state->CH_Ctrl[18].bit[0] = 3;
1438 state->CH_Ctrl[18].val[0] = 0;
1439 state->CH_Ctrl[18].addr[1] = 107;
1440 state->CH_Ctrl[18].bit[1] = 4;
1441 state->CH_Ctrl[18].val[1] = 0;
1442 state->CH_Ctrl[18].addr[2] = 107;
1443 state->CH_Ctrl[18].bit[2] = 5;
1444 state->CH_Ctrl[18].val[2] = 0;
1445 state->CH_Ctrl[18].addr[3] = 107;
1446 state->CH_Ctrl[18].bit[3] = 6;
1447 state->CH_Ctrl[18].val[3] = 0;
1448
1449 state->CH_Ctrl[19].Ctrl_Num = TG_LO_SELVAL ;
1450 state->CH_Ctrl[19].size = 3 ;
1451 state->CH_Ctrl[19].addr[0] = 107;
1452 state->CH_Ctrl[19].bit[0] = 7;
1453 state->CH_Ctrl[19].val[0] = 1;
1454 state->CH_Ctrl[19].addr[1] = 106;
1455 state->CH_Ctrl[19].bit[1] = 0;
1456 state->CH_Ctrl[19].val[1] = 1;
1457 state->CH_Ctrl[19].addr[2] = 106;
1458 state->CH_Ctrl[19].bit[2] = 1;
1459 state->CH_Ctrl[19].val[2] = 1;
1460
1461 state->CH_Ctrl[20].Ctrl_Num = TG_DIV_VAL ;
1462 state->CH_Ctrl[20].size = 11 ;
1463 state->CH_Ctrl[20].addr[0] = 109;
1464 state->CH_Ctrl[20].bit[0] = 2;
1465 state->CH_Ctrl[20].val[0] = 0;
1466 state->CH_Ctrl[20].addr[1] = 109;
1467 state->CH_Ctrl[20].bit[1] = 3;
1468 state->CH_Ctrl[20].val[1] = 0;
1469 state->CH_Ctrl[20].addr[2] = 109;
1470 state->CH_Ctrl[20].bit[2] = 4;
1471 state->CH_Ctrl[20].val[2] = 0;
1472 state->CH_Ctrl[20].addr[3] = 109;
1473 state->CH_Ctrl[20].bit[3] = 5;
1474 state->CH_Ctrl[20].val[3] = 0;
1475 state->CH_Ctrl[20].addr[4] = 109;
1476 state->CH_Ctrl[20].bit[4] = 6;
1477 state->CH_Ctrl[20].val[4] = 0;
1478 state->CH_Ctrl[20].addr[5] = 109;
1479 state->CH_Ctrl[20].bit[5] = 7;
1480 state->CH_Ctrl[20].val[5] = 0;
1481 state->CH_Ctrl[20].addr[6] = 108;
1482 state->CH_Ctrl[20].bit[6] = 0;
1483 state->CH_Ctrl[20].val[6] = 0;
1484 state->CH_Ctrl[20].addr[7] = 108;
1485 state->CH_Ctrl[20].bit[7] = 1;
1486 state->CH_Ctrl[20].val[7] = 0;
1487 state->CH_Ctrl[20].addr[8] = 108;
1488 state->CH_Ctrl[20].bit[8] = 2;
1489 state->CH_Ctrl[20].val[8] = 1;
1490 state->CH_Ctrl[20].addr[9] = 108;
1491 state->CH_Ctrl[20].bit[9] = 3;
1492 state->CH_Ctrl[20].val[9] = 1;
1493 state->CH_Ctrl[20].addr[10] = 108;
1494 state->CH_Ctrl[20].bit[10] = 4;
1495 state->CH_Ctrl[20].val[10] = 1;
1496
1497 state->CH_Ctrl[21].Ctrl_Num = TG_VCO_BIAS ;
1498 state->CH_Ctrl[21].size = 6 ;
1499 state->CH_Ctrl[21].addr[0] = 106;
1500 state->CH_Ctrl[21].bit[0] = 2;
1501 state->CH_Ctrl[21].val[0] = 0;
1502 state->CH_Ctrl[21].addr[1] = 106;
1503 state->CH_Ctrl[21].bit[1] = 3;
1504 state->CH_Ctrl[21].val[1] = 0;
1505 state->CH_Ctrl[21].addr[2] = 106;
1506 state->CH_Ctrl[21].bit[2] = 4;
1507 state->CH_Ctrl[21].val[2] = 0;
1508 state->CH_Ctrl[21].addr[3] = 106;
1509 state->CH_Ctrl[21].bit[3] = 5;
1510 state->CH_Ctrl[21].val[3] = 0;
1511 state->CH_Ctrl[21].addr[4] = 106;
1512 state->CH_Ctrl[21].bit[4] = 6;
1513 state->CH_Ctrl[21].val[4] = 0;
1514 state->CH_Ctrl[21].addr[5] = 106;
1515 state->CH_Ctrl[21].bit[5] = 7;
1516 state->CH_Ctrl[21].val[5] = 1;
1517
1518 state->CH_Ctrl[22].Ctrl_Num = SEQ_EXTPOWERUP ;
1519 state->CH_Ctrl[22].size = 1 ;
1520 state->CH_Ctrl[22].addr[0] = 138;
1521 state->CH_Ctrl[22].bit[0] = 4;
1522 state->CH_Ctrl[22].val[0] = 1;
1523
1524 state->CH_Ctrl[23].Ctrl_Num = OVERRIDE_2 ;
1525 state->CH_Ctrl[23].size = 1 ;
1526 state->CH_Ctrl[23].addr[0] = 17;
1527 state->CH_Ctrl[23].bit[0] = 5;
1528 state->CH_Ctrl[23].val[0] = 0;
1529
1530 state->CH_Ctrl[24].Ctrl_Num = OVERRIDE_3 ;
1531 state->CH_Ctrl[24].size = 1 ;
1532 state->CH_Ctrl[24].addr[0] = 111;
1533 state->CH_Ctrl[24].bit[0] = 3;
1534 state->CH_Ctrl[24].val[0] = 0;
1535
1536 state->CH_Ctrl[25].Ctrl_Num = OVERRIDE_4 ;
1537 state->CH_Ctrl[25].size = 1 ;
1538 state->CH_Ctrl[25].addr[0] = 112;
1539 state->CH_Ctrl[25].bit[0] = 7;
1540 state->CH_Ctrl[25].val[0] = 0;
1541
1542 state->CH_Ctrl[26].Ctrl_Num = SEQ_FSM_PULSE ;
1543 state->CH_Ctrl[26].size = 1 ;
1544 state->CH_Ctrl[26].addr[0] = 136;
1545 state->CH_Ctrl[26].bit[0] = 7;
1546 state->CH_Ctrl[26].val[0] = 0;
1547
1548 state->CH_Ctrl[27].Ctrl_Num = GPIO_4B ;
1549 state->CH_Ctrl[27].size = 1 ;
1550 state->CH_Ctrl[27].addr[0] = 149;
1551 state->CH_Ctrl[27].bit[0] = 7;
1552 state->CH_Ctrl[27].val[0] = 0;
1553
1554 state->CH_Ctrl[28].Ctrl_Num = GPIO_3B ;
1555 state->CH_Ctrl[28].size = 1 ;
1556 state->CH_Ctrl[28].addr[0] = 149;
1557 state->CH_Ctrl[28].bit[0] = 6;
1558 state->CH_Ctrl[28].val[0] = 0;
1559
1560 state->CH_Ctrl[29].Ctrl_Num = GPIO_4 ;
1561 state->CH_Ctrl[29].size = 1 ;
1562 state->CH_Ctrl[29].addr[0] = 149;
1563 state->CH_Ctrl[29].bit[0] = 5;
1564 state->CH_Ctrl[29].val[0] = 1;
1565
1566 state->CH_Ctrl[30].Ctrl_Num = GPIO_3 ;
1567 state->CH_Ctrl[30].size = 1 ;
1568 state->CH_Ctrl[30].addr[0] = 149;
1569 state->CH_Ctrl[30].bit[0] = 4;
1570 state->CH_Ctrl[30].val[0] = 1;
1571
1572 state->CH_Ctrl[31].Ctrl_Num = GPIO_1B ;
1573 state->CH_Ctrl[31].size = 1 ;
1574 state->CH_Ctrl[31].addr[0] = 149;
1575 state->CH_Ctrl[31].bit[0] = 3;
1576 state->CH_Ctrl[31].val[0] = 0;
1577
1578 state->CH_Ctrl[32].Ctrl_Num = DAC_A_ENABLE ;
1579 state->CH_Ctrl[32].size = 1 ;
1580 state->CH_Ctrl[32].addr[0] = 93;
1581 state->CH_Ctrl[32].bit[0] = 1;
1582 state->CH_Ctrl[32].val[0] = 0;
1583
1584 state->CH_Ctrl[33].Ctrl_Num = DAC_B_ENABLE ;
1585 state->CH_Ctrl[33].size = 1 ;
1586 state->CH_Ctrl[33].addr[0] = 93;
1587 state->CH_Ctrl[33].bit[0] = 0;
1588 state->CH_Ctrl[33].val[0] = 0;
1589
1590 state->CH_Ctrl[34].Ctrl_Num = DAC_DIN_A ;
1591 state->CH_Ctrl[34].size = 6 ;
1592 state->CH_Ctrl[34].addr[0] = 92;
1593 state->CH_Ctrl[34].bit[0] = 2;
1594 state->CH_Ctrl[34].val[0] = 0;
1595 state->CH_Ctrl[34].addr[1] = 92;
1596 state->CH_Ctrl[34].bit[1] = 3;
1597 state->CH_Ctrl[34].val[1] = 0;
1598 state->CH_Ctrl[34].addr[2] = 92;
1599 state->CH_Ctrl[34].bit[2] = 4;
1600 state->CH_Ctrl[34].val[2] = 0;
1601 state->CH_Ctrl[34].addr[3] = 92;
1602 state->CH_Ctrl[34].bit[3] = 5;
1603 state->CH_Ctrl[34].val[3] = 0;
1604 state->CH_Ctrl[34].addr[4] = 92;
1605 state->CH_Ctrl[34].bit[4] = 6;
1606 state->CH_Ctrl[34].val[4] = 0;
1607 state->CH_Ctrl[34].addr[5] = 92;
1608 state->CH_Ctrl[34].bit[5] = 7;
1609 state->CH_Ctrl[34].val[5] = 0;
1610
1611 state->CH_Ctrl[35].Ctrl_Num = DAC_DIN_B ;
1612 state->CH_Ctrl[35].size = 6 ;
1613 state->CH_Ctrl[35].addr[0] = 93;
1614 state->CH_Ctrl[35].bit[0] = 2;
1615 state->CH_Ctrl[35].val[0] = 0;
1616 state->CH_Ctrl[35].addr[1] = 93;
1617 state->CH_Ctrl[35].bit[1] = 3;
1618 state->CH_Ctrl[35].val[1] = 0;
1619 state->CH_Ctrl[35].addr[2] = 93;
1620 state->CH_Ctrl[35].bit[2] = 4;
1621 state->CH_Ctrl[35].val[2] = 0;
1622 state->CH_Ctrl[35].addr[3] = 93;
1623 state->CH_Ctrl[35].bit[3] = 5;
1624 state->CH_Ctrl[35].val[3] = 0;
1625 state->CH_Ctrl[35].addr[4] = 93;
1626 state->CH_Ctrl[35].bit[4] = 6;
1627 state->CH_Ctrl[35].val[4] = 0;
1628 state->CH_Ctrl[35].addr[5] = 93;
1629 state->CH_Ctrl[35].bit[5] = 7;
1630 state->CH_Ctrl[35].val[5] = 0;
52c99bda
ST		 1631
1632#ifdef _MXL_PRODUCTION
3935c254
ST		 1633 state->CH_Ctrl[36].Ctrl_Num = RFSYN_EN_DIV ;
1634 state->CH_Ctrl[36].size = 1 ;
1635 state->CH_Ctrl[36].addr[0] = 109;
1636 state->CH_Ctrl[36].bit[0] = 1;
1637 state->CH_Ctrl[36].val[0] = 1;
1638
1639 state->CH_Ctrl[37].Ctrl_Num = RFSYN_DIVM ;
1640 state->CH_Ctrl[37].size = 2 ;
1641 state->CH_Ctrl[37].addr[0] = 112;
1642 state->CH_Ctrl[37].bit[0] = 5;
1643 state->CH_Ctrl[37].val[0] = 0;
1644 state->CH_Ctrl[37].addr[1] = 112;
1645 state->CH_Ctrl[37].bit[1] = 6;
1646 state->CH_Ctrl[37].val[1] = 0;
1647
1648 state->CH_Ctrl[38].Ctrl_Num = DN_BYPASS_AGC_I2C ;
1649 state->CH_Ctrl[38].size = 1 ;
1650 state->CH_Ctrl[38].addr[0] = 65;
1651 state->CH_Ctrl[38].bit[0] = 1;
1652 state->CH_Ctrl[38].val[0] = 0;
52c99bda
ST		 1653#endif
1654
1655 return 0 ;
1656}
1657
52c99bda 1658// MaxLinear source code - MXL5005_c.cpp
52c99bda
ST		 1659// MXL5005.cpp : Defines the initialization routines for the DLL.
1660// 2.6.12
3935c254 1661void InitTunerControls(struct dvb_frontend *fe)
52c99bda 1662{
3935c254
ST		 1663 MXL5005_RegisterInit(fe);
1664 MXL5005_ControlInit(fe);
52c99bda 1665#ifdef _MXL_INTERNAL
3935c254 1666 MXL5005_MXLControlInit(fe);
52c99bda
ST		 1667#endif
1668}
1669
52c99bda
ST		 1670///////////////////////////////////////////////////////////////////////////////
1671// //
1672// Function: MXL_ConfigTuner //
1673// //
1674// Description: Configure MXL5005Tuner structure for desired //
1675// Channel Bandwidth/Channel Frequency //
1676// //
1677// //
1678// Functions used: //
a8214d48 1679// MXL_SynthIFLO_Calc //
52c99bda
ST		 1680// //
1681// Inputs: //
1682// Tuner_struct: structure defined at higher level //
1683// Mode: Tuner Mode (Analog/Digital) //
1684// IF_Mode: IF Mode ( Zero/Low ) //
3935c254 1685// Bandwidth: Filter Channel Bandwidth (in Hz) //
52c99bda
ST		 1686// IF_out: Desired IF out Frequency (in Hz) //
1687// Fxtal: Crystal Frerquency (in Hz) //
3935c254
ST		 1688// TOP: 0: Dual AGC; Value: take over point //
1689// IF_OUT_LOAD: IF out load resistor (200/300 Ohms) //
1690// CLOCK_OUT: 0: Turn off clock out; 1: turn on clock out //
1691// DIV_OUT: 0: Div-1; 1: Div-4 //
1692// CAPSELECT: 0: Disable On-chip pulling cap; 1: Enable //
1693// EN_RSSI: 0: Disable RSSI; 1: Enable RSSI //
52c99bda
ST		 1694// //
1695// Outputs: //
1696// Tuner //
1697// //
1698// Return: //
1699// 0 : Successful //
1700// > 0 : Failed //
1701// //
1702///////////////////////////////////////////////////////////////////////////////
3935c254
ST		 1703u16 MXL5005_TunerConfig(struct dvb_frontend *fe,
1704 u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
1705 u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
1706 u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
1707 u32 IF_out, /* Desired IF Out Frequency */
1708 u32 Fxtal, /* XTAL Frequency */
1709 u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
1710 u16 TOP, /* 0: Dual AGC; Value: take over point */
1711 u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
1712 u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */
1713 u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */
1714 u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
1715 u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
1716 u8 Mod_Type, /* Modulation Type; */
1717 /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
1718 u8 TF_Type /* Tracking Filter */
1719 /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
52c99bda
ST		 1720 )
1721{
85d220d0 1722 struct mxl5005s_state *state = fe->tuner_priv;
3935c254 1723 u16 status = 0;
52c99bda 1724
3935c254
ST		 1725 state->Mode = Mode;
1726 state->IF_Mode = IF_mode;
1727 state->Chan_Bandwidth = Bandwidth;
1728 state->IF_OUT = IF_out;
1729 state->Fxtal = Fxtal;
1730 state->AGC_Mode = AGC_Mode;
1731 state->TOP = TOP;
1732 state->IF_OUT_LOAD = IF_OUT_LOAD;
1733 state->CLOCK_OUT = CLOCK_OUT;
1734 state->DIV_OUT = DIV_OUT;
1735 state->CAPSELECT = CAPSELECT;
1736 state->EN_RSSI = EN_RSSI;
1737 state->Mod_Type = Mod_Type;
1738 state->TF_Type = TF_Type;
52c99bda 1739
a8214d48 1740 /* Initialize all the controls and registers */
3935c254 1741 InitTunerControls(fe);
a8214d48
ST		 1742
1743 /* Synthesizer LO frequency calculation */
3935c254 1744 MXL_SynthIFLO_Calc(fe);
52c99bda 1745
3935c254 1746 return status;
52c99bda
ST		 1747}
1748
1749///////////////////////////////////////////////////////////////////////////////
1750// //
1751// Function: MXL_SynthIFLO_Calc //
1752// //
1753// Description: Calculate Internal IF-LO Frequency //
1754// //
1755// Globals: //
1756// NONE //
1757// //
1758// Functions used: //
1759// NONE //
1760// //
1761// Inputs: //
1762// Tuner_struct: structure defined at higher level //
1763// //
1764// Outputs: //
1765// Tuner //
1766// //
1767// Return: //
1768// 0 : Successful //
1769// > 0 : Failed //
1770// //
1771///////////////////////////////////////////////////////////////////////////////
3935c254 1772void MXL_SynthIFLO_Calc(struct dvb_frontend *fe)
52c99bda 1773{
85d220d0
ST		 1774 struct mxl5005s_state *state = fe->tuner_priv;
1775 if (state->Mode == 1) /* Digital Mode */
3935c254
ST		 1776 state->IF_LO = state->IF_OUT;
1777 else /* Analog Mode */
52c99bda 1778 {
3935c254
ST		 1779 if(state->IF_Mode == 0) /* Analog Zero IF mode */
1780 state->IF_LO = state->IF_OUT + 400000;
1781 else /* Analog Low IF mode */
1782 state->IF_LO = state->IF_OUT + state->Chan_Bandwidth/2;
52c99bda
ST		 1783 }
1784}
1785
1786///////////////////////////////////////////////////////////////////////////////
1787// //
1788// Function: MXL_SynthRFTGLO_Calc //
1789// //
1790// Description: Calculate Internal RF-LO frequency and //
1791// internal Tone-Gen(TG)-LO frequency //
1792// //
1793// Globals: //
1794// NONE //
1795// //
1796// Functions used: //
1797// NONE //
1798// //
1799// Inputs: //
1800// Tuner_struct: structure defined at higher level //
1801// //
1802// Outputs: //
1803// Tuner //
1804// //
1805// Return: //
1806// 0 : Successful //
1807// > 0 : Failed //
1808// //
1809///////////////////////////////////////////////////////////////////////////////
3935c254 1810void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe)
52c99bda 1811{
85d220d0 1812 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 1813
1814 if (state->Mode == 1) /* Digital Mode */ {
52c99bda 1815 //remove 20.48MHz setting for 2.6.10
3935c254
ST		 1816 state->RF_LO = state->RF_IN;
1817 state->TG_LO = state->RF_IN - 750000; //change for 2.6.6
1818 } else /* Analog Mode */ {
1819 if(state->IF_Mode == 0) /* Analog Zero IF mode */ {
1820 state->RF_LO = state->RF_IN - 400000;
1821 state->TG_LO = state->RF_IN - 1750000;
1822 } else /* Analog Low IF mode */ {
1823 state->RF_LO = state->RF_IN - state->Chan_Bandwidth/2;
1824 state->TG_LO = state->RF_IN - state->Chan_Bandwidth + 500000;
52c99bda
ST		 1825 }
1826 }
1827}
1828
1829///////////////////////////////////////////////////////////////////////////////
1830// //
1831// Function: MXL_OverwriteICDefault //
1832// //
1833// Description: Overwrite the Default Register Setting //
1834// //
1835// //
1836// Functions used: //
1837// //
1838// Inputs: //
1839// Tuner_struct: structure defined at higher level //
1840// Outputs: //
1841// Tuner //
1842// //
1843// Return: //
1844// 0 : Successful //
1845// > 0 : Failed //
1846// //
1847///////////////////////////////////////////////////////////////////////////////
3935c254 1848u16 MXL_OverwriteICDefault(struct dvb_frontend *fe)
52c99bda 1849{
3935c254 1850 u16 status = 0;
52c99bda 1851
3935c254
ST		 1852 status += MXL_ControlWrite(fe, OVERRIDE_1, 1);
1853 status += MXL_ControlWrite(fe, OVERRIDE_2, 1);
1854 status += MXL_ControlWrite(fe, OVERRIDE_3, 1);
1855 status += MXL_ControlWrite(fe, OVERRIDE_4, 1);
52c99bda 1856
3935c254 1857 return status;
52c99bda
ST		 1858}
1859
1860///////////////////////////////////////////////////////////////////////////////
1861// //
1862// Function: MXL_BlockInit //
1863// //
1864// Description: Tuner Initialization as a function of 'User Settings' //
1865// * User settings in Tuner strcuture must be assigned //
1866// first //
1867// //
1868// Globals: //
1869// NONE //
1870// //
1871// Functions used: //
1872// Tuner_struct: structure defined at higher level //
1873// //
1874// Inputs: //
1875// Tuner : Tuner structure defined at higher level //
1876// //
1877// Outputs: //
1878// Tuner //
1879// //
1880// Return: //
1881// 0 : Successful //
1882// > 0 : Failed //
1883// //
1884///////////////////////////////////////////////////////////////////////////////
3935c254 1885u16 MXL_BlockInit(struct dvb_frontend *fe)
52c99bda 1886{
85d220d0 1887 struct mxl5005s_state *state = fe->tuner_priv;
3935c254 1888 u16 status = 0;
52c99bda 1889
3935c254 1890 status += MXL_OverwriteICDefault(fe);
52c99bda 1891
3935c254
ST		 1892 /* Downconverter Control Dig Ana */
1893 status += MXL_ControlWrite(fe, DN_IQTN_AMP_CUT, state->Mode ? 1 : 0);
52c99bda 1894
3935c254
ST		 1895 /* Filter Control Dig Ana */
1896 status += MXL_ControlWrite(fe, BB_MODE, state->Mode ? 0 : 1);
1897 status += MXL_ControlWrite(fe, BB_BUF, state->Mode ? 3 : 2);
1898 status += MXL_ControlWrite(fe, BB_BUF_OA, state->Mode ? 1 : 0);
1899 status += MXL_ControlWrite(fe, BB_IQSWAP, state->Mode ? 0 : 1);
1900 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 0);
1901
1902 /* Initialize Low-Pass Filter */
1903 if (state->Mode) { /* Digital Mode */
1904 switch (state->Chan_Bandwidth) {
52c99bda 1905 case 8000000:
3935c254
ST		 1906 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 0);
1907 break;
52c99bda 1908 case 7000000:
3935c254
ST		 1909 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 2);
1910 break;
52c99bda 1911 case 6000000:
48937295 1912 printk("%s() doing 6MHz digital\n", __func__);
3935c254
ST		 1913 status += MXL_ControlWrite(fe, BB_DLPF_BANDSEL, 3);
1914 break;
1915 }
1916 } else { /* Analog Mode */
1917 switch (state->Chan_Bandwidth) {
1918 case 8000000: /* Low Zero */
1919 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 0 : 3));
1920 break;
52c99bda 1921 case 7000000:
3935c254
ST		 1922 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 1 : 4));
1923 break;
52c99bda 1924 case 6000000:
3935c254
ST		 1925 status += MXL_ControlWrite(fe, BB_ALPF_BANDSELECT, (state->IF_Mode ? 2 : 5));
1926 break;
52c99bda
ST		 1927 }
1928 }
1929
3935c254
ST		 1930 /* Charge Pump Control Dig Ana */
1931 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, state->Mode ? 5 : 8);
1932 status += MXL_ControlWrite(fe, RFSYN_EN_CHP_HIGAIN, state->Mode ? 1 : 1);
1933 status += MXL_ControlWrite(fe, EN_CHP_LIN_B, state->Mode ? 0 : 0);
52c99bda 1934
3935c254
ST		 1935 /* AGC TOP Control */
1936 if (state->AGC_Mode == 0) /* Dual AGC */ {
1937 status += MXL_ControlWrite(fe, AGC_IF, 15);
1938 status += MXL_ControlWrite(fe, AGC_RF, 15);
52c99bda 1939 }
3935c254
ST		 1940 else /* Single AGC Mode Dig Ana */
1941 status += MXL_ControlWrite(fe, AGC_RF, state->Mode ? 15 : 12);
52c99bda 1942
3935c254
ST		 1943 if (state->TOP == 55) /* TOP == 5.5 */
1944 status += MXL_ControlWrite(fe, AGC_IF, 0x0);
52c99bda 1945
3935c254
ST		 1946 if (state->TOP == 72) /* TOP == 7.2 */
1947 status += MXL_ControlWrite(fe, AGC_IF, 0x1);
52c99bda 1948
3935c254
ST		 1949 if (state->TOP == 92) /* TOP == 9.2 */
1950 status += MXL_ControlWrite(fe, AGC_IF, 0x2);
52c99bda 1951
3935c254
ST		 1952 if (state->TOP == 110) /* TOP == 11.0 */
1953 status += MXL_ControlWrite(fe, AGC_IF, 0x3);
52c99bda 1954
3935c254
ST		 1955 if (state->TOP == 129) /* TOP == 12.9 */
1956 status += MXL_ControlWrite(fe, AGC_IF, 0x4);
52c99bda 1957
3935c254
ST		 1958 if (state->TOP == 147) /* TOP == 14.7 */
1959 status += MXL_ControlWrite(fe, AGC_IF, 0x5);
52c99bda 1960
3935c254
ST		 1961 if (state->TOP == 168) /* TOP == 16.8 */
1962 status += MXL_ControlWrite(fe, AGC_IF, 0x6);
52c99bda 1963
3935c254
ST		 1964 if (state->TOP == 194) /* TOP == 19.4 */
1965 status += MXL_ControlWrite(fe, AGC_IF, 0x7);
52c99bda 1966
3935c254
ST		 1967 if (state->TOP == 212) /* TOP == 21.2 */
1968 status += MXL_ControlWrite(fe, AGC_IF, 0x9);
52c99bda 1969
3935c254
ST		 1970 if (state->TOP == 232) /* TOP == 23.2 */
1971 status += MXL_ControlWrite(fe, AGC_IF, 0xA);
52c99bda 1972
3935c254
ST		 1973 if (state->TOP == 252) /* TOP == 25.2 */
1974 status += MXL_ControlWrite(fe, AGC_IF, 0xB);
52c99bda 1975
3935c254
ST		 1976 if (state->TOP == 271) /* TOP == 27.1 */
1977 status += MXL_ControlWrite(fe, AGC_IF, 0xC);
52c99bda 1978
3935c254
ST		 1979 if (state->TOP == 292) /* TOP == 29.2 */
1980 status += MXL_ControlWrite(fe, AGC_IF, 0xD);
52c99bda 1981
3935c254
ST		 1982 if (state->TOP == 317) /* TOP == 31.7 */
1983 status += MXL_ControlWrite(fe, AGC_IF, 0xE);
52c99bda 1984
3935c254
ST		 1985 if (state->TOP == 349) /* TOP == 34.9 */
1986 status += MXL_ControlWrite(fe, AGC_IF, 0xF);
52c99bda 1987
3935c254
ST		 1988 /* IF Synthesizer Control */
1989 status += MXL_IFSynthInit(fe);
52c99bda 1990
3935c254
ST		 1991 /* IF UpConverter Control */
1992 if (state->IF_OUT_LOAD == 200) {
1993 status += MXL_ControlWrite(fe, DRV_RES_SEL, 6);
1994 status += MXL_ControlWrite(fe, I_DRIVER, 2);
52c99bda 1995 }
3935c254
ST		 1996 if (state->IF_OUT_LOAD == 300) {
1997 status += MXL_ControlWrite(fe, DRV_RES_SEL, 4);
1998 status += MXL_ControlWrite(fe, I_DRIVER, 1);
52c99bda
ST		 1999 }
2000
3935c254
ST		 2001 /* Anti-Alias Filtering Control
2002 * initialise Anti-Aliasing Filter
2003 */
2004 if (state->Mode) { /* Digital Mode */
2005 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 6280000UL) {
2006 status += MXL_ControlWrite(fe, EN_AAF, 1);
2007 status += MXL_ControlWrite(fe, EN_3P, 1);
2008 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2009 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
2010 }
2011 if ((state->IF_OUT == 36125000UL) || (state->IF_OUT == 36150000UL)) {
2012 status += MXL_ControlWrite(fe, EN_AAF, 1);
2013 status += MXL_ControlWrite(fe, EN_3P, 1);
2014 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2015 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
2016 }
2017 if (state->IF_OUT > 36150000UL) {
2018 status += MXL_ControlWrite(fe, EN_AAF, 0);
2019 status += MXL_ControlWrite(fe, EN_3P, 1);
2020 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2021 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 1);
2022 }
2023 } else { /* Analog Mode */
2024 if (state->IF_OUT >= 4000000UL && state->IF_OUT <= 5000000UL)
52c99bda 2025 {
3935c254
ST		 2026 status += MXL_ControlWrite(fe, EN_AAF, 1);
2027 status += MXL_ControlWrite(fe, EN_3P, 1);
2028 status += MXL_ControlWrite(fe, EN_AUX_3P, 1);
2029 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
52c99bda 2030 }
3935c254 2031 if (state->IF_OUT > 5000000UL)
52c99bda 2032 {
3935c254
ST		 2033 status += MXL_ControlWrite(fe, EN_AAF, 0);
2034 status += MXL_ControlWrite(fe, EN_3P, 0);
2035 status += MXL_ControlWrite(fe, EN_AUX_3P, 0);
2036 status += MXL_ControlWrite(fe, SEL_AAF_BAND, 0);
52c99bda
ST		 2037 }
2038 }
2039
3935c254
ST		 2040 /* Demod Clock Out */
2041 if (state->CLOCK_OUT)
2042 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 1);
52c99bda 2043 else
3935c254 2044 status += MXL_ControlWrite(fe, SEQ_ENCLK16_CLK_OUT, 0);
52c99bda 2045
3935c254
ST		 2046 if (state->DIV_OUT == 1)
2047 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 1);
2048 if (state->DIV_OUT == 0)
2049 status += MXL_ControlWrite(fe, SEQ_SEL4_16B, 0);
52c99bda 2050
3935c254
ST		 2051 /* Crystal Control */
2052 if (state->CAPSELECT)
2053 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 1);
52c99bda 2054 else
3935c254 2055 status += MXL_ControlWrite(fe, XTAL_CAPSELECT, 0);
52c99bda 2056
3935c254
ST		 2057 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
2058 status += MXL_ControlWrite(fe, IF_SEL_DBL, 1);
2059 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
2060 status += MXL_ControlWrite(fe, IF_SEL_DBL, 0);
52c99bda 2061
3935c254
ST		 2062 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2063 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 3);
2064 if (state->Fxtal > 22000000UL && state->Fxtal <= 32000000UL)
2065 status += MXL_ControlWrite(fe, RFSYN_R_DIV, 0);
52c99bda 2066
3935c254 2067 /* Misc Controls */
85d220d0 2068 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog LowIF mode */
3935c254 2069 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 0);
52c99bda 2070 else
3935c254 2071 status += MXL_ControlWrite(fe, SEQ_EXTIQFSMPULSE, 1);
52c99bda 2072
3935c254 2073 /* status += MXL_ControlRead(fe, IF_DIVVAL, &IF_DIVVAL_Val); */
52c99bda 2074
3935c254
ST		 2075 /* Set TG_R_DIV */
2076 status += MXL_ControlWrite(fe, TG_R_DIV, MXL_Ceiling(state->Fxtal, 1000000));
52c99bda 2077
3935c254 2078 /* Apply Default value to BB_INITSTATE_DLPF_TUNE */
52c99bda 2079
3935c254
ST		 2080 /* RSSI Control */
2081 if (state->EN_RSSI)
52c99bda 2082 {
3935c254
ST		 2083 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2084 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2085 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2086 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2087
2088 /* RSSI reference point */
2089 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2090 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 3);
2091 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2092
2093 /* TOP point */
2094 status += MXL_ControlWrite(fe, RFA_FLR, 0);
2095 status += MXL_ControlWrite(fe, RFA_CEIL, 12);
52c99bda
ST		 2096 }
2097
3935c254
ST		 2098 /* Modulation type bit settings
2099 * Override the control values preset
2100 */
2101 if (state->Mod_Type == MXL_DVBT) /* DVB-T Mode */
52c99bda 2102 {
3935c254
ST		 2103 state->AGC_Mode = 1; /* Single AGC Mode */
2104
2105 /* Enable RSSI */
2106 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2107 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2108 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2109 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2110
2111 /* RSSI reference point */
2112 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2113 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2114 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2115
2116 /* TOP point */
2117 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2118 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2119 if (state->IF_OUT <= 6280000UL) /* Low IF */
2120 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2121 else /* High IF */
2122 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda
ST		 2123
2124 }
3935c254 2125 if (state->Mod_Type == MXL_ATSC) /* ATSC Mode */
52c99bda 2126 {
85d220d0 2127 state->AGC_Mode = 1; /* Single AGC Mode */
3935c254
ST		 2128
2129 /* Enable RSSI */
2130 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2131 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2132 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2133 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2134
2135 /* RSSI reference point */
2136 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 2);
2137 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 4);
2138 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 1);
2139
2140 /* TOP point */
2141 status += MXL_ControlWrite(fe, RFA_FLR, 2);
2142 status += MXL_ControlWrite(fe, RFA_CEIL, 13);
2143 status += MXL_ControlWrite(fe, BB_INITSTATE_DLPF_TUNE, 1);
2144 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5); /* Low Zero */
2145 if (state->IF_OUT <= 6280000UL) /* Low IF */
2146 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2147 else /* High IF */
2148 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda 2149 }
3935c254 2150 if (state->Mod_Type == MXL_QAM) /* QAM Mode */
52c99bda 2151 {
3935c254
ST		 2152 state->Mode = MXL_DIGITAL_MODE;
2153
2154 /* state->AGC_Mode = 1; */ /* Single AGC Mode */
2155
2156 /* Disable RSSI */ /* change here for v2.6.5 */
2157 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2158 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2159 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2160 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2161
2162 /* RSSI reference point */
2163 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2164 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2165 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2166 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3); /* change here for v2.6.5 */
2167
2168 if (state->IF_OUT <= 6280000UL) /* Low IF */
2169 status += MXL_ControlWrite(fe, BB_IQSWAP, 0);
2170 else /* High IF */
2171 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
48937295
ST		 2172 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2);
2173
52c99bda 2174 }
3935c254
ST		 2175 if (state->Mod_Type == MXL_ANALOG_CABLE) {
2176 /* Analog Cable Mode */
85d220d0 2177 /* state->Mode = MXL_DIGITAL_MODE; */
3935c254
ST		 2178
2179 state->AGC_Mode = 1; /* Single AGC Mode */
2180
2181 /* Disable RSSI */
2182 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2183 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2184 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2185 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2186 status += MXL_ControlWrite(fe, AGC_IF, 1); /* change for 2.6.3 */
2187 status += MXL_ControlWrite(fe, AGC_RF, 15);
2188 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda
ST		 2189 }
2190
3935c254
ST		 2191 if (state->Mod_Type == MXL_ANALOG_OTA) {
2192 /* Analog OTA Terrestrial mode add for 2.6.7 */
2193 /* state->Mode = MXL_ANALOG_MODE; */
2194
2195 /* Enable RSSI */
2196 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2197 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2198 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1);
2199 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
2200
2201 /* RSSI reference point */
2202 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5);
2203 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3);
2204 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2);
2205 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3);
2206 status += MXL_ControlWrite(fe, BB_IQSWAP, 1);
52c99bda
ST		 2207 }
2208
3935c254 2209 /* RSSI disable */
48937295 2210 if(state->EN_RSSI == 0) {
3935c254
ST		 2211 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1);
2212 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1);
2213 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0);
2214 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1);
52c99bda
ST		 2215 }
2216
3935c254 2217 return status;
52c99bda
ST		 2218}
2219
2220///////////////////////////////////////////////////////////////////////////////
2221// //
2222// Function: MXL_IFSynthInit //
2223// //
2224// Description: Tuner IF Synthesizer related register initialization //
2225// //
2226// Globals: //
2227// NONE //
2228// //
2229// Functions used: //
2230// Tuner_struct: structure defined at higher level //
2231// //
2232// Inputs: //
2233// Tuner : Tuner structure defined at higher level //
2234// //
2235// Outputs: //
2236// Tuner //
2237// //
2238// Return: //
2239// 0 : Successful //
2240// > 0 : Failed //
2241// //
2242///////////////////////////////////////////////////////////////////////////////
85d220d0 2243u16 MXL_IFSynthInit(struct dvb_frontend *fe)
52c99bda 2244{
85d220d0 2245 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48 2246 u16 status = 0 ;
52c99bda 2247 // Declare Local Variables
a8214d48
ST		 2248 u32 Fref = 0 ;
2249 u32 Kdbl, intModVal ;
2250 u32 fracModVal ;
52c99bda
ST		 2251 Kdbl = 2 ;
2252
3935c254 2253 if (state->Fxtal >= 12000000UL && state->Fxtal <= 16000000UL)
52c99bda 2254 Kdbl = 2 ;
3935c254 2255 if (state->Fxtal > 16000000UL && state->Fxtal <= 32000000UL)
52c99bda
ST		 2256 Kdbl = 1 ;
2257
2258 //
2259 // IF Synthesizer Control
2260 //
85d220d0 2261 if (state->Mode == 0 && state->IF_Mode == 1) // Analog Low IF mode
52c99bda 2262 {
85d220d0 2263 if (state->IF_LO == 41000000UL) {
3935c254
ST		 2264 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2265 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2266 Fref = 328000000UL ;
2267 }
85d220d0 2268 if (state->IF_LO == 47000000UL) {
3935c254
ST		 2269 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2270 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2271 Fref = 376000000UL ;
2272 }
85d220d0 2273 if (state->IF_LO == 54000000UL) {
3935c254
ST		 2274 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2275 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2276 Fref = 324000000UL ;
2277 }
85d220d0 2278 if (state->IF_LO == 60000000UL) {
3935c254
ST		 2279 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2280 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2281 Fref = 360000000UL ;
2282 }
85d220d0 2283 if (state->IF_LO == 39250000UL) {
3935c254
ST		 2284 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2285 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2286 Fref = 314000000UL ;
2287 }
85d220d0 2288 if (state->IF_LO == 39650000UL) {
3935c254
ST		 2289 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2290 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2291 Fref = 317200000UL ;
2292 }
85d220d0 2293 if (state->IF_LO == 40150000UL) {
3935c254
ST		 2294 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2295 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2296 Fref = 321200000UL ;
2297 }
85d220d0 2298 if (state->IF_LO == 40650000UL) {
3935c254
ST		 2299 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2300 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2301 Fref = 325200000UL ;
2302 }
2303 }
2304
85d220d0 2305 if (state->Mode || (state->Mode == 0 && state->IF_Mode == 0))
52c99bda 2306 {
85d220d0 2307 if (state->IF_LO == 57000000UL) {
3935c254
ST		 2308 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2309 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2310 Fref = 342000000UL ;
2311 }
85d220d0 2312 if (state->IF_LO == 44000000UL) {
3935c254
ST		 2313 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2314 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2315 Fref = 352000000UL ;
2316 }
85d220d0 2317 if (state->IF_LO == 43750000UL) {
3935c254
ST		 2318 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2319 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2320 Fref = 350000000UL ;
2321 }
85d220d0 2322 if (state->IF_LO == 36650000UL) {
3935c254
ST		 2323 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2324 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2325 Fref = 366500000UL ;
2326 }
85d220d0 2327 if (state->IF_LO == 36150000UL) {
3935c254
ST		 2328 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2329 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2330 Fref = 361500000UL ;
2331 }
85d220d0 2332 if (state->IF_LO == 36000000UL) {
3935c254
ST		 2333 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2334 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2335 Fref = 360000000UL ;
2336 }
85d220d0 2337 if (state->IF_LO == 35250000UL) {
3935c254
ST		 2338 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2339 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2340 Fref = 352500000UL ;
2341 }
85d220d0 2342 if (state->IF_LO == 34750000UL) {
3935c254
ST		 2343 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2344 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2345 Fref = 347500000UL ;
2346 }
85d220d0 2347 if (state->IF_LO == 6280000UL) {
3935c254
ST		 2348 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2349 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2350 Fref = 376800000UL ;
2351 }
85d220d0 2352 if (state->IF_LO == 5000000UL) {
3935c254
ST		 2353 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2354 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2355 Fref = 360000000UL ;
2356 }
85d220d0 2357 if (state->IF_LO == 4500000UL) {
3935c254
ST		 2358 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2359 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2360 Fref = 360000000UL ;
2361 }
85d220d0 2362 if (state->IF_LO == 4570000UL) {
3935c254
ST		 2363 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2364 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2365 Fref = 365600000UL ;
2366 }
85d220d0 2367 if (state->IF_LO == 4000000UL) {
3935c254
ST		 2368 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ;
2369 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2370 Fref = 360000000UL ;
2371 }
85d220d0 2372 if (state->IF_LO == 57400000UL)
52c99bda 2373 {
3935c254
ST		 2374 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x10) ;
2375 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2376 Fref = 344400000UL ;
2377 }
85d220d0 2378 if (state->IF_LO == 44400000UL)
52c99bda 2379 {
3935c254
ST		 2380 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2381 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2382 Fref = 355200000UL ;
2383 }
85d220d0 2384 if (state->IF_LO == 44150000UL)
52c99bda 2385 {
3935c254
ST		 2386 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x08) ;
2387 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2388 Fref = 353200000UL ;
2389 }
85d220d0 2390 if (state->IF_LO == 37050000UL)
52c99bda 2391 {
3935c254
ST		 2392 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2393 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2394 Fref = 370500000UL ;
2395 }
85d220d0 2396 if (state->IF_LO == 36550000UL)
52c99bda 2397 {
3935c254
ST		 2398 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2399 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2400 Fref = 365500000UL ;
2401 }
85d220d0 2402 if (state->IF_LO == 36125000UL) {
3935c254
ST		 2403 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x04) ;
2404 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2405 Fref = 361250000UL ;
2406 }
85d220d0 2407 if (state->IF_LO == 6000000UL) {
3935c254
ST		 2408 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2409 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2410 Fref = 360000000UL ;
2411 }
85d220d0 2412 if (state->IF_LO == 5400000UL)
52c99bda 2413 {
3935c254
ST		 2414 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2415 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2416 Fref = 324000000UL ;
2417 }
85d220d0 2418 if (state->IF_LO == 5380000UL) {
48937295 2419 printk("%s() doing 5.38\n", __func__);
3935c254
ST		 2420 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x07) ;
2421 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x0C) ;
52c99bda
ST		 2422 Fref = 322800000UL ;
2423 }
85d220d0 2424 if (state->IF_LO == 5200000UL) {
3935c254
ST		 2425 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2426 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2427 Fref = 374400000UL ;
2428 }
85d220d0 2429 if (state->IF_LO == 4900000UL)
52c99bda 2430 {
3935c254
ST		 2431 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x09) ;
2432 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2433 Fref = 352800000UL ;
2434 }
85d220d0 2435 if (state->IF_LO == 4400000UL)
52c99bda 2436 {
3935c254
ST		 2437 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x06) ;
2438 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2439 Fref = 352000000UL ;
2440 }
85d220d0 2441 if (state->IF_LO == 4063000UL) //add for 2.6.8
52c99bda 2442 {
3935c254
ST		 2443 status += MXL_ControlWrite(fe, IF_DIVVAL, 0x05) ;
2444 status += MXL_ControlWrite(fe, IF_VCO_BIAS, 0x08) ;
52c99bda
ST		 2445 Fref = 365670000UL ;
2446 }
2447 }
2448 // CHCAL_INT_MOD_IF
2449 // CHCAL_FRAC_MOD_IF
3935c254
ST		 2450 intModVal = Fref / (state->Fxtal * Kdbl/2) ;
2451 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_IF, intModVal ) ;
52c99bda 2452
3935c254
ST		 2453 fracModVal = (2<<15)*(Fref/1000 - (state->Fxtal/1000 * Kdbl/2) * intModVal);
2454 fracModVal = fracModVal / ((state->Fxtal * Kdbl/2)/1000) ;
2455 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_IF, fracModVal) ;
52c99bda 2456
52c99bda
ST		 2457 return status ;
2458}
2459
2460///////////////////////////////////////////////////////////////////////////////
2461// //
2462// Function: MXL_GetXtalInt //
2463// //
a8214d48
ST		 2464// Description: return the Crystal Integration Value for //
2465// TG_VCO_BIAS calculation //
52c99bda
ST		 2466// //
2467// Globals: //
2468// NONE //
2469// //
2470// Functions used: //
a8214d48 2471// NONE //
52c99bda
ST		 2472// //
2473// Inputs: //
2474// Crystal Frequency Value in Hz //
2475// //
2476// Outputs: //
2477// Calculated Crystal Frequency Integration Value //
2478// //
2479// Return: //
2480// 0 : Successful //
2481// > 0 : Failed //
2482// //
2483///////////////////////////////////////////////////////////////////////////////
a8214d48 2484u32 MXL_GetXtalInt(u32 Xtal_Freq)
52c99bda
ST		 2485{
2486 if ((Xtal_Freq % 1000000) == 0)
2487 return (Xtal_Freq / 10000) ;
2488 else
2489 return (((Xtal_Freq / 1000000) + 1)*100) ;
2490}
2491
2492///////////////////////////////////////////////////////////////////////////////
2493// //
2494// Function: MXL5005_TuneRF //
2495// //
2496// Description: Set control names to tune to requested RF_IN frequency //
2497// //
2498// Globals: //
2499// None //
2500// //
2501// Functions used: //
2502// MXL_SynthRFTGLO_Calc //
2503// MXL5005_ControlWrite //
3935c254 2504// MXL_GetXtalInt //
52c99bda
ST		 2505// //
2506// Inputs: //
2507// Tuner : Tuner structure defined at higher level //
2508// //
2509// Outputs: //
2510// Tuner //
2511// //
2512// Return: //
2513// 0 : Successful //
2514// 1 : Unsuccessful //
2515///////////////////////////////////////////////////////////////////////////////
3935c254 2516u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq)
52c99bda 2517{
85d220d0 2518 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda 2519 // Declare Local Variables
3935c254
ST		 2520 u16 status = 0;
2521 u32 divider_val, E3, E4, E5, E5A;
2522 u32 Fmax, Fmin, FmaxBin, FminBin;
a8214d48 2523 u32 Kdbl_RF = 2;
3935c254
ST		 2524 u32 tg_divval;
2525 u32 tg_lo;
2526 u32 Xtal_Int;
52c99bda 2527
a8214d48
ST		 2528 u32 Fref_TG;
2529 u32 Fvco;
2530// u32 temp;
52c99bda
ST		 2531
2532
3935c254 2533 Xtal_Int = MXL_GetXtalInt(state->Fxtal);
52c99bda 2534
3935c254 2535 state->RF_IN = RF_Freq;
52c99bda 2536
3935c254 2537 MXL_SynthRFTGLO_Calc(fe);
52c99bda 2538
3935c254
ST		 2539 if (state->Fxtal >= 12000000UL && state->Fxtal <= 22000000UL)
2540 Kdbl_RF = 2;
2541 if (state->Fxtal > 22000000 && state->Fxtal <= 32000000)
2542 Kdbl_RF = 1;
52c99bda
ST		 2543
2544 //
2545 // Downconverter Controls
2546 //
2547 // Look-Up Table Implementation for:
2548 // DN_POLY
2549 // DN_RFGAIN
2550 // DN_CAP_RFLPF
2551 // DN_EN_VHFUHFBAR
2552 // DN_GAIN_ADJUST
2553 // Change the boundary reference from RF_IN to RF_LO
3935c254 2554 if (state->RF_LO < 40000000UL) {
52c99bda
ST		 2555 return -1;
2556 }
3935c254 2557 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
52c99bda 2558 // Look-Up Table implementation
3935c254
ST		 2559 status += MXL_ControlWrite(fe, DN_POLY, 2);
2560 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2561 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 423);
2562 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2563 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
52c99bda 2564 }
3935c254 2565 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
52c99bda 2566 // Look-Up Table implementation
3935c254
ST		 2567 status += MXL_ControlWrite(fe, DN_POLY, 3);
2568 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2569 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 222);
2570 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2571 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 1);
52c99bda 2572 }
3935c254 2573 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
52c99bda 2574 // Look-Up Table implementation
3935c254
ST		 2575 status += MXL_ControlWrite(fe, DN_POLY, 3);
2576 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2577 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 147);
2578 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2579 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
52c99bda 2580 }
3935c254 2581 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
52c99bda 2582 // Look-Up Table implementation
3935c254
ST		 2583 status += MXL_ControlWrite(fe, DN_POLY, 3);
2584 status += MXL_ControlWrite(fe, DN_RFGAIN, 3);
2585 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 9);
2586 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1);
2587 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 2);
52c99bda 2588 }
3935c254 2589 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
52c99bda 2590 // Look-Up Table implementation
3935c254
ST		 2591 status += MXL_ControlWrite(fe, DN_POLY, 3) ;
2592 status += MXL_ControlWrite(fe, DN_RFGAIN, 3) ;
2593 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ;
2594 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 1) ;
2595 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
52c99bda 2596 }
3935c254 2597 if (state->RF_LO > 300000000UL && state->RF_LO <= 650000000UL) {
52c99bda 2598 // Look-Up Table implementation
3935c254
ST		 2599 status += MXL_ControlWrite(fe, DN_POLY, 3) ;
2600 status += MXL_ControlWrite(fe, DN_RFGAIN, 1) ;
2601 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ;
2602 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ;
2603 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
52c99bda 2604 }
3935c254 2605 if (state->RF_LO > 650000000UL && state->RF_LO <= 900000000UL) {
52c99bda 2606 // Look-Up Table implementation
3935c254
ST		 2607 status += MXL_ControlWrite(fe, DN_POLY, 3) ;
2608 status += MXL_ControlWrite(fe, DN_RFGAIN, 2) ;
2609 status += MXL_ControlWrite(fe, DN_CAP_RFLPF, 0) ;
2610 status += MXL_ControlWrite(fe, DN_EN_VHFUHFBAR, 0) ;
2611 status += MXL_ControlWrite(fe, DN_GAIN_ADJUST, 3) ;
52c99bda 2612 }
3935c254 2613 if (state->RF_LO > 900000000UL) {
52c99bda
ST		 2614 return -1;
2615 }
2616 // DN_IQTNBUF_AMP
2617 // DN_IQTNGNBFBIAS_BST
3935c254
ST		 2618 if (state->RF_LO >= 40000000UL && state->RF_LO <= 75000000UL) {
2619 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2620 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2621 }
3935c254
ST		 2622 if (state->RF_LO > 75000000UL && state->RF_LO <= 100000000UL) {
2623 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2624 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2625 }
3935c254
ST		 2626 if (state->RF_LO > 100000000UL && state->RF_LO <= 150000000UL) {
2627 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2628 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2629 }
3935c254
ST		 2630 if (state->RF_LO > 150000000UL && state->RF_LO <= 200000000UL) {
2631 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2632 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2633 }
3935c254
ST		 2634 if (state->RF_LO > 200000000UL && state->RF_LO <= 300000000UL) {
2635 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2636 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2637 }
3935c254
ST		 2638 if (state->RF_LO > 300000000UL && state->RF_LO <= 400000000UL) {
2639 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2640 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2641 }
3935c254
ST		 2642 if (state->RF_LO > 400000000UL && state->RF_LO <= 450000000UL) {
2643 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2644 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2645 }
3935c254
ST		 2646 if (state->RF_LO > 450000000UL && state->RF_LO <= 500000000UL) {
2647 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2648 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2649 }
3935c254
ST		 2650 if (state->RF_LO > 500000000UL && state->RF_LO <= 550000000UL) {
2651 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2652 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2653 }
3935c254
ST		 2654 if (state->RF_LO > 550000000UL && state->RF_LO <= 600000000UL) {
2655 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2656 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2657 }
3935c254
ST		 2658 if (state->RF_LO > 600000000UL && state->RF_LO <= 650000000UL) {
2659 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2660 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2661 }
3935c254
ST		 2662 if (state->RF_LO > 650000000UL && state->RF_LO <= 700000000UL) {
2663 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2664 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2665 }
3935c254
ST		 2666 if (state->RF_LO > 700000000UL && state->RF_LO <= 750000000UL) {
2667 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2668 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2669 }
3935c254
ST		 2670 if (state->RF_LO > 750000000UL && state->RF_LO <= 800000000UL) {
2671 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 1);
2672 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 0);
52c99bda 2673 }
3935c254
ST		 2674 if (state->RF_LO > 800000000UL && state->RF_LO <= 850000000UL) {
2675 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2676 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
52c99bda 2677 }
3935c254
ST		 2678 if (state->RF_LO > 850000000UL && state->RF_LO <= 900000000UL) {
2679 status += MXL_ControlWrite(fe, DN_IQTNBUF_AMP, 10);
2680 status += MXL_ControlWrite(fe, DN_IQTNGNBFBIAS_BST, 1);
52c99bda
ST		 2681 }
2682
2683 //
2684 // Set RF Synth and LO Path Control
2685 //
2686 // Look-Up table implementation for:
2687 // RFSYN_EN_OUTMUX
2688 // RFSYN_SEL_VCO_OUT
2689 // RFSYN_SEL_VCO_HI
2690 // RFSYN_SEL_DIVM
2691 // RFSYN_RF_DIV_BIAS
2692 // DN_SEL_FREQ
2693 //
2694 // Set divider_val, Fmax, Fmix to use in Equations
2695 FminBin = 28000000UL ;
2696 FmaxBin = 42500000UL ;
3935c254
ST		 2697 if (state->RF_LO >= 40000000UL && state->RF_LO <= FmaxBin) {
2698 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2699 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2700 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
2701 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2702 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2703 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
52c99bda
ST		 2704 divider_val = 64 ;
2705 Fmax = FmaxBin ;
2706 Fmin = FminBin ;
2707 }
2708 FminBin = 42500000UL ;
2709 FmaxBin = 56000000UL ;
3935c254
ST		 2710 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2711 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1);
2712 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0);
2713 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
2714 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
2715 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
2716 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1);
52c99bda
ST		 2717 divider_val = 64 ;
2718 Fmax = FmaxBin ;
2719 Fmin = FminBin ;
2720 }
2721 FminBin = 56000000UL ;
2722 FmaxBin = 85000000UL ;
3935c254
ST		 2723 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2724 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2725 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2726 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2727 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2728 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2729 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ;
52c99bda
ST		 2730 divider_val = 32 ;
2731 Fmax = FmaxBin ;
2732 Fmin = FminBin ;
2733 }
2734 FminBin = 85000000UL ;
2735 FmaxBin = 112000000UL ;
3935c254
ST		 2736 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2737 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2738 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2739 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2740 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2741 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2742 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 1) ;
52c99bda
ST		 2743 divider_val = 32 ;
2744 Fmax = FmaxBin ;
2745 Fmin = FminBin ;
2746 }
2747 FminBin = 112000000UL ;
2748 FmaxBin = 170000000UL ;
3935c254
ST		 2749 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2750 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2751 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2752 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2753 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2754 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2755 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ;
52c99bda
ST		 2756 divider_val = 16 ;
2757 Fmax = FmaxBin ;
2758 Fmin = FminBin ;
2759 }
2760 FminBin = 170000000UL ;
2761 FmaxBin = 225000000UL ;
3935c254
ST		 2762 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2763 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2764 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2765 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2766 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2767 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2768 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 2) ;
52c99bda
ST		 2769 divider_val = 16 ;
2770 Fmax = FmaxBin ;
2771 Fmin = FminBin ;
2772 }
2773 FminBin = 225000000UL ;
2774 FmaxBin = 300000000UL ;
3935c254
ST		 2775 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2776 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2777 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2778 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2779 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2780 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2781 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 4) ;
52c99bda
ST		 2782 divider_val = 8 ;
2783 Fmax = 340000000UL ;
2784 Fmin = FminBin ;
2785 }
2786 FminBin = 300000000UL ;
2787 FmaxBin = 340000000UL ;
3935c254
ST		 2788 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2789 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ;
2790 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ;
2791 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2792 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2793 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2794 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2795 divider_val = 8 ;
2796 Fmax = FmaxBin ;
2797 Fmin = 225000000UL ;
2798 }
2799 FminBin = 340000000UL ;
2800 FmaxBin = 450000000UL ;
3935c254
ST		 2801 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2802 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 1) ;
2803 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 0) ;
2804 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2805 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0) ;
2806 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 2) ;
2807 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2808 divider_val = 8 ;
2809 Fmax = FmaxBin ;
2810 Fmin = FminBin ;
2811 }
2812 FminBin = 450000000UL ;
2813 FmaxBin = 680000000UL ;
3935c254
ST		 2814 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2815 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2816 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2817 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0) ;
2818 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ;
2819 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2820 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2821 divider_val = 4 ;
2822 Fmax = FmaxBin ;
2823 Fmin = FminBin ;
2824 }
2825 FminBin = 680000000UL ;
2826 FmaxBin = 900000000UL ;
3935c254
ST		 2827 if (state->RF_LO > FminBin && state->RF_LO <= FmaxBin) {
2828 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0) ;
2829 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1) ;
2830 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1) ;
2831 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 1) ;
2832 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1) ;
2833 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0) ;
52c99bda
ST		 2834 divider_val = 4 ;
2835 Fmax = FmaxBin ;
2836 Fmin = FminBin ;
2837 }
2838
2839 // CHCAL_INT_MOD_RF
2840 // CHCAL_FRAC_MOD_RF
2841 // RFSYN_LPF_R
2842 // CHCAL_EN_INT_RF
2843
2844 // Equation E3
2845 // RFSYN_VCO_BIAS
3935c254
ST		 2846 E3 = (((Fmax-state->RF_LO)/1000)*32)/((Fmax-Fmin)/1000) + 8 ;
2847 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, E3) ;
52c99bda
ST		 2848
2849 // Equation E4
2850 // CHCAL_INT_MOD_RF
3935c254
ST		 2851 E4 = (state->RF_LO*divider_val/1000)/(2*state->Fxtal*Kdbl_RF/1000) ;
2852 MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, E4) ;
52c99bda
ST		 2853
2854 // Equation E5
2855 // CHCAL_FRAC_MOD_RF
2856 // CHCAL_EN_INT_RF
3935c254
ST		 2857 E5 = ((2<<17)*(state->RF_LO/10000*divider_val - (E4*(2*state->Fxtal*Kdbl_RF)/10000)))/(2*state->Fxtal*Kdbl_RF/10000) ;
2858 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ;
52c99bda
ST		 2859
2860 // Equation E5A
2861 // RFSYN_LPF_R
3935c254
ST		 2862 E5A = (((Fmax - state->RF_LO)/1000)*4/((Fmax-Fmin)/1000)) + 1 ;
2863 status += MXL_ControlWrite(fe, RFSYN_LPF_R, E5A) ;
52c99bda
ST		 2864
2865 // Euqation E5B
2866 // CHCAL_EN_INIT_RF
3935c254 2867 status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, ((E5 == 0) ? 1 : 0));
52c99bda 2868 //if (E5 == 0)
3935c254 2869 // status += MXL_ControlWrite(fe, CHCAL_EN_INT_RF, 1);
52c99bda 2870 //else
3935c254 2871 // status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, E5) ;
52c99bda
ST		 2872
2873 //
2874 // Set TG Synth
2875 //
2876 // Look-Up table implementation for:
2877 // TG_LO_DIVVAL
2878 // TG_LO_SELVAL
2879 //
2880 // Set divider_val, Fmax, Fmix to use in Equations
3935c254 2881 if (state->TG_LO < 33000000UL) {
52c99bda
ST		 2882 return -1;
2883 }
2884 FminBin = 33000000UL ;
2885 FmaxBin = 50000000UL ;
3935c254
ST		 2886 if (state->TG_LO >= FminBin && state->TG_LO <= FmaxBin) {
2887 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x6) ;
2888 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ;
52c99bda
ST		 2889 divider_val = 36 ;
2890 Fmax = FmaxBin ;
2891 Fmin = FminBin ;
2892 }
2893 FminBin = 50000000UL ;
2894 FmaxBin = 67000000UL ;
3935c254
ST		 2895 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2896 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x1) ;
2897 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x0) ;
52c99bda
ST		 2898 divider_val = 24 ;
2899 Fmax = FmaxBin ;
2900 Fmin = FminBin ;
2901 }
2902 FminBin = 67000000UL ;
2903 FmaxBin = 100000000UL ;
3935c254
ST		 2904 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2905 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0xC) ;
2906 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ;
52c99bda
ST		 2907 divider_val = 18 ;
2908 Fmax = FmaxBin ;
2909 Fmin = FminBin ;
2910 }
2911 FminBin = 100000000UL ;
2912 FmaxBin = 150000000UL ;
3935c254
ST		 2913 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2914 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ;
2915 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ;
52c99bda
ST		 2916 divider_val = 12 ;
2917 Fmax = FmaxBin ;
2918 Fmin = FminBin ;
2919 }
2920 FminBin = 150000000UL ;
2921 FmaxBin = 200000000UL ;
3935c254
ST		 2922 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2923 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ;
2924 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x2) ;
52c99bda
ST		 2925 divider_val = 8 ;
2926 Fmax = FmaxBin ;
2927 Fmin = FminBin ;
2928 }
2929 FminBin = 200000000UL ;
2930 FmaxBin = 300000000UL ;
3935c254
ST		 2931 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2932 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ;
2933 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ;
52c99bda
ST		 2934 divider_val = 6 ;
2935 Fmax = FmaxBin ;
2936 Fmin = FminBin ;
2937 }
2938 FminBin = 300000000UL ;
2939 FmaxBin = 400000000UL ;
3935c254
ST		 2940 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2941 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ;
2942 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x3) ;
52c99bda
ST		 2943 divider_val = 4 ;
2944 Fmax = FmaxBin ;
2945 Fmin = FminBin ;
2946 }
2947 FminBin = 400000000UL ;
2948 FmaxBin = 600000000UL ;
3935c254
ST		 2949 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2950 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x8) ;
2951 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ;
52c99bda
ST		 2952 divider_val = 3 ;
2953 Fmax = FmaxBin ;
2954 Fmin = FminBin ;
2955 }
2956 FminBin = 600000000UL ;
2957 FmaxBin = 900000000UL ;
3935c254
ST		 2958 if (state->TG_LO > FminBin && state->TG_LO <= FmaxBin) {
2959 status += MXL_ControlWrite(fe, TG_LO_DIVVAL, 0x0) ;
2960 status += MXL_ControlWrite(fe, TG_LO_SELVAL, 0x7) ;
52c99bda
ST		 2961 divider_val = 2 ;
2962 Fmax = FmaxBin ;
2963 Fmin = FminBin ;
2964 }
2965
2966 // TG_DIV_VAL
3935c254
ST		 2967 tg_divval = (state->TG_LO*divider_val/100000)
2968 *(MXL_Ceiling(state->Fxtal,1000000) * 100) / (state->Fxtal/1000) ;
2969 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval) ;
52c99bda 2970
3935c254
ST		 2971 if (state->TG_LO > 600000000UL)
2972 status += MXL_ControlWrite(fe, TG_DIV_VAL, tg_divval + 1 ) ;
52c99bda
ST		 2973
2974 Fmax = 1800000000UL ;
2975 Fmin = 1200000000UL ;
2976
2977
2978
2979 // to prevent overflow of 32 bit unsigned integer, use following equation. Edit for v2.6.4
3935c254 2980 Fref_TG = (state->Fxtal/1000)/ MXL_Ceiling(state->Fxtal, 1000000) ; // Fref_TF = Fref_TG*1000
52c99bda 2981
3935c254 2982 Fvco = (state->TG_LO/10000) * divider_val * Fref_TG; //Fvco = Fvco/10
52c99bda
ST		 2983
2984 tg_lo = (((Fmax/10 - Fvco)/100)*32) / ((Fmax-Fmin)/1000)+8;
2985
2986 //below equation is same as above but much harder to debug.
3935c254 2987 //tg_lo = ( ((Fmax/10000 * Xtal_Int)/100) - ((state->TG_LO/10000)*divider_val*(state->Fxtal/10000)/100) )*32/((Fmax-Fmin)/10000 * Xtal_Int/100) + 8 ;
52c99bda
ST		 2988
2989
3935c254 2990 status += MXL_ControlWrite(fe, TG_VCO_BIAS , tg_lo) ;
52c99bda
ST		 2991
2992
2993
2994 //add for 2.6.5
2995 //Special setting for QAM
3935c254 2996 if(state->Mod_Type == MXL_QAM)
52c99bda 2997 {
3935c254
ST		 2998 if(state->RF_IN < 680000000)
2999 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ;
52c99bda 3000 else
3935c254 3001 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 2) ;
52c99bda
ST		 3002 }
3003
3004
3005 //remove 20.48MHz setting for 2.6.10
3006
3007 //
3008 // Off Chip Tracking Filter Control
3009 //
85d220d0 3010 if (state->TF_Type == MXL_TF_OFF) // Tracking Filter Off State; turn off all the banks
52c99bda 3011 {
3935c254
ST		 3012 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
3013 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
52c99bda 3014
3935c254
ST		 3015 status += MXL_SetGPIO(fe, 3, 1) ; // turn off Bank 1
3016 status += MXL_SetGPIO(fe, 1, 1) ; // turn off Bank 2
3017 status += MXL_SetGPIO(fe, 4, 1) ; // turn off Bank 3
52c99bda
ST		 3018 }
3019
85d220d0 3020 if (state->TF_Type == MXL_TF_C) // Tracking Filter type C
52c99bda 3021 {
3935c254
ST		 3022 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ;
3023 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
52c99bda 3024
3935c254 3025 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
52c99bda
ST		 3026 {
3027
3935c254
ST		 3028 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3029 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3030 status += MXL_SetGPIO(fe, 3, 0) ; // Bank1 On
3031 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3032 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3033 }
3935c254 3034 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000)
52c99bda 3035 {
3935c254
ST		 3036 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3037 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3038 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3039 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3040 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3041 }
3935c254 3042 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000)
52c99bda 3043 {
3935c254
ST		 3044 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3045 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3046 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3047 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3048 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3049 }
3935c254 3050 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000)
52c99bda 3051 {
3935c254
ST		 3052 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3053 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3054 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3055 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3056 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3057 }
3935c254 3058 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000)
52c99bda 3059 {
3935c254
ST		 3060 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3061 status += MXL_ControlWrite(fe, DAC_DIN_B, 29) ;
3062 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3063 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3064 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3065 }
3935c254 3066 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000)
52c99bda 3067 {
3935c254
ST		 3068 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3069 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3070 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3071 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3072 status += MXL_SetGPIO(fe, 4, 0) ; // Bank3 On
52c99bda 3073 }
3935c254 3074 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000)
52c99bda 3075 {
3935c254
ST		 3076 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3077 status += MXL_ControlWrite(fe, DAC_DIN_B, 16) ;
3078 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3079 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3080 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3081 }
3935c254 3082 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000)
52c99bda 3083 {
3935c254
ST		 3084 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3085 status += MXL_ControlWrite(fe, DAC_DIN_B, 7) ;
3086 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3087 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3088 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda 3089 }
3935c254 3090 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
52c99bda 3091 {
3935c254
ST		 3092 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3093 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
3094 status += MXL_SetGPIO(fe, 3, 1) ; // Bank1 Off
3095 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3096 status += MXL_SetGPIO(fe, 4, 1) ; // Bank3 Off
52c99bda
ST		 3097 }
3098 }
3099
85d220d0 3100 if (state->TF_Type == MXL_TF_C_H) // Tracking Filter type C-H for Hauppauge only
52c99bda 3101 {
48937295 3102 printk("%s() CH filter\n", __func__);
3935c254 3103 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
52c99bda 3104
3935c254 3105 if (state->RF_IN >= 43000000 && state->RF_IN < 150000000)
52c99bda
ST		 3106 {
3107
3935c254
ST		 3108 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3109 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3110 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3111 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3112 }
3935c254 3113 if (state->RF_IN >= 150000000 && state->RF_IN < 280000000)
52c99bda 3114 {
3935c254
ST		 3115 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3116 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3117 status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On
3118 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3119 }
3935c254 3120 if (state->RF_IN >= 280000000 && state->RF_IN < 360000000)
52c99bda 3121 {
3935c254
ST		 3122 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3123 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3124 status += MXL_SetGPIO(fe, 3, 0) ; // Bank2 On
3125 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3126 }
3935c254 3127 if (state->RF_IN >= 360000000 && state->RF_IN < 560000000)
52c99bda 3128 {
3935c254
ST		 3129 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3130 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3131 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3132 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3133 }
3935c254 3134 if (state->RF_IN >= 560000000 && state->RF_IN < 580000000)
52c99bda 3135 {
3935c254
ST		 3136 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3137 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3138 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3139 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3140 }
3935c254 3141 if (state->RF_IN >= 580000000 && state->RF_IN < 630000000)
52c99bda 3142 {
3935c254
ST		 3143 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3144 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3145 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3146 status += MXL_SetGPIO(fe, 1, 0) ; // Bank3 On
52c99bda 3147 }
3935c254 3148 if (state->RF_IN >= 630000000 && state->RF_IN < 700000000)
52c99bda 3149 {
3935c254
ST		 3150 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3151 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3152 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3153 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3154 }
3935c254 3155 if (state->RF_IN >= 700000000 && state->RF_IN < 760000000)
52c99bda 3156 {
3935c254
ST		 3157 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3158 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3159 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3160 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda 3161 }
3935c254 3162 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
52c99bda 3163 {
3935c254
ST		 3164 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3165 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3166 status += MXL_SetGPIO(fe, 3, 1) ; // Bank2 Off
3167 status += MXL_SetGPIO(fe, 1, 1) ; // Bank3 Off
52c99bda
ST		 3168 }
3169 }
3170
85d220d0 3171 if (state->TF_Type == MXL_TF_D) // Tracking Filter type D
52c99bda 3172 {
3935c254 3173 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3174
3935c254 3175 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3176 {
3177
3935c254
ST		 3178 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3179 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3180 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3181 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3182 }
3935c254 3183 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3184 {
3935c254
ST		 3185 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3186 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3187 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3188 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3189 }
3935c254 3190 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000)
52c99bda 3191 {
3935c254
ST		 3192 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3193 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3194 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3195 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3196 }
3935c254 3197 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000)
52c99bda 3198 {
3935c254
ST		 3199 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3200 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3201 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3202 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3203 }
3935c254 3204 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000)
52c99bda 3205 {
3935c254
ST		 3206 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3207 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3208 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3209 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3210 }
3935c254 3211 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
52c99bda 3212 {
3935c254
ST		 3213 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3214 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3215 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3216 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3217 }
3935c254 3218 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
52c99bda 3219 {
3935c254
ST		 3220 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3221 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3222 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3223 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3224 }
3225 }
3226
3227
85d220d0 3228 if (state->TF_Type == MXL_TF_D_L) // Tracking Filter type D-L for Lumanate ONLY change for 2.6.3
52c99bda 3229 {
3935c254 3230 status += MXL_ControlWrite(fe, DAC_DIN_A, 0) ;
52c99bda 3231
a8214d48 3232 // if UHF and terrestrial => Turn off Tracking Filter
3935c254 3233 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0)
52c99bda
ST		 3234 {
3235 // Turn off all the banks
3935c254
ST		 3236 status += MXL_SetGPIO(fe, 3, 1) ;
3237 status += MXL_SetGPIO(fe, 1, 1) ;
3238 status += MXL_SetGPIO(fe, 4, 1) ;
3239 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ;
52c99bda 3240
3935c254 3241 status += MXL_ControlWrite(fe, AGC_IF, 10) ;
52c99bda
ST		 3242 }
3243
3244 else // if VHF or cable => Turn on Tracking Filter
3245 {
3935c254 3246 if (state->RF_IN >= 43000000 && state->RF_IN < 140000000)
52c99bda
ST		 3247 {
3248
3935c254
ST		 3249 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3250 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3251 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3252 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
52c99bda 3253 }
3935c254 3254 if (state->RF_IN >= 140000000 && state->RF_IN < 240000000)
52c99bda 3255 {
3935c254
ST		 3256 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3257 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3258 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3259 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
52c99bda 3260 }
3935c254 3261 if (state->RF_IN >= 240000000 && state->RF_IN < 340000000)
52c99bda 3262 {
3935c254
ST		 3263 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3264 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3265 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 On
3266 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 Off
52c99bda 3267 }
3935c254 3268 if (state->RF_IN >= 340000000 && state->RF_IN < 430000000)
52c99bda 3269 {
3935c254
ST		 3270 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 Off
3271 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3272 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3273 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
52c99bda 3274 }
3935c254 3275 if (state->RF_IN >= 430000000 && state->RF_IN < 470000000)
52c99bda 3276 {
3935c254
ST		 3277 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 Off
3278 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3279 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3280 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
52c99bda 3281 }
3935c254 3282 if (state->RF_IN >= 470000000 && state->RF_IN < 570000000)
52c99bda 3283 {
3935c254
ST		 3284 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3285 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3286 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3287 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 On
52c99bda 3288 }
3935c254 3289 if (state->RF_IN >= 570000000 && state->RF_IN < 620000000)
52c99bda 3290 {
3935c254
ST		 3291 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 0) ; // Bank4 On
3292 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3293 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3294 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Offq
52c99bda 3295 }
3935c254 3296 if (state->RF_IN >= 620000000 && state->RF_IN < 760000000)
52c99bda 3297 {
3935c254
ST		 3298 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3299 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 Off
3300 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3301 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3302 }
3935c254 3303 if (state->RF_IN >= 760000000 && state->RF_IN <= 900000000)
52c99bda 3304 {
3935c254
ST		 3305 status += MXL_ControlWrite(fe, DAC_A_ENABLE, 1) ; // Bank4 On
3306 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3307 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3308 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3309 }
3310 }
3311 }
3312
85d220d0 3313 if (state->TF_Type == MXL_TF_E) // Tracking Filter type E
52c99bda 3314 {
3935c254 3315 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3316
3935c254 3317 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3318 {
3319
3935c254
ST		 3320 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3321 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3322 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3323 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3324 }
3935c254 3325 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3326 {
3935c254
ST		 3327 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3328 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3329 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3330 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3331 }
3935c254 3332 if (state->RF_IN >= 250000000 && state->RF_IN < 310000000)
52c99bda 3333 {
3935c254
ST		 3334 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3335 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3336 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3337 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3338 }
3935c254 3339 if (state->RF_IN >= 310000000 && state->RF_IN < 360000000)
52c99bda 3340 {
3935c254
ST		 3341 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3342 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3343 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3344 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3345 }
3935c254 3346 if (state->RF_IN >= 360000000 && state->RF_IN < 470000000)
52c99bda 3347 {
3935c254
ST		 3348 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3349 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3350 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3351 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3352 }
3935c254 3353 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
52c99bda 3354 {
3935c254
ST		 3355 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3356 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3357 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3358 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3359 }
3935c254 3360 if (state->RF_IN >= 640000000 && state->RF_IN <= 900000000)
52c99bda 3361 {
3935c254
ST		 3362 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3363 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3364 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3365 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3366 }
3367 }
3368
85d220d0 3369 if (state->TF_Type == MXL_TF_F) // Tracking Filter type F
52c99bda 3370 {
3935c254 3371 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3372
3935c254 3373 if (state->RF_IN >= 43000000 && state->RF_IN < 160000000)
52c99bda
ST		 3374 {
3375
3935c254
ST		 3376 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3377 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3378 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3379 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3380 }
3935c254 3381 if (state->RF_IN >= 160000000 && state->RF_IN < 210000000)
52c99bda 3382 {
3935c254
ST		 3383 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3384 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3385 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3386 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3387 }
3935c254 3388 if (state->RF_IN >= 210000000 && state->RF_IN < 300000000)
52c99bda 3389 {
3935c254
ST		 3390 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3391 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3392 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3393 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3394 }
3935c254 3395 if (state->RF_IN >= 300000000 && state->RF_IN < 390000000)
52c99bda 3396 {
3935c254
ST		 3397 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3398 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3399 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3400 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3401 }
3935c254 3402 if (state->RF_IN >= 390000000 && state->RF_IN < 515000000)
52c99bda 3403 {
3935c254
ST		 3404 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3405 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3406 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3407 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3408 }
3935c254 3409 if (state->RF_IN >= 515000000 && state->RF_IN < 650000000)
52c99bda 3410 {
3935c254
ST		 3411 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3412 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3413 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3414 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3415 }
3935c254 3416 if (state->RF_IN >= 650000000 && state->RF_IN <= 900000000)
52c99bda 3417 {
3935c254
ST		 3418 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3419 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3420 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3421 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3422 }
3423 }
3424
85d220d0 3425 if (state->TF_Type == MXL_TF_E_2) // Tracking Filter type E_2
52c99bda 3426 {
3935c254 3427 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3428
3935c254 3429 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3430 {
3431
3935c254
ST		 3432 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3433 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3434 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3435 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3436 }
3935c254 3437 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3438 {
3935c254
ST		 3439 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3440 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3441 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3442 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3443 }
3935c254 3444 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000)
52c99bda 3445 {
3935c254
ST		 3446 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3447 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3448 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3449 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3450 }
3935c254 3451 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
52c99bda 3452 {
3935c254
ST		 3453 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3454 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3455 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3456 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3457 }
3935c254 3458 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000)
52c99bda 3459 {
3935c254
ST		 3460 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3461 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3462 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3463 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3464 }
3935c254 3465 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000)
52c99bda 3466 {
3935c254
ST		 3467 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3468 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3469 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3470 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3471 }
3935c254 3472 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
52c99bda 3473 {
3935c254
ST		 3474 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3475 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3476 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3477 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3478 }
3479 }
3480
85d220d0 3481 if (state->TF_Type == MXL_TF_G) // Tracking Filter type G add for v2.6.8
52c99bda 3482 {
3935c254 3483 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3484
3935c254 3485 if (state->RF_IN >= 50000000 && state->RF_IN < 190000000)
52c99bda
ST		 3486 {
3487
3935c254
ST		 3488 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3489 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3490 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3491 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3492 }
3935c254 3493 if (state->RF_IN >= 190000000 && state->RF_IN < 280000000)
52c99bda 3494 {
3935c254
ST		 3495 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3496 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3497 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3498 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3499 }
3935c254 3500 if (state->RF_IN >= 280000000 && state->RF_IN < 350000000)
52c99bda 3501 {
3935c254
ST		 3502 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3503 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3504 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3505 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3506 }
3935c254 3507 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
52c99bda 3508 {
3935c254
ST		 3509 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3510 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3511 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3512 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3513 }
3935c254 3514 if (state->RF_IN >= 400000000 && state->RF_IN < 470000000) //modified for 2.6.11
52c99bda 3515 {
3935c254
ST		 3516 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3517 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 On
3518 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 Off
3519 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3520 }
3935c254 3521 if (state->RF_IN >= 470000000 && state->RF_IN < 640000000)
52c99bda 3522 {
3935c254
ST		 3523 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3524 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3525 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3526 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3527 }
3935c254 3528 if (state->RF_IN >= 640000000 && state->RF_IN < 820000000)
52c99bda 3529 {
3935c254
ST		 3530 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3531 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3532 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3533 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3534 }
3935c254 3535 if (state->RF_IN >= 820000000 && state->RF_IN <= 900000000)
52c99bda 3536 {
3935c254
ST		 3537 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3538 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3539 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3540 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3541 }
3542 }
3543
85d220d0 3544 if (state->TF_Type == MXL_TF_E_NA) // Tracking Filter type E-NA for Empia ONLY change for 2.6.8
52c99bda 3545 {
3935c254 3546 status += MXL_ControlWrite(fe, DAC_DIN_B, 0) ;
52c99bda 3547
a8214d48 3548 // if UHF and terrestrial=> Turn off Tracking Filter
3935c254 3549 if (state->RF_IN >= 471000000 && (state->RF_IN - 471000000)%6000000 != 0)
52c99bda
ST		 3550 {
3551 // Turn off all the banks
3935c254
ST		 3552 status += MXL_SetGPIO(fe, 3, 1) ;
3553 status += MXL_SetGPIO(fe, 1, 1) ;
3554 status += MXL_SetGPIO(fe, 4, 1) ;
3555 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ;
52c99bda
ST		 3556
3557 //2.6.12
3558 //Turn on RSSI
3935c254
ST		 3559 status += MXL_ControlWrite(fe, SEQ_EXTSYNTHCALIF, 1) ;
3560 status += MXL_ControlWrite(fe, SEQ_EXTDCCAL, 1) ;
3561 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 1) ;
3562 status += MXL_ControlWrite(fe, RFA_ENCLKRFAGC, 1) ;
52c99bda
ST		 3563
3564 // RSSI reference point
3935c254
ST		 3565 status += MXL_ControlWrite(fe, RFA_RSSI_REFH, 5) ;
3566 status += MXL_ControlWrite(fe, RFA_RSSI_REF, 3) ;
3567 status += MXL_ControlWrite(fe, RFA_RSSI_REFL, 2) ;
52c99bda
ST		 3568
3569
3935c254 3570 //status += MXL_ControlWrite(fe, AGC_IF, 10) ; //doesn't matter since RSSI is turn on
52c99bda
ST		 3571
3572 //following parameter is from analog OTA mode, can be change to seek better performance
3935c254 3573 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 3) ;
52c99bda
ST		 3574 }
3575
3576 else //if VHF or Cable => Turn on Tracking Filter
3577 {
3578 //2.6.12
3579 //Turn off RSSI
3935c254 3580 status += MXL_ControlWrite(fe, AGC_EN_RSSI, 0) ;
52c99bda
ST		 3581
3582 //change back from above condition
3935c254 3583 status += MXL_ControlWrite(fe, RFSYN_CHP_GAIN, 5) ;
52c99bda
ST		 3584
3585
3935c254 3586 if (state->RF_IN >= 43000000 && state->RF_IN < 174000000)
52c99bda
ST		 3587 {
3588
3935c254
ST		 3589 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3590 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3591 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3592 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3593 }
3935c254 3594 if (state->RF_IN >= 174000000 && state->RF_IN < 250000000)
52c99bda 3595 {
3935c254
ST		 3596 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3597 status += MXL_SetGPIO(fe, 4, 0) ; // Bank1 On
3598 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3599 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3600 }
3935c254 3601 if (state->RF_IN >= 250000000 && state->RF_IN < 350000000)
52c99bda 3602 {
3935c254
ST		 3603 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3604 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3605 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3606 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda 3607 }
3935c254 3608 if (state->RF_IN >= 350000000 && state->RF_IN < 400000000)
52c99bda 3609 {
3935c254
ST		 3610 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3611 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3612 status += MXL_SetGPIO(fe, 1, 0) ; // Bank2 On
3613 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3614 }
3935c254 3615 if (state->RF_IN >= 400000000 && state->RF_IN < 570000000)
52c99bda 3616 {
3935c254
ST		 3617 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 0) ; // Bank4 Off
3618 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3619 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3620 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3621 }
3935c254 3622 if (state->RF_IN >= 570000000 && state->RF_IN < 770000000)
52c99bda 3623 {
3935c254
ST		 3624 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3625 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3626 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3627 status += MXL_SetGPIO(fe, 3, 0) ; // Bank3 On
52c99bda 3628 }
3935c254 3629 if (state->RF_IN >= 770000000 && state->RF_IN <= 900000000)
52c99bda 3630 {
3935c254
ST		 3631 status += MXL_ControlWrite(fe, DAC_B_ENABLE, 1) ; // Bank4 On
3632 status += MXL_SetGPIO(fe, 4, 1) ; // Bank1 Off
3633 status += MXL_SetGPIO(fe, 1, 1) ; // Bank2 Off
3634 status += MXL_SetGPIO(fe, 3, 1) ; // Bank3 Off
52c99bda
ST		 3635 }
3636 }
3637 }
3638 return status ;
3639}
3640
3935c254 3641u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val)
52c99bda 3642{
3935c254 3643 u16 status = 0;
52c99bda
ST		 3644
3645 if (GPIO_Num == 1)
3935c254
ST		 3646 status += MXL_ControlWrite(fe, GPIO_1B, GPIO_Val ? 0 : 1);
3647
3648 /* GPIO2 is not available */
3649
3650 if (GPIO_Num == 3) {
52c99bda 3651 if (GPIO_Val == 1) {
3935c254
ST		 3652 status += MXL_ControlWrite(fe, GPIO_3, 0);
3653 status += MXL_ControlWrite(fe, GPIO_3B, 0);
52c99bda
ST		 3654 }
3655 if (GPIO_Val == 0) {
3935c254
ST		 3656 status += MXL_ControlWrite(fe, GPIO_3, 1);
3657 status += MXL_ControlWrite(fe, GPIO_3B, 1);
52c99bda 3658 }
3935c254
ST		 3659 if (GPIO_Val == 3) { /* tri-state */
3660 status += MXL_ControlWrite(fe, GPIO_3, 0);
3661 status += MXL_ControlWrite(fe, GPIO_3B, 1);
52c99bda
ST		 3662 }
3663 }
3935c254 3664 if (GPIO_Num == 4) {
52c99bda 3665 if (GPIO_Val == 1) {
3935c254
ST		 3666 status += MXL_ControlWrite(fe, GPIO_4, 0);
3667 status += MXL_ControlWrite(fe, GPIO_4B, 0);
52c99bda
ST		 3668 }
3669 if (GPIO_Val == 0) {
3935c254
ST		 3670 status += MXL_ControlWrite(fe, GPIO_4, 1);
3671 status += MXL_ControlWrite(fe, GPIO_4B, 1);
52c99bda 3672 }
3935c254
ST		 3673 if (GPIO_Val == 3) { /* tri-state */
3674 status += MXL_ControlWrite(fe, GPIO_4, 0);
3675 status += MXL_ControlWrite(fe, GPIO_4B, 1);
52c99bda
ST		 3676 }
3677 }
3678
3935c254 3679 return status;
52c99bda
ST		 3680}
3681
3682///////////////////////////////////////////////////////////////////////////////
3683// //
3684// Function: MXL_ControlWrite //
3685// //
3686// Description: Update control name value //
3687// //
3688// Globals: //
3689// NONE //
3690// //
3691// Functions used: //
3692// MXL_ControlWrite( Tuner, controlName, value, Group ) //
3693// //
3694// Inputs: //
3695// Tuner : Tuner structure //
3696// ControlName : Control name to be updated //
3697// value : Value to be written //
3698// //
3699// Outputs: //
3700// Tuner : Tuner structure defined at higher level //
3701// //
3702// Return: //
3703// 0 : Successful write //
3704// >0 : Value exceed maximum allowed for control number //
3705// //
3706///////////////////////////////////////////////////////////////////////////////
3935c254 3707u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value)
52c99bda 3708{
3935c254
ST		 3709 u16 status = 0;
3710
3711 /* Will write ALL Matching Control Name */
85d220d0
ST		 3712 status += MXL_ControlWrite_Group(fe, ControlNum, value, 1); /* Write Matching INIT Control */
3713 status += MXL_ControlWrite_Group(fe, ControlNum, value, 2); /* Write Matching CH Control */
52c99bda 3714#ifdef _MXL_INTERNAL
85d220d0 3715 status += MXL_ControlWrite_Group(fe, ControlNum, value, 3); /* Write Matching MXL Control */
52c99bda 3716#endif
3935c254 3717 return status;
52c99bda
ST		 3718}
3719
3720///////////////////////////////////////////////////////////////////////////////
3721// //
3722// Function: MXL_ControlWrite //
3723// //
3724// Description: Update control name value //
3725// //
3726// Globals: //
3727// NONE //
3728// //
3729// Functions used: //
3730// strcmp //
3731// //
3732// Inputs: //
3733// Tuner_struct: structure defined at higher level //
3734// ControlName : Control Name //
3735// value : Value Assigned to Control Name //
3736// controlGroup : Control Register Group //
3737// //
3738// Outputs: //
3739// NONE //
3740// //
3741// Return: //
3742// 0 : Successful write //
3743// 1 : Value exceed maximum allowed for control name //
3744// 2 : Control name not found //
3745// //
3746///////////////////////////////////////////////////////////////////////////////
3935c254 3747u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup)
52c99bda 3748{
85d220d0 3749 struct mxl5005s_state *state = fe->tuner_priv;
3935c254
ST		 3750 u16 i, j, k;
3751 u32 highLimit;
3752 u32 ctrlVal;
52c99bda 3753
3935c254
ST		 3754 if (controlGroup == 1) /* Initial Control */ {
3755
3756 for (i = 0; i < state->Init_Ctrl_Num; i++) {
3757
3758 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3759
3760 highLimit = 1 << state->Init_Ctrl[i].size;
3761 if (value < highLimit) {
3762 for (j = 0; j < state->Init_Ctrl[i].size; j++) {
3763 state->Init_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3764 MXL_RegWriteBit(fe, (u8)(state->Init_Ctrl[i].addr[j]),
3765 (u8)(state->Init_Ctrl[i].bit[j]),
3766 (u8)((value>>j) & 0x01) );
52c99bda 3767 }
3935c254
ST		 3768 ctrlVal = 0;
3769 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3770 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
52c99bda
ST		 3771 }
3772 else
3935c254 3773 return -1;
52c99bda
ST		 3774 }
3775 }
3776 }
3935c254
ST		 3777 if (controlGroup == 2) /* Chan change Control */ {
3778
3779 for (i = 0; i < state->CH_Ctrl_Num; i++) {
3780
3781 if (controlNum == state->CH_Ctrl[i].Ctrl_Num ) {
3782
3783 highLimit = 1 << state->CH_Ctrl[i].size;
3784 if (value < highLimit) {
3785 for (j = 0; j < state->CH_Ctrl[i].size; j++) {
3786 state->CH_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3787 MXL_RegWriteBit(fe, (u8)(state->CH_Ctrl[i].addr[j]),
3788 (u8)(state->CH_Ctrl[i].bit[j]),
3789 (u8)((value>>j) & 0x01) );
52c99bda 3790 }
3935c254
ST		 3791 ctrlVal = 0;
3792 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3793 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
52c99bda
ST		 3794 }
3795 else
3935c254 3796 return -1;
52c99bda
ST		 3797 }
3798 }
3799 }
3800#ifdef _MXL_INTERNAL
3935c254
ST		 3801 if (controlGroup == 3) /* Maxlinear Control */ {
3802
3803 for (i = 0; i < state->MXL_Ctrl_Num; i++) {
3804
3805 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num ) {
3806
3807 highLimit = (1 << state->MXL_Ctrl[i].size) ;
3808 if (value < highLimit) {
3809 for (j = 0; j < state->MXL_Ctrl[i].size; j++) {
3810 state->MXL_Ctrl[i].val[j] = (u8)((value >> j) & 0x01);
3811 MXL_RegWriteBit(fe, (u8)(state->MXL_Ctrl[i].addr[j]),
3812 (u8)(state->MXL_Ctrl[i].bit[j]),
3813 (u8)((value>>j) & 0x01) );
52c99bda 3814 }
3935c254
ST		 3815 ctrlVal = 0;
3816 for(k = 0; k < state->MXL_Ctrl[i].size; k++)
3817 ctrlVal += state->MXL_Ctrl[i].val[k] * (1 << k);
52c99bda
ST		 3818 }
3819 else
3935c254 3820 return -1;
52c99bda
ST		 3821 }
3822 }
3823 }
3824#endif
3935c254 3825 return 0 ; /* successful return */
52c99bda
ST		 3826}
3827
3828///////////////////////////////////////////////////////////////////////////////
3829// //
3830// Function: MXL_RegWrite //
3831// //
3832// Description: Update tuner register value //
3833// //
3834// Globals: //
3835// NONE //
3836// //
3837// Functions used: //
3838// NONE //
3839// //
3840// Inputs: //
3841// Tuner_struct: structure defined at higher level //
3842// RegNum : Register address to be assigned a value //
3843// RegVal : Register value to write //
3844// //
3845// Outputs: //
3846// NONE //
3847// //
3848// Return: //
3849// 0 : Successful write //
3850// -1 : Invalid Register Address //
3851// //
3852///////////////////////////////////////////////////////////////////////////////
3935c254 3853u16 MXL_RegWrite(struct dvb_frontend *fe, u8 RegNum, u8 RegVal)
52c99bda 3854{
85d220d0 3855 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda
ST		 3856 int i ;
3857
3935c254
ST		 3858 for (i = 0; i < 104; i++) {
3859 if (RegNum == state->TunerRegs[i].Reg_Num) {
3860 state->TunerRegs[i].Reg_Val = RegVal;
3861 return 0;
52c99bda
ST		 3862 }
3863 }
3864
3935c254 3865 return 1;
52c99bda
ST		 3866}
3867
3868///////////////////////////////////////////////////////////////////////////////
3869// //
3870// Function: MXL_RegRead //
3871// //
3872// Description: Retrieve tuner register value //
3873// //
3874// Globals: //
3875// NONE //
3876// //
3877// Functions used: //
3878// NONE //
3879// //
3880// Inputs: //
3881// Tuner_struct: structure defined at higher level //
3882// RegNum : Register address to be assigned a value //
3883// //
3884// Outputs: //
3885// RegVal : Retrieved register value //
3886// //
3887// Return: //
3888// 0 : Successful read //
3889// -1 : Invalid Register Address //
3890// //
3891///////////////////////////////////////////////////////////////////////////////
3935c254 3892u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal)
52c99bda 3893{
85d220d0 3894 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda
ST		 3895 int i ;
3896
3935c254
ST		 3897 for (i = 0; i < 104; i++) {
3898 if (RegNum == state->TunerRegs[i].Reg_Num ) {
3899 *RegVal = (u8)(state->TunerRegs[i].Reg_Val);
3900 return 0;
52c99bda
ST		 3901 }
3902 }
3903
3935c254 3904 return 1;
52c99bda
ST		 3905}
3906
3907///////////////////////////////////////////////////////////////////////////////
3908// //
3909// Function: MXL_ControlRead //
3910// //
3911// Description: Retrieve the control value based on the control name //
3912// //
3913// Globals: //
3914// NONE //
3915// //
3916// Inputs: //
3917// Tuner_struct : structure defined at higher level //
3918// ControlName : Control Name //
3919// //
3920// Outputs: //
3921// value : returned control value //
3922// //
3923// Return: //
3924// 0 : Successful read //
3925// -1 : Invalid control name //
3926// //
3927///////////////////////////////////////////////////////////////////////////////
85d220d0 3928u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value)
52c99bda 3929{
85d220d0 3930 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48
ST		 3931 u32 ctrlVal ;
3932 u16 i, k ;
52c99bda 3933
3935c254
ST		 3934 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
3935
3936 if (controlNum == state->Init_Ctrl[i].Ctrl_Num) {
3937
3938 ctrlVal = 0;
3939 for (k = 0; k < state->Init_Ctrl[i].size; k++)
3940 ctrlVal += state->Init_Ctrl[i].val[k] * (1 << k);
3941 *value = ctrlVal;
3942 return 0;
52c99bda
ST		 3943 }
3944 }
3935c254
ST		 3945
3946 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
3947
3948 if (controlNum == state->CH_Ctrl[i].Ctrl_Num) {
3949
3950 ctrlVal = 0;
3951 for (k = 0; k < state->CH_Ctrl[i].size; k++)
3952 ctrlVal += state->CH_Ctrl[i].val[k] * (1 << k);
3953 *value = ctrlVal;
3954 return 0;
3955
52c99bda
ST		 3956 }
3957 }
3958
3959#ifdef _MXL_INTERNAL
3935c254
ST		 3960 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
3961
3962 if (controlNum == state->MXL_Ctrl[i].Ctrl_Num) {
3963
3964 ctrlVal = 0;
3965 for (k = 0; k < state->MXL_Ctrl[i].size; k++)
3966 ctrlVal += state->MXL_Ctrl[i].val[k] * (1<<k);
3967 *value = ctrlVal;
3968 return 0;
3969
52c99bda
ST		 3970 }
3971 }
3972#endif
3935c254 3973 return 1;
52c99bda
ST		 3974}
3975
3976///////////////////////////////////////////////////////////////////////////////
3977// //
3978// Function: MXL_ControlRegRead //
3979// //
3980// Description: Retrieve the register addresses and count related to a //
a8214d48 3981// a specific control name //
52c99bda
ST		 3982// //
3983// Globals: //
3984// NONE //
3985// //
3986// Inputs: //
3987// Tuner_struct : structure defined at higher level //
3988// ControlName : Control Name //
3989// //
3990// Outputs: //
3991// RegNum : returned register address array //
a8214d48 3992// count : returned register count related to a control //
52c99bda
ST		 3993// //
3994// Return: //
3995// 0 : Successful read //
3996// -1 : Invalid control name //
3997// //
3998///////////////////////////////////////////////////////////////////////////////
3935c254 3999u16 MXL_ControlRegRead(struct dvb_frontend *fe, u16 controlNum, u8 *RegNum, int * count)
52c99bda 4000{
85d220d0 4001 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48
ST		 4002 u16 i, j, k ;
4003 u16 Count ;
52c99bda 4004
3935c254
ST		 4005 for (i = 0; i < state->Init_Ctrl_Num ; i++) {
4006
4007 if ( controlNum == state->Init_Ctrl[i].Ctrl_Num ) {
4008
4009 Count = 1;
4010 RegNum[0] = (u8)(state->Init_Ctrl[i].addr[0]);
4011
4012 for (k = 1; k < state->Init_Ctrl[i].size; k++) {
4013
4014 for (j = 0; j < Count; j++) {
4015
4016 if (state->Init_Ctrl[i].addr[k] != RegNum[j]) {
4017
4018 Count ++;
4019 RegNum[Count-1] = (u8)(state->Init_Ctrl[i].addr[k]);
52c99bda 4020
52c99bda
ST		 4021 }
4022 }
4023
4024 }
3935c254
ST		 4025 *count = Count;
4026 return 0;
52c99bda
ST		 4027 }
4028 }
3935c254
ST		 4029 for (i = 0; i < state->CH_Ctrl_Num ; i++) {
4030
4031 if ( controlNum == state->CH_Ctrl[i].Ctrl_Num ) {
4032
4033 Count = 1;
4034 RegNum[0] = (u8)(state->CH_Ctrl[i].addr[0]);
4035
4036 for (k = 1; k < state->CH_Ctrl[i].size; k++) {
4037
4038 for (j= 0; j<Count; j++) {
4039
4040 if (state->CH_Ctrl[i].addr[k] != RegNum[j]) {
4041
4042 Count ++;
4043 RegNum[Count-1] = (u8)(state->CH_Ctrl[i].addr[k]);
52c99bda 4044
52c99bda
ST		 4045 }
4046 }
4047 }
3935c254
ST		 4048 *count = Count;
4049 return 0;
52c99bda
ST		 4050 }
4051 }
4052#ifdef _MXL_INTERNAL
3935c254
ST		 4053 for (i = 0; i < state->MXL_Ctrl_Num ; i++) {
4054
4055 if ( controlNum == state->MXL_Ctrl[i].Ctrl_Num ) {
4056
4057 Count = 1;
4058 RegNum[0] = (u8)(state->MXL_Ctrl[i].addr[0]);
4059
4060 for (k = 1; k < state->MXL_Ctrl[i].size; k++) {
4061
4062 for (j = 0; j<Count; j++) {
4063
4064 if (state->MXL_Ctrl[i].addr[k] != RegNum[j]) {
4065
4066 Count ++;
4067 RegNum[Count-1] = (u8)state->MXL_Ctrl[i].addr[k];
52c99bda 4068
52c99bda
ST		 4069 }
4070 }
4071 }
3935c254
ST		 4072 *count = Count;
4073 return 0;
52c99bda
ST		 4074 }
4075 }
4076#endif
3935c254
ST		 4077 *count = 0;
4078 return 1;
52c99bda
ST		 4079}
4080
4081///////////////////////////////////////////////////////////////////////////////
4082// //
4083// Function: MXL_RegWriteBit //
4084// //
4085// Description: Write a register for specified register address, //
4086// register bit and register bit value //
4087// //
4088// Globals: //
4089// NONE //
4090// //
4091// Inputs: //
4092// Tuner_struct : structure defined at higher level //
4093// address : register address //
3935c254 4094// bit : register bit number //
a8214d48 4095// bitVal : register bit value //
52c99bda
ST		 4096// //
4097// Outputs: //
4098// NONE //
4099// //
4100// Return: //
4101// NONE //
4102// //
4103///////////////////////////////////////////////////////////////////////////////
3935c254 4104void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal)
52c99bda 4105{
85d220d0 4106 struct mxl5005s_state *state = fe->tuner_priv;
52c99bda
ST		 4107 int i ;
4108
a8214d48 4109 const u8 AND_MAP[8] = {
52c99bda
ST		 4110 0xFE, 0xFD, 0xFB, 0xF7,
4111 0xEF, 0xDF, 0xBF, 0x7F } ;
4112
a8214d48 4113 const u8 OR_MAP[8] = {
52c99bda
ST		 4114 0x01, 0x02, 0x04, 0x08,
4115 0x10, 0x20, 0x40, 0x80 } ;
4116
3935c254
ST		 4117 for (i = 0; i < state->TunerRegs_Num; i++) {
4118 if (state->TunerRegs[i].Reg_Num == address) {
52c99bda 4119 if (bitVal)
3935c254 4120 state->TunerRegs[i].Reg_Val |= OR_MAP[bit];
52c99bda 4121 else
3935c254 4122 state->TunerRegs[i].Reg_Val &= AND_MAP[bit];
52c99bda
ST		 4123 break ;
4124 }
4125 }
3935c254 4126}
52c99bda
ST		 4127
4128///////////////////////////////////////////////////////////////////////////////
4129// //
4130// Function: MXL_Ceiling //
4131// //
4132// Description: Complete to closest increment of resolution //
4133// //
4134// Globals: //
4135// NONE //
4136// //
4137// Functions used: //
4138// NONE //
4139// //
4140// Inputs: //
4141// value : Input number to compute //
4142// resolution : Increment step //
4143// //
4144// Outputs: //
4145// NONE //
4146// //
4147// Return: //
4148// Computed value //
4149// //
4150///////////////////////////////////////////////////////////////////////////////
3935c254 4151u32 MXL_Ceiling(u32 value, u32 resolution)
52c99bda 4152{
3935c254
ST		 4153 return (value/resolution + (value % resolution > 0 ? 1 : 0));
4154}
52c99bda
ST		 4155
4156//
4157// Retrieve the Initialzation Registers
4158//
3935c254 4159u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4160{
a8214d48 4161 u16 status = 0;
52c99bda
ST		 4162 int i ;
4163
3935c254
ST		 4164 u8 RegAddr[] = {
4165 11, 12, 13, 22, 32, 43, 44, 53, 56, 59, 73,
4166 76, 77, 91, 134, 135, 137, 147,
4167 156, 166, 167, 168, 25 };
52c99bda 4168
3935c254 4169 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4170
3935c254
ST		 4171 status += MXL_BlockInit(fe);
4172
4173 for (i = 0 ; i < *count; i++) {
4174 RegNum[i] = RegAddr[i];
4175 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda
ST		 4176 }
4177
3935c254 4178 return status;
52c99bda
ST		 4179}
4180
3935c254 4181u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4182{
a8214d48 4183 u16 status = 0;
52c99bda
ST		 4184 int i ;
4185
4186//add 77, 166, 167, 168 register for 2.6.12
4187#ifdef _MXL_PRODUCTION
a8214d48
ST		 4188 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 65, 68, 69, 70, 73, 92, 93, 106,
4189 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
52c99bda 4190#else
a8214d48
ST		 4191 u8 RegAddr[] = {14, 15, 16, 17, 22, 43, 68, 69, 70, 73, 92, 93, 106,
4192 107, 108, 109, 110, 111, 112, 136, 138, 149, 77, 166, 167, 168 } ;
4193 //u8 RegAddr[171];
52c99bda
ST		 4194 //for (i=0; i<=170; i++)
4195 // RegAddr[i] = i;
4196#endif
4197
3935c254 4198 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4199
3935c254
ST		 4200 for (i = 0 ; i < *count; i++) {
4201 RegNum[i] = RegAddr[i];
4202 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda
ST		 4203 }
4204
3935c254 4205 return status;
52c99bda
ST		 4206}
4207
3935c254 4208u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4209{
3935c254
ST		 4210 u16 status = 0;
4211 int i;
52c99bda 4212
3935c254 4213 u8 RegAddr[] = {43, 136};
52c99bda 4214
3935c254 4215 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4216
3935c254
ST		 4217 for (i = 0; i < *count; i++) {
4218 RegNum[i] = RegAddr[i];
4219 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda 4220 }
52c99bda 4221
3935c254 4222 return status;
52c99bda
ST		 4223}
4224
3935c254 4225u16 MXL_GetCHRegister_LowIF(struct dvb_frontend *fe, u8 * RegNum, u8 *RegVal, int *count)
52c99bda 4226{
3935c254
ST		 4227 u16 status = 0;
4228 int i;
52c99bda 4229
3935c254 4230 u8 RegAddr[] = { 138 };
52c99bda 4231
3935c254 4232 *count = sizeof(RegAddr) / sizeof(u8);
52c99bda 4233
3935c254
ST		 4234 for (i = 0; i < *count; i++) {
4235 RegNum[i] = RegAddr[i];
4236 status += MXL_RegRead(fe, RegNum[i], &RegVal[i]);
52c99bda 4237 }
52c99bda 4238
3935c254 4239 return status;
52c99bda
ST		 4240}
4241
a8214d48 4242u16 MXL_GetMasterControl(u8 *MasterReg, int state)
52c99bda 4243{
3935c254
ST		 4244 if (state == 1) /* Load_Start */
4245 *MasterReg = 0xF3;
4246 if (state == 2) /* Power_Down */
4247 *MasterReg = 0x41;
4248 if (state == 3) /* Synth_Reset */
4249 *MasterReg = 0xB1;
4250 if (state == 4) /* Seq_Off */
4251 *MasterReg = 0xF1;
4252
4253 return 0;
52c99bda
ST		 4254}
4255
4256#ifdef _MXL_PRODUCTION
3935c254 4257u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range)
52c99bda 4258{
85d220d0 4259 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48
ST		 4260 u16 status = 0 ;
4261
4262 if (VCO_Range == 1) {
3935c254
ST		 4263 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4264 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4265 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4266 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4267 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4268 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4269 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4270 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4271 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4272 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4273 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4274 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224);
4275 }
4276 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4277 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4278 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4279 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4280 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822);
4281 }
4282 if (state->Mode == 1) /* Digital Mode */ {
4283 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4284 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4285 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56);
4286 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376);
a8214d48
ST		 4287 }
4288 }
52c99bda 4289
a8214d48 4290 if (VCO_Range == 2) {
3935c254
ST		 4291 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4292 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4293 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4294 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4295 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4296 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4297 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4298 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4299 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4300 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4301 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4302 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4303 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4304 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4305 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4306 }
4307 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4308 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4309 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4310 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4311 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4312 }
4313 if (state->Mode == 1) /* Digital Mode */ {
4314 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1);
4315 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4316 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41);
4317 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384);
a8214d48
ST		 4318 }
4319 }
52c99bda 4320
a8214d48 4321 if (VCO_Range == 3) {
3935c254
ST		 4322 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4323 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4324 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4325 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4326 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4327 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4328 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4329 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4330 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4331 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4332 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4333 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4334 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4335 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4336 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670);
4337 }
4338 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4339 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4340 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4341 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44);
4342 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670);
4343 }
4344 if (state->Mode == 1) /* Digital Mode */ {
4345 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4346 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8);
4347 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42);
4348 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760);
a8214d48
ST		 4349 }
4350 }
52c99bda 4351
a8214d48 4352 if (VCO_Range == 4) {
3935c254
ST		 4353 status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1);
4354 status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0);
4355 status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0);
4356 status += MXL_ControlWrite(fe, RFSYN_DIVM, 1);
4357 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1);
4358 status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1);
4359 status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0);
4360 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4361 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4362 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4363 if (state->Mode == 0 && state->IF_Mode == 1) /* Analog Low IF Mode */ {
4364 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4365 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4366 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4367 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4368 }
4369 if (state->Mode == 0 && state->IF_Mode == 0) /* Analog Zero IF Mode */ {
4370 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4371 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4372 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4373 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438);
4374 }
4375 if (state->Mode == 1) /* Digital Mode */ {
4376 status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0);
4377 status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40);
4378 status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27);
4379 status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992);
a8214d48
ST		 4380 }
4381 }
52c99bda 4382
a8214d48
ST		 4383 return status;
4384}
52c99bda 4385
3935c254 4386u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis)
a8214d48 4387{
85d220d0 4388 struct mxl5005s_state *state = fe->tuner_priv;
a8214d48 4389 u16 status = 0;
52c99bda 4390
a8214d48 4391 if (Hystersis == 1)
3935c254 4392 status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1);
52c99bda 4393
a8214d48
ST		 4394 return status;
4395}
a8214d48 4396#endif
48937295
ST		 4397/* End: Reference driver code found in the Realtek driver that
4398 * is copyright MaxLinear */
7f5c3aff 4399
48937295
ST		 4400/* ----------------------------------------------------------------
4401 * Begin: Everything after here is new code to adapt the
4402 * proprietary Realtek driver into a Linux API tuner.
4403 * Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
4404 */
4405static int mxl5005s_reset(struct dvb_frontend *fe)
7f5c3aff 4406{
48937295
ST		 4407 struct mxl5005s_state *state = fe->tuner_priv;
4408 int ret = 0;
7f5c3aff 4409
48937295
ST		 4410 u8 buf[2] = { 0xff, 0x00 };
4411 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
4412 .buf = buf, .len = 2 };
7f5c3aff 4413
48937295 4414 dprintk(2, "%s()\n", __func__);
7f5c3aff 4415
48937295
ST		 4416 if (fe->ops.i2c_gate_ctrl)
4417 fe->ops.i2c_gate_ctrl(fe, 1);
7f5c3aff 4418
48937295
ST		 4419 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
4420 printk(KERN_WARNING "mxl5005s I2C reset failed\n");
4421 ret = -EREMOTEIO;
4422 }
7f5c3aff 4423
48937295
ST		 4424 if (fe->ops.i2c_gate_ctrl)
4425 fe->ops.i2c_gate_ctrl(fe, 0);
7f5c3aff 4426
48937295 4427 return ret;
7f5c3aff
ST		 4428}
4429
48937295
ST		 4430/* Write a single byte to a single reg, latch the value if required by
4431 * following the transaction with the latch byte.
4432 */
4433static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch)
7f5c3aff
ST		 4434{
4435 struct mxl5005s_state *state = fe->tuner_priv;
48937295
ST		 4436 u8 buf[3] = { reg, val, MXL5005S_LATCH_BYTE };
4437 struct i2c_msg msg = { .addr = state->config->i2c_address, .flags = 0,
4438 .buf = buf, .len = 3 };
7f5c3aff 4439
48937295
ST		 4440 if (latch == 0)
4441 msg.len = 2;
7f5c3aff 4442
48937295
ST		 4443 dprintk(2, "%s(reg = 0x%x val = 0x%x addr = 0x%x)\n", __func__, reg, val, msg.addr);
4444
4445 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
4446 printk(KERN_WARNING "mxl5005s I2C write failed\n");
4447 return -EREMOTEIO;
4448 }
7f5c3aff
ST		 4449 return 0;
4450}
4451
48937295 4452int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len)
7f5c3aff 4453{
48937295 4454 int ret = 0, i;
7f5c3aff 4455
48937295
ST		 4456 if (fe->ops.i2c_gate_ctrl)
4457 fe->ops.i2c_gate_ctrl(fe, 1);
7f5c3aff 4458
48937295
ST		 4459 for (i = 0 ; i < len-1; i++) {
4460 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 0);
4461 if (ret < 0)
4462 break;
4463 }
4464
4465 ret = mxl5005s_writereg(fe, addrtable[i], datatable[i], 1);
4466
4467 if (fe->ops.i2c_gate_ctrl)
4468 fe->ops.i2c_gate_ctrl(fe, 0);
4469
4470 return ret;
7f5c3aff 4471}
52c99bda 4472
48937295
ST		 4473
4474int mxl5005s_init(struct dvb_frontend *fe)
7f5c3aff
ST		 4475{
4476 dprintk(1, "%s()\n", __func__);
48937295 4477 return mxl5005s_reconfigure(fe, MXL_QAM, MXL5005S_BANDWIDTH_6MHZ);
7f5c3aff
ST		 4478}
4479
48937295 4480int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth)
8c66a19d
ST		 4481{
4482 struct mxl5005s_state *state = fe->tuner_priv;
48937295 4483
8c66a19d
ST		 4484 u8 AddrTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4485 u8 ByteTable[MXL5005S_REG_WRITING_TABLE_LEN_MAX];
4486 int TableLen;
4487
48937295 4488 dprintk(1, "%s(type=%d, bw=%d)\n", __func__, mod_type, bandwidth);
8c66a19d 4489
48937295 4490 mxl5005s_reset(fe);
8c66a19d
ST		 4491
4492 /* Tuner initialization stage 0 */
4493 MXL_GetMasterControl(ByteTable, MC_SYNTH_RESET);
4494 AddrTable[0] = MASTER_CONTROL_ADDR;
4495 ByteTable[0] |= state->config->AgcMasterByte;
85d220d0 4496
48937295
ST		 4497 mxl5005s_writeregs(fe, AddrTable, ByteTable, 1);
4498
4499 mxl5005s_AssignTunerMode(fe, mod_type, bandwidth);
8c66a19d
ST		 4500
4501 /* Tuner initialization stage 1 */
4502 MXL_GetInitRegister(fe, AddrTable, ByteTable, &TableLen);
4503
48937295
ST		 4504 mxl5005s_writeregs(fe, AddrTable, ByteTable, TableLen);
4505
4506 return 0;
4507}
4508
4509int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth)
4510{
4511 struct mxl5005s_state *state = fe->tuner_priv;
4512 struct mxl5005s_config *c = state->config;
4513
4514 InitTunerControls(fe);
4515
4516 /* Set MxL5005S parameters. */
4517 MXL5005_TunerConfig(
4518 fe,
4519 c->mod_mode,
4520 c->if_mode,
4521 bandwidth,
4522 c->if_freq,
4523 c->xtal_freq,
4524 c->agc_mode,
4525 c->top,
4526 c->output_load,
4527 c->clock_out,
4528 c->div_out,
4529 c->cap_select,
4530 c->rssi_enable,
4531 mod_type,
4532 c->tracking_filter);
4533
4534 return 0;
4535}
4536
4537static int mxl5005s_set_params(struct dvb_frontend *fe,
4538 struct dvb_frontend_parameters *params)
4539{
4540 struct mxl5005s_state *state = fe->tuner_priv;
4541 u32 req_mode, req_bw = 0;
4542 int ret;
4543
4544 dprintk(1, "%s()\n", __func__);
4545
4546 if (fe->ops.info.type == FE_ATSC) {
4547 switch (params->u.vsb.modulation) {
4548 case VSB_8:
4549 req_mode = MXL_ATSC; break;
4550 default:
4551 case QAM_64:
4552 case QAM_256:
4553 case QAM_AUTO:
4554 req_mode = MXL_QAM; break;
4555 }
4556 }
4557 else req_mode = MXL_DVBT;
4558
4559 /* Change tuner for new modulation type if reqd */
4560 if (req_mode != state->current_mode) {
4561 switch (req_mode) {
4562 case VSB_8:
4563 case QAM_64:
4564 case QAM_256:
4565 case QAM_AUTO:
4566 req_bw = MXL5005S_BANDWIDTH_6MHZ;
4567 break;
4568 default:
4569 /* Assume DVB-T */
4570 switch (params->u.ofdm.bandwidth) {
4571 case BANDWIDTH_6_MHZ:
4572 req_bw = MXL5005S_BANDWIDTH_6MHZ;
4573 break;
4574 case BANDWIDTH_7_MHZ:
4575 req_bw = MXL5005S_BANDWIDTH_7MHZ;
4576 break;
4577 case BANDWIDTH_AUTO:
4578 case BANDWIDTH_8_MHZ:
4579 req_bw = MXL5005S_BANDWIDTH_8MHZ;
4580 break;
4581 }
4582 }
4583
4584 state->current_mode = req_mode;
4585 ret = mxl5005s_reconfigure(fe, req_mode, req_bw);
4586
4587 } else
4588 ret = 0;
4589
4590 if (ret == 0) {
4591 dprintk(1, "%s() freq=%d\n", __func__, params->frequency);
4592 ret = mxl5005s_SetRfFreqHz(fe, params->frequency);
4593 }
4594
4595 return ret;
4596}
4597
4598static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency)
4599{
4600 struct mxl5005s_state *state = fe->tuner_priv;
4601 dprintk(1, "%s()\n", __func__);
4602
4603 *frequency = state->RF_IN;
4604
4605 return 0;
4606}
4607
4608static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
4609{
4610 struct mxl5005s_state *state = fe->tuner_priv;
4611 dprintk(1, "%s()\n", __func__);
4612
4613 *bandwidth = state->Chan_Bandwidth;
85d220d0
ST		 4614
4615 return 0;
4616}
4617
85d220d0
ST		 4618static int mxl5005s_release(struct dvb_frontend *fe)
4619{
4620 dprintk(1, "%s()\n", __func__);
4621 kfree(fe->tuner_priv);
4622 fe->tuner_priv = NULL;
4623 return 0;
4624}
4625
4626static const struct dvb_tuner_ops mxl5005s_tuner_ops = {
4627 .info = {
4628 .name = "MaxLinear MXL5005S",
4629 .frequency_min = 48000000,
4630 .frequency_max = 860000000,
4631 .frequency_step = 50000,
4632 },
4633
4634 .release = mxl5005s_release,
4635 .init = mxl5005s_init,
4636
4637 .set_params = mxl5005s_set_params,
4638 .get_frequency = mxl5005s_get_frequency,
4639 .get_bandwidth = mxl5005s_get_bandwidth,
85d220d0
ST		 4640};
4641
4642struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
4643 struct i2c_adapter *i2c,
4644 struct mxl5005s_config *config)
4645{
4646 struct mxl5005s_state *state = NULL;
4647 dprintk(1, "%s()\n", __func__);
4648
4649 state = kzalloc(sizeof(struct mxl5005s_state), GFP_KERNEL);
4650 if (state == NULL)
4651 return NULL;
4652
4653 state->frontend = fe;
4654 state->config = config;
4655 state->i2c = i2c;
48937295 4656 state->current_mode = MXL_QAM;
85d220d0
ST		 4657
4658 printk(KERN_INFO "MXL5005S: Attached at address 0x%02x\n", config->i2c_address);
4659
4660 memcpy(&fe->ops.tuner_ops, &mxl5005s_tuner_ops, sizeof(struct dvb_tuner_ops));
4661
4662 fe->tuner_priv = state;
4663 return fe;
4664}
4665EXPORT_SYMBOL(mxl5005s_attach);
4666
4667MODULE_DESCRIPTION("MaxLinear MXL5005S silicon tuner driver");
85d220d0
ST		 4668MODULE_AUTHOR("Steven Toth");
4669MODULE_LICENSE("GPL");
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