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1/*
2 * mxl5007t.c - driver for the MaxLinear MxL5007T silicon tuner
3 *
7434ca43 4 * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
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5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/i2c.h>
22#include <linux/types.h>
23#include <linux/videodev2.h>
24#include "tuner-i2c.h"
25#include "mxl5007t.h"
26
27static DEFINE_MUTEX(mxl5007t_list_mutex);
28static LIST_HEAD(hybrid_tuner_instance_list);
29
30static int mxl5007t_debug;
31module_param_named(debug, mxl5007t_debug, int, 0644);
32MODULE_PARM_DESC(debug, "set debug level");
33
34/* ------------------------------------------------------------------------- */
35
36#define mxl_printk(kern, fmt, arg...) \
37 printk(kern "%s: " fmt "\n", __func__, ##arg)
38
39#define mxl_err(fmt, arg...) \
40 mxl_printk(KERN_ERR, "%d: " fmt, __LINE__, ##arg)
41
42#define mxl_warn(fmt, arg...) \
43 mxl_printk(KERN_WARNING, fmt, ##arg)
44
45#define mxl_info(fmt, arg...) \
46 mxl_printk(KERN_INFO, fmt, ##arg)
47
48#define mxl_debug(fmt, arg...) \
49({ \
50 if (mxl5007t_debug) \
51 mxl_printk(KERN_DEBUG, fmt, ##arg); \
52})
53
54#define mxl_fail(ret) \
55({ \
56 int __ret; \
57 __ret = (ret < 0); \
58 if (__ret) \
59 mxl_printk(KERN_ERR, "error %d on line %d", \
60 ret, __LINE__); \
61 __ret; \
62})
63
64/* ------------------------------------------------------------------------- */
65
66#define MHz 1000000
67
68enum mxl5007t_mode {
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69 MxL_MODE_ISDBT = 0,
70 MxL_MODE_DVBT = 1,
71 MxL_MODE_ATSC = 2,
72 MxL_MODE_CABLE = 0x10,
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73};
74
75enum mxl5007t_chip_version {
76 MxL_UNKNOWN_ID = 0x00,
77 MxL_5007_V1_F1 = 0x11,
78 MxL_5007_V1_F2 = 0x12,
7434ca43 79 MxL_5007_V4 = 0x14,
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80 MxL_5007_V2_100_F1 = 0x21,
81 MxL_5007_V2_100_F2 = 0x22,
82 MxL_5007_V2_200_F1 = 0x23,
83 MxL_5007_V2_200_F2 = 0x24,
84};
85
86struct reg_pair_t {
87 u8 reg;
88 u8 val;
89};
90
91/* ------------------------------------------------------------------------- */
92
93static struct reg_pair_t init_tab[] = {
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94 { 0x02, 0x06 },
95 { 0x03, 0x48 },
96 { 0x05, 0x04 },
97 { 0x06, 0x10 },
98 { 0x2e, 0x15 }, /* OVERRIDE */
99 { 0x30, 0x10 }, /* OVERRIDE */
100 { 0x45, 0x58 }, /* OVERRIDE */
101 { 0x48, 0x19 }, /* OVERRIDE */
102 { 0x52, 0x03 }, /* OVERRIDE */
103 { 0x53, 0x44 }, /* OVERRIDE */
104 { 0x6a, 0x4b }, /* OVERRIDE */
105 { 0x76, 0x00 }, /* OVERRIDE */
106 { 0x78, 0x18 }, /* OVERRIDE */
107 { 0x7a, 0x17 }, /* OVERRIDE */
108 { 0x85, 0x06 }, /* OVERRIDE */
109 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
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110 { 0, 0 }
111};
112
113static struct reg_pair_t init_tab_cable[] = {
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114 { 0x02, 0x06 },
115 { 0x03, 0x48 },
116 { 0x05, 0x04 },
117 { 0x06, 0x10 },
118 { 0x09, 0x3f },
119 { 0x0a, 0x3f },
120 { 0x0b, 0x3f },
121 { 0x2e, 0x15 }, /* OVERRIDE */
122 { 0x30, 0x10 }, /* OVERRIDE */
123 { 0x45, 0x58 }, /* OVERRIDE */
124 { 0x48, 0x19 }, /* OVERRIDE */
125 { 0x52, 0x03 }, /* OVERRIDE */
126 { 0x53, 0x44 }, /* OVERRIDE */
127 { 0x6a, 0x4b }, /* OVERRIDE */
128 { 0x76, 0x00 }, /* OVERRIDE */
129 { 0x78, 0x18 }, /* OVERRIDE */
130 { 0x7a, 0x17 }, /* OVERRIDE */
131 { 0x85, 0x06 }, /* OVERRIDE */
132 { 0x01, 0x01 }, /* TOP_MASTER_ENABLE */
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133 { 0, 0 }
134};
135
136/* ------------------------------------------------------------------------- */
137
138static struct reg_pair_t reg_pair_rftune[] = {
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139 { 0x0f, 0x00 }, /* abort tune */
140 { 0x0c, 0x15 },
141 { 0x0d, 0x40 },
142 { 0x0e, 0x0e },
143 { 0x1f, 0x87 }, /* OVERRIDE */
144 { 0x20, 0x1f }, /* OVERRIDE */
145 { 0x21, 0x87 }, /* OVERRIDE */
146 { 0x22, 0x1f }, /* OVERRIDE */
147 { 0x80, 0x01 }, /* freq dependent */
148 { 0x0f, 0x01 }, /* start tune */
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149 { 0, 0 }
150};
151
152/* ------------------------------------------------------------------------- */
153
154struct mxl5007t_state {
155 struct list_head hybrid_tuner_instance_list;
156 struct tuner_i2c_props i2c_props;
157
158 struct mutex lock;
159
160 struct mxl5007t_config *config;
161
162 enum mxl5007t_chip_version chip_id;
163
164 struct reg_pair_t tab_init[ARRAY_SIZE(init_tab)];
165 struct reg_pair_t tab_init_cable[ARRAY_SIZE(init_tab_cable)];
166 struct reg_pair_t tab_rftune[ARRAY_SIZE(reg_pair_rftune)];
167
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168 enum mxl5007t_if_freq if_freq;
169
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170 u32 frequency;
171 u32 bandwidth;
172};
173
174/* ------------------------------------------------------------------------- */
175
176/* called by _init and _rftun to manipulate the register arrays */
177
178static void set_reg_bits(struct reg_pair_t *reg_pair, u8 reg, u8 mask, u8 val)
179{
180 unsigned int i = 0;
181
182 while (reg_pair[i].reg || reg_pair[i].val) {
183 if (reg_pair[i].reg == reg) {
184 reg_pair[i].val &= ~mask;
185 reg_pair[i].val |= val;
186 }
187 i++;
188
189 }
190 return;
191}
192
193static void copy_reg_bits(struct reg_pair_t *reg_pair1,
194 struct reg_pair_t *reg_pair2)
195{
196 unsigned int i, j;
197
198 i = j = 0;
199
200 while (reg_pair1[i].reg || reg_pair1[i].val) {
c95a419a 201 while (reg_pair2[j].reg || reg_pair2[j].val) {
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202 if (reg_pair1[i].reg != reg_pair2[j].reg) {
203 j++;
204 continue;
205 }
206 reg_pair2[j].val = reg_pair1[i].val;
207 break;
208 }
209 i++;
210 }
211 return;
212}
213
214/* ------------------------------------------------------------------------- */
215
216static void mxl5007t_set_mode_bits(struct mxl5007t_state *state,
217 enum mxl5007t_mode mode,
218 s32 if_diff_out_level)
219{
220 switch (mode) {
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221 case MxL_MODE_ATSC:
222 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x12);
2a83e4d5 223 break;
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224 case MxL_MODE_DVBT:
225 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x11);
2a83e4d5 226 break;
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227 case MxL_MODE_ISDBT:
228 set_reg_bits(state->tab_init, 0x06, 0x1f, 0x10);
229 break;
230 case MxL_MODE_CABLE:
231 set_reg_bits(state->tab_init_cable, 0x09, 0xff, 0xc1);
232 set_reg_bits(state->tab_init_cable, 0x0a, 0xff,
2a83e4d5 233 8 - if_diff_out_level);
7434ca43 234 set_reg_bits(state->tab_init_cable, 0x0b, 0xff, 0x17);
2a83e4d5 235 break;
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236 default:
237 mxl_fail(-EINVAL);
238 }
239 return;
240}
241
242static void mxl5007t_set_if_freq_bits(struct mxl5007t_state *state,
243 enum mxl5007t_if_freq if_freq,
244 int invert_if)
245{
246 u8 val;
247
248 switch (if_freq) {
249 case MxL_IF_4_MHZ:
250 val = 0x00;
251 break;
252 case MxL_IF_4_5_MHZ:
7434ca43 253 val = 0x02;
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254 break;
255 case MxL_IF_4_57_MHZ:
7434ca43 256 val = 0x03;
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257 break;
258 case MxL_IF_5_MHZ:
7434ca43 259 val = 0x04;
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260 break;
261 case MxL_IF_5_38_MHZ:
7434ca43 262 val = 0x05;
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263 break;
264 case MxL_IF_6_MHZ:
7434ca43 265 val = 0x06;
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266 break;
267 case MxL_IF_6_28_MHZ:
7434ca43 268 val = 0x07;
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269 break;
270 case MxL_IF_9_1915_MHZ:
7434ca43 271 val = 0x08;
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272 break;
273 case MxL_IF_35_25_MHZ:
7434ca43 274 val = 0x09;
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275 break;
276 case MxL_IF_36_15_MHZ:
7434ca43 277 val = 0x0a;
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278 break;
279 case MxL_IF_44_MHZ:
7434ca43 280 val = 0x0b;
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281 break;
282 default:
283 mxl_fail(-EINVAL);
284 return;
285 }
7434ca43 286 set_reg_bits(state->tab_init, 0x02, 0x0f, val);
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287
288 /* set inverted IF or normal IF */
7434ca43 289 set_reg_bits(state->tab_init, 0x02, 0x10, invert_if ? 0x10 : 0x00);
2a83e4d5 290
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291 state->if_freq = if_freq;
292
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293 return;
294}
295
296static void mxl5007t_set_xtal_freq_bits(struct mxl5007t_state *state,
297 enum mxl5007t_xtal_freq xtal_freq)
298{
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299 switch (xtal_freq) {
300 case MxL_XTAL_16_MHZ:
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301 /* select xtal freq & ref freq */
302 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x00);
303 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x00);
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304 break;
305 case MxL_XTAL_20_MHZ:
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306 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x10);
307 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x01);
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308 break;
309 case MxL_XTAL_20_25_MHZ:
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310 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x20);
311 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x02);
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312 break;
313 case MxL_XTAL_20_48_MHZ:
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314 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x30);
315 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x03);
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316 break;
317 case MxL_XTAL_24_MHZ:
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318 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x40);
319 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x04);
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320 break;
321 case MxL_XTAL_25_MHZ:
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322 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x50);
323 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x05);
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324 break;
325 case MxL_XTAL_25_14_MHZ:
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326 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x60);
327 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x06);
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328 break;
329 case MxL_XTAL_27_MHZ:
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330 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x70);
331 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x07);
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332 break;
333 case MxL_XTAL_28_8_MHZ:
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334 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x80);
335 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x08);
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336 break;
337 case MxL_XTAL_32_MHZ:
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338 set_reg_bits(state->tab_init, 0x03, 0xf0, 0x90);
339 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x09);
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340 break;
341 case MxL_XTAL_40_MHZ:
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342 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xa0);
343 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0a);
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344 break;
345 case MxL_XTAL_44_MHZ:
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346 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xb0);
347 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0b);
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348 break;
349 case MxL_XTAL_48_MHZ:
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350 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xc0);
351 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0c);
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352 break;
353 case MxL_XTAL_49_3811_MHZ:
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354 set_reg_bits(state->tab_init, 0x03, 0xf0, 0xd0);
355 set_reg_bits(state->tab_init, 0x05, 0x0f, 0x0d);
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356 break;
357 default:
358 mxl_fail(-EINVAL);
359 return;
360 }
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361
362 return;
363}
364
365static struct reg_pair_t *mxl5007t_calc_init_regs(struct mxl5007t_state *state,
366 enum mxl5007t_mode mode)
367{
368 struct mxl5007t_config *cfg = state->config;
369
370 memcpy(&state->tab_init, &init_tab, sizeof(init_tab));
371 memcpy(&state->tab_init_cable, &init_tab_cable, sizeof(init_tab_cable));
372
373 mxl5007t_set_mode_bits(state, mode, cfg->if_diff_out_level);
374 mxl5007t_set_if_freq_bits(state, cfg->if_freq_hz, cfg->invert_if);
375 mxl5007t_set_xtal_freq_bits(state, cfg->xtal_freq_hz);
376
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377 set_reg_bits(state->tab_init, 0x04, 0x01, cfg->loop_thru_enable);
378 set_reg_bits(state->tab_init, 0x03, 0x08, cfg->clk_out_enable << 3);
379 set_reg_bits(state->tab_init, 0x03, 0x07, cfg->clk_out_amp);
2a83e4d5 380
7434ca43 381 if (mode >= MxL_MODE_CABLE) {
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382 copy_reg_bits(state->tab_init, state->tab_init_cable);
383 return state->tab_init_cable;
384 } else
385 return state->tab_init;
386}
387
388/* ------------------------------------------------------------------------- */
389
390enum mxl5007t_bw_mhz {
391 MxL_BW_6MHz = 6,
392 MxL_BW_7MHz = 7,
393 MxL_BW_8MHz = 8,
394};
395
396static void mxl5007t_set_bw_bits(struct mxl5007t_state *state,
397 enum mxl5007t_bw_mhz bw)
398{
399 u8 val;
400
401 switch (bw) {
402 case MxL_BW_6MHz:
403 val = 0x15; /* set DIG_MODEINDEX, DIG_MODEINDEX_A,
404 * and DIG_MODEINDEX_CSF */
405 break;
406 case MxL_BW_7MHz:
7434ca43 407 val = 0x2a;
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408 break;
409 case MxL_BW_8MHz:
410 val = 0x3f;
411 break;
412 default:
413 mxl_fail(-EINVAL);
414 return;
415 }
7434ca43 416 set_reg_bits(state->tab_rftune, 0x0c, 0x3f, val);
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417
418 return;
419}
420
421static struct
422reg_pair_t *mxl5007t_calc_rf_tune_regs(struct mxl5007t_state *state,
423 u32 rf_freq, enum mxl5007t_bw_mhz bw)
424{
425 u32 dig_rf_freq = 0;
426 u32 temp;
427 u32 frac_divider = 1000000;
428 unsigned int i;
429
430 memcpy(&state->tab_rftune, &reg_pair_rftune, sizeof(reg_pair_rftune));
431
432 mxl5007t_set_bw_bits(state, bw);
433
434 /* Convert RF frequency into 16 bits =>
435 * 10 bit integer (MHz) + 6 bit fraction */
436 dig_rf_freq = rf_freq / MHz;
437
438 temp = rf_freq % MHz;
439
440 for (i = 0; i < 6; i++) {
441 dig_rf_freq <<= 1;
442 frac_divider /= 2;
443 if (temp > frac_divider) {
444 temp -= frac_divider;
445 dig_rf_freq++;
446 }
447 }
448
449 /* add to have shift center point by 7.8124 kHz */
450 if (temp > 7812)
451 dig_rf_freq++;
452
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453 set_reg_bits(state->tab_rftune, 0x0d, 0xff, (u8) dig_rf_freq);
454 set_reg_bits(state->tab_rftune, 0x0e, 0xff, (u8) (dig_rf_freq >> 8));
455
456 if (rf_freq >= 333000000)
457 set_reg_bits(state->tab_rftune, 0x80, 0x40, 0x40);
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458
459 return state->tab_rftune;
460}
461
462/* ------------------------------------------------------------------------- */
463
464static int mxl5007t_write_reg(struct mxl5007t_state *state, u8 reg, u8 val)
465{
466 u8 buf[] = { reg, val };
467 struct i2c_msg msg = { .addr = state->i2c_props.addr, .flags = 0,
468 .buf = buf, .len = 2 };
469 int ret;
470
471 ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
472 if (ret != 1) {
473 mxl_err("failed!");
474 return -EREMOTEIO;
475 }
476 return 0;
477}
478
479static int mxl5007t_write_regs(struct mxl5007t_state *state,
480 struct reg_pair_t *reg_pair)
481{
482 unsigned int i = 0;
483 int ret = 0;
484
485 while ((ret == 0) && (reg_pair[i].reg || reg_pair[i].val)) {
486 ret = mxl5007t_write_reg(state,
487 reg_pair[i].reg, reg_pair[i].val);
488 i++;
489 }
490 return ret;
491}
492
493static int mxl5007t_read_reg(struct mxl5007t_state *state, u8 reg, u8 *val)
494{
576b849e 495 u8 buf[2] = { 0xfb, reg };
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496 struct i2c_msg msg[] = {
497 { .addr = state->i2c_props.addr, .flags = 0,
576b849e 498 .buf = buf, .len = 2 },
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499 { .addr = state->i2c_props.addr, .flags = I2C_M_RD,
500 .buf = val, .len = 1 },
501 };
502 int ret;
503
504 ret = i2c_transfer(state->i2c_props.adap, msg, 2);
505 if (ret != 2) {
506 mxl_err("failed!");
507 return -EREMOTEIO;
508 }
509 return 0;
510}
511
512static int mxl5007t_soft_reset(struct mxl5007t_state *state)
513{
514 u8 d = 0xff;
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515 struct i2c_msg msg = {
516 .addr = state->i2c_props.addr, .flags = 0,
517 .buf = &d, .len = 1
518 };
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519 int ret = i2c_transfer(state->i2c_props.adap, &msg, 1);
520
521 if (ret != 1) {
522 mxl_err("failed!");
523 return -EREMOTEIO;
524 }
525 return 0;
526}
527
528static int mxl5007t_tuner_init(struct mxl5007t_state *state,
529 enum mxl5007t_mode mode)
530{
531 struct reg_pair_t *init_regs;
532 int ret;
533
534 ret = mxl5007t_soft_reset(state);
535 if (mxl_fail(ret))
536 goto fail;
537
538 /* calculate initialization reg array */
539 init_regs = mxl5007t_calc_init_regs(state, mode);
540
541 ret = mxl5007t_write_regs(state, init_regs);
542 if (mxl_fail(ret))
543 goto fail;
544 mdelay(1);
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545fail:
546 return ret;
547}
548
549static int mxl5007t_tuner_rf_tune(struct mxl5007t_state *state, u32 rf_freq_hz,
550 enum mxl5007t_bw_mhz bw)
551{
552 struct reg_pair_t *rf_tune_regs;
553 int ret;
554
555 /* calculate channel change reg array */
556 rf_tune_regs = mxl5007t_calc_rf_tune_regs(state, rf_freq_hz, bw);
557
558 ret = mxl5007t_write_regs(state, rf_tune_regs);
559 if (mxl_fail(ret))
560 goto fail;
561 msleep(3);
562fail:
563 return ret;
564}
565
566/* ------------------------------------------------------------------------- */
567
568static int mxl5007t_synth_lock_status(struct mxl5007t_state *state,
569 int *rf_locked, int *ref_locked)
570{
571 u8 d;
572 int ret;
573
574 *rf_locked = 0;
575 *ref_locked = 0;
576
7434ca43 577 ret = mxl5007t_read_reg(state, 0xd8, &d);
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578 if (mxl_fail(ret))
579 goto fail;
580
581 if ((d & 0x0c) == 0x0c)
582 *rf_locked = 1;
583
584 if ((d & 0x03) == 0x03)
585 *ref_locked = 1;
586fail:
587 return ret;
588}
589
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MK
590/* ------------------------------------------------------------------------- */
591
592static int mxl5007t_get_status(struct dvb_frontend *fe, u32 *status)
593{
594 struct mxl5007t_state *state = fe->tuner_priv;
d90958e6
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595 int rf_locked, ref_locked, ret;
596
597 *status = 0;
2a83e4d5 598
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599 if (fe->ops.i2c_gate_ctrl)
600 fe->ops.i2c_gate_ctrl(fe, 1);
601
602 ret = mxl5007t_synth_lock_status(state, &rf_locked, &ref_locked);
603 if (mxl_fail(ret))
604 goto fail;
605 mxl_debug("%s%s", rf_locked ? "rf locked " : "",
606 ref_locked ? "ref locked" : "");
d90958e6
MK
607
608 if ((rf_locked) || (ref_locked))
609 *status |= TUNER_STATUS_LOCKED;
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610fail:
611 if (fe->ops.i2c_gate_ctrl)
612 fe->ops.i2c_gate_ctrl(fe, 0);
613
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614 return ret;
615}
616
617/* ------------------------------------------------------------------------- */
618
14d24d14 619static int mxl5007t_set_params(struct dvb_frontend *fe)
2a83e4d5 620{
e12617e6
MCC
621 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
622 u32 delsys = c->delivery_system;
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MK
623 struct mxl5007t_state *state = fe->tuner_priv;
624 enum mxl5007t_bw_mhz bw;
625 enum mxl5007t_mode mode;
626 int ret;
e12617e6
MCC
627 u32 freq = c->frequency;
628 u32 band = BANDWIDTH_6_MHZ;
2a83e4d5 629
e12617e6
MCC
630 switch (delsys) {
631 case SYS_ATSC:
632 mode = MxL_MODE_ATSC;
633 bw = MxL_BW_6MHz;
634 break;
635 case SYS_DVBC_ANNEX_B:
636 mode = MxL_MODE_CABLE;
2a83e4d5 637 bw = MxL_BW_6MHz;
e12617e6
MCC
638 break;
639 case SYS_DVBT:
640 case SYS_DVBT2:
641 mode = MxL_MODE_DVBT;
642 switch (c->bandwidth_hz) {
643 case 6000000:
2a83e4d5
MK
644 bw = MxL_BW_6MHz;
645 break;
e12617e6 646 case 7000000:
2a83e4d5 647 bw = MxL_BW_7MHz;
e12617e6
MCC
648 band = BANDWIDTH_7_MHZ;
649 case 8000000:
2a83e4d5 650 bw = MxL_BW_8MHz;
e12617e6 651 band = BANDWIDTH_8_MHZ;
2a83e4d5 652 default:
2a83e4d5
MK
653 return -EINVAL;
654 }
e12617e6
MCC
655 break;
656 default:
2a83e4d5
MK
657 mxl_err("modulation type not supported!");
658 return -EINVAL;
659 }
660
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661 if (fe->ops.i2c_gate_ctrl)
662 fe->ops.i2c_gate_ctrl(fe, 1);
663
c39c1fd2
MK
664 mutex_lock(&state->lock);
665
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MK
666 ret = mxl5007t_tuner_init(state, mode);
667 if (mxl_fail(ret))
668 goto fail;
669
670 ret = mxl5007t_tuner_rf_tune(state, freq, bw);
671 if (mxl_fail(ret))
672 goto fail;
673
674 state->frequency = freq;
e12617e6 675 state->bandwidth = band;
2a83e4d5 676fail:
c39c1fd2
MK
677 mutex_unlock(&state->lock);
678
2a83e4d5
MK
679 if (fe->ops.i2c_gate_ctrl)
680 fe->ops.i2c_gate_ctrl(fe, 0);
681
2a83e4d5
MK
682 return ret;
683}
684
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685/* ------------------------------------------------------------------------- */
686
687static int mxl5007t_init(struct dvb_frontend *fe)
688{
689 struct mxl5007t_state *state = fe->tuner_priv;
452a53a2 690 int ret;
2a83e4d5 691
452a53a2
MK
692 if (fe->ops.i2c_gate_ctrl)
693 fe->ops.i2c_gate_ctrl(fe, 1);
694
7434ca43
MK
695 /* wake from standby */
696 ret = mxl5007t_write_reg(state, 0x01, 0x01);
452a53a2 697 mxl_fail(ret);
7434ca43 698
452a53a2
MK
699 if (fe->ops.i2c_gate_ctrl)
700 fe->ops.i2c_gate_ctrl(fe, 0);
701
452a53a2 702 return ret;
2a83e4d5
MK
703}
704
705static int mxl5007t_sleep(struct dvb_frontend *fe)
706{
707 struct mxl5007t_state *state = fe->tuner_priv;
452a53a2 708 int ret;
2a83e4d5 709
452a53a2
MK
710 if (fe->ops.i2c_gate_ctrl)
711 fe->ops.i2c_gate_ctrl(fe, 1);
712
7434ca43
MK
713 /* enter standby mode */
714 ret = mxl5007t_write_reg(state, 0x01, 0x00);
452a53a2 715 mxl_fail(ret);
7434ca43
MK
716 ret = mxl5007t_write_reg(state, 0x0f, 0x00);
717 mxl_fail(ret);
718
452a53a2
MK
719 if (fe->ops.i2c_gate_ctrl)
720 fe->ops.i2c_gate_ctrl(fe, 0);
721
452a53a2 722 return ret;
2a83e4d5
MK
723}
724
725/* ------------------------------------------------------------------------- */
726
727static int mxl5007t_get_frequency(struct dvb_frontend *fe, u32 *frequency)
728{
729 struct mxl5007t_state *state = fe->tuner_priv;
730 *frequency = state->frequency;
731 return 0;
732}
733
734static int mxl5007t_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
735{
736 struct mxl5007t_state *state = fe->tuner_priv;
737 *bandwidth = state->bandwidth;
738 return 0;
739}
740
d697b4ce
MK
741static int mxl5007t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
742{
743 struct mxl5007t_state *state = fe->tuner_priv;
744
745 *frequency = 0;
746
747 switch (state->if_freq) {
748 case MxL_IF_4_MHZ:
749 *frequency = 4000000;
750 break;
751 case MxL_IF_4_5_MHZ:
752 *frequency = 4500000;
753 break;
754 case MxL_IF_4_57_MHZ:
755 *frequency = 4570000;
756 break;
757 case MxL_IF_5_MHZ:
758 *frequency = 5000000;
759 break;
760 case MxL_IF_5_38_MHZ:
761 *frequency = 5380000;
762 break;
763 case MxL_IF_6_MHZ:
764 *frequency = 6000000;
765 break;
766 case MxL_IF_6_28_MHZ:
767 *frequency = 6280000;
768 break;
769 case MxL_IF_9_1915_MHZ:
770 *frequency = 9191500;
771 break;
772 case MxL_IF_35_25_MHZ:
773 *frequency = 35250000;
774 break;
775 case MxL_IF_36_15_MHZ:
776 *frequency = 36150000;
777 break;
778 case MxL_IF_44_MHZ:
779 *frequency = 44000000;
780 break;
781 }
782 return 0;
783}
784
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785static int mxl5007t_release(struct dvb_frontend *fe)
786{
787 struct mxl5007t_state *state = fe->tuner_priv;
788
789 mutex_lock(&mxl5007t_list_mutex);
790
791 if (state)
792 hybrid_tuner_release_state(state);
793
794 mutex_unlock(&mxl5007t_list_mutex);
795
796 fe->tuner_priv = NULL;
797
798 return 0;
799}
800
801/* ------------------------------------------------------------------------- */
802
803static struct dvb_tuner_ops mxl5007t_tuner_ops = {
804 .info = {
805 .name = "MaxLinear MxL5007T",
806 },
807 .init = mxl5007t_init,
808 .sleep = mxl5007t_sleep,
809 .set_params = mxl5007t_set_params,
2a83e4d5
MK
810 .get_status = mxl5007t_get_status,
811 .get_frequency = mxl5007t_get_frequency,
812 .get_bandwidth = mxl5007t_get_bandwidth,
813 .release = mxl5007t_release,
d697b4ce 814 .get_if_frequency = mxl5007t_get_if_frequency,
2a83e4d5
MK
815};
816
817static int mxl5007t_get_chip_id(struct mxl5007t_state *state)
818{
819 char *name;
820 int ret;
821 u8 id;
822
7434ca43 823 ret = mxl5007t_read_reg(state, 0xd9, &id);
2a83e4d5
MK
824 if (mxl_fail(ret))
825 goto fail;
826
827 switch (id) {
828 case MxL_5007_V1_F1:
829 name = "MxL5007.v1.f1";
830 break;
831 case MxL_5007_V1_F2:
832 name = "MxL5007.v1.f2";
833 break;
834 case MxL_5007_V2_100_F1:
835 name = "MxL5007.v2.100.f1";
836 break;
837 case MxL_5007_V2_100_F2:
838 name = "MxL5007.v2.100.f2";
839 break;
840 case MxL_5007_V2_200_F1:
841 name = "MxL5007.v2.200.f1";
842 break;
843 case MxL_5007_V2_200_F2:
844 name = "MxL5007.v2.200.f2";
845 break;
7434ca43
MK
846 case MxL_5007_V4:
847 name = "MxL5007T.v4";
848 break;
2a83e4d5
MK
849 default:
850 name = "MxL5007T";
d202515b 851 printk(KERN_WARNING "%s: unknown rev (%02x)\n", __func__, id);
2a83e4d5
MK
852 id = MxL_UNKNOWN_ID;
853 }
854 state->chip_id = id;
855 mxl_info("%s detected @ %d-%04x", name,
856 i2c_adapter_id(state->i2c_props.adap),
857 state->i2c_props.addr);
858 return 0;
859fail:
860 mxl_warn("unable to identify device @ %d-%04x",
861 i2c_adapter_id(state->i2c_props.adap),
862 state->i2c_props.addr);
863
864 state->chip_id = MxL_UNKNOWN_ID;
865 return ret;
866}
867
868struct dvb_frontend *mxl5007t_attach(struct dvb_frontend *fe,
869 struct i2c_adapter *i2c, u8 addr,
870 struct mxl5007t_config *cfg)
871{
872 struct mxl5007t_state *state = NULL;
873 int instance, ret;
874
875 mutex_lock(&mxl5007t_list_mutex);
876 instance = hybrid_tuner_request_state(struct mxl5007t_state, state,
877 hybrid_tuner_instance_list,
3d0081dd 878 i2c, addr, "mxl5007t");
2a83e4d5
MK
879 switch (instance) {
880 case 0:
881 goto fail;
2a83e4d5
MK
882 case 1:
883 /* new tuner instance */
884 state->config = cfg;
885
886 mutex_init(&state->lock);
887
2a83e4d5
MK
888 if (fe->ops.i2c_gate_ctrl)
889 fe->ops.i2c_gate_ctrl(fe, 1);
890
891 ret = mxl5007t_get_chip_id(state);
892
893 if (fe->ops.i2c_gate_ctrl)
894 fe->ops.i2c_gate_ctrl(fe, 0);
895
2a83e4d5
MK
896 /* check return value of mxl5007t_get_chip_id */
897 if (mxl_fail(ret))
898 goto fail;
899 break;
900 default:
901 /* existing tuner instance */
902 break;
903 }
904 fe->tuner_priv = state;
905 mutex_unlock(&mxl5007t_list_mutex);
906
907 memcpy(&fe->ops.tuner_ops, &mxl5007t_tuner_ops,
908 sizeof(struct dvb_tuner_ops));
909
910 return fe;
911fail:
912 mutex_unlock(&mxl5007t_list_mutex);
913
914 mxl5007t_release(fe);
915 return NULL;
916}
917EXPORT_SYMBOL_GPL(mxl5007t_attach);
918MODULE_DESCRIPTION("MaxLinear MxL5007T Silicon IC tuner driver");
919MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
920MODULE_LICENSE("GPL");
7434ca43 921MODULE_VERSION("0.2");
2a83e4d5
MK
922
923/*
924 * Overrides for Emacs so that we follow Linus's tabbing style.
925 * ---------------------------------------------------------------------------
926 * Local variables:
927 * c-basic-offset: 8
928 * End:
929 */