[mirror_ubuntu-hirsute-kernel.git] / drivers / media / dvb / frontends / cx22702.c

/*
    Conexant 22702 DVB OFDM demodulator driver

    based on:
	Alps TDMB7 DVB OFDM demodulator driver

    Copyright (C) 2001-2002 Convergence Integrated Media GmbH
	  Holger Waechtler <holger@convergence.de>

    Copyright (C) 2004 Steven Toth <stoth@hauppauge.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

*/

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "dvb_frontend.h"
#include "dvb-pll.h"
#include "cx22702.h"


struct cx22702_state {

	struct i2c_adapter* i2c;

	struct dvb_frontend_ops ops;

	/* configuration settings */
	const struct cx22702_config* config;

	struct dvb_frontend frontend;

	/* previous uncorrected block counter */
	u8 prevUCBlocks;
};

static int debug = 0;
#define dprintk	if (debug) printk

/* Register values to initialise the demod */
static u8 init_tab [] = {
	0x00, 0x00, /* Stop aquisition */
	0x0B, 0x06,
	0x09, 0x01,
	0x0D, 0x41,
	0x16, 0x32,
	0x20, 0x0A,
	0x21, 0x17,
	0x24, 0x3e,
	0x26, 0xff,
	0x27, 0x10,
	0x28, 0x00,
	0x29, 0x00,
	0x2a, 0x10,
	0x2b, 0x00,
	0x2c, 0x10,
	0x2d, 0x00,
	0x48, 0xd4,
	0x49, 0x56,
	0x6b, 0x1e,
	0xc8, 0x02,
	0xf9, 0x00,
	0xfa, 0x00,
	0xfb, 0x00,
	0xfc, 0x00,
	0xfd, 0x00,
};

static int cx22702_writereg (struct cx22702_state* state, u8 reg, u8 data)
{
	int ret;
	u8 buf [] = { reg, data };
	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };

	ret = i2c_transfer(state->i2c, &msg, 1);

	if (ret != 1)
		printk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
			__FUNCTION__, reg, data, ret);

	return (ret != 1) ? -1 : 0;
}

static u8 cx22702_readreg (struct cx22702_state* state, u8 reg)
{
	int ret;
	u8 b0 [] = { reg };
	u8 b1 [] = { 0 };

	struct i2c_msg msg [] = {
		{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
		{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };

	ret = i2c_transfer(state->i2c, msg, 2);

	if (ret != 2)
		printk("%s: readreg error (ret == %i)\n", __FUNCTION__, ret);

	return b1[0];
}

static int cx22702_set_inversion (struct cx22702_state *state, int inversion)
{
	u8 val;

	switch (inversion) {

		case INVERSION_AUTO:
			return -EOPNOTSUPP;

		case INVERSION_ON:
			val = cx22702_readreg (state, 0x0C);
			return cx22702_writereg (state, 0x0C, val | 0x01);

		case INVERSION_OFF:
			val = cx22702_readreg (state, 0x0C);
			return cx22702_writereg (state, 0x0C, val & 0xfe);

		default:
			return -EINVAL;

	}

}

/* Retrieve the demod settings */
static int cx22702_get_tps (struct cx22702_state *state, struct dvb_ofdm_parameters *p)
{
	u8 val;

	/* Make sure the TPS regs are valid */
	if (!(cx22702_readreg(state, 0x0A) & 0x20))
		return -EAGAIN;

	val = cx22702_readreg (state, 0x01);
	switch( (val&0x18)>>3) {
		case 0: p->constellation =   QPSK; break;
		case 1: p->constellation = QAM_16; break;
		case 2: p->constellation = QAM_64; break;
	}
	switch( val&0x07 ) {
		case 0: p->hierarchy_information = HIERARCHY_NONE; break;
		case 1: p->hierarchy_information =    HIERARCHY_1; break;
		case 2: p->hierarchy_information =    HIERARCHY_2; break;
		case 3: p->hierarchy_information =    HIERARCHY_4; break;
	}


	val = cx22702_readreg (state, 0x02);
	switch( (val&0x38)>>3 ) {
		case 0: p->code_rate_HP = FEC_1_2; break;
		case 1: p->code_rate_HP = FEC_2_3; break;
		case 2: p->code_rate_HP = FEC_3_4; break;
		case 3: p->code_rate_HP = FEC_5_6; break;
		case 4: p->code_rate_HP = FEC_7_8; break;
	}
	switch( val&0x07 ) {
		case 0: p->code_rate_LP = FEC_1_2; break;
		case 1: p->code_rate_LP = FEC_2_3; break;
		case 2: p->code_rate_LP = FEC_3_4; break;
		case 3: p->code_rate_LP = FEC_5_6; break;
		case 4: p->code_rate_LP = FEC_7_8; break;
	}


	val = cx22702_readreg (state, 0x03);
	switch( (val&0x0c)>>2 ) {
		case 0: p->guard_interval = GUARD_INTERVAL_1_32; break;
		case 1: p->guard_interval = GUARD_INTERVAL_1_16; break;
		case 2: p->guard_interval =  GUARD_INTERVAL_1_8; break;
		case 3: p->guard_interval =  GUARD_INTERVAL_1_4; break;
	}
	switch( val&0x03 ) {
		case 0: p->transmission_mode = TRANSMISSION_MODE_2K; break;
		case 1: p->transmission_mode = TRANSMISSION_MODE_8K; break;
	}

	return 0;
}

/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
static int cx22702_set_tps (struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
	u8 val;
	struct cx22702_state* state = fe->demodulator_priv;

	/* set PLL */
	cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) &0xfe);
	if (state->config->pll_set) {
		state->config->pll_set(fe, p);
	} else if (state->config->pll_desc) {
		u8 pllbuf[4];
		struct i2c_msg msg = { .addr = state->config->pll_address,
				       .buf = pllbuf, .len = 4 };
		dvb_pll_configure(state->config->pll_desc, pllbuf,
				  p->frequency,
				  p->u.ofdm.bandwidth);
		i2c_transfer(state->i2c, &msg, 1);
	} else {
		BUG();
	}
	cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) | 1);

	/* set inversion */
	cx22702_set_inversion (state, p->inversion);

	/* set bandwidth */
	switch(p->u.ofdm.bandwidth) {
	case BANDWIDTH_6_MHZ:
		cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xcf) | 0x20 );
		break;
	case BANDWIDTH_7_MHZ:
		cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xcf) | 0x10 );
		break;
	case BANDWIDTH_8_MHZ:
		cx22702_writereg(state, 0x0C, cx22702_readreg(state, 0x0C) &0xcf );
		break;
	default:
		dprintk ("%s: invalid bandwidth\n",__FUNCTION__);
		return -EINVAL;
	}


	p->u.ofdm.code_rate_LP = FEC_AUTO; //temp hack as manual not working

	/* use auto configuration? */
	if((p->u.ofdm.hierarchy_information==HIERARCHY_AUTO) ||
	   (p->u.ofdm.constellation==QAM_AUTO) ||
	   (p->u.ofdm.code_rate_HP==FEC_AUTO) ||
	   (p->u.ofdm.code_rate_LP==FEC_AUTO) ||
	   (p->u.ofdm.guard_interval==GUARD_INTERVAL_AUTO) ||
	   (p->u.ofdm.transmission_mode==TRANSMISSION_MODE_AUTO) ) {

		/* TPS Source - use hardware driven values */
		cx22702_writereg(state, 0x06, 0x10);
		cx22702_writereg(state, 0x07, 0x9);
		cx22702_writereg(state, 0x08, 0xC1);
		cx22702_writereg(state, 0x0B, cx22702_readreg(state, 0x0B) & 0xfc );
		cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xBF) | 0x40 );
		cx22702_writereg(state, 0x00, 0x01); /* Begin aquisition */
		dprintk("%s: Autodetecting\n",__FUNCTION__);
		return 0;
	}

	/* manually programmed values */
	val=0;
	switch(p->u.ofdm.constellation) {
		case   QPSK: val = (val&0xe7); break;
		case QAM_16: val = (val&0xe7)|0x08; break;
		case QAM_64: val = (val&0xe7)|0x10; break;
		default:
			dprintk ("%s: invalid constellation\n",__FUNCTION__);
			return -EINVAL;
	}
	switch(p->u.ofdm.hierarchy_information) {
		case HIERARCHY_NONE: val = (val&0xf8); break;
		case    HIERARCHY_1: val = (val&0xf8)|1; break;
		case    HIERARCHY_2: val = (val&0xf8)|2; break;
		case    HIERARCHY_4: val = (val&0xf8)|3; break;
		default:
			dprintk ("%s: invalid hierarchy\n",__FUNCTION__);
			return -EINVAL;
	}
	cx22702_writereg (state, 0x06, val);

	val=0;
	switch(p->u.ofdm.code_rate_HP) {
		case FEC_NONE:
		case FEC_1_2: val = (val&0xc7); break;
		case FEC_2_3: val = (val&0xc7)|0x08; break;
		case FEC_3_4: val = (val&0xc7)|0x10; break;
		case FEC_5_6: val = (val&0xc7)|0x18; break;
		case FEC_7_8: val = (val&0xc7)|0x20; break;
		default:
			dprintk ("%s: invalid code_rate_HP\n",__FUNCTION__);
			return -EINVAL;
	}
	switch(p->u.ofdm.code_rate_LP) {
		case FEC_NONE:
		case FEC_1_2: val = (val&0xf8); break;
		case FEC_2_3: val = (val&0xf8)|1; break;
		case FEC_3_4: val = (val&0xf8)|2; break;
		case FEC_5_6: val = (val&0xf8)|3; break;
		case FEC_7_8: val = (val&0xf8)|4; break;
		default:
			dprintk ("%s: invalid code_rate_LP\n",__FUNCTION__);
			return -EINVAL;
	}
	cx22702_writereg (state, 0x07, val);

	val=0;
	switch(p->u.ofdm.guard_interval) {
		case GUARD_INTERVAL_1_32: val = (val&0xf3); break;
		case GUARD_INTERVAL_1_16: val = (val&0xf3)|0x04; break;
		case  GUARD_INTERVAL_1_8: val = (val&0xf3)|0x08; break;
		case  GUARD_INTERVAL_1_4: val = (val&0xf3)|0x0c; break;
		default:
			dprintk ("%s: invalid guard_interval\n",__FUNCTION__);
			return -EINVAL;
	}
	switch(p->u.ofdm.transmission_mode) {
		case TRANSMISSION_MODE_2K: val = (val&0xfc); break;
		case TRANSMISSION_MODE_8K: val = (val&0xfc)|1; break;
		default:
			dprintk ("%s: invalid transmission_mode\n",__FUNCTION__);
			return -EINVAL;
	}
	cx22702_writereg(state, 0x08, val);
	cx22702_writereg(state, 0x0B, (cx22702_readreg(state, 0x0B) & 0xfc) | 0x02 );
	cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xBF) | 0x40 );

	/* Begin channel aquisition */
	cx22702_writereg(state, 0x00, 0x01);

	return 0;
}

/* Reset the demod hardware and reset all of the configuration registers
   to a default state. */
static int cx22702_init (struct dvb_frontend* fe)
{
	int i;
	struct cx22702_state* state = fe->demodulator_priv;

	cx22702_writereg (state, 0x00, 0x02);

	msleep(10);

	for (i=0; i<sizeof(init_tab); i+=2)
		cx22702_writereg (state, init_tab[i], init_tab[i+1]);

	cx22702_writereg (state, 0xf8, (state->config->output_mode << 1) & 0x02);

	/* init PLL */
	if (state->config->pll_init) {
		cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) & 0xfe);
		state->config->pll_init(fe);
		cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) | 1);
	}

	return 0;
}

static int cx22702_read_status(struct dvb_frontend* fe, fe_status_t* status)
{
	struct cx22702_state* state = fe->demodulator_priv;
	u8 reg0A;
	u8 reg23;

	*status = 0;

	reg0A = cx22702_readreg (state, 0x0A);
	reg23 = cx22702_readreg (state, 0x23);

	dprintk ("%s: status demod=0x%02x agc=0x%02x\n"
		,__FUNCTION__,reg0A,reg23);

	if(reg0A & 0x10) {
		*status |= FE_HAS_LOCK;
		*status |= FE_HAS_VITERBI;
		*status |= FE_HAS_SYNC;
	}

	if(reg0A & 0x20)
		*status |= FE_HAS_CARRIER;

	if(reg23 < 0xf0)
		*status |= FE_HAS_SIGNAL;

	return 0;
}

static int cx22702_read_ber(struct dvb_frontend* fe, u32* ber)
{
	struct cx22702_state* state = fe->demodulator_priv;

	if(cx22702_readreg (state, 0xE4) & 0x02) {
		/* Realtime statistics */
		*ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 7
			| (cx22702_readreg (state, 0xDF)&0x7F);
	} else {
		/* Averagtine statistics */
		*ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 7
			| cx22702_readreg (state, 0xDF);
	}

	return 0;
}

static int cx22702_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
{
	struct cx22702_state* state = fe->demodulator_priv;

	*signal_strength = cx22702_readreg (state, 0x23);

	return 0;
}

static int cx22702_read_snr(struct dvb_frontend* fe, u16* snr)
{
	struct cx22702_state* state = fe->demodulator_priv;

	u16 rs_ber=0;
	if(cx22702_readreg (state, 0xE4) & 0x02) {
		/* Realtime statistics */
		rs_ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 7
			| (cx22702_readreg (state, 0xDF)& 0x7F);
	} else {
		/* Averagine statistics */
		rs_ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 8
			| cx22702_readreg (state, 0xDF);
	}
	*snr = ~rs_ber;

	return 0;
}

static int cx22702_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
{
	struct cx22702_state* state = fe->demodulator_priv;

	u8 _ucblocks;

	/* RS Uncorrectable Packet Count then reset */
	_ucblocks = cx22702_readreg (state, 0xE3);
	if (state->prevUCBlocks < _ucblocks)
		*ucblocks = (_ucblocks - state->prevUCBlocks);
	else
		*ucblocks = state->prevUCBlocks - _ucblocks;
	state->prevUCBlocks = _ucblocks;

	return 0;
}

static int cx22702_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
{
	struct cx22702_state* state = fe->demodulator_priv;

	u8 reg0C = cx22702_readreg (state, 0x0C);

	p->inversion = reg0C & 0x1 ? INVERSION_ON : INVERSION_OFF;
	return cx22702_get_tps (state, &p->u.ofdm);
}

static int cx22702_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
{
	tune->min_delay_ms = 1000;
	return 0;
}

static void cx22702_release(struct dvb_frontend* fe)
{
	struct cx22702_state* state = fe->demodulator_priv;
	kfree(state);
}

static struct dvb_frontend_ops cx22702_ops;

struct dvb_frontend* cx22702_attach(const struct cx22702_config* config,
				    struct i2c_adapter* i2c)
{
	struct cx22702_state* state = NULL;

	/* allocate memory for the internal state */
	state = kmalloc(sizeof(struct cx22702_state), GFP_KERNEL);
	if (state == NULL)
		goto error;

	/* setup the state */
	state->config = config;
	state->i2c = i2c;
	memcpy(&state->ops, &cx22702_ops, sizeof(struct dvb_frontend_ops));
	state->prevUCBlocks = 0;

	/* check if the demod is there */
	if (cx22702_readreg(state, 0x1f) != 0x3)
		goto error;

	/* create dvb_frontend */
	state->frontend.ops = &state->ops;
	state->frontend.demodulator_priv = state;
	return &state->frontend;

error:
	kfree(state);
	return NULL;
}

static struct dvb_frontend_ops cx22702_ops = {

	.info = {
		.name			= "Conexant CX22702 DVB-T",
		.type			= FE_OFDM,
		.frequency_min		= 177000000,
		.frequency_max		= 858000000,
		.frequency_stepsize	= 166666,
		.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
		FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
		FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
		FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
		FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
	},

	.release = cx22702_release,

	.init = cx22702_init,

	.set_frontend = cx22702_set_tps,
	.get_frontend = cx22702_get_frontend,
	.get_tune_settings = cx22702_get_tune_settings,

	.read_status = cx22702_read_status,
	.read_ber = cx22702_read_ber,
	.read_signal_strength = cx22702_read_signal_strength,
	.read_snr = cx22702_read_snr,
	.read_ucblocks = cx22702_read_ucblocks,
};

module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Enable verbose debug messages");

MODULE_DESCRIPTION("Conexant CX22702 DVB-T Demodulator driver");
MODULE_AUTHOR("Steven Toth");
MODULE_LICENSE("GPL");

EXPORT_SYMBOL(cx22702_attach);
Commit	Line	Data
1da177e4 LT	1	/*
	2	Conexant 22702 DVB OFDM demodulator driver
	3
	4	based on:
9101e622	5	Alps TDMB7 DVB OFDM demodulator driver
1da177e4 LT	6
	7	Copyright (C) 2001-2002 Convergence Integrated Media GmbH
	8	Holger Waechtler <holger@convergence.de>
	9
9b9225f0	10	Copyright (C) 2004 Steven Toth <stoth@hauppauge.com>
1da177e4 LT	11
	12	This program is free software; you can redistribute it and/or modify
	13	it under the terms of the GNU General Public License as published by
	14	the Free Software Foundation; either version 2 of the License, or
	15	(at your option) any later version.
	16
	17	This program is distributed in the hope that it will be useful,
	18	but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	GNU General Public License for more details.
	21
	22	You should have received a copy of the GNU General Public License
	23	along with this program; if not, write to the Free Software
	24	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	25
	26	*/
	27
	28	#include <linux/kernel.h>
	29	#include <linux/init.h>
	30	#include <linux/module.h>
	31	#include <linux/string.h>
	32	#include <linux/slab.h>
	33	#include <linux/delay.h>
	34	#include "dvb_frontend.h"
9990d744	35	#include "dvb-pll.h"
1da177e4 LT	36	#include "cx22702.h"
	37
	38
	39	struct cx22702_state {
	40
	41	struct i2c_adapter* i2c;
	42
	43	struct dvb_frontend_ops ops;
	44
	45	/* configuration settings */
	46	const struct cx22702_config* config;
	47
	48	struct dvb_frontend frontend;
	49
	50	/* previous uncorrected block counter */
	51	u8 prevUCBlocks;
	52	};
	53
	54	static int debug = 0;
	55	#define dprintk if (debug) printk
	56
	57	/* Register values to initialise the demod */
	58	static u8 init_tab [] = {
	59	0x00, 0x00, /* Stop aquisition */
	60	0x0B, 0x06,
	61	0x09, 0x01,
	62	0x0D, 0x41,
	63	0x16, 0x32,
	64	0x20, 0x0A,
	65	0x21, 0x17,
	66	0x24, 0x3e,
	67	0x26, 0xff,
	68	0x27, 0x10,
	69	0x28, 0x00,
	70	0x29, 0x00,
	71	0x2a, 0x10,
	72	0x2b, 0x00,
	73	0x2c, 0x10,
	74	0x2d, 0x00,
	75	0x48, 0xd4,
	76	0x49, 0x56,
	77	0x6b, 0x1e,
	78	0xc8, 0x02,
1da177e4 LT	79	0xf9, 0x00,
	80	0xfa, 0x00,
	81	0xfb, 0x00,
	82	0xfc, 0x00,
	83	0xfd, 0x00,
	84	};
	85
	86	static int cx22702_writereg (struct cx22702_state* state, u8 reg, u8 data)
	87	{
	88	int ret;
	89	u8 buf [] = { reg, data };
	90	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
	91
	92	ret = i2c_transfer(state->i2c, &msg, 1);
	93
	94	if (ret != 1)
	95	printk("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",
	96	__FUNCTION__, reg, data, ret);
	97
	98	return (ret != 1) ? -1 : 0;
	99	}
	100
	101	static u8 cx22702_readreg (struct cx22702_state* state, u8 reg)
	102	{
	103	int ret;
	104	u8 b0 [] = { reg };
	105	u8 b1 [] = { 0 };
	106
	107	struct i2c_msg msg [] = {
	108	{ .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
	109	{ .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
	110
	111	ret = i2c_transfer(state->i2c, msg, 2);
	112
	113	if (ret != 2)
	114	printk("%s: readreg error (ret == %i)\n", __FUNCTION__, ret);
	115
	116	return b1[0];
	117	}
	118
	119	static int cx22702_set_inversion (struct cx22702_state *state, int inversion)
	120	{
	121	u8 val;
	122
	123	switch (inversion) {
	124
	125	case INVERSION_AUTO:
	126	return -EOPNOTSUPP;
	127
	128	case INVERSION_ON:
	129	val = cx22702_readreg (state, 0x0C);
	130	return cx22702_writereg (state, 0x0C, val \| 0x01);
	131
	132	case INVERSION_OFF:
	133	val = cx22702_readreg (state, 0x0C);
	134	return cx22702_writereg (state, 0x0C, val & 0xfe);
	135
	136	default:
	137	return -EINVAL;
	138
	139	}
	140
	141	}
	142
143	/* Retrieve the demod settings */
144	static int cx22702_get_tps (struct cx22702_state state, struct dvb_ofdm_parameters p)
145	{
146	u8 val;
147
148	/* Make sure the TPS regs are valid */
149	if (!(cx22702_readreg(state, 0x0A) & 0x20))
150	return -EAGAIN;
151
152	val = cx22702_readreg (state, 0x01);
153	switch( (val&0x18)>>3) {
154	case 0: p->constellation = QPSK; break;
155	case 1: p->constellation = QAM_16; break;
156	case 2: p->constellation = QAM_64; break;
157	}
158	switch( val&0x07 ) {
159	case 0: p->hierarchy_information = HIERARCHY_NONE; break;
160	case 1: p->hierarchy_information = HIERARCHY_1; break;
161	case 2: p->hierarchy_information = HIERARCHY_2; break;
162	case 3: p->hierarchy_information = HIERARCHY_4; break;
163	}
164
165
166	val = cx22702_readreg (state, 0x02);
167	switch( (val&0x38)>>3 ) {
168	case 0: p->code_rate_HP = FEC_1_2; break;
169	case 1: p->code_rate_HP = FEC_2_3; break;
170	case 2: p->code_rate_HP = FEC_3_4; break;
171	case 3: p->code_rate_HP = FEC_5_6; break;
172	case 4: p->code_rate_HP = FEC_7_8; break;
173	}
174	switch( val&0x07 ) {
175	case 0: p->code_rate_LP = FEC_1_2; break;
176	case 1: p->code_rate_LP = FEC_2_3; break;
177	case 2: p->code_rate_LP = FEC_3_4; break;
178	case 3: p->code_rate_LP = FEC_5_6; break;
179	case 4: p->code_rate_LP = FEC_7_8; break;
180	}
181
182
183	val = cx22702_readreg (state, 0x03);
184	switch( (val&0x0c)>>2 ) {
185	case 0: p->guard_interval = GUARD_INTERVAL_1_32; break;
186	case 1: p->guard_interval = GUARD_INTERVAL_1_16; break;
187	case 2: p->guard_interval = GUARD_INTERVAL_1_8; break;
188	case 3: p->guard_interval = GUARD_INTERVAL_1_4; break;
189	}
190	switch( val&0x03 ) {
191	case 0: p->transmission_mode = TRANSMISSION_MODE_2K; break;
192	case 1: p->transmission_mode = TRANSMISSION_MODE_8K; break;
193	}
194
195	return 0;
196	}
197
198	/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
199	static int cx22702_set_tps (struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
200	{
201	u8 val;
b8742700	202	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	203
1da177e4 LT	204	/* set PLL */
f46dbb05	205	cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) &0xfe);
9990d744 GK	206	if (state->config->pll_set) {
	207	state->config->pll_set(fe, p);
	208	} else if (state->config->pll_desc) {
	209	u8 pllbuf[4];
	210	struct i2c_msg msg = { .addr = state->config->pll_address,
	211	.buf = pllbuf, .len = 4 };
	212	dvb_pll_configure(state->config->pll_desc, pllbuf,
	213	p->frequency,
	214	p->u.ofdm.bandwidth);
	215	i2c_transfer(state->i2c, &msg, 1);
	216	} else {
	217	BUG();
	218	}
f46dbb05	219	cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) \| 1);
1da177e4 LT	220
	221	/* set inversion */
	222	cx22702_set_inversion (state, p->inversion);
	223
	224	/* set bandwidth */
	225	switch(p->u.ofdm.bandwidth) {
	226	case BANDWIDTH_6_MHZ:
	227	cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xcf) \| 0x20 );
	228	break;
	229	case BANDWIDTH_7_MHZ:
	230	cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xcf) \| 0x10 );
	231	break;
	232	case BANDWIDTH_8_MHZ:
	233	cx22702_writereg(state, 0x0C, cx22702_readreg(state, 0x0C) &0xcf );
	234	break;
	235	default:
	236	dprintk ("%s: invalid bandwidth\n",__FUNCTION__);
	237	return -EINVAL;
	238	}
	239
	240
	241	p->u.ofdm.code_rate_LP = FEC_AUTO; //temp hack as manual not working
	242
	243	/* use auto configuration? */
	244	if((p->u.ofdm.hierarchy_information==HIERARCHY_AUTO) \|\|
	245	(p->u.ofdm.constellation==QAM_AUTO) \|\|
	246	(p->u.ofdm.code_rate_HP==FEC_AUTO) \|\|
	247	(p->u.ofdm.code_rate_LP==FEC_AUTO) \|\|
	248	(p->u.ofdm.guard_interval==GUARD_INTERVAL_AUTO) \|\|
	249	(p->u.ofdm.transmission_mode==TRANSMISSION_MODE_AUTO) ) {
	250
	251	/* TPS Source - use hardware driven values */
	252	cx22702_writereg(state, 0x06, 0x10);
	253	cx22702_writereg(state, 0x07, 0x9);
	254	cx22702_writereg(state, 0x08, 0xC1);
	255	cx22702_writereg(state, 0x0B, cx22702_readreg(state, 0x0B) & 0xfc );
	256	cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xBF) \| 0x40 );
	257	cx22702_writereg(state, 0x00, 0x01); /* Begin aquisition */
f46dbb05	258	dprintk("%s: Autodetecting\n",__FUNCTION__);
1da177e4 LT	259	return 0;
	260	}
	261
	262	/* manually programmed values */
	263	val=0;
	264	switch(p->u.ofdm.constellation) {
	265	case QPSK: val = (val&0xe7); break;
	266	case QAM_16: val = (val&0xe7)\|0x08; break;
	267	case QAM_64: val = (val&0xe7)\|0x10; break;
	268	default:
	269	dprintk ("%s: invalid constellation\n",__FUNCTION__);
	270	return -EINVAL;
	271	}
	272	switch(p->u.ofdm.hierarchy_information) {
	273	case HIERARCHY_NONE: val = (val&0xf8); break;
	274	case HIERARCHY_1: val = (val&0xf8)\|1; break;
	275	case HIERARCHY_2: val = (val&0xf8)\|2; break;
	276	case HIERARCHY_4: val = (val&0xf8)\|3; break;
	277	default:
	278	dprintk ("%s: invalid hierarchy\n",__FUNCTION__);
	279	return -EINVAL;
	280	}
	281	cx22702_writereg (state, 0x06, val);
	282
	283	val=0;
	284	switch(p->u.ofdm.code_rate_HP) {
	285	case FEC_NONE:
	286	case FEC_1_2: val = (val&0xc7); break;
	287	case FEC_2_3: val = (val&0xc7)\|0x08; break;
	288	case FEC_3_4: val = (val&0xc7)\|0x10; break;
	289	case FEC_5_6: val = (val&0xc7)\|0x18; break;
	290	case FEC_7_8: val = (val&0xc7)\|0x20; break;
	291	default:
	292	dprintk ("%s: invalid code_rate_HP\n",__FUNCTION__);
	293	return -EINVAL;
	294	}
	295	switch(p->u.ofdm.code_rate_LP) {
	296	case FEC_NONE:
	297	case FEC_1_2: val = (val&0xf8); break;
	298	case FEC_2_3: val = (val&0xf8)\|1; break;
	299	case FEC_3_4: val = (val&0xf8)\|2; break;
	300	case FEC_5_6: val = (val&0xf8)\|3; break;
	301	case FEC_7_8: val = (val&0xf8)\|4; break;
	302	default:
	303	dprintk ("%s: invalid code_rate_LP\n",__FUNCTION__);
	304	return -EINVAL;
	305	}
	306	cx22702_writereg (state, 0x07, val);
	307
	308	val=0;
	309	switch(p->u.ofdm.guard_interval) {
	310	case GUARD_INTERVAL_1_32: val = (val&0xf3); break;
	311	case GUARD_INTERVAL_1_16: val = (val&0xf3)\|0x04; break;
	312	case GUARD_INTERVAL_1_8: val = (val&0xf3)\|0x08; break;
	313	case GUARD_INTERVAL_1_4: val = (val&0xf3)\|0x0c; break;
	314	default:
	315	dprintk ("%s: invalid guard_interval\n",__FUNCTION__);
	316	return -EINVAL;
	317	}
	318	switch(p->u.ofdm.transmission_mode) {
	319	case TRANSMISSION_MODE_2K: val = (val&0xfc); break;
	320	case TRANSMISSION_MODE_8K: val = (val&0xfc)\|1; break;
	321	default:
	322	dprintk ("%s: invalid transmission_mode\n",__FUNCTION__);
323	return -EINVAL;
324	}
325	cx22702_writereg(state, 0x08, val);
326	cx22702_writereg(state, 0x0B, (cx22702_readreg(state, 0x0B) & 0xfc) \| 0x02 );
327	cx22702_writereg(state, 0x0C, (cx22702_readreg(state, 0x0C) & 0xBF) \| 0x40 );
328
329	/* Begin channel aquisition */
330	cx22702_writereg(state, 0x00, 0x01);
331
332	return 0;
333	}
334
335	/* Reset the demod hardware and reset all of the configuration registers
336	to a default state. */
337	static int cx22702_init (struct dvb_frontend* fe)
338	{
339	int i;
b8742700	340	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	341
	342	cx22702_writereg (state, 0x00, 0x02);
	343
	344	msleep(10);
	345
	346	for (i=0; i<sizeof(init_tab); i+=2)
	347	cx22702_writereg (state, init_tab[i], init_tab[i+1]);
	348
f46dbb05	349	cx22702_writereg (state, 0xf8, (state->config->output_mode << 1) & 0x02);
1da177e4 LT	350
	351	/* init PLL */
	352	if (state->config->pll_init) {
f46dbb05	353	cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) & 0xfe);
1da177e4 LT	354	state->config->pll_init(fe);
	355	cx22702_writereg (state, 0x0D, cx22702_readreg(state,0x0D) \| 1);
	356	}
	357
	358	return 0;
	359	}
	360
	361	static int cx22702_read_status(struct dvb_frontend* fe, fe_status_t* status)
	362	{
b8742700	363	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	364	u8 reg0A;
	365	u8 reg23;
	366
	367	*status = 0;
	368
	369	reg0A = cx22702_readreg (state, 0x0A);
	370	reg23 = cx22702_readreg (state, 0x23);
	371
	372	dprintk ("%s: status demod=0x%02x agc=0x%02x\n"
	373	,__FUNCTION__,reg0A,reg23);
	374
	375	if(reg0A & 0x10) {
	376	*status \|= FE_HAS_LOCK;
	377	*status \|= FE_HAS_VITERBI;
	378	*status \|= FE_HAS_SYNC;
	379	}
	380
	381	if(reg0A & 0x20)
	382	*status \|= FE_HAS_CARRIER;
	383
	384	if(reg23 < 0xf0)
	385	*status \|= FE_HAS_SIGNAL;
	386
	387	return 0;
	388	}
	389
	390	static int cx22702_read_ber(struct dvb_frontend* fe, u32* ber)
	391	{
b8742700	392	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	393
	394	if(cx22702_readreg (state, 0xE4) & 0x02) {
	395	/* Realtime statistics */
	396	*ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 7
	397	\| (cx22702_readreg (state, 0xDF)&0x7F);
	398	} else {
	399	/* Averagtine statistics */
	400	*ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 7
	401	\| cx22702_readreg (state, 0xDF);
	402	}
	403
	404	return 0;
	405	}
	406
	407	static int cx22702_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
	408	{
b8742700	409	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	410
	411	*signal_strength = cx22702_readreg (state, 0x23);
	412
	413	return 0;
	414	}
	415
	416	static int cx22702_read_snr(struct dvb_frontend* fe, u16* snr)
	417	{
b8742700	418	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	419
	420	u16 rs_ber=0;
	421	if(cx22702_readreg (state, 0xE4) & 0x02) {
	422	/* Realtime statistics */
	423	rs_ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 7
	424	\| (cx22702_readreg (state, 0xDF)& 0x7F);
	425	} else {
	426	/* Averagine statistics */
	427	rs_ber = (cx22702_readreg (state, 0xDE) & 0x7F) << 8
	428	\| cx22702_readreg (state, 0xDF);
	429	}
	430	*snr = ~rs_ber;
	431
	432	return 0;
	433	}
	434
	435	static int cx22702_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
	436	{
b8742700	437	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	438
	439	u8 _ucblocks;
	440
	441	/* RS Uncorrectable Packet Count then reset */
	442	_ucblocks = cx22702_readreg (state, 0xE3);
f46dbb05 PB	443	if (state->prevUCBlocks < _ucblocks)
	444	*ucblocks = (_ucblocks - state->prevUCBlocks);
	445	else
	446	*ucblocks = state->prevUCBlocks - _ucblocks;
1da177e4 LT	447	state->prevUCBlocks = _ucblocks;
	448
	449	return 0;
	450	}
	451
	452	static int cx22702_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
	453	{
b8742700	454	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	455
	456	u8 reg0C = cx22702_readreg (state, 0x0C);
	457
	458	p->inversion = reg0C & 0x1 ? INVERSION_ON : INVERSION_OFF;
	459	return cx22702_get_tps (state, &p->u.ofdm);
	460	}
	461
f46dbb05 PB	462	static int cx22702_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
	463	{
	464	tune->min_delay_ms = 1000;
	465	return 0;
	466	}
	467
1da177e4 LT	468	static void cx22702_release(struct dvb_frontend* fe)
1da177e4 LT	469	{
b8742700	470	struct cx22702_state* state = fe->demodulator_priv;
1da177e4 LT	471	kfree(state);
	472	}
	473
	474	static struct dvb_frontend_ops cx22702_ops;
	475
	476	struct dvb_frontend* cx22702_attach(const struct cx22702_config* config,
	477	struct i2c_adapter* i2c)
	478	{
	479	struct cx22702_state* state = NULL;
	480
	481	/* allocate memory for the internal state */
b8742700	482	state = kmalloc(sizeof(struct cx22702_state), GFP_KERNEL);
f46dbb05 PB	483	if (state == NULL)
f46dbb05 PB	484	goto error;
1da177e4 LT	485
	486	/* setup the state */
	487	state->config = config;
	488	state->i2c = i2c;
	489	memcpy(&state->ops, &cx22702_ops, sizeof(struct dvb_frontend_ops));
	490	state->prevUCBlocks = 0;
	491
	492	/* check if the demod is there */
f46dbb05 PB	493	if (cx22702_readreg(state, 0x1f) != 0x3)
f46dbb05 PB	494	goto error;
1da177e4 LT	495
	496	/* create dvb_frontend */
	497	state->frontend.ops = &state->ops;
	498	state->frontend.demodulator_priv = state;
	499	return &state->frontend;
	500
	501	error:
	502	kfree(state);
	503	return NULL;
	504	}
	505
	506	static struct dvb_frontend_ops cx22702_ops = {
	507
	508	.info = {
	509	.name = "Conexant CX22702 DVB-T",
	510	.type = FE_OFDM,
	511	.frequency_min = 177000000,
	512	.frequency_max = 858000000,
	513	.frequency_stepsize = 166666,
	514	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \| FE_CAN_FEC_3_4 \|
	515	FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \| FE_CAN_FEC_AUTO \|
	516	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
	517	FE_CAN_HIERARCHY_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
	518	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_RECOVER
	519	},
	520
	521	.release = cx22702_release,
	522
	523	.init = cx22702_init,
	524
	525	.set_frontend = cx22702_set_tps,
	526	.get_frontend = cx22702_get_frontend,
f46dbb05	527	.get_tune_settings = cx22702_get_tune_settings,
1da177e4 LT	528
	529	.read_status = cx22702_read_status,
	530	.read_ber = cx22702_read_ber,
	531	.read_signal_strength = cx22702_read_signal_strength,
	532	.read_snr = cx22702_read_snr,
	533	.read_ucblocks = cx22702_read_ucblocks,
	534	};
	535
	536	module_param(debug, int, 0644);
	537	MODULE_PARM_DESC(debug, "Enable verbose debug messages");
	538
	539	MODULE_DESCRIPTION("Conexant CX22702 DVB-T Demodulator driver");
	540	MODULE_AUTHOR("Steven Toth");
	541	MODULE_LICENSE("GPL");
	542
	543	EXPORT_SYMBOL(cx22702_attach);