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Commit | Line | Data |
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b79cb653 | 1 | /* |
ca06fa79 PB |
2 | * Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver |
3 | * | |
4 | * Copyright (C) 2005 Steven Toth <stoth@hauppauge.com> | |
5 | * | |
6 | * Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> | |
7 | * | |
8 | * Support for CX24123/CX24113-NIM by Patrick Boettcher <pb@linuxtv.org> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
18 | * General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
b79cb653 ST |
24 | |
25 | #include <linux/slab.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
b79cb653 ST |
28 | #include <linux/init.h> |
29 | ||
30 | #include "dvb_frontend.h" | |
31 | #include "cx24123.h" | |
32 | ||
a74b51fc VC |
33 | #define XTAL 10111000 |
34 | ||
70047f9c | 35 | static int force_band; |
b79cb653 | 36 | static int debug; |
ca06fa79 PB |
37 | |
38 | #define info(args...) do { printk(KERN_INFO "CX24123: " args); } while (0) | |
39 | #define err(args...) do { printk(KERN_ERR "CX24123: " args); } while (0) | |
40 | ||
b79cb653 ST |
41 | #define dprintk(args...) \ |
42 | do { \ | |
ca06fa79 PB |
43 | if (debug) { \ |
44 | printk(KERN_DEBUG "CX24123: %s: ", __func__); \ | |
45 | printk(args); \ | |
46 | } \ | |
b79cb653 ST |
47 | } while (0) |
48 | ||
e3b152bc JS |
49 | struct cx24123_state |
50 | { | |
b79cb653 | 51 | struct i2c_adapter* i2c; |
b79cb653 ST |
52 | const struct cx24123_config* config; |
53 | ||
54 | struct dvb_frontend frontend; | |
55 | ||
b79cb653 ST |
56 | /* Some PLL specifics for tuning */ |
57 | u32 VCAarg; | |
58 | u32 VGAarg; | |
59 | u32 bandselectarg; | |
60 | u32 pllarg; | |
a74b51fc | 61 | u32 FILTune; |
b79cb653 | 62 | |
ca06fa79 PB |
63 | struct i2c_adapter tuner_i2c_adapter; |
64 | ||
65 | u8 demod_rev; | |
66 | ||
b79cb653 ST |
67 | /* The Demod/Tuner can't easily provide these, we cache them */ |
68 | u32 currentfreq; | |
69 | u32 currentsymbolrate; | |
70 | }; | |
71 | ||
e3b152bc JS |
72 | /* Various tuner defaults need to be established for a given symbol rate Sps */ |
73 | static struct | |
74 | { | |
75 | u32 symbolrate_low; | |
76 | u32 symbolrate_high; | |
e3b152bc JS |
77 | u32 VCAprogdata; |
78 | u32 VGAprogdata; | |
a74b51fc | 79 | u32 FILTune; |
e3b152bc JS |
80 | } cx24123_AGC_vals[] = |
81 | { | |
82 | { | |
83 | .symbolrate_low = 1000000, | |
84 | .symbolrate_high = 4999999, | |
a74b51fc VC |
85 | /* the specs recommend other values for VGA offsets, |
86 | but tests show they are wrong */ | |
0e4558ab YP |
87 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
88 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, | |
89 | .FILTune = 0x27f /* 0.41 V */ | |
e3b152bc JS |
90 | }, |
91 | { | |
92 | .symbolrate_low = 5000000, | |
93 | .symbolrate_high = 14999999, | |
0e4558ab YP |
94 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
95 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, | |
a74b51fc | 96 | .FILTune = 0x317 /* 0.90 V */ |
e3b152bc JS |
97 | }, |
98 | { | |
99 | .symbolrate_low = 15000000, | |
100 | .symbolrate_high = 45000000, | |
0e4558ab YP |
101 | .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, |
102 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, | |
103 | .FILTune = 0x145 /* 2.70 V */ | |
e3b152bc JS |
104 | }, |
105 | }; | |
106 | ||
107 | /* | |
108 | * Various tuner defaults need to be established for a given frequency kHz. | |
109 | * fixme: The bounds on the bands do not match the doc in real life. | |
110 | * fixme: Some of them have been moved, other might need adjustment. | |
111 | */ | |
112 | static struct | |
113 | { | |
114 | u32 freq_low; | |
115 | u32 freq_high; | |
e3b152bc | 116 | u32 VCOdivider; |
e3b152bc JS |
117 | u32 progdata; |
118 | } cx24123_bandselect_vals[] = | |
119 | { | |
70047f9c | 120 | /* band 1 */ |
e3b152bc JS |
121 | { |
122 | .freq_low = 950000, | |
e3b152bc | 123 | .freq_high = 1074999, |
e3b152bc | 124 | .VCOdivider = 4, |
70047f9c | 125 | .progdata = (0 << 19) | (0 << 9) | 0x40, |
e3b152bc | 126 | }, |
70047f9c YP |
127 | |
128 | /* band 2 */ | |
e3b152bc JS |
129 | { |
130 | .freq_low = 1075000, | |
70047f9c YP |
131 | .freq_high = 1177999, |
132 | .VCOdivider = 4, | |
133 | .progdata = (0 << 19) | (0 << 9) | 0x80, | |
e3b152bc | 134 | }, |
70047f9c YP |
135 | |
136 | /* band 3 */ | |
e3b152bc | 137 | { |
70047f9c YP |
138 | .freq_low = 1178000, |
139 | .freq_high = 1295999, | |
e3b152bc | 140 | .VCOdivider = 2, |
70047f9c | 141 | .progdata = (0 << 19) | (1 << 9) | 0x01, |
e3b152bc | 142 | }, |
70047f9c YP |
143 | |
144 | /* band 4 */ | |
e3b152bc | 145 | { |
70047f9c YP |
146 | .freq_low = 1296000, |
147 | .freq_high = 1431999, | |
e3b152bc | 148 | .VCOdivider = 2, |
70047f9c | 149 | .progdata = (0 << 19) | (1 << 9) | 0x02, |
e3b152bc | 150 | }, |
70047f9c YP |
151 | |
152 | /* band 5 */ | |
e3b152bc | 153 | { |
70047f9c YP |
154 | .freq_low = 1432000, |
155 | .freq_high = 1575999, | |
e3b152bc | 156 | .VCOdivider = 2, |
70047f9c | 157 | .progdata = (0 << 19) | (1 << 9) | 0x04, |
e3b152bc | 158 | }, |
70047f9c YP |
159 | |
160 | /* band 6 */ | |
e3b152bc | 161 | { |
70047f9c | 162 | .freq_low = 1576000, |
e3b152bc | 163 | .freq_high = 1717999, |
e3b152bc | 164 | .VCOdivider = 2, |
70047f9c | 165 | .progdata = (0 << 19) | (1 << 9) | 0x08, |
e3b152bc | 166 | }, |
70047f9c YP |
167 | |
168 | /* band 7 */ | |
e3b152bc JS |
169 | { |
170 | .freq_low = 1718000, | |
171 | .freq_high = 1855999, | |
e3b152bc | 172 | .VCOdivider = 2, |
70047f9c | 173 | .progdata = (0 << 19) | (1 << 9) | 0x10, |
e3b152bc | 174 | }, |
70047f9c YP |
175 | |
176 | /* band 8 */ | |
e3b152bc JS |
177 | { |
178 | .freq_low = 1856000, | |
179 | .freq_high = 2035999, | |
e3b152bc | 180 | .VCOdivider = 2, |
70047f9c | 181 | .progdata = (0 << 19) | (1 << 9) | 0x20, |
e3b152bc | 182 | }, |
70047f9c YP |
183 | |
184 | /* band 9 */ | |
e3b152bc JS |
185 | { |
186 | .freq_low = 2036000, | |
70047f9c | 187 | .freq_high = 2150000, |
e3b152bc | 188 | .VCOdivider = 2, |
70047f9c | 189 | .progdata = (0 << 19) | (1 << 9) | 0x40, |
e3b152bc JS |
190 | }, |
191 | }; | |
192 | ||
b79cb653 ST |
193 | static struct { |
194 | u8 reg; | |
195 | u8 data; | |
196 | } cx24123_regdata[] = | |
197 | { | |
198 | {0x00, 0x03}, /* Reset system */ | |
199 | {0x00, 0x00}, /* Clear reset */ | |
0e4558ab YP |
200 | {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ |
201 | {0x04, 0x10}, /* MPEG */ | |
202 | {0x05, 0x04}, /* MPEG */ | |
203 | {0x06, 0x31}, /* MPEG (default) */ | |
204 | {0x0b, 0x00}, /* Freq search start point (default) */ | |
205 | {0x0c, 0x00}, /* Demodulator sample gain (default) */ | |
d93f8860 | 206 | {0x0d, 0x7f}, /* Force driver to shift until the maximum (+-10 MHz) */ |
0e4558ab YP |
207 | {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ |
208 | {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ | |
209 | {0x10, 0x01}, /* Default search inversion, no repeat (default) */ | |
210 | {0x16, 0x00}, /* Enable reading of frequency */ | |
211 | {0x17, 0x01}, /* Enable EsNO Ready Counter */ | |
212 | {0x1c, 0x80}, /* Enable error counter */ | |
213 | {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ | |
214 | {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ | |
215 | {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ | |
216 | {0x29, 0x00}, /* DiSEqC LNB_DC off */ | |
217 | {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ | |
218 | {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ | |
219 | {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ | |
b79cb653 ST |
220 | {0x2d, 0x00}, |
221 | {0x2e, 0x00}, | |
222 | {0x2f, 0x00}, | |
223 | {0x30, 0x00}, | |
224 | {0x31, 0x00}, | |
0e4558ab YP |
225 | {0x32, 0x8c}, /* DiSEqC Parameters (default) */ |
226 | {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ | |
b79cb653 | 227 | {0x34, 0x00}, |
0e4558ab YP |
228 | {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ |
229 | {0x36, 0x02}, /* DiSEqC Parameters (default) */ | |
230 | {0x37, 0x3a}, /* DiSEqC Parameters (default) */ | |
231 | {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ | |
232 | {0x44, 0x00}, /* Constellation (default) */ | |
233 | {0x45, 0x00}, /* Symbol count (default) */ | |
234 | {0x46, 0x0d}, /* Symbol rate estimator on (default) */ | |
18c053b3 | 235 | {0x56, 0xc1}, /* Error Counter = Viterbi BER */ |
0e4558ab | 236 | {0x57, 0xff}, /* Error Counter Window (default) */ |
d93f8860 | 237 | {0x5c, 0x20}, /* Acquisition AFC Expiration window (default is 0x10) */ |
0e4558ab | 238 | {0x67, 0x83}, /* Non-DCII symbol clock */ |
b79cb653 ST |
239 | }; |
240 | ||
ca06fa79 PB |
241 | static int cx24123_i2c_writereg(struct cx24123_state *state, |
242 | u8 i2c_addr, int reg, int data) | |
b79cb653 ST |
243 | { |
244 | u8 buf[] = { reg, data }; | |
ca06fa79 PB |
245 | struct i2c_msg msg = { |
246 | .addr = i2c_addr, .flags = 0, .buf = buf, .len = 2 | |
247 | }; | |
b79cb653 ST |
248 | int err; |
249 | ||
ca06fa79 | 250 | /* printk(KERN_DEBUG "wr(%02x): %02x %02x\n", i2c_addr, reg, data); */ |
caf970e0 | 251 | |
b79cb653 ST |
252 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
253 | printk("%s: writereg error(err == %i, reg == 0x%02x," | |
ca06fa79 PB |
254 | " data == 0x%02x)\n", __func__, err, reg, data); |
255 | return err; | |
b79cb653 ST |
256 | } |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
ca06fa79 | 261 | static int cx24123_i2c_readreg(struct cx24123_state *state, u8 i2c_addr, u8 reg) |
b79cb653 ST |
262 | { |
263 | int ret; | |
ca06fa79 | 264 | u8 b = 0; |
b79cb653 | 265 | struct i2c_msg msg[] = { |
ca06fa79 PB |
266 | { .addr = i2c_addr, .flags = 0, .buf = ®, .len = 1 }, |
267 | { .addr = i2c_addr, .flags = I2C_M_RD, .buf = &b, .len = 1 } | |
b79cb653 ST |
268 | }; |
269 | ||
270 | ret = i2c_transfer(state->i2c, msg, 2); | |
271 | ||
272 | if (ret != 2) { | |
ca06fa79 | 273 | err("%s: reg=0x%x (error=%d)\n", __func__, reg, ret); |
b79cb653 ST |
274 | return ret; |
275 | } | |
276 | ||
ca06fa79 | 277 | /* printk(KERN_DEBUG "rd(%02x): %02x %02x\n", i2c_addr, reg, b); */ |
caf970e0 | 278 | |
ca06fa79 | 279 | return b; |
b79cb653 ST |
280 | } |
281 | ||
ca06fa79 PB |
282 | #define cx24123_readreg(state, reg) \ |
283 | cx24123_i2c_readreg(state, state->config->demod_address, reg) | |
284 | #define cx24123_writereg(state, reg, val) \ | |
285 | cx24123_i2c_writereg(state, state->config->demod_address, reg, val) | |
286 | ||
b79cb653 ST |
287 | static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion) |
288 | { | |
0e4558ab YP |
289 | u8 nom_reg = cx24123_readreg(state, 0x0e); |
290 | u8 auto_reg = cx24123_readreg(state, 0x10); | |
291 | ||
b79cb653 ST |
292 | switch (inversion) { |
293 | case INVERSION_OFF: | |
ca06fa79 | 294 | dprintk("inversion off\n"); |
0e4558ab YP |
295 | cx24123_writereg(state, 0x0e, nom_reg & ~0x80); |
296 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
297 | break; |
298 | case INVERSION_ON: | |
ca06fa79 | 299 | dprintk("inversion on\n"); |
0e4558ab YP |
300 | cx24123_writereg(state, 0x0e, nom_reg | 0x80); |
301 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
302 | break; |
303 | case INVERSION_AUTO: | |
ca06fa79 | 304 | dprintk("inversion auto\n"); |
0e4558ab | 305 | cx24123_writereg(state, 0x10, auto_reg & ~0x80); |
b79cb653 ST |
306 | break; |
307 | default: | |
308 | return -EINVAL; | |
309 | } | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
314 | static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion) | |
315 | { | |
316 | u8 val; | |
317 | ||
318 | val = cx24123_readreg(state, 0x1b) >> 7; | |
319 | ||
caf970e0 | 320 | if (val == 0) { |
ca06fa79 | 321 | dprintk("read inversion off\n"); |
e3b152bc | 322 | *inversion = INVERSION_OFF; |
caf970e0 | 323 | } else { |
ca06fa79 | 324 | dprintk("read inversion on\n"); |
e3b152bc | 325 | *inversion = INVERSION_ON; |
caf970e0 | 326 | } |
b79cb653 ST |
327 | |
328 | return 0; | |
329 | } | |
330 | ||
331 | static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec) | |
332 | { | |
0e4558ab YP |
333 | u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; |
334 | ||
b79cb653 | 335 | if ( (fec < FEC_NONE) || (fec > FEC_AUTO) ) |
e3b152bc | 336 | fec = FEC_AUTO; |
b79cb653 | 337 | |
d12a9b91 YP |
338 | /* Set the soft decision threshold */ |
339 | if(fec == FEC_1_2) | |
340 | cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) | 0x01); | |
341 | else | |
342 | cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) & ~0x01); | |
343 | ||
b79cb653 | 344 | switch (fec) { |
b79cb653 | 345 | case FEC_1_2: |
ca06fa79 | 346 | dprintk("set FEC to 1/2\n"); |
0e4558ab YP |
347 | cx24123_writereg(state, 0x0e, nom_reg | 0x01); |
348 | cx24123_writereg(state, 0x0f, 0x02); | |
349 | break; | |
b79cb653 | 350 | case FEC_2_3: |
ca06fa79 | 351 | dprintk("set FEC to 2/3\n"); |
0e4558ab YP |
352 | cx24123_writereg(state, 0x0e, nom_reg | 0x02); |
353 | cx24123_writereg(state, 0x0f, 0x04); | |
354 | break; | |
b79cb653 | 355 | case FEC_3_4: |
ca06fa79 | 356 | dprintk("set FEC to 3/4\n"); |
0e4558ab YP |
357 | cx24123_writereg(state, 0x0e, nom_reg | 0x03); |
358 | cx24123_writereg(state, 0x0f, 0x08); | |
359 | break; | |
360 | case FEC_4_5: | |
ca06fa79 | 361 | dprintk("set FEC to 4/5\n"); |
0e4558ab YP |
362 | cx24123_writereg(state, 0x0e, nom_reg | 0x04); |
363 | cx24123_writereg(state, 0x0f, 0x10); | |
364 | break; | |
365 | case FEC_5_6: | |
ca06fa79 | 366 | dprintk("set FEC to 5/6\n"); |
0e4558ab YP |
367 | cx24123_writereg(state, 0x0e, nom_reg | 0x05); |
368 | cx24123_writereg(state, 0x0f, 0x20); | |
369 | break; | |
370 | case FEC_6_7: | |
ca06fa79 | 371 | dprintk("set FEC to 6/7\n"); |
0e4558ab YP |
372 | cx24123_writereg(state, 0x0e, nom_reg | 0x06); |
373 | cx24123_writereg(state, 0x0f, 0x40); | |
374 | break; | |
375 | case FEC_7_8: | |
ca06fa79 | 376 | dprintk("set FEC to 7/8\n"); |
0e4558ab YP |
377 | cx24123_writereg(state, 0x0e, nom_reg | 0x07); |
378 | cx24123_writereg(state, 0x0f, 0x80); | |
379 | break; | |
b79cb653 | 380 | case FEC_AUTO: |
ca06fa79 | 381 | dprintk("set FEC to auto\n"); |
0e4558ab YP |
382 | cx24123_writereg(state, 0x0f, 0xfe); |
383 | break; | |
b79cb653 ST |
384 | default: |
385 | return -EOPNOTSUPP; | |
386 | } | |
0e4558ab YP |
387 | |
388 | return 0; | |
b79cb653 ST |
389 | } |
390 | ||
391 | static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec) | |
392 | { | |
e3b152bc | 393 | int ret; |
b79cb653 | 394 | |
e3b152bc JS |
395 | ret = cx24123_readreg (state, 0x1b); |
396 | if (ret < 0) | |
397 | return ret; | |
a74b51fc VC |
398 | ret = ret & 0x07; |
399 | ||
400 | switch (ret) { | |
b79cb653 | 401 | case 1: |
e3b152bc JS |
402 | *fec = FEC_1_2; |
403 | break; | |
a74b51fc | 404 | case 2: |
e3b152bc JS |
405 | *fec = FEC_2_3; |
406 | break; | |
a74b51fc | 407 | case 3: |
e3b152bc JS |
408 | *fec = FEC_3_4; |
409 | break; | |
a74b51fc | 410 | case 4: |
e3b152bc JS |
411 | *fec = FEC_4_5; |
412 | break; | |
a74b51fc | 413 | case 5: |
e3b152bc JS |
414 | *fec = FEC_5_6; |
415 | break; | |
a74b51fc VC |
416 | case 6: |
417 | *fec = FEC_6_7; | |
418 | break; | |
b79cb653 | 419 | case 7: |
e3b152bc JS |
420 | *fec = FEC_7_8; |
421 | break; | |
b79cb653 | 422 | default: |
0e4558ab YP |
423 | /* this can happen when there's no lock */ |
424 | *fec = FEC_NONE; | |
b79cb653 ST |
425 | } |
426 | ||
e3b152bc | 427 | return 0; |
b79cb653 ST |
428 | } |
429 | ||
0e4558ab YP |
430 | /* Approximation of closest integer of log2(a/b). It actually gives the |
431 | lowest integer i such that 2^i >= round(a/b) */ | |
432 | static u32 cx24123_int_log2(u32 a, u32 b) | |
433 | { | |
434 | u32 exp, nearest = 0; | |
435 | u32 div = a / b; | |
436 | if(a % b >= b / 2) ++div; | |
437 | if(div < (1 << 31)) | |
438 | { | |
439 | for(exp = 1; div > exp; nearest++) | |
440 | exp += exp; | |
441 | } | |
442 | return nearest; | |
443 | } | |
444 | ||
b79cb653 ST |
445 | static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate) |
446 | { | |
0e4558ab | 447 | u32 tmp, sample_rate, ratio, sample_gain; |
a74b51fc VC |
448 | u8 pll_mult; |
449 | ||
450 | /* check if symbol rate is within limits */ | |
dea74869 PB |
451 | if ((srate > state->frontend.ops.info.symbol_rate_max) || |
452 | (srate < state->frontend.ops.info.symbol_rate_min)) | |
a74b51fc VC |
453 | return -EOPNOTSUPP;; |
454 | ||
455 | /* choose the sampling rate high enough for the required operation, | |
456 | while optimizing the power consumed by the demodulator */ | |
457 | if (srate < (XTAL*2)/2) | |
458 | pll_mult = 2; | |
459 | else if (srate < (XTAL*3)/2) | |
460 | pll_mult = 3; | |
461 | else if (srate < (XTAL*4)/2) | |
462 | pll_mult = 4; | |
463 | else if (srate < (XTAL*5)/2) | |
464 | pll_mult = 5; | |
465 | else if (srate < (XTAL*6)/2) | |
466 | pll_mult = 6; | |
467 | else if (srate < (XTAL*7)/2) | |
468 | pll_mult = 7; | |
469 | else if (srate < (XTAL*8)/2) | |
470 | pll_mult = 8; | |
471 | else | |
472 | pll_mult = 9; | |
473 | ||
474 | ||
475 | sample_rate = pll_mult * XTAL; | |
b79cb653 | 476 | |
a74b51fc VC |
477 | /* |
478 | SYSSymbolRate[21:0] = (srate << 23) / sample_rate | |
b79cb653 | 479 | |
a74b51fc VC |
480 | We have to use 32 bit unsigned arithmetic without precision loss. |
481 | The maximum srate is 45000000 or 0x02AEA540. This number has | |
482 | only 6 clear bits on top, hence we can shift it left only 6 bits | |
483 | at a time. Borrowed from cx24110.c | |
484 | */ | |
b79cb653 | 485 | |
a74b51fc VC |
486 | tmp = srate << 6; |
487 | ratio = tmp / sample_rate; | |
488 | ||
489 | tmp = (tmp % sample_rate) << 6; | |
490 | ratio = (ratio << 6) + (tmp / sample_rate); | |
491 | ||
492 | tmp = (tmp % sample_rate) << 6; | |
493 | ratio = (ratio << 6) + (tmp / sample_rate); | |
494 | ||
495 | tmp = (tmp % sample_rate) << 5; | |
496 | ratio = (ratio << 5) + (tmp / sample_rate); | |
497 | ||
498 | ||
499 | cx24123_writereg(state, 0x01, pll_mult * 6); | |
500 | ||
501 | cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f ); | |
502 | cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff ); | |
503 | cx24123_writereg(state, 0x0a, (ratio ) & 0xff ); | |
504 | ||
0e4558ab YP |
505 | /* also set the demodulator sample gain */ |
506 | sample_gain = cx24123_int_log2(sample_rate, srate); | |
507 | tmp = cx24123_readreg(state, 0x0c) & ~0xe0; | |
508 | cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); | |
509 | ||
ca06fa79 PB |
510 | dprintk("srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", |
511 | srate, ratio, sample_rate, sample_gain); | |
b79cb653 ST |
512 | |
513 | return 0; | |
514 | } | |
515 | ||
516 | /* | |
517 | * Based on the required frequency and symbolrate, the tuner AGC has to be configured | |
518 | * and the correct band selected. Calculate those values | |
519 | */ | |
520 | static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
521 | { | |
522 | struct cx24123_state *state = fe->demodulator_priv; | |
e3b152bc JS |
523 | u32 ndiv = 0, adiv = 0, vco_div = 0; |
524 | int i = 0; | |
a74b51fc | 525 | int pump = 2; |
70047f9c | 526 | int band = 0; |
0496daa7 | 527 | int num_bands = ARRAY_SIZE(cx24123_bandselect_vals); |
b79cb653 ST |
528 | |
529 | /* Defaults for low freq, low rate */ | |
530 | state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; | |
531 | state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; | |
532 | state->bandselectarg = cx24123_bandselect_vals[0].progdata; | |
533 | vco_div = cx24123_bandselect_vals[0].VCOdivider; | |
534 | ||
a74b51fc | 535 | /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */ |
0496daa7 | 536 | for (i = 0; i < ARRAY_SIZE(cx24123_AGC_vals); i++) |
b79cb653 ST |
537 | { |
538 | if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) && | |
a74b51fc | 539 | (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) { |
b79cb653 ST |
540 | state->VCAarg = cx24123_AGC_vals[i].VCAprogdata; |
541 | state->VGAarg = cx24123_AGC_vals[i].VGAprogdata; | |
a74b51fc | 542 | state->FILTune = cx24123_AGC_vals[i].FILTune; |
b79cb653 ST |
543 | } |
544 | } | |
545 | ||
70047f9c YP |
546 | /* determine the band to use */ |
547 | if(force_band < 1 || force_band > num_bands) | |
b79cb653 | 548 | { |
70047f9c YP |
549 | for (i = 0; i < num_bands; i++) |
550 | { | |
551 | if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) && | |
552 | (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) | |
553 | band = i; | |
b79cb653 ST |
554 | } |
555 | } | |
70047f9c YP |
556 | else |
557 | band = force_band - 1; | |
558 | ||
559 | state->bandselectarg = cx24123_bandselect_vals[band].progdata; | |
560 | vco_div = cx24123_bandselect_vals[band].VCOdivider; | |
561 | ||
562 | /* determine the charge pump current */ | |
563 | if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 ) | |
564 | pump = 0x01; | |
565 | else | |
566 | pump = 0x02; | |
b79cb653 ST |
567 | |
568 | /* Determine the N/A dividers for the requested lband freq (in kHz). */ | |
a74b51fc VC |
569 | /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */ |
570 | ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff; | |
571 | adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f; | |
b79cb653 | 572 | |
9b5a4a67 ST |
573 | if (adiv == 0 && ndiv > 0) |
574 | ndiv--; | |
b79cb653 | 575 | |
a74b51fc VC |
576 | /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */ |
577 | state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv; | |
b79cb653 ST |
578 | |
579 | return 0; | |
580 | } | |
581 | ||
582 | /* | |
583 | * Tuner data is 21 bits long, must be left-aligned in data. | |
584 | * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip. | |
585 | */ | |
586 | static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data) | |
587 | { | |
588 | struct cx24123_state *state = fe->demodulator_priv; | |
0144f314 | 589 | unsigned long timeout; |
b79cb653 | 590 | |
ca06fa79 | 591 | dprintk("pll writereg called, data=0x%08x\n", data); |
caf970e0 | 592 | |
b79cb653 ST |
593 | /* align the 21 bytes into to bit23 boundary */ |
594 | data = data << 3; | |
595 | ||
596 | /* Reset the demod pll word length to 0x15 bits */ | |
597 | cx24123_writereg(state, 0x21, 0x15); | |
598 | ||
b79cb653 | 599 | /* write the msb 8 bits, wait for the send to be completed */ |
0144f314 | 600 | timeout = jiffies + msecs_to_jiffies(40); |
e3b152bc | 601 | cx24123_writereg(state, 0x22, (data >> 16) & 0xff); |
0144f314 ST |
602 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
603 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
604 | err("%s: demodulator is not responding, "\ |
605 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
606 | return -EREMOTEIO; |
607 | } | |
0144f314 | 608 | msleep(10); |
b79cb653 ST |
609 | } |
610 | ||
b79cb653 | 611 | /* send another 8 bytes, wait for the send to be completed */ |
0144f314 | 612 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 613 | cx24123_writereg(state, 0x22, (data>>8) & 0xff ); |
0144f314 ST |
614 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
615 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
616 | err("%s: demodulator is not responding, "\ |
617 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
618 | return -EREMOTEIO; |
619 | } | |
0144f314 | 620 | msleep(10); |
b79cb653 ST |
621 | } |
622 | ||
b79cb653 | 623 | /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */ |
0144f314 | 624 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 625 | cx24123_writereg(state, 0x22, (data) & 0xff ); |
0144f314 ST |
626 | while ((cx24123_readreg(state, 0x20) & 0x80)) { |
627 | if (time_after(jiffies, timeout)) { | |
ca06fa79 PB |
628 | err("%s: demodulator is not responding," \ |
629 | "possibly hung, aborting.\n", __func__); | |
b79cb653 ST |
630 | return -EREMOTEIO; |
631 | } | |
0144f314 | 632 | msleep(10); |
b79cb653 ST |
633 | } |
634 | ||
635 | /* Trigger the demod to configure the tuner */ | |
636 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); | |
637 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); | |
638 | ||
639 | return 0; | |
640 | } | |
641 | ||
642 | static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
643 | { | |
644 | struct cx24123_state *state = fe->demodulator_priv; | |
a74b51fc VC |
645 | u8 val; |
646 | ||
647 | dprintk("frequency=%i\n", p->frequency); | |
b79cb653 | 648 | |
e3b152bc | 649 | if (cx24123_pll_calculate(fe, p) != 0) { |
ca06fa79 | 650 | err("%s: cx24123_pll_calcutate failed\n", __func__); |
b79cb653 ST |
651 | return -EINVAL; |
652 | } | |
653 | ||
654 | /* Write the new VCO/VGA */ | |
655 | cx24123_pll_writereg(fe, p, state->VCAarg); | |
656 | cx24123_pll_writereg(fe, p, state->VGAarg); | |
657 | ||
658 | /* Write the new bandselect and pll args */ | |
659 | cx24123_pll_writereg(fe, p, state->bandselectarg); | |
660 | cx24123_pll_writereg(fe, p, state->pllarg); | |
661 | ||
a74b51fc VC |
662 | /* set the FILTUNE voltage */ |
663 | val = cx24123_readreg(state, 0x28) & ~0x3; | |
664 | cx24123_writereg(state, 0x27, state->FILTune >> 2); | |
665 | cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); | |
666 | ||
ca06fa79 PB |
667 | dprintk("pll tune VCA=%d, band=%d, pll=%d\n", state->VCAarg, |
668 | state->bandselectarg, state->pllarg); | |
caf970e0 | 669 | |
b79cb653 ST |
670 | return 0; |
671 | } | |
672 | ||
ca06fa79 PB |
673 | |
674 | /* | |
675 | * 0x23: | |
676 | * [7:7] = BTI enabled | |
677 | * [6:6] = I2C repeater enabled | |
678 | * [5:5] = I2C repeater start | |
679 | * [0:0] = BTI start | |
680 | */ | |
681 | ||
682 | /* mode == 1 -> i2c-repeater, 0 -> bti */ | |
683 | static int cx24123_repeater_mode(struct cx24123_state *state, u8 mode, u8 start) | |
684 | { | |
685 | u8 r = cx24123_readreg(state, 0x23) & 0x1e; | |
686 | if (mode) | |
687 | r |= (1 << 6) | (start << 5); | |
688 | else | |
689 | r |= (1 << 7) | (start); | |
690 | return cx24123_writereg(state, 0x23, r); | |
691 | } | |
692 | ||
b79cb653 ST |
693 | static int cx24123_initfe(struct dvb_frontend* fe) |
694 | { | |
695 | struct cx24123_state *state = fe->demodulator_priv; | |
696 | int i; | |
697 | ||
ca06fa79 | 698 | dprintk("init frontend\n"); |
caf970e0 | 699 | |
b79cb653 | 700 | /* Configure the demod to a good set of defaults */ |
0496daa7 | 701 | for (i = 0; i < ARRAY_SIZE(cx24123_regdata); i++) |
b79cb653 ST |
702 | cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data); |
703 | ||
ef76856d YP |
704 | /* Set the LNB polarity */ |
705 | if(state->config->lnb_polarity) | |
706 | cx24123_writereg(state, 0x32, cx24123_readreg(state, 0x32) | 0x02); | |
707 | ||
ca06fa79 PB |
708 | if (state->config->dont_use_pll) |
709 | cx24123_repeater_mode(state, 1, 0); | |
710 | ||
b79cb653 ST |
711 | return 0; |
712 | } | |
713 | ||
714 | static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage) | |
715 | { | |
716 | struct cx24123_state *state = fe->demodulator_priv; | |
717 | u8 val; | |
718 | ||
cd20ca9f | 719 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 720 | |
cd20ca9f AQ |
721 | switch (voltage) { |
722 | case SEC_VOLTAGE_13: | |
ca06fa79 | 723 | dprintk("setting voltage 13V\n"); |
ccd214b2 | 724 | return cx24123_writereg(state, 0x29, val & 0x7f); |
cd20ca9f | 725 | case SEC_VOLTAGE_18: |
ca06fa79 | 726 | dprintk("setting voltage 18V\n"); |
ccd214b2 | 727 | return cx24123_writereg(state, 0x29, val | 0x80); |
ef76856d YP |
728 | case SEC_VOLTAGE_OFF: |
729 | /* already handled in cx88-dvb */ | |
730 | return 0; | |
cd20ca9f AQ |
731 | default: |
732 | return -EINVAL; | |
733 | }; | |
1c956a3a VC |
734 | |
735 | return 0; | |
b79cb653 ST |
736 | } |
737 | ||
dce1dfc2 YP |
738 | /* wait for diseqc queue to become ready (or timeout) */ |
739 | static void cx24123_wait_for_diseqc(struct cx24123_state *state) | |
740 | { | |
741 | unsigned long timeout = jiffies + msecs_to_jiffies(200); | |
742 | while (!(cx24123_readreg(state, 0x29) & 0x40)) { | |
743 | if(time_after(jiffies, timeout)) { | |
ca06fa79 PB |
744 | err("%s: diseqc queue not ready, " \ |
745 | "command may be lost.\n", __func__); | |
dce1dfc2 YP |
746 | break; |
747 | } | |
748 | msleep(10); | |
749 | } | |
750 | } | |
751 | ||
a74b51fc | 752 | static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd) |
b79cb653 | 753 | { |
a74b51fc | 754 | struct cx24123_state *state = fe->demodulator_priv; |
cd20ca9f | 755 | int i, val, tone; |
a74b51fc | 756 | |
ca06fa79 | 757 | dprintk("\n"); |
b79cb653 | 758 | |
cd20ca9f AQ |
759 | /* stop continuous tone if enabled */ |
760 | tone = cx24123_readreg(state, 0x29); | |
761 | if (tone & 0x10) | |
762 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 763 | |
dce1dfc2 YP |
764 | /* wait for diseqc queue ready */ |
765 | cx24123_wait_for_diseqc(state); | |
766 | ||
a74b51fc | 767 | /* select tone mode */ |
cd20ca9f | 768 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc VC |
769 | |
770 | for (i = 0; i < cmd->msg_len; i++) | |
771 | cx24123_writereg(state, 0x2C + i, cmd->msg[i]); | |
772 | ||
773 | val = cx24123_readreg(state, 0x29); | |
774 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); | |
775 | ||
dce1dfc2 YP |
776 | /* wait for diseqc message to finish sending */ |
777 | cx24123_wait_for_diseqc(state); | |
a74b51fc | 778 | |
cd20ca9f AQ |
779 | /* restart continuous tone if enabled */ |
780 | if (tone & 0x10) { | |
781 | cx24123_writereg(state, 0x29, tone & ~0x40); | |
782 | } | |
783 | ||
a74b51fc VC |
784 | return 0; |
785 | } | |
786 | ||
787 | static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) | |
788 | { | |
789 | struct cx24123_state *state = fe->demodulator_priv; | |
cd20ca9f | 790 | int val, tone; |
a74b51fc | 791 | |
ca06fa79 | 792 | dprintk("\n"); |
a74b51fc | 793 | |
cd20ca9f AQ |
794 | /* stop continuous tone if enabled */ |
795 | tone = cx24123_readreg(state, 0x29); | |
796 | if (tone & 0x10) | |
797 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 798 | |
cd20ca9f | 799 | /* wait for diseqc queue ready */ |
dce1dfc2 YP |
800 | cx24123_wait_for_diseqc(state); |
801 | ||
a74b51fc | 802 | /* select tone mode */ |
cd20ca9f AQ |
803 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); |
804 | msleep(30); | |
a74b51fc | 805 | val = cx24123_readreg(state, 0x29); |
a74b51fc VC |
806 | if (burst == SEC_MINI_A) |
807 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); | |
808 | else if (burst == SEC_MINI_B) | |
809 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); | |
810 | else | |
811 | return -EINVAL; | |
812 | ||
dce1dfc2 | 813 | cx24123_wait_for_diseqc(state); |
cd20ca9f | 814 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc | 815 | |
cd20ca9f AQ |
816 | /* restart continuous tone if enabled */ |
817 | if (tone & 0x10) { | |
818 | cx24123_writereg(state, 0x29, tone & ~0x40); | |
819 | } | |
a74b51fc | 820 | return 0; |
b79cb653 ST |
821 | } |
822 | ||
823 | static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status) | |
824 | { | |
825 | struct cx24123_state *state = fe->demodulator_priv; | |
b79cb653 | 826 | int sync = cx24123_readreg(state, 0x14); |
b79cb653 ST |
827 | |
828 | *status = 0; | |
ca06fa79 PB |
829 | if (state->config->dont_use_pll) { |
830 | u32 tun_status = 0; | |
831 | if (fe->ops.tuner_ops.get_status) | |
832 | fe->ops.tuner_ops.get_status(fe, &tun_status); | |
833 | if (tun_status & TUNER_STATUS_LOCKED) | |
834 | *status |= FE_HAS_SIGNAL; | |
835 | } else { | |
836 | int lock = cx24123_readreg(state, 0x20); | |
837 | if (lock & 0x01) | |
838 | *status |= FE_HAS_SIGNAL; | |
839 | } | |
840 | ||
a74b51fc | 841 | if (sync & 0x02) |
d93f8860 | 842 | *status |= FE_HAS_CARRIER; /* Phase locked */ |
b79cb653 ST |
843 | if (sync & 0x04) |
844 | *status |= FE_HAS_VITERBI; | |
d93f8860 MCC |
845 | |
846 | /* Reed-Solomon Status */ | |
b79cb653 | 847 | if (sync & 0x08) |
a74b51fc | 848 | *status |= FE_HAS_SYNC; |
b79cb653 | 849 | if (sync & 0x80) |
d93f8860 | 850 | *status |= FE_HAS_LOCK; /*Full Sync */ |
b79cb653 ST |
851 | |
852 | return 0; | |
853 | } | |
854 | ||
855 | /* | |
856 | * Configured to return the measurement of errors in blocks, because no UCBLOCKS value | |
857 | * is available, so this value doubles up to satisfy both measurements | |
858 | */ | |
ca06fa79 | 859 | static int cx24123_read_ber(struct dvb_frontend *fe, u32 *ber) |
b79cb653 ST |
860 | { |
861 | struct cx24123_state *state = fe->demodulator_priv; | |
862 | ||
18c053b3 YP |
863 | /* The true bit error rate is this value divided by |
864 | the window size (set as 256 * 255) */ | |
865 | *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | | |
b79cb653 | 866 | (cx24123_readreg(state, 0x1d) << 8 | |
18c053b3 | 867 | cx24123_readreg(state, 0x1e)); |
caf970e0 | 868 | |
ca06fa79 | 869 | dprintk("BER = %d\n", *ber); |
b79cb653 ST |
870 | |
871 | return 0; | |
872 | } | |
873 | ||
ca06fa79 PB |
874 | static int cx24123_read_signal_strength(struct dvb_frontend *fe, |
875 | u16 *signal_strength) | |
b79cb653 ST |
876 | { |
877 | struct cx24123_state *state = fe->demodulator_priv; | |
d93f8860 | 878 | |
b79cb653 ST |
879 | *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */ |
880 | ||
ca06fa79 | 881 | dprintk("Signal strength = %d\n", *signal_strength); |
caf970e0 | 882 | |
b79cb653 ST |
883 | return 0; |
884 | } | |
885 | ||
ca06fa79 | 886 | static int cx24123_read_snr(struct dvb_frontend *fe, u16 *snr) |
b79cb653 ST |
887 | { |
888 | struct cx24123_state *state = fe->demodulator_priv; | |
b79cb653 | 889 | |
18c053b3 YP |
890 | /* Inverted raw Es/N0 count, totally bogus but better than the |
891 | BER threshold. */ | |
892 | *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | | |
893 | (u16)cx24123_readreg(state, 0x19)); | |
caf970e0 | 894 | |
ca06fa79 | 895 | dprintk("read S/N index = %d\n", *snr); |
caf970e0 | 896 | |
b79cb653 ST |
897 | return 0; |
898 | } | |
899 | ||
ca06fa79 PB |
900 | static int cx24123_set_frontend(struct dvb_frontend *fe, |
901 | struct dvb_frontend_parameters *p) | |
b79cb653 ST |
902 | { |
903 | struct cx24123_state *state = fe->demodulator_priv; | |
904 | ||
ca06fa79 | 905 | dprintk("\n"); |
caf970e0 | 906 | |
b79cb653 ST |
907 | if (state->config->set_ts_params) |
908 | state->config->set_ts_params(fe, 0); | |
909 | ||
910 | state->currentfreq=p->frequency; | |
e3b152bc | 911 | state->currentsymbolrate = p->u.qpsk.symbol_rate; |
b79cb653 ST |
912 | |
913 | cx24123_set_inversion(state, p->inversion); | |
914 | cx24123_set_fec(state, p->u.qpsk.fec_inner); | |
915 | cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate); | |
ca06fa79 PB |
916 | |
917 | if (!state->config->dont_use_pll) | |
918 | cx24123_pll_tune(fe, p); | |
919 | else if (fe->ops.tuner_ops.set_params) | |
920 | fe->ops.tuner_ops.set_params(fe, p); | |
921 | else | |
922 | err("it seems I don't have a tuner..."); | |
b79cb653 ST |
923 | |
924 | /* Enable automatic aquisition and reset cycle */ | |
e3b152bc | 925 | cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); |
b79cb653 ST |
926 | cx24123_writereg(state, 0x00, 0x10); |
927 | cx24123_writereg(state, 0x00, 0); | |
928 | ||
ca06fa79 PB |
929 | if (state->config->agc_callback) |
930 | state->config->agc_callback(fe); | |
931 | ||
b79cb653 ST |
932 | return 0; |
933 | } | |
934 | ||
935 | static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
936 | { | |
937 | struct cx24123_state *state = fe->demodulator_priv; | |
938 | ||
ca06fa79 | 939 | dprintk("\n"); |
caf970e0 | 940 | |
b79cb653 | 941 | if (cx24123_get_inversion(state, &p->inversion) != 0) { |
ca06fa79 | 942 | err("%s: Failed to get inversion status\n", __func__); |
b79cb653 ST |
943 | return -EREMOTEIO; |
944 | } | |
945 | if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) { | |
ca06fa79 | 946 | err("%s: Failed to get fec status\n", __func__); |
b79cb653 ST |
947 | return -EREMOTEIO; |
948 | } | |
949 | p->frequency = state->currentfreq; | |
950 | p->u.qpsk.symbol_rate = state->currentsymbolrate; | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) | |
956 | { | |
957 | struct cx24123_state *state = fe->demodulator_priv; | |
958 | u8 val; | |
959 | ||
cd20ca9f AQ |
960 | /* wait for diseqc queue ready */ |
961 | cx24123_wait_for_diseqc(state); | |
1c956a3a | 962 | |
cd20ca9f | 963 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 964 | |
cd20ca9f AQ |
965 | switch (tone) { |
966 | case SEC_TONE_ON: | |
ca06fa79 | 967 | dprintk("setting tone on\n"); |
cd20ca9f AQ |
968 | return cx24123_writereg(state, 0x29, val | 0x10); |
969 | case SEC_TONE_OFF: | |
ca06fa79 | 970 | dprintk("setting tone off\n"); |
cd20ca9f AQ |
971 | return cx24123_writereg(state, 0x29, val & 0xef); |
972 | default: | |
ca06fa79 | 973 | err("CASE reached default with tone=%d\n", tone); |
cd20ca9f | 974 | return -EINVAL; |
b79cb653 | 975 | } |
1c956a3a VC |
976 | |
977 | return 0; | |
b79cb653 ST |
978 | } |
979 | ||
174ff219 YP |
980 | static int cx24123_tune(struct dvb_frontend* fe, |
981 | struct dvb_frontend_parameters* params, | |
982 | unsigned int mode_flags, | |
3ea96615 | 983 | unsigned int *delay, |
174ff219 YP |
984 | fe_status_t *status) |
985 | { | |
986 | int retval = 0; | |
987 | ||
988 | if (params != NULL) | |
989 | retval = cx24123_set_frontend(fe, params); | |
990 | ||
991 | if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) | |
992 | cx24123_read_status(fe, status); | |
993 | *delay = HZ/10; | |
994 | ||
995 | return retval; | |
996 | } | |
997 | ||
998 | static int cx24123_get_algo(struct dvb_frontend *fe) | |
999 | { | |
1000 | return 1; //FE_ALGO_HW | |
1001 | } | |
1002 | ||
b79cb653 ST |
1003 | static void cx24123_release(struct dvb_frontend* fe) |
1004 | { | |
1005 | struct cx24123_state* state = fe->demodulator_priv; | |
ca06fa79 PB |
1006 | dprintk("\n"); |
1007 | i2c_del_adapter(&state->tuner_i2c_adapter); | |
b79cb653 ST |
1008 | kfree(state); |
1009 | } | |
1010 | ||
ca06fa79 PB |
1011 | static int cx24123_tuner_i2c_tuner_xfer(struct i2c_adapter *i2c_adap, |
1012 | struct i2c_msg msg[], int num) | |
1013 | { | |
1014 | struct cx24123_state *state = i2c_get_adapdata(i2c_adap); | |
1015 | /* this repeater closes after the first stop */ | |
1016 | cx24123_repeater_mode(state, 1, 1); | |
1017 | return i2c_transfer(state->i2c, msg, num); | |
1018 | } | |
1019 | ||
1020 | static u32 cx24123_tuner_i2c_func(struct i2c_adapter *adapter) | |
1021 | { | |
1022 | return I2C_FUNC_I2C; | |
1023 | } | |
1024 | ||
1025 | static struct i2c_algorithm cx24123_tuner_i2c_algo = { | |
1026 | .master_xfer = cx24123_tuner_i2c_tuner_xfer, | |
1027 | .functionality = cx24123_tuner_i2c_func, | |
1028 | }; | |
1029 | ||
1030 | struct i2c_adapter * | |
1031 | cx24123_get_tuner_i2c_adapter(struct dvb_frontend *fe) | |
1032 | { | |
1033 | struct cx24123_state *state = fe->demodulator_priv; | |
1034 | return &state->tuner_i2c_adapter; | |
1035 | } | |
1036 | EXPORT_SYMBOL(cx24123_get_tuner_i2c_adapter); | |
1037 | ||
b79cb653 ST |
1038 | static struct dvb_frontend_ops cx24123_ops; |
1039 | ||
e3b152bc JS |
1040 | struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, |
1041 | struct i2c_adapter* i2c) | |
b79cb653 | 1042 | { |
ca06fa79 PB |
1043 | struct cx24123_state *state = |
1044 | kzalloc(sizeof(struct cx24123_state), GFP_KERNEL); | |
b79cb653 | 1045 | |
ca06fa79 | 1046 | dprintk("\n"); |
b79cb653 | 1047 | /* allocate memory for the internal state */ |
b79cb653 | 1048 | if (state == NULL) { |
ca06fa79 | 1049 | err("Unable to kmalloc\n"); |
b79cb653 ST |
1050 | goto error; |
1051 | } | |
1052 | ||
1053 | /* setup the state */ | |
1054 | state->config = config; | |
1055 | state->i2c = i2c; | |
b79cb653 ST |
1056 | |
1057 | /* check if the demod is there */ | |
ca06fa79 PB |
1058 | state->demod_rev = cx24123_readreg(state, 0x00); |
1059 | switch (state->demod_rev) { | |
1060 | case 0xe1: info("detected CX24123C\n"); break; | |
1061 | case 0xd1: info("detected CX24123\n"); break; | |
1062 | default: | |
1063 | err("wrong demod revision: %x\n", state->demod_rev); | |
b79cb653 ST |
1064 | goto error; |
1065 | } | |
1066 | ||
1067 | /* create dvb_frontend */ | |
dea74869 | 1068 | memcpy(&state->frontend.ops, &cx24123_ops, sizeof(struct dvb_frontend_ops)); |
b79cb653 | 1069 | state->frontend.demodulator_priv = state; |
ca06fa79 PB |
1070 | |
1071 | /* create tuner i2c adapter */ | |
1072 | if (config->dont_use_pll) | |
1073 | cx24123_repeater_mode(state, 1, 0); | |
1074 | ||
1075 | strncpy(state->tuner_i2c_adapter.name, | |
1076 | "CX24123 tuner I2C bus", I2C_NAME_SIZE); | |
1077 | state->tuner_i2c_adapter.class = I2C_CLASS_TV_DIGITAL, | |
1078 | state->tuner_i2c_adapter.algo = &cx24123_tuner_i2c_algo; | |
1079 | state->tuner_i2c_adapter.algo_data = NULL; | |
1080 | i2c_set_adapdata(&state->tuner_i2c_adapter, state); | |
1081 | if (i2c_add_adapter(&state->tuner_i2c_adapter) < 0) { | |
1082 | err("tuner i2c bus could not be initialized\n"); | |
1083 | goto error; | |
1084 | } | |
1085 | ||
b79cb653 ST |
1086 | return &state->frontend; |
1087 | ||
1088 | error: | |
1089 | kfree(state); | |
1090 | ||
1091 | return NULL; | |
1092 | } | |
1093 | ||
1094 | static struct dvb_frontend_ops cx24123_ops = { | |
1095 | ||
1096 | .info = { | |
1097 | .name = "Conexant CX24123/CX24109", | |
1098 | .type = FE_QPSK, | |
1099 | .frequency_min = 950000, | |
1100 | .frequency_max = 2150000, | |
1101 | .frequency_stepsize = 1011, /* kHz for QPSK frontends */ | |
0e4558ab | 1102 | .frequency_tolerance = 5000, |
b79cb653 ST |
1103 | .symbol_rate_min = 1000000, |
1104 | .symbol_rate_max = 45000000, | |
1105 | .caps = FE_CAN_INVERSION_AUTO | | |
1106 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
0e4558ab YP |
1107 | FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | |
1108 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
b79cb653 ST |
1109 | FE_CAN_QPSK | FE_CAN_RECOVER |
1110 | }, | |
1111 | ||
1112 | .release = cx24123_release, | |
1113 | ||
1114 | .init = cx24123_initfe, | |
1115 | .set_frontend = cx24123_set_frontend, | |
1116 | .get_frontend = cx24123_get_frontend, | |
1117 | .read_status = cx24123_read_status, | |
1118 | .read_ber = cx24123_read_ber, | |
1119 | .read_signal_strength = cx24123_read_signal_strength, | |
1120 | .read_snr = cx24123_read_snr, | |
b79cb653 | 1121 | .diseqc_send_master_cmd = cx24123_send_diseqc_msg, |
a74b51fc | 1122 | .diseqc_send_burst = cx24123_diseqc_send_burst, |
b79cb653 ST |
1123 | .set_tone = cx24123_set_tone, |
1124 | .set_voltage = cx24123_set_voltage, | |
174ff219 YP |
1125 | .tune = cx24123_tune, |
1126 | .get_frontend_algo = cx24123_get_algo, | |
b79cb653 ST |
1127 | }; |
1128 | ||
1129 | module_param(debug, int, 0644); | |
caf970e0 | 1130 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); |
b79cb653 | 1131 | |
70047f9c YP |
1132 | module_param(force_band, int, 0644); |
1133 | MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off)."); | |
1134 | ||
ca06fa79 PB |
1135 | MODULE_DESCRIPTION("DVB Frontend module for Conexant " \ |
1136 | "CX24123/CX24109/CX24113 hardware"); | |
b79cb653 ST |
1137 | MODULE_AUTHOR("Steven Toth"); |
1138 | MODULE_LICENSE("GPL"); | |
1139 | ||
1140 | EXPORT_SYMBOL(cx24123_attach); |