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Commit | Line | Data |
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b79cb653 ST |
1 | /* |
2 | Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver | |
3 | ||
4 | Copyright (C) 2005 Steven Toth <stoth@hauppauge.com> | |
5 | ||
1c956a3a VC |
6 | Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> |
7 | ||
b79cb653 ST |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/slab.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/init.h> | |
28 | ||
29 | #include "dvb_frontend.h" | |
30 | #include "cx24123.h" | |
31 | ||
a74b51fc VC |
32 | #define XTAL 10111000 |
33 | ||
70047f9c | 34 | static int force_band; |
b79cb653 ST |
35 | static int debug; |
36 | #define dprintk(args...) \ | |
37 | do { \ | |
38 | if (debug) printk (KERN_DEBUG "cx24123: " args); \ | |
39 | } while (0) | |
40 | ||
e3b152bc JS |
41 | struct cx24123_state |
42 | { | |
b79cb653 | 43 | struct i2c_adapter* i2c; |
b79cb653 ST |
44 | const struct cx24123_config* config; |
45 | ||
46 | struct dvb_frontend frontend; | |
47 | ||
b79cb653 ST |
48 | /* Some PLL specifics for tuning */ |
49 | u32 VCAarg; | |
50 | u32 VGAarg; | |
51 | u32 bandselectarg; | |
52 | u32 pllarg; | |
a74b51fc | 53 | u32 FILTune; |
b79cb653 ST |
54 | |
55 | /* The Demod/Tuner can't easily provide these, we cache them */ | |
56 | u32 currentfreq; | |
57 | u32 currentsymbolrate; | |
58 | }; | |
59 | ||
e3b152bc JS |
60 | /* Various tuner defaults need to be established for a given symbol rate Sps */ |
61 | static struct | |
62 | { | |
63 | u32 symbolrate_low; | |
64 | u32 symbolrate_high; | |
e3b152bc JS |
65 | u32 VCAprogdata; |
66 | u32 VGAprogdata; | |
a74b51fc | 67 | u32 FILTune; |
e3b152bc JS |
68 | } cx24123_AGC_vals[] = |
69 | { | |
70 | { | |
71 | .symbolrate_low = 1000000, | |
72 | .symbolrate_high = 4999999, | |
a74b51fc VC |
73 | /* the specs recommend other values for VGA offsets, |
74 | but tests show they are wrong */ | |
0e4558ab YP |
75 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
76 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, | |
77 | .FILTune = 0x27f /* 0.41 V */ | |
e3b152bc JS |
78 | }, |
79 | { | |
80 | .symbolrate_low = 5000000, | |
81 | .symbolrate_high = 14999999, | |
0e4558ab YP |
82 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
83 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, | |
a74b51fc | 84 | .FILTune = 0x317 /* 0.90 V */ |
e3b152bc JS |
85 | }, |
86 | { | |
87 | .symbolrate_low = 15000000, | |
88 | .symbolrate_high = 45000000, | |
0e4558ab YP |
89 | .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, |
90 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, | |
91 | .FILTune = 0x145 /* 2.70 V */ | |
e3b152bc JS |
92 | }, |
93 | }; | |
94 | ||
95 | /* | |
96 | * Various tuner defaults need to be established for a given frequency kHz. | |
97 | * fixme: The bounds on the bands do not match the doc in real life. | |
98 | * fixme: Some of them have been moved, other might need adjustment. | |
99 | */ | |
100 | static struct | |
101 | { | |
102 | u32 freq_low; | |
103 | u32 freq_high; | |
e3b152bc | 104 | u32 VCOdivider; |
e3b152bc JS |
105 | u32 progdata; |
106 | } cx24123_bandselect_vals[] = | |
107 | { | |
70047f9c | 108 | /* band 1 */ |
e3b152bc JS |
109 | { |
110 | .freq_low = 950000, | |
e3b152bc | 111 | .freq_high = 1074999, |
e3b152bc | 112 | .VCOdivider = 4, |
70047f9c | 113 | .progdata = (0 << 19) | (0 << 9) | 0x40, |
e3b152bc | 114 | }, |
70047f9c YP |
115 | |
116 | /* band 2 */ | |
e3b152bc JS |
117 | { |
118 | .freq_low = 1075000, | |
70047f9c YP |
119 | .freq_high = 1177999, |
120 | .VCOdivider = 4, | |
121 | .progdata = (0 << 19) | (0 << 9) | 0x80, | |
e3b152bc | 122 | }, |
70047f9c YP |
123 | |
124 | /* band 3 */ | |
e3b152bc | 125 | { |
70047f9c YP |
126 | .freq_low = 1178000, |
127 | .freq_high = 1295999, | |
e3b152bc | 128 | .VCOdivider = 2, |
70047f9c | 129 | .progdata = (0 << 19) | (1 << 9) | 0x01, |
e3b152bc | 130 | }, |
70047f9c YP |
131 | |
132 | /* band 4 */ | |
e3b152bc | 133 | { |
70047f9c YP |
134 | .freq_low = 1296000, |
135 | .freq_high = 1431999, | |
e3b152bc | 136 | .VCOdivider = 2, |
70047f9c | 137 | .progdata = (0 << 19) | (1 << 9) | 0x02, |
e3b152bc | 138 | }, |
70047f9c YP |
139 | |
140 | /* band 5 */ | |
e3b152bc | 141 | { |
70047f9c YP |
142 | .freq_low = 1432000, |
143 | .freq_high = 1575999, | |
e3b152bc | 144 | .VCOdivider = 2, |
70047f9c | 145 | .progdata = (0 << 19) | (1 << 9) | 0x04, |
e3b152bc | 146 | }, |
70047f9c YP |
147 | |
148 | /* band 6 */ | |
e3b152bc | 149 | { |
70047f9c | 150 | .freq_low = 1576000, |
e3b152bc | 151 | .freq_high = 1717999, |
e3b152bc | 152 | .VCOdivider = 2, |
70047f9c | 153 | .progdata = (0 << 19) | (1 << 9) | 0x08, |
e3b152bc | 154 | }, |
70047f9c YP |
155 | |
156 | /* band 7 */ | |
e3b152bc JS |
157 | { |
158 | .freq_low = 1718000, | |
159 | .freq_high = 1855999, | |
e3b152bc | 160 | .VCOdivider = 2, |
70047f9c | 161 | .progdata = (0 << 19) | (1 << 9) | 0x10, |
e3b152bc | 162 | }, |
70047f9c YP |
163 | |
164 | /* band 8 */ | |
e3b152bc JS |
165 | { |
166 | .freq_low = 1856000, | |
167 | .freq_high = 2035999, | |
e3b152bc | 168 | .VCOdivider = 2, |
70047f9c | 169 | .progdata = (0 << 19) | (1 << 9) | 0x20, |
e3b152bc | 170 | }, |
70047f9c YP |
171 | |
172 | /* band 9 */ | |
e3b152bc JS |
173 | { |
174 | .freq_low = 2036000, | |
70047f9c | 175 | .freq_high = 2150000, |
e3b152bc | 176 | .VCOdivider = 2, |
70047f9c | 177 | .progdata = (0 << 19) | (1 << 9) | 0x40, |
e3b152bc JS |
178 | }, |
179 | }; | |
180 | ||
b79cb653 ST |
181 | static struct { |
182 | u8 reg; | |
183 | u8 data; | |
184 | } cx24123_regdata[] = | |
185 | { | |
186 | {0x00, 0x03}, /* Reset system */ | |
187 | {0x00, 0x00}, /* Clear reset */ | |
0e4558ab YP |
188 | {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ |
189 | {0x04, 0x10}, /* MPEG */ | |
190 | {0x05, 0x04}, /* MPEG */ | |
191 | {0x06, 0x31}, /* MPEG (default) */ | |
192 | {0x0b, 0x00}, /* Freq search start point (default) */ | |
193 | {0x0c, 0x00}, /* Demodulator sample gain (default) */ | |
194 | {0x0d, 0x02}, /* Frequency search range = Fsymbol / 4 (default) */ | |
195 | {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ | |
196 | {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ | |
197 | {0x10, 0x01}, /* Default search inversion, no repeat (default) */ | |
198 | {0x16, 0x00}, /* Enable reading of frequency */ | |
199 | {0x17, 0x01}, /* Enable EsNO Ready Counter */ | |
200 | {0x1c, 0x80}, /* Enable error counter */ | |
201 | {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ | |
202 | {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ | |
203 | {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ | |
204 | {0x29, 0x00}, /* DiSEqC LNB_DC off */ | |
205 | {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ | |
206 | {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ | |
207 | {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ | |
b79cb653 ST |
208 | {0x2d, 0x00}, |
209 | {0x2e, 0x00}, | |
210 | {0x2f, 0x00}, | |
211 | {0x30, 0x00}, | |
212 | {0x31, 0x00}, | |
0e4558ab YP |
213 | {0x32, 0x8c}, /* DiSEqC Parameters (default) */ |
214 | {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ | |
b79cb653 | 215 | {0x34, 0x00}, |
0e4558ab YP |
216 | {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ |
217 | {0x36, 0x02}, /* DiSEqC Parameters (default) */ | |
218 | {0x37, 0x3a}, /* DiSEqC Parameters (default) */ | |
219 | {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ | |
220 | {0x44, 0x00}, /* Constellation (default) */ | |
221 | {0x45, 0x00}, /* Symbol count (default) */ | |
222 | {0x46, 0x0d}, /* Symbol rate estimator on (default) */ | |
18c053b3 | 223 | {0x56, 0xc1}, /* Error Counter = Viterbi BER */ |
0e4558ab YP |
224 | {0x57, 0xff}, /* Error Counter Window (default) */ |
225 | {0x67, 0x83}, /* Non-DCII symbol clock */ | |
b79cb653 ST |
226 | }; |
227 | ||
228 | static int cx24123_writereg(struct cx24123_state* state, int reg, int data) | |
229 | { | |
230 | u8 buf[] = { reg, data }; | |
231 | struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; | |
232 | int err; | |
233 | ||
caf970e0 MCC |
234 | if (debug>1) |
235 | printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n", | |
236 | __FUNCTION__,reg, data); | |
237 | ||
b79cb653 ST |
238 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
239 | printk("%s: writereg error(err == %i, reg == 0x%02x," | |
240 | " data == 0x%02x)\n", __FUNCTION__, err, reg, data); | |
241 | return -EREMOTEIO; | |
242 | } | |
243 | ||
244 | return 0; | |
245 | } | |
246 | ||
b79cb653 ST |
247 | static int cx24123_readreg(struct cx24123_state* state, u8 reg) |
248 | { | |
249 | int ret; | |
250 | u8 b0[] = { reg }; | |
251 | u8 b1[] = { 0 }; | |
252 | struct i2c_msg msg[] = { | |
253 | { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, | |
254 | { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } | |
255 | }; | |
256 | ||
257 | ret = i2c_transfer(state->i2c, msg, 2); | |
258 | ||
259 | if (ret != 2) { | |
260 | printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret); | |
261 | return ret; | |
262 | } | |
263 | ||
caf970e0 MCC |
264 | if (debug>1) |
265 | printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret); | |
266 | ||
b79cb653 ST |
267 | return b1[0]; |
268 | } | |
269 | ||
b79cb653 ST |
270 | static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion) |
271 | { | |
0e4558ab YP |
272 | u8 nom_reg = cx24123_readreg(state, 0x0e); |
273 | u8 auto_reg = cx24123_readreg(state, 0x10); | |
274 | ||
b79cb653 ST |
275 | switch (inversion) { |
276 | case INVERSION_OFF: | |
caf970e0 | 277 | dprintk("%s: inversion off\n",__FUNCTION__); |
0e4558ab YP |
278 | cx24123_writereg(state, 0x0e, nom_reg & ~0x80); |
279 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
280 | break; |
281 | case INVERSION_ON: | |
caf970e0 | 282 | dprintk("%s: inversion on\n",__FUNCTION__); |
0e4558ab YP |
283 | cx24123_writereg(state, 0x0e, nom_reg | 0x80); |
284 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
285 | break; |
286 | case INVERSION_AUTO: | |
caf970e0 | 287 | dprintk("%s: inversion auto\n",__FUNCTION__); |
0e4558ab | 288 | cx24123_writereg(state, 0x10, auto_reg & ~0x80); |
b79cb653 ST |
289 | break; |
290 | default: | |
291 | return -EINVAL; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion) | |
298 | { | |
299 | u8 val; | |
300 | ||
301 | val = cx24123_readreg(state, 0x1b) >> 7; | |
302 | ||
caf970e0 MCC |
303 | if (val == 0) { |
304 | dprintk("%s: read inversion off\n",__FUNCTION__); | |
e3b152bc | 305 | *inversion = INVERSION_OFF; |
caf970e0 MCC |
306 | } else { |
307 | dprintk("%s: read inversion on\n",__FUNCTION__); | |
e3b152bc | 308 | *inversion = INVERSION_ON; |
caf970e0 | 309 | } |
b79cb653 ST |
310 | |
311 | return 0; | |
312 | } | |
313 | ||
314 | static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec) | |
315 | { | |
0e4558ab YP |
316 | u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; |
317 | ||
b79cb653 | 318 | if ( (fec < FEC_NONE) || (fec > FEC_AUTO) ) |
e3b152bc | 319 | fec = FEC_AUTO; |
b79cb653 | 320 | |
d12a9b91 YP |
321 | /* Set the soft decision threshold */ |
322 | if(fec == FEC_1_2) | |
323 | cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) | 0x01); | |
324 | else | |
325 | cx24123_writereg(state, 0x43, cx24123_readreg(state, 0x43) & ~0x01); | |
326 | ||
b79cb653 | 327 | switch (fec) { |
b79cb653 | 328 | case FEC_1_2: |
caf970e0 | 329 | dprintk("%s: set FEC to 1/2\n",__FUNCTION__); |
0e4558ab YP |
330 | cx24123_writereg(state, 0x0e, nom_reg | 0x01); |
331 | cx24123_writereg(state, 0x0f, 0x02); | |
332 | break; | |
b79cb653 | 333 | case FEC_2_3: |
caf970e0 | 334 | dprintk("%s: set FEC to 2/3\n",__FUNCTION__); |
0e4558ab YP |
335 | cx24123_writereg(state, 0x0e, nom_reg | 0x02); |
336 | cx24123_writereg(state, 0x0f, 0x04); | |
337 | break; | |
b79cb653 | 338 | case FEC_3_4: |
caf970e0 | 339 | dprintk("%s: set FEC to 3/4\n",__FUNCTION__); |
0e4558ab YP |
340 | cx24123_writereg(state, 0x0e, nom_reg | 0x03); |
341 | cx24123_writereg(state, 0x0f, 0x08); | |
342 | break; | |
343 | case FEC_4_5: | |
caf970e0 | 344 | dprintk("%s: set FEC to 4/5\n",__FUNCTION__); |
0e4558ab YP |
345 | cx24123_writereg(state, 0x0e, nom_reg | 0x04); |
346 | cx24123_writereg(state, 0x0f, 0x10); | |
347 | break; | |
348 | case FEC_5_6: | |
caf970e0 | 349 | dprintk("%s: set FEC to 5/6\n",__FUNCTION__); |
0e4558ab YP |
350 | cx24123_writereg(state, 0x0e, nom_reg | 0x05); |
351 | cx24123_writereg(state, 0x0f, 0x20); | |
352 | break; | |
353 | case FEC_6_7: | |
354 | dprintk("%s: set FEC to 6/7\n",__FUNCTION__); | |
355 | cx24123_writereg(state, 0x0e, nom_reg | 0x06); | |
356 | cx24123_writereg(state, 0x0f, 0x40); | |
357 | break; | |
358 | case FEC_7_8: | |
359 | dprintk("%s: set FEC to 7/8\n",__FUNCTION__); | |
360 | cx24123_writereg(state, 0x0e, nom_reg | 0x07); | |
361 | cx24123_writereg(state, 0x0f, 0x80); | |
362 | break; | |
b79cb653 | 363 | case FEC_AUTO: |
caf970e0 | 364 | dprintk("%s: set FEC to auto\n",__FUNCTION__); |
0e4558ab YP |
365 | cx24123_writereg(state, 0x0f, 0xfe); |
366 | break; | |
b79cb653 ST |
367 | default: |
368 | return -EOPNOTSUPP; | |
369 | } | |
0e4558ab YP |
370 | |
371 | return 0; | |
b79cb653 ST |
372 | } |
373 | ||
374 | static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec) | |
375 | { | |
e3b152bc | 376 | int ret; |
b79cb653 | 377 | |
e3b152bc JS |
378 | ret = cx24123_readreg (state, 0x1b); |
379 | if (ret < 0) | |
380 | return ret; | |
a74b51fc VC |
381 | ret = ret & 0x07; |
382 | ||
383 | switch (ret) { | |
b79cb653 | 384 | case 1: |
e3b152bc JS |
385 | *fec = FEC_1_2; |
386 | break; | |
a74b51fc | 387 | case 2: |
e3b152bc JS |
388 | *fec = FEC_2_3; |
389 | break; | |
a74b51fc | 390 | case 3: |
e3b152bc JS |
391 | *fec = FEC_3_4; |
392 | break; | |
a74b51fc | 393 | case 4: |
e3b152bc JS |
394 | *fec = FEC_4_5; |
395 | break; | |
a74b51fc | 396 | case 5: |
e3b152bc JS |
397 | *fec = FEC_5_6; |
398 | break; | |
a74b51fc VC |
399 | case 6: |
400 | *fec = FEC_6_7; | |
401 | break; | |
b79cb653 | 402 | case 7: |
e3b152bc JS |
403 | *fec = FEC_7_8; |
404 | break; | |
b79cb653 | 405 | default: |
0e4558ab YP |
406 | /* this can happen when there's no lock */ |
407 | *fec = FEC_NONE; | |
b79cb653 ST |
408 | } |
409 | ||
e3b152bc | 410 | return 0; |
b79cb653 ST |
411 | } |
412 | ||
0e4558ab YP |
413 | /* Approximation of closest integer of log2(a/b). It actually gives the |
414 | lowest integer i such that 2^i >= round(a/b) */ | |
415 | static u32 cx24123_int_log2(u32 a, u32 b) | |
416 | { | |
417 | u32 exp, nearest = 0; | |
418 | u32 div = a / b; | |
419 | if(a % b >= b / 2) ++div; | |
420 | if(div < (1 << 31)) | |
421 | { | |
422 | for(exp = 1; div > exp; nearest++) | |
423 | exp += exp; | |
424 | } | |
425 | return nearest; | |
426 | } | |
427 | ||
b79cb653 ST |
428 | static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate) |
429 | { | |
0e4558ab | 430 | u32 tmp, sample_rate, ratio, sample_gain; |
a74b51fc VC |
431 | u8 pll_mult; |
432 | ||
433 | /* check if symbol rate is within limits */ | |
dea74869 PB |
434 | if ((srate > state->frontend.ops.info.symbol_rate_max) || |
435 | (srate < state->frontend.ops.info.symbol_rate_min)) | |
a74b51fc VC |
436 | return -EOPNOTSUPP;; |
437 | ||
438 | /* choose the sampling rate high enough for the required operation, | |
439 | while optimizing the power consumed by the demodulator */ | |
440 | if (srate < (XTAL*2)/2) | |
441 | pll_mult = 2; | |
442 | else if (srate < (XTAL*3)/2) | |
443 | pll_mult = 3; | |
444 | else if (srate < (XTAL*4)/2) | |
445 | pll_mult = 4; | |
446 | else if (srate < (XTAL*5)/2) | |
447 | pll_mult = 5; | |
448 | else if (srate < (XTAL*6)/2) | |
449 | pll_mult = 6; | |
450 | else if (srate < (XTAL*7)/2) | |
451 | pll_mult = 7; | |
452 | else if (srate < (XTAL*8)/2) | |
453 | pll_mult = 8; | |
454 | else | |
455 | pll_mult = 9; | |
456 | ||
457 | ||
458 | sample_rate = pll_mult * XTAL; | |
b79cb653 | 459 | |
a74b51fc VC |
460 | /* |
461 | SYSSymbolRate[21:0] = (srate << 23) / sample_rate | |
b79cb653 | 462 | |
a74b51fc VC |
463 | We have to use 32 bit unsigned arithmetic without precision loss. |
464 | The maximum srate is 45000000 or 0x02AEA540. This number has | |
465 | only 6 clear bits on top, hence we can shift it left only 6 bits | |
466 | at a time. Borrowed from cx24110.c | |
467 | */ | |
b79cb653 | 468 | |
a74b51fc VC |
469 | tmp = srate << 6; |
470 | ratio = tmp / sample_rate; | |
471 | ||
472 | tmp = (tmp % sample_rate) << 6; | |
473 | ratio = (ratio << 6) + (tmp / sample_rate); | |
474 | ||
475 | tmp = (tmp % sample_rate) << 6; | |
476 | ratio = (ratio << 6) + (tmp / sample_rate); | |
477 | ||
478 | tmp = (tmp % sample_rate) << 5; | |
479 | ratio = (ratio << 5) + (tmp / sample_rate); | |
480 | ||
481 | ||
482 | cx24123_writereg(state, 0x01, pll_mult * 6); | |
483 | ||
484 | cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f ); | |
485 | cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff ); | |
486 | cx24123_writereg(state, 0x0a, (ratio ) & 0xff ); | |
487 | ||
0e4558ab YP |
488 | /* also set the demodulator sample gain */ |
489 | sample_gain = cx24123_int_log2(sample_rate, srate); | |
490 | tmp = cx24123_readreg(state, 0x0c) & ~0xe0; | |
491 | cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); | |
492 | ||
493 | dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain); | |
b79cb653 ST |
494 | |
495 | return 0; | |
496 | } | |
497 | ||
498 | /* | |
499 | * Based on the required frequency and symbolrate, the tuner AGC has to be configured | |
500 | * and the correct band selected. Calculate those values | |
501 | */ | |
502 | static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
503 | { | |
504 | struct cx24123_state *state = fe->demodulator_priv; | |
e3b152bc JS |
505 | u32 ndiv = 0, adiv = 0, vco_div = 0; |
506 | int i = 0; | |
a74b51fc | 507 | int pump = 2; |
70047f9c YP |
508 | int band = 0; |
509 | int num_bands = sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); | |
b79cb653 ST |
510 | |
511 | /* Defaults for low freq, low rate */ | |
512 | state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; | |
513 | state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; | |
514 | state->bandselectarg = cx24123_bandselect_vals[0].progdata; | |
515 | vco_div = cx24123_bandselect_vals[0].VCOdivider; | |
516 | ||
a74b51fc | 517 | /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */ |
e3b152bc | 518 | for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++) |
b79cb653 ST |
519 | { |
520 | if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) && | |
a74b51fc | 521 | (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) { |
b79cb653 ST |
522 | state->VCAarg = cx24123_AGC_vals[i].VCAprogdata; |
523 | state->VGAarg = cx24123_AGC_vals[i].VGAprogdata; | |
a74b51fc | 524 | state->FILTune = cx24123_AGC_vals[i].FILTune; |
b79cb653 ST |
525 | } |
526 | } | |
527 | ||
70047f9c YP |
528 | /* determine the band to use */ |
529 | if(force_band < 1 || force_band > num_bands) | |
b79cb653 | 530 | { |
70047f9c YP |
531 | for (i = 0; i < num_bands; i++) |
532 | { | |
533 | if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) && | |
534 | (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) | |
535 | band = i; | |
b79cb653 ST |
536 | } |
537 | } | |
70047f9c YP |
538 | else |
539 | band = force_band - 1; | |
540 | ||
541 | state->bandselectarg = cx24123_bandselect_vals[band].progdata; | |
542 | vco_div = cx24123_bandselect_vals[band].VCOdivider; | |
543 | ||
544 | /* determine the charge pump current */ | |
545 | if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 ) | |
546 | pump = 0x01; | |
547 | else | |
548 | pump = 0x02; | |
b79cb653 ST |
549 | |
550 | /* Determine the N/A dividers for the requested lband freq (in kHz). */ | |
a74b51fc VC |
551 | /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */ |
552 | ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff; | |
553 | adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f; | |
b79cb653 ST |
554 | |
555 | if (adiv == 0) | |
a74b51fc | 556 | ndiv++; |
b79cb653 | 557 | |
a74b51fc VC |
558 | /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */ |
559 | state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv; | |
b79cb653 ST |
560 | |
561 | return 0; | |
562 | } | |
563 | ||
564 | /* | |
565 | * Tuner data is 21 bits long, must be left-aligned in data. | |
566 | * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip. | |
567 | */ | |
568 | static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data) | |
569 | { | |
570 | struct cx24123_state *state = fe->demodulator_priv; | |
0144f314 | 571 | unsigned long timeout; |
b79cb653 | 572 | |
caf970e0 MCC |
573 | dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data); |
574 | ||
b79cb653 ST |
575 | /* align the 21 bytes into to bit23 boundary */ |
576 | data = data << 3; | |
577 | ||
578 | /* Reset the demod pll word length to 0x15 bits */ | |
579 | cx24123_writereg(state, 0x21, 0x15); | |
580 | ||
b79cb653 | 581 | /* write the msb 8 bits, wait for the send to be completed */ |
0144f314 | 582 | timeout = jiffies + msecs_to_jiffies(40); |
e3b152bc | 583 | cx24123_writereg(state, 0x22, (data >> 16) & 0xff); |
0144f314 ST |
584 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
585 | if (time_after(jiffies, timeout)) { | |
586 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
587 | return -EREMOTEIO; |
588 | } | |
0144f314 | 589 | msleep(10); |
b79cb653 ST |
590 | } |
591 | ||
b79cb653 | 592 | /* send another 8 bytes, wait for the send to be completed */ |
0144f314 | 593 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 594 | cx24123_writereg(state, 0x22, (data>>8) & 0xff ); |
0144f314 ST |
595 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
596 | if (time_after(jiffies, timeout)) { | |
597 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
598 | return -EREMOTEIO; |
599 | } | |
0144f314 | 600 | msleep(10); |
b79cb653 ST |
601 | } |
602 | ||
b79cb653 | 603 | /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */ |
0144f314 | 604 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 605 | cx24123_writereg(state, 0x22, (data) & 0xff ); |
0144f314 ST |
606 | while ((cx24123_readreg(state, 0x20) & 0x80)) { |
607 | if (time_after(jiffies, timeout)) { | |
608 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
609 | return -EREMOTEIO; |
610 | } | |
0144f314 | 611 | msleep(10); |
b79cb653 ST |
612 | } |
613 | ||
614 | /* Trigger the demod to configure the tuner */ | |
615 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); | |
616 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); | |
617 | ||
618 | return 0; | |
619 | } | |
620 | ||
621 | static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
622 | { | |
623 | struct cx24123_state *state = fe->demodulator_priv; | |
a74b51fc VC |
624 | u8 val; |
625 | ||
626 | dprintk("frequency=%i\n", p->frequency); | |
b79cb653 | 627 | |
e3b152bc | 628 | if (cx24123_pll_calculate(fe, p) != 0) { |
b79cb653 ST |
629 | printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__); |
630 | return -EINVAL; | |
631 | } | |
632 | ||
633 | /* Write the new VCO/VGA */ | |
634 | cx24123_pll_writereg(fe, p, state->VCAarg); | |
635 | cx24123_pll_writereg(fe, p, state->VGAarg); | |
636 | ||
637 | /* Write the new bandselect and pll args */ | |
638 | cx24123_pll_writereg(fe, p, state->bandselectarg); | |
639 | cx24123_pll_writereg(fe, p, state->pllarg); | |
640 | ||
a74b51fc VC |
641 | /* set the FILTUNE voltage */ |
642 | val = cx24123_readreg(state, 0x28) & ~0x3; | |
643 | cx24123_writereg(state, 0x27, state->FILTune >> 2); | |
644 | cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); | |
645 | ||
caf970e0 MCC |
646 | dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg, |
647 | state->bandselectarg,state->pllarg); | |
648 | ||
b79cb653 ST |
649 | return 0; |
650 | } | |
651 | ||
652 | static int cx24123_initfe(struct dvb_frontend* fe) | |
653 | { | |
654 | struct cx24123_state *state = fe->demodulator_priv; | |
655 | int i; | |
656 | ||
caf970e0 MCC |
657 | dprintk("%s: init frontend\n",__FUNCTION__); |
658 | ||
b79cb653 | 659 | /* Configure the demod to a good set of defaults */ |
e3b152bc | 660 | for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++) |
b79cb653 ST |
661 | cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data); |
662 | ||
b79cb653 ST |
663 | return 0; |
664 | } | |
665 | ||
666 | static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage) | |
667 | { | |
668 | struct cx24123_state *state = fe->demodulator_priv; | |
669 | u8 val; | |
670 | ||
cd20ca9f | 671 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 672 | |
cd20ca9f AQ |
673 | switch (voltage) { |
674 | case SEC_VOLTAGE_13: | |
675 | dprintk("%s: setting voltage 13V\n", __FUNCTION__); | |
ccd214b2 | 676 | return cx24123_writereg(state, 0x29, val & 0x7f); |
cd20ca9f AQ |
677 | case SEC_VOLTAGE_18: |
678 | dprintk("%s: setting voltage 18V\n", __FUNCTION__); | |
ccd214b2 | 679 | return cx24123_writereg(state, 0x29, val | 0x80); |
cd20ca9f AQ |
680 | default: |
681 | return -EINVAL; | |
682 | }; | |
1c956a3a VC |
683 | |
684 | return 0; | |
b79cb653 ST |
685 | } |
686 | ||
dce1dfc2 YP |
687 | /* wait for diseqc queue to become ready (or timeout) */ |
688 | static void cx24123_wait_for_diseqc(struct cx24123_state *state) | |
689 | { | |
690 | unsigned long timeout = jiffies + msecs_to_jiffies(200); | |
691 | while (!(cx24123_readreg(state, 0x29) & 0x40)) { | |
692 | if(time_after(jiffies, timeout)) { | |
693 | printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__); | |
694 | break; | |
695 | } | |
696 | msleep(10); | |
697 | } | |
698 | } | |
699 | ||
a74b51fc | 700 | static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd) |
b79cb653 | 701 | { |
a74b51fc | 702 | struct cx24123_state *state = fe->demodulator_priv; |
cd20ca9f | 703 | int i, val, tone; |
a74b51fc VC |
704 | |
705 | dprintk("%s:\n",__FUNCTION__); | |
b79cb653 | 706 | |
cd20ca9f AQ |
707 | /* stop continuous tone if enabled */ |
708 | tone = cx24123_readreg(state, 0x29); | |
709 | if (tone & 0x10) | |
710 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 711 | |
dce1dfc2 YP |
712 | /* wait for diseqc queue ready */ |
713 | cx24123_wait_for_diseqc(state); | |
714 | ||
a74b51fc | 715 | /* select tone mode */ |
cd20ca9f | 716 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc VC |
717 | |
718 | for (i = 0; i < cmd->msg_len; i++) | |
719 | cx24123_writereg(state, 0x2C + i, cmd->msg[i]); | |
720 | ||
721 | val = cx24123_readreg(state, 0x29); | |
722 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); | |
723 | ||
dce1dfc2 YP |
724 | /* wait for diseqc message to finish sending */ |
725 | cx24123_wait_for_diseqc(state); | |
a74b51fc | 726 | |
cd20ca9f AQ |
727 | /* restart continuous tone if enabled */ |
728 | if (tone & 0x10) { | |
729 | cx24123_writereg(state, 0x29, tone & ~0x40); | |
730 | } | |
731 | ||
a74b51fc VC |
732 | return 0; |
733 | } | |
734 | ||
735 | static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) | |
736 | { | |
737 | struct cx24123_state *state = fe->demodulator_priv; | |
cd20ca9f | 738 | int val, tone; |
a74b51fc VC |
739 | |
740 | dprintk("%s:\n", __FUNCTION__); | |
741 | ||
cd20ca9f AQ |
742 | /* stop continuous tone if enabled */ |
743 | tone = cx24123_readreg(state, 0x29); | |
744 | if (tone & 0x10) | |
745 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 746 | |
cd20ca9f | 747 | /* wait for diseqc queue ready */ |
dce1dfc2 YP |
748 | cx24123_wait_for_diseqc(state); |
749 | ||
a74b51fc | 750 | /* select tone mode */ |
cd20ca9f AQ |
751 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); |
752 | msleep(30); | |
a74b51fc | 753 | val = cx24123_readreg(state, 0x29); |
a74b51fc VC |
754 | if (burst == SEC_MINI_A) |
755 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); | |
756 | else if (burst == SEC_MINI_B) | |
757 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); | |
758 | else | |
759 | return -EINVAL; | |
760 | ||
dce1dfc2 | 761 | cx24123_wait_for_diseqc(state); |
cd20ca9f | 762 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc | 763 | |
cd20ca9f AQ |
764 | /* restart continuous tone if enabled */ |
765 | if (tone & 0x10) { | |
766 | cx24123_writereg(state, 0x29, tone & ~0x40); | |
767 | } | |
a74b51fc | 768 | return 0; |
b79cb653 ST |
769 | } |
770 | ||
771 | static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status) | |
772 | { | |
773 | struct cx24123_state *state = fe->demodulator_priv; | |
774 | ||
775 | int sync = cx24123_readreg(state, 0x14); | |
776 | int lock = cx24123_readreg(state, 0x20); | |
777 | ||
778 | *status = 0; | |
779 | if (lock & 0x01) | |
a74b51fc VC |
780 | *status |= FE_HAS_SIGNAL; |
781 | if (sync & 0x02) | |
782 | *status |= FE_HAS_CARRIER; | |
b79cb653 ST |
783 | if (sync & 0x04) |
784 | *status |= FE_HAS_VITERBI; | |
785 | if (sync & 0x08) | |
a74b51fc | 786 | *status |= FE_HAS_SYNC; |
b79cb653 | 787 | if (sync & 0x80) |
a74b51fc | 788 | *status |= FE_HAS_LOCK; |
b79cb653 ST |
789 | |
790 | return 0; | |
791 | } | |
792 | ||
793 | /* | |
794 | * Configured to return the measurement of errors in blocks, because no UCBLOCKS value | |
795 | * is available, so this value doubles up to satisfy both measurements | |
796 | */ | |
797 | static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber) | |
798 | { | |
799 | struct cx24123_state *state = fe->demodulator_priv; | |
800 | ||
18c053b3 YP |
801 | /* The true bit error rate is this value divided by |
802 | the window size (set as 256 * 255) */ | |
803 | *ber = ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | | |
b79cb653 | 804 | (cx24123_readreg(state, 0x1d) << 8 | |
18c053b3 | 805 | cx24123_readreg(state, 0x1e)); |
caf970e0 | 806 | |
18c053b3 | 807 | dprintk("%s: BER = %d\n",__FUNCTION__,*ber); |
b79cb653 ST |
808 | |
809 | return 0; | |
810 | } | |
811 | ||
812 | static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength) | |
813 | { | |
814 | struct cx24123_state *state = fe->demodulator_priv; | |
815 | *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */ | |
816 | ||
caf970e0 MCC |
817 | dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength); |
818 | ||
b79cb653 ST |
819 | return 0; |
820 | } | |
821 | ||
822 | static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr) | |
823 | { | |
824 | struct cx24123_state *state = fe->demodulator_priv; | |
b79cb653 | 825 | |
18c053b3 YP |
826 | /* Inverted raw Es/N0 count, totally bogus but better than the |
827 | BER threshold. */ | |
828 | *snr = 65535 - (((u16)cx24123_readreg(state, 0x18) << 8) | | |
829 | (u16)cx24123_readreg(state, 0x19)); | |
caf970e0 | 830 | |
18c053b3 | 831 | dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr); |
caf970e0 | 832 | |
b79cb653 ST |
833 | return 0; |
834 | } | |
835 | ||
836 | static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
837 | { | |
838 | struct cx24123_state *state = fe->demodulator_priv; | |
839 | ||
caf970e0 MCC |
840 | dprintk("%s: set_frontend\n",__FUNCTION__); |
841 | ||
b79cb653 ST |
842 | if (state->config->set_ts_params) |
843 | state->config->set_ts_params(fe, 0); | |
844 | ||
845 | state->currentfreq=p->frequency; | |
e3b152bc | 846 | state->currentsymbolrate = p->u.qpsk.symbol_rate; |
b79cb653 ST |
847 | |
848 | cx24123_set_inversion(state, p->inversion); | |
849 | cx24123_set_fec(state, p->u.qpsk.fec_inner); | |
850 | cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate); | |
851 | cx24123_pll_tune(fe, p); | |
852 | ||
853 | /* Enable automatic aquisition and reset cycle */ | |
e3b152bc | 854 | cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); |
b79cb653 ST |
855 | cx24123_writereg(state, 0x00, 0x10); |
856 | cx24123_writereg(state, 0x00, 0); | |
857 | ||
858 | return 0; | |
859 | } | |
860 | ||
861 | static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
862 | { | |
863 | struct cx24123_state *state = fe->demodulator_priv; | |
864 | ||
caf970e0 MCC |
865 | dprintk("%s: get_frontend\n",__FUNCTION__); |
866 | ||
b79cb653 ST |
867 | if (cx24123_get_inversion(state, &p->inversion) != 0) { |
868 | printk("%s: Failed to get inversion status\n",__FUNCTION__); | |
869 | return -EREMOTEIO; | |
870 | } | |
871 | if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) { | |
872 | printk("%s: Failed to get fec status\n",__FUNCTION__); | |
873 | return -EREMOTEIO; | |
874 | } | |
875 | p->frequency = state->currentfreq; | |
876 | p->u.qpsk.symbol_rate = state->currentsymbolrate; | |
877 | ||
878 | return 0; | |
879 | } | |
880 | ||
881 | static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) | |
882 | { | |
883 | struct cx24123_state *state = fe->demodulator_priv; | |
884 | u8 val; | |
885 | ||
cd20ca9f AQ |
886 | /* wait for diseqc queue ready */ |
887 | cx24123_wait_for_diseqc(state); | |
1c956a3a | 888 | |
cd20ca9f | 889 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 890 | |
cd20ca9f AQ |
891 | switch (tone) { |
892 | case SEC_TONE_ON: | |
893 | dprintk("%s: setting tone on\n", __FUNCTION__); | |
894 | return cx24123_writereg(state, 0x29, val | 0x10); | |
895 | case SEC_TONE_OFF: | |
896 | dprintk("%s: setting tone off\n",__FUNCTION__); | |
897 | return cx24123_writereg(state, 0x29, val & 0xef); | |
898 | default: | |
899 | printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone); | |
900 | return -EINVAL; | |
b79cb653 | 901 | } |
1c956a3a VC |
902 | |
903 | return 0; | |
b79cb653 ST |
904 | } |
905 | ||
174ff219 YP |
906 | static int cx24123_tune(struct dvb_frontend* fe, |
907 | struct dvb_frontend_parameters* params, | |
908 | unsigned int mode_flags, | |
909 | int *delay, | |
910 | fe_status_t *status) | |
911 | { | |
912 | int retval = 0; | |
913 | ||
914 | if (params != NULL) | |
915 | retval = cx24123_set_frontend(fe, params); | |
916 | ||
917 | if (!(mode_flags & FE_TUNE_MODE_ONESHOT)) | |
918 | cx24123_read_status(fe, status); | |
919 | *delay = HZ/10; | |
920 | ||
921 | return retval; | |
922 | } | |
923 | ||
924 | static int cx24123_get_algo(struct dvb_frontend *fe) | |
925 | { | |
926 | return 1; //FE_ALGO_HW | |
927 | } | |
928 | ||
b79cb653 ST |
929 | static void cx24123_release(struct dvb_frontend* fe) |
930 | { | |
931 | struct cx24123_state* state = fe->demodulator_priv; | |
932 | dprintk("%s\n",__FUNCTION__); | |
933 | kfree(state); | |
934 | } | |
935 | ||
936 | static struct dvb_frontend_ops cx24123_ops; | |
937 | ||
e3b152bc JS |
938 | struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, |
939 | struct i2c_adapter* i2c) | |
b79cb653 ST |
940 | { |
941 | struct cx24123_state* state = NULL; | |
942 | int ret; | |
943 | ||
944 | dprintk("%s\n",__FUNCTION__); | |
945 | ||
946 | /* allocate memory for the internal state */ | |
947 | state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL); | |
948 | if (state == NULL) { | |
949 | printk("Unable to kmalloc\n"); | |
950 | goto error; | |
951 | } | |
952 | ||
953 | /* setup the state */ | |
954 | state->config = config; | |
955 | state->i2c = i2c; | |
b79cb653 ST |
956 | state->VCAarg = 0; |
957 | state->VGAarg = 0; | |
958 | state->bandselectarg = 0; | |
959 | state->pllarg = 0; | |
960 | state->currentfreq = 0; | |
961 | state->currentsymbolrate = 0; | |
962 | ||
963 | /* check if the demod is there */ | |
964 | ret = cx24123_readreg(state, 0x00); | |
965 | if ((ret != 0xd1) && (ret != 0xe1)) { | |
966 | printk("Version != d1 or e1\n"); | |
967 | goto error; | |
968 | } | |
969 | ||
970 | /* create dvb_frontend */ | |
dea74869 | 971 | memcpy(&state->frontend.ops, &cx24123_ops, sizeof(struct dvb_frontend_ops)); |
b79cb653 ST |
972 | state->frontend.demodulator_priv = state; |
973 | return &state->frontend; | |
974 | ||
975 | error: | |
976 | kfree(state); | |
977 | ||
978 | return NULL; | |
979 | } | |
980 | ||
981 | static struct dvb_frontend_ops cx24123_ops = { | |
982 | ||
983 | .info = { | |
984 | .name = "Conexant CX24123/CX24109", | |
985 | .type = FE_QPSK, | |
986 | .frequency_min = 950000, | |
987 | .frequency_max = 2150000, | |
988 | .frequency_stepsize = 1011, /* kHz for QPSK frontends */ | |
0e4558ab | 989 | .frequency_tolerance = 5000, |
b79cb653 ST |
990 | .symbol_rate_min = 1000000, |
991 | .symbol_rate_max = 45000000, | |
992 | .caps = FE_CAN_INVERSION_AUTO | | |
993 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
0e4558ab YP |
994 | FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | |
995 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
b79cb653 ST |
996 | FE_CAN_QPSK | FE_CAN_RECOVER |
997 | }, | |
998 | ||
999 | .release = cx24123_release, | |
1000 | ||
1001 | .init = cx24123_initfe, | |
1002 | .set_frontend = cx24123_set_frontend, | |
1003 | .get_frontend = cx24123_get_frontend, | |
1004 | .read_status = cx24123_read_status, | |
1005 | .read_ber = cx24123_read_ber, | |
1006 | .read_signal_strength = cx24123_read_signal_strength, | |
1007 | .read_snr = cx24123_read_snr, | |
b79cb653 | 1008 | .diseqc_send_master_cmd = cx24123_send_diseqc_msg, |
a74b51fc | 1009 | .diseqc_send_burst = cx24123_diseqc_send_burst, |
b79cb653 ST |
1010 | .set_tone = cx24123_set_tone, |
1011 | .set_voltage = cx24123_set_voltage, | |
174ff219 YP |
1012 | .tune = cx24123_tune, |
1013 | .get_frontend_algo = cx24123_get_algo, | |
b79cb653 ST |
1014 | }; |
1015 | ||
1016 | module_param(debug, int, 0644); | |
caf970e0 | 1017 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); |
b79cb653 | 1018 | |
70047f9c YP |
1019 | module_param(force_band, int, 0644); |
1020 | MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off)."); | |
1021 | ||
b79cb653 ST |
1022 | MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware"); |
1023 | MODULE_AUTHOR("Steven Toth"); | |
1024 | MODULE_LICENSE("GPL"); | |
1025 | ||
1026 | EXPORT_SYMBOL(cx24123_attach); |