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Commit | Line | Data |
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b79cb653 ST |
1 | /* |
2 | Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver | |
3 | ||
4 | Copyright (C) 2005 Steven Toth <stoth@hauppauge.com> | |
5 | ||
1c956a3a VC |
6 | Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> |
7 | ||
b79cb653 ST |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/slab.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/init.h> | |
28 | ||
29 | #include "dvb_frontend.h" | |
30 | #include "cx24123.h" | |
31 | ||
a74b51fc VC |
32 | #define XTAL 10111000 |
33 | ||
70047f9c | 34 | static int force_band; |
b79cb653 ST |
35 | static int debug; |
36 | #define dprintk(args...) \ | |
37 | do { \ | |
38 | if (debug) printk (KERN_DEBUG "cx24123: " args); \ | |
39 | } while (0) | |
40 | ||
e3b152bc JS |
41 | struct cx24123_state |
42 | { | |
b79cb653 ST |
43 | struct i2c_adapter* i2c; |
44 | struct dvb_frontend_ops ops; | |
45 | const struct cx24123_config* config; | |
46 | ||
47 | struct dvb_frontend frontend; | |
48 | ||
49 | u32 lastber; | |
50 | u16 snr; | |
51 | u8 lnbreg; | |
52 | ||
53 | /* Some PLL specifics for tuning */ | |
54 | u32 VCAarg; | |
55 | u32 VGAarg; | |
56 | u32 bandselectarg; | |
57 | u32 pllarg; | |
a74b51fc | 58 | u32 FILTune; |
b79cb653 ST |
59 | |
60 | /* The Demod/Tuner can't easily provide these, we cache them */ | |
61 | u32 currentfreq; | |
62 | u32 currentsymbolrate; | |
63 | }; | |
64 | ||
e3b152bc JS |
65 | /* Various tuner defaults need to be established for a given symbol rate Sps */ |
66 | static struct | |
67 | { | |
68 | u32 symbolrate_low; | |
69 | u32 symbolrate_high; | |
e3b152bc JS |
70 | u32 VCAprogdata; |
71 | u32 VGAprogdata; | |
a74b51fc | 72 | u32 FILTune; |
e3b152bc JS |
73 | } cx24123_AGC_vals[] = |
74 | { | |
75 | { | |
76 | .symbolrate_low = 1000000, | |
77 | .symbolrate_high = 4999999, | |
a74b51fc VC |
78 | /* the specs recommend other values for VGA offsets, |
79 | but tests show they are wrong */ | |
0e4558ab YP |
80 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
81 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, | |
82 | .FILTune = 0x27f /* 0.41 V */ | |
e3b152bc JS |
83 | }, |
84 | { | |
85 | .symbolrate_low = 5000000, | |
86 | .symbolrate_high = 14999999, | |
0e4558ab YP |
87 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
88 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, | |
a74b51fc | 89 | .FILTune = 0x317 /* 0.90 V */ |
e3b152bc JS |
90 | }, |
91 | { | |
92 | .symbolrate_low = 15000000, | |
93 | .symbolrate_high = 45000000, | |
0e4558ab YP |
94 | .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, |
95 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, | |
96 | .FILTune = 0x145 /* 2.70 V */ | |
e3b152bc JS |
97 | }, |
98 | }; | |
99 | ||
100 | /* | |
101 | * Various tuner defaults need to be established for a given frequency kHz. | |
102 | * fixme: The bounds on the bands do not match the doc in real life. | |
103 | * fixme: Some of them have been moved, other might need adjustment. | |
104 | */ | |
105 | static struct | |
106 | { | |
107 | u32 freq_low; | |
108 | u32 freq_high; | |
e3b152bc | 109 | u32 VCOdivider; |
e3b152bc JS |
110 | u32 progdata; |
111 | } cx24123_bandselect_vals[] = | |
112 | { | |
70047f9c | 113 | /* band 1 */ |
e3b152bc JS |
114 | { |
115 | .freq_low = 950000, | |
e3b152bc | 116 | .freq_high = 1074999, |
e3b152bc | 117 | .VCOdivider = 4, |
70047f9c | 118 | .progdata = (0 << 19) | (0 << 9) | 0x40, |
e3b152bc | 119 | }, |
70047f9c YP |
120 | |
121 | /* band 2 */ | |
e3b152bc JS |
122 | { |
123 | .freq_low = 1075000, | |
70047f9c YP |
124 | .freq_high = 1177999, |
125 | .VCOdivider = 4, | |
126 | .progdata = (0 << 19) | (0 << 9) | 0x80, | |
e3b152bc | 127 | }, |
70047f9c YP |
128 | |
129 | /* band 3 */ | |
e3b152bc | 130 | { |
70047f9c YP |
131 | .freq_low = 1178000, |
132 | .freq_high = 1295999, | |
e3b152bc | 133 | .VCOdivider = 2, |
70047f9c | 134 | .progdata = (0 << 19) | (1 << 9) | 0x01, |
e3b152bc | 135 | }, |
70047f9c YP |
136 | |
137 | /* band 4 */ | |
e3b152bc | 138 | { |
70047f9c YP |
139 | .freq_low = 1296000, |
140 | .freq_high = 1431999, | |
e3b152bc | 141 | .VCOdivider = 2, |
70047f9c | 142 | .progdata = (0 << 19) | (1 << 9) | 0x02, |
e3b152bc | 143 | }, |
70047f9c YP |
144 | |
145 | /* band 5 */ | |
e3b152bc | 146 | { |
70047f9c YP |
147 | .freq_low = 1432000, |
148 | .freq_high = 1575999, | |
e3b152bc | 149 | .VCOdivider = 2, |
70047f9c | 150 | .progdata = (0 << 19) | (1 << 9) | 0x04, |
e3b152bc | 151 | }, |
70047f9c YP |
152 | |
153 | /* band 6 */ | |
e3b152bc | 154 | { |
70047f9c | 155 | .freq_low = 1576000, |
e3b152bc | 156 | .freq_high = 1717999, |
e3b152bc | 157 | .VCOdivider = 2, |
70047f9c | 158 | .progdata = (0 << 19) | (1 << 9) | 0x08, |
e3b152bc | 159 | }, |
70047f9c YP |
160 | |
161 | /* band 7 */ | |
e3b152bc JS |
162 | { |
163 | .freq_low = 1718000, | |
164 | .freq_high = 1855999, | |
e3b152bc | 165 | .VCOdivider = 2, |
70047f9c | 166 | .progdata = (0 << 19) | (1 << 9) | 0x10, |
e3b152bc | 167 | }, |
70047f9c YP |
168 | |
169 | /* band 8 */ | |
e3b152bc JS |
170 | { |
171 | .freq_low = 1856000, | |
172 | .freq_high = 2035999, | |
e3b152bc | 173 | .VCOdivider = 2, |
70047f9c | 174 | .progdata = (0 << 19) | (1 << 9) | 0x20, |
e3b152bc | 175 | }, |
70047f9c YP |
176 | |
177 | /* band 9 */ | |
e3b152bc JS |
178 | { |
179 | .freq_low = 2036000, | |
70047f9c | 180 | .freq_high = 2150000, |
e3b152bc | 181 | .VCOdivider = 2, |
70047f9c | 182 | .progdata = (0 << 19) | (1 << 9) | 0x40, |
e3b152bc JS |
183 | }, |
184 | }; | |
185 | ||
b79cb653 ST |
186 | static struct { |
187 | u8 reg; | |
188 | u8 data; | |
189 | } cx24123_regdata[] = | |
190 | { | |
191 | {0x00, 0x03}, /* Reset system */ | |
192 | {0x00, 0x00}, /* Clear reset */ | |
0e4558ab YP |
193 | {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ |
194 | {0x04, 0x10}, /* MPEG */ | |
195 | {0x05, 0x04}, /* MPEG */ | |
196 | {0x06, 0x31}, /* MPEG (default) */ | |
197 | {0x0b, 0x00}, /* Freq search start point (default) */ | |
198 | {0x0c, 0x00}, /* Demodulator sample gain (default) */ | |
199 | {0x0d, 0x02}, /* Frequency search range = Fsymbol / 4 (default) */ | |
200 | {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ | |
201 | {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ | |
202 | {0x10, 0x01}, /* Default search inversion, no repeat (default) */ | |
203 | {0x16, 0x00}, /* Enable reading of frequency */ | |
204 | {0x17, 0x01}, /* Enable EsNO Ready Counter */ | |
205 | {0x1c, 0x80}, /* Enable error counter */ | |
206 | {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ | |
207 | {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ | |
208 | {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ | |
209 | {0x29, 0x00}, /* DiSEqC LNB_DC off */ | |
210 | {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ | |
211 | {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ | |
212 | {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ | |
b79cb653 ST |
213 | {0x2d, 0x00}, |
214 | {0x2e, 0x00}, | |
215 | {0x2f, 0x00}, | |
216 | {0x30, 0x00}, | |
217 | {0x31, 0x00}, | |
0e4558ab YP |
218 | {0x32, 0x8c}, /* DiSEqC Parameters (default) */ |
219 | {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ | |
b79cb653 | 220 | {0x34, 0x00}, |
0e4558ab YP |
221 | {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ |
222 | {0x36, 0x02}, /* DiSEqC Parameters (default) */ | |
223 | {0x37, 0x3a}, /* DiSEqC Parameters (default) */ | |
224 | {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ | |
225 | {0x44, 0x00}, /* Constellation (default) */ | |
226 | {0x45, 0x00}, /* Symbol count (default) */ | |
227 | {0x46, 0x0d}, /* Symbol rate estimator on (default) */ | |
228 | {0x56, 0x41}, /* Various (default) */ | |
229 | {0x57, 0xff}, /* Error Counter Window (default) */ | |
230 | {0x67, 0x83}, /* Non-DCII symbol clock */ | |
b79cb653 ST |
231 | }; |
232 | ||
233 | static int cx24123_writereg(struct cx24123_state* state, int reg, int data) | |
234 | { | |
235 | u8 buf[] = { reg, data }; | |
236 | struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; | |
237 | int err; | |
238 | ||
caf970e0 MCC |
239 | if (debug>1) |
240 | printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n", | |
241 | __FUNCTION__,reg, data); | |
242 | ||
b79cb653 ST |
243 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
244 | printk("%s: writereg error(err == %i, reg == 0x%02x," | |
245 | " data == 0x%02x)\n", __FUNCTION__, err, reg, data); | |
246 | return -EREMOTEIO; | |
247 | } | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | static int cx24123_writelnbreg(struct cx24123_state* state, int reg, int data) | |
253 | { | |
254 | u8 buf[] = { reg, data }; | |
255 | /* fixme: put the intersil addr int the config */ | |
256 | struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 2 }; | |
257 | int err; | |
258 | ||
caf970e0 MCC |
259 | if (debug>1) |
260 | printk("cx24123: %s: writeln addr=0x08, reg 0x%02x, value 0x%02x\n", | |
261 | __FUNCTION__,reg, data); | |
262 | ||
b79cb653 ST |
263 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
264 | printk("%s: writelnbreg error (err == %i, reg == 0x%02x," | |
265 | " data == 0x%02x)\n", __FUNCTION__, err, reg, data); | |
266 | return -EREMOTEIO; | |
267 | } | |
268 | ||
269 | /* cache the write, no way to read back */ | |
270 | state->lnbreg = data; | |
271 | ||
272 | return 0; | |
273 | } | |
274 | ||
275 | static int cx24123_readreg(struct cx24123_state* state, u8 reg) | |
276 | { | |
277 | int ret; | |
278 | u8 b0[] = { reg }; | |
279 | u8 b1[] = { 0 }; | |
280 | struct i2c_msg msg[] = { | |
281 | { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, | |
282 | { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } | |
283 | }; | |
284 | ||
285 | ret = i2c_transfer(state->i2c, msg, 2); | |
286 | ||
287 | if (ret != 2) { | |
288 | printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret); | |
289 | return ret; | |
290 | } | |
291 | ||
caf970e0 MCC |
292 | if (debug>1) |
293 | printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret); | |
294 | ||
b79cb653 ST |
295 | return b1[0]; |
296 | } | |
297 | ||
298 | static int cx24123_readlnbreg(struct cx24123_state* state, u8 reg) | |
299 | { | |
300 | return state->lnbreg; | |
301 | } | |
302 | ||
303 | static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion) | |
304 | { | |
0e4558ab YP |
305 | u8 nom_reg = cx24123_readreg(state, 0x0e); |
306 | u8 auto_reg = cx24123_readreg(state, 0x10); | |
307 | ||
b79cb653 ST |
308 | switch (inversion) { |
309 | case INVERSION_OFF: | |
caf970e0 | 310 | dprintk("%s: inversion off\n",__FUNCTION__); |
0e4558ab YP |
311 | cx24123_writereg(state, 0x0e, nom_reg & ~0x80); |
312 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
313 | break; |
314 | case INVERSION_ON: | |
caf970e0 | 315 | dprintk("%s: inversion on\n",__FUNCTION__); |
0e4558ab YP |
316 | cx24123_writereg(state, 0x0e, nom_reg | 0x80); |
317 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
318 | break; |
319 | case INVERSION_AUTO: | |
caf970e0 | 320 | dprintk("%s: inversion auto\n",__FUNCTION__); |
0e4558ab | 321 | cx24123_writereg(state, 0x10, auto_reg & ~0x80); |
b79cb653 ST |
322 | break; |
323 | default: | |
324 | return -EINVAL; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
330 | static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion) | |
331 | { | |
332 | u8 val; | |
333 | ||
334 | val = cx24123_readreg(state, 0x1b) >> 7; | |
335 | ||
caf970e0 MCC |
336 | if (val == 0) { |
337 | dprintk("%s: read inversion off\n",__FUNCTION__); | |
e3b152bc | 338 | *inversion = INVERSION_OFF; |
caf970e0 MCC |
339 | } else { |
340 | dprintk("%s: read inversion on\n",__FUNCTION__); | |
e3b152bc | 341 | *inversion = INVERSION_ON; |
caf970e0 | 342 | } |
b79cb653 ST |
343 | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec) | |
348 | { | |
0e4558ab YP |
349 | u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; |
350 | ||
b79cb653 | 351 | if ( (fec < FEC_NONE) || (fec > FEC_AUTO) ) |
e3b152bc | 352 | fec = FEC_AUTO; |
b79cb653 | 353 | |
b79cb653 | 354 | switch (fec) { |
b79cb653 | 355 | case FEC_1_2: |
caf970e0 | 356 | dprintk("%s: set FEC to 1/2\n",__FUNCTION__); |
0e4558ab YP |
357 | cx24123_writereg(state, 0x0e, nom_reg | 0x01); |
358 | cx24123_writereg(state, 0x0f, 0x02); | |
359 | break; | |
b79cb653 | 360 | case FEC_2_3: |
caf970e0 | 361 | dprintk("%s: set FEC to 2/3\n",__FUNCTION__); |
0e4558ab YP |
362 | cx24123_writereg(state, 0x0e, nom_reg | 0x02); |
363 | cx24123_writereg(state, 0x0f, 0x04); | |
364 | break; | |
b79cb653 | 365 | case FEC_3_4: |
caf970e0 | 366 | dprintk("%s: set FEC to 3/4\n",__FUNCTION__); |
0e4558ab YP |
367 | cx24123_writereg(state, 0x0e, nom_reg | 0x03); |
368 | cx24123_writereg(state, 0x0f, 0x08); | |
369 | break; | |
370 | case FEC_4_5: | |
caf970e0 | 371 | dprintk("%s: set FEC to 4/5\n",__FUNCTION__); |
0e4558ab YP |
372 | cx24123_writereg(state, 0x0e, nom_reg | 0x04); |
373 | cx24123_writereg(state, 0x0f, 0x10); | |
374 | break; | |
375 | case FEC_5_6: | |
caf970e0 | 376 | dprintk("%s: set FEC to 5/6\n",__FUNCTION__); |
0e4558ab YP |
377 | cx24123_writereg(state, 0x0e, nom_reg | 0x05); |
378 | cx24123_writereg(state, 0x0f, 0x20); | |
379 | break; | |
380 | case FEC_6_7: | |
381 | dprintk("%s: set FEC to 6/7\n",__FUNCTION__); | |
382 | cx24123_writereg(state, 0x0e, nom_reg | 0x06); | |
383 | cx24123_writereg(state, 0x0f, 0x40); | |
384 | break; | |
385 | case FEC_7_8: | |
386 | dprintk("%s: set FEC to 7/8\n",__FUNCTION__); | |
387 | cx24123_writereg(state, 0x0e, nom_reg | 0x07); | |
388 | cx24123_writereg(state, 0x0f, 0x80); | |
389 | break; | |
b79cb653 | 390 | case FEC_AUTO: |
caf970e0 | 391 | dprintk("%s: set FEC to auto\n",__FUNCTION__); |
0e4558ab YP |
392 | cx24123_writereg(state, 0x0f, 0xfe); |
393 | break; | |
b79cb653 ST |
394 | default: |
395 | return -EOPNOTSUPP; | |
396 | } | |
0e4558ab YP |
397 | |
398 | return 0; | |
b79cb653 ST |
399 | } |
400 | ||
401 | static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec) | |
402 | { | |
e3b152bc | 403 | int ret; |
b79cb653 | 404 | |
e3b152bc JS |
405 | ret = cx24123_readreg (state, 0x1b); |
406 | if (ret < 0) | |
407 | return ret; | |
a74b51fc VC |
408 | ret = ret & 0x07; |
409 | ||
410 | switch (ret) { | |
b79cb653 | 411 | case 1: |
e3b152bc JS |
412 | *fec = FEC_1_2; |
413 | break; | |
a74b51fc | 414 | case 2: |
e3b152bc JS |
415 | *fec = FEC_2_3; |
416 | break; | |
a74b51fc | 417 | case 3: |
e3b152bc JS |
418 | *fec = FEC_3_4; |
419 | break; | |
a74b51fc | 420 | case 4: |
e3b152bc JS |
421 | *fec = FEC_4_5; |
422 | break; | |
a74b51fc | 423 | case 5: |
e3b152bc JS |
424 | *fec = FEC_5_6; |
425 | break; | |
a74b51fc VC |
426 | case 6: |
427 | *fec = FEC_6_7; | |
428 | break; | |
b79cb653 | 429 | case 7: |
e3b152bc JS |
430 | *fec = FEC_7_8; |
431 | break; | |
b79cb653 | 432 | default: |
0e4558ab YP |
433 | /* this can happen when there's no lock */ |
434 | *fec = FEC_NONE; | |
b79cb653 ST |
435 | } |
436 | ||
e3b152bc | 437 | return 0; |
b79cb653 ST |
438 | } |
439 | ||
0e4558ab YP |
440 | /* Approximation of closest integer of log2(a/b). It actually gives the |
441 | lowest integer i such that 2^i >= round(a/b) */ | |
442 | static u32 cx24123_int_log2(u32 a, u32 b) | |
443 | { | |
444 | u32 exp, nearest = 0; | |
445 | u32 div = a / b; | |
446 | if(a % b >= b / 2) ++div; | |
447 | if(div < (1 << 31)) | |
448 | { | |
449 | for(exp = 1; div > exp; nearest++) | |
450 | exp += exp; | |
451 | } | |
452 | return nearest; | |
453 | } | |
454 | ||
b79cb653 ST |
455 | static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate) |
456 | { | |
0e4558ab | 457 | u32 tmp, sample_rate, ratio, sample_gain; |
a74b51fc VC |
458 | u8 pll_mult; |
459 | ||
460 | /* check if symbol rate is within limits */ | |
461 | if ((srate > state->ops.info.symbol_rate_max) || | |
462 | (srate < state->ops.info.symbol_rate_min)) | |
463 | return -EOPNOTSUPP;; | |
464 | ||
465 | /* choose the sampling rate high enough for the required operation, | |
466 | while optimizing the power consumed by the demodulator */ | |
467 | if (srate < (XTAL*2)/2) | |
468 | pll_mult = 2; | |
469 | else if (srate < (XTAL*3)/2) | |
470 | pll_mult = 3; | |
471 | else if (srate < (XTAL*4)/2) | |
472 | pll_mult = 4; | |
473 | else if (srate < (XTAL*5)/2) | |
474 | pll_mult = 5; | |
475 | else if (srate < (XTAL*6)/2) | |
476 | pll_mult = 6; | |
477 | else if (srate < (XTAL*7)/2) | |
478 | pll_mult = 7; | |
479 | else if (srate < (XTAL*8)/2) | |
480 | pll_mult = 8; | |
481 | else | |
482 | pll_mult = 9; | |
483 | ||
484 | ||
485 | sample_rate = pll_mult * XTAL; | |
b79cb653 | 486 | |
a74b51fc VC |
487 | /* |
488 | SYSSymbolRate[21:0] = (srate << 23) / sample_rate | |
b79cb653 | 489 | |
a74b51fc VC |
490 | We have to use 32 bit unsigned arithmetic without precision loss. |
491 | The maximum srate is 45000000 or 0x02AEA540. This number has | |
492 | only 6 clear bits on top, hence we can shift it left only 6 bits | |
493 | at a time. Borrowed from cx24110.c | |
494 | */ | |
b79cb653 | 495 | |
a74b51fc VC |
496 | tmp = srate << 6; |
497 | ratio = tmp / sample_rate; | |
498 | ||
499 | tmp = (tmp % sample_rate) << 6; | |
500 | ratio = (ratio << 6) + (tmp / sample_rate); | |
501 | ||
502 | tmp = (tmp % sample_rate) << 6; | |
503 | ratio = (ratio << 6) + (tmp / sample_rate); | |
504 | ||
505 | tmp = (tmp % sample_rate) << 5; | |
506 | ratio = (ratio << 5) + (tmp / sample_rate); | |
507 | ||
508 | ||
509 | cx24123_writereg(state, 0x01, pll_mult * 6); | |
510 | ||
511 | cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f ); | |
512 | cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff ); | |
513 | cx24123_writereg(state, 0x0a, (ratio ) & 0xff ); | |
514 | ||
0e4558ab YP |
515 | /* also set the demodulator sample gain */ |
516 | sample_gain = cx24123_int_log2(sample_rate, srate); | |
517 | tmp = cx24123_readreg(state, 0x0c) & ~0xe0; | |
518 | cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); | |
519 | ||
520 | dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain); | |
b79cb653 ST |
521 | |
522 | return 0; | |
523 | } | |
524 | ||
525 | /* | |
526 | * Based on the required frequency and symbolrate, the tuner AGC has to be configured | |
527 | * and the correct band selected. Calculate those values | |
528 | */ | |
529 | static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
530 | { | |
531 | struct cx24123_state *state = fe->demodulator_priv; | |
e3b152bc JS |
532 | u32 ndiv = 0, adiv = 0, vco_div = 0; |
533 | int i = 0; | |
a74b51fc | 534 | int pump = 2; |
70047f9c YP |
535 | int band = 0; |
536 | int num_bands = sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); | |
b79cb653 ST |
537 | |
538 | /* Defaults for low freq, low rate */ | |
539 | state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; | |
540 | state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; | |
541 | state->bandselectarg = cx24123_bandselect_vals[0].progdata; | |
542 | vco_div = cx24123_bandselect_vals[0].VCOdivider; | |
543 | ||
a74b51fc | 544 | /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */ |
e3b152bc | 545 | for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++) |
b79cb653 ST |
546 | { |
547 | if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) && | |
a74b51fc | 548 | (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) { |
b79cb653 ST |
549 | state->VCAarg = cx24123_AGC_vals[i].VCAprogdata; |
550 | state->VGAarg = cx24123_AGC_vals[i].VGAprogdata; | |
a74b51fc | 551 | state->FILTune = cx24123_AGC_vals[i].FILTune; |
b79cb653 ST |
552 | } |
553 | } | |
554 | ||
70047f9c YP |
555 | /* determine the band to use */ |
556 | if(force_band < 1 || force_band > num_bands) | |
b79cb653 | 557 | { |
70047f9c YP |
558 | for (i = 0; i < num_bands; i++) |
559 | { | |
560 | if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) && | |
561 | (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) | |
562 | band = i; | |
b79cb653 ST |
563 | } |
564 | } | |
70047f9c YP |
565 | else |
566 | band = force_band - 1; | |
567 | ||
568 | state->bandselectarg = cx24123_bandselect_vals[band].progdata; | |
569 | vco_div = cx24123_bandselect_vals[band].VCOdivider; | |
570 | ||
571 | /* determine the charge pump current */ | |
572 | if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 ) | |
573 | pump = 0x01; | |
574 | else | |
575 | pump = 0x02; | |
b79cb653 ST |
576 | |
577 | /* Determine the N/A dividers for the requested lband freq (in kHz). */ | |
a74b51fc VC |
578 | /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */ |
579 | ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff; | |
580 | adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f; | |
b79cb653 ST |
581 | |
582 | if (adiv == 0) | |
a74b51fc | 583 | ndiv++; |
b79cb653 | 584 | |
a74b51fc VC |
585 | /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */ |
586 | state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv; | |
b79cb653 ST |
587 | |
588 | return 0; | |
589 | } | |
590 | ||
591 | /* | |
592 | * Tuner data is 21 bits long, must be left-aligned in data. | |
593 | * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip. | |
594 | */ | |
595 | static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data) | |
596 | { | |
597 | struct cx24123_state *state = fe->demodulator_priv; | |
0144f314 | 598 | unsigned long timeout; |
b79cb653 | 599 | |
caf970e0 MCC |
600 | dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data); |
601 | ||
b79cb653 ST |
602 | /* align the 21 bytes into to bit23 boundary */ |
603 | data = data << 3; | |
604 | ||
605 | /* Reset the demod pll word length to 0x15 bits */ | |
606 | cx24123_writereg(state, 0x21, 0x15); | |
607 | ||
b79cb653 | 608 | /* write the msb 8 bits, wait for the send to be completed */ |
0144f314 | 609 | timeout = jiffies + msecs_to_jiffies(40); |
e3b152bc | 610 | cx24123_writereg(state, 0x22, (data >> 16) & 0xff); |
0144f314 ST |
611 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
612 | if (time_after(jiffies, timeout)) { | |
613 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
614 | return -EREMOTEIO; |
615 | } | |
0144f314 | 616 | msleep(10); |
b79cb653 ST |
617 | } |
618 | ||
b79cb653 | 619 | /* send another 8 bytes, wait for the send to be completed */ |
0144f314 | 620 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 621 | cx24123_writereg(state, 0x22, (data>>8) & 0xff ); |
0144f314 ST |
622 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
623 | if (time_after(jiffies, timeout)) { | |
624 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
625 | return -EREMOTEIO; |
626 | } | |
0144f314 | 627 | msleep(10); |
b79cb653 ST |
628 | } |
629 | ||
b79cb653 | 630 | /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */ |
0144f314 | 631 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 632 | cx24123_writereg(state, 0x22, (data) & 0xff ); |
0144f314 ST |
633 | while ((cx24123_readreg(state, 0x20) & 0x80)) { |
634 | if (time_after(jiffies, timeout)) { | |
635 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
636 | return -EREMOTEIO; |
637 | } | |
0144f314 | 638 | msleep(10); |
b79cb653 ST |
639 | } |
640 | ||
641 | /* Trigger the demod to configure the tuner */ | |
642 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); | |
643 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
649 | { | |
650 | struct cx24123_state *state = fe->demodulator_priv; | |
a74b51fc VC |
651 | u8 val; |
652 | ||
653 | dprintk("frequency=%i\n", p->frequency); | |
b79cb653 | 654 | |
e3b152bc | 655 | if (cx24123_pll_calculate(fe, p) != 0) { |
b79cb653 ST |
656 | printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__); |
657 | return -EINVAL; | |
658 | } | |
659 | ||
660 | /* Write the new VCO/VGA */ | |
661 | cx24123_pll_writereg(fe, p, state->VCAarg); | |
662 | cx24123_pll_writereg(fe, p, state->VGAarg); | |
663 | ||
664 | /* Write the new bandselect and pll args */ | |
665 | cx24123_pll_writereg(fe, p, state->bandselectarg); | |
666 | cx24123_pll_writereg(fe, p, state->pllarg); | |
667 | ||
a74b51fc VC |
668 | /* set the FILTUNE voltage */ |
669 | val = cx24123_readreg(state, 0x28) & ~0x3; | |
670 | cx24123_writereg(state, 0x27, state->FILTune >> 2); | |
671 | cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); | |
672 | ||
caf970e0 MCC |
673 | dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg, |
674 | state->bandselectarg,state->pllarg); | |
675 | ||
b79cb653 ST |
676 | return 0; |
677 | } | |
678 | ||
679 | static int cx24123_initfe(struct dvb_frontend* fe) | |
680 | { | |
681 | struct cx24123_state *state = fe->demodulator_priv; | |
682 | int i; | |
683 | ||
caf970e0 MCC |
684 | dprintk("%s: init frontend\n",__FUNCTION__); |
685 | ||
b79cb653 | 686 | /* Configure the demod to a good set of defaults */ |
e3b152bc | 687 | for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++) |
b79cb653 ST |
688 | cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data); |
689 | ||
b79cb653 | 690 | /* Configure the LNB for 14V */ |
1c956a3a VC |
691 | if (state->config->use_isl6421) |
692 | cx24123_writelnbreg(state, 0x0, 0x2a); | |
b79cb653 ST |
693 | |
694 | return 0; | |
695 | } | |
696 | ||
697 | static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage) | |
698 | { | |
699 | struct cx24123_state *state = fe->demodulator_priv; | |
700 | u8 val; | |
701 | ||
1c956a3a | 702 | switch (state->config->use_isl6421) { |
b79cb653 | 703 | |
1c956a3a VC |
704 | case 1: |
705 | ||
706 | val = cx24123_readlnbreg(state, 0x0); | |
707 | ||
708 | switch (voltage) { | |
709 | case SEC_VOLTAGE_13: | |
caf970e0 | 710 | dprintk("%s: isl6421 voltage = 13V\n",__FUNCTION__); |
1c956a3a VC |
711 | return cx24123_writelnbreg(state, 0x0, val & 0x32); /* V 13v */ |
712 | case SEC_VOLTAGE_18: | |
caf970e0 | 713 | dprintk("%s: isl6421 voltage = 18V\n",__FUNCTION__); |
1c956a3a VC |
714 | return cx24123_writelnbreg(state, 0x0, val | 0x04); /* H 18v */ |
715 | case SEC_VOLTAGE_OFF: | |
caf970e0 | 716 | dprintk("%s: isl5421 voltage off\n",__FUNCTION__); |
1c956a3a VC |
717 | return cx24123_writelnbreg(state, 0x0, val & 0x30); |
718 | default: | |
719 | return -EINVAL; | |
720 | }; | |
721 | ||
722 | case 0: | |
723 | ||
724 | val = cx24123_readreg(state, 0x29); | |
725 | ||
726 | switch (voltage) { | |
727 | case SEC_VOLTAGE_13: | |
728 | dprintk("%s: setting voltage 13V\n", __FUNCTION__); | |
729 | if (state->config->enable_lnb_voltage) | |
730 | state->config->enable_lnb_voltage(fe, 1); | |
731 | return cx24123_writereg(state, 0x29, val | 0x80); | |
732 | case SEC_VOLTAGE_18: | |
733 | dprintk("%s: setting voltage 18V\n", __FUNCTION__); | |
734 | if (state->config->enable_lnb_voltage) | |
735 | state->config->enable_lnb_voltage(fe, 1); | |
736 | return cx24123_writereg(state, 0x29, val & 0x7f); | |
737 | case SEC_VOLTAGE_OFF: | |
738 | dprintk("%s: setting voltage off\n", __FUNCTION__); | |
739 | if (state->config->enable_lnb_voltage) | |
740 | state->config->enable_lnb_voltage(fe, 0); | |
741 | return 0; | |
742 | default: | |
743 | return -EINVAL; | |
744 | }; | |
745 | } | |
746 | ||
747 | return 0; | |
b79cb653 ST |
748 | } |
749 | ||
dce1dfc2 YP |
750 | /* wait for diseqc queue to become ready (or timeout) */ |
751 | static void cx24123_wait_for_diseqc(struct cx24123_state *state) | |
752 | { | |
753 | unsigned long timeout = jiffies + msecs_to_jiffies(200); | |
754 | while (!(cx24123_readreg(state, 0x29) & 0x40)) { | |
755 | if(time_after(jiffies, timeout)) { | |
756 | printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__); | |
757 | break; | |
758 | } | |
759 | msleep(10); | |
760 | } | |
761 | } | |
762 | ||
a74b51fc | 763 | static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd) |
b79cb653 | 764 | { |
a74b51fc VC |
765 | struct cx24123_state *state = fe->demodulator_priv; |
766 | int i, val; | |
a74b51fc VC |
767 | |
768 | dprintk("%s:\n",__FUNCTION__); | |
b79cb653 | 769 | |
dce1dfc2 | 770 | /* check if continuous tone has been stopped */ |
a74b51fc VC |
771 | if (state->config->use_isl6421) |
772 | val = cx24123_readlnbreg(state, 0x00) & 0x10; | |
773 | else | |
774 | val = cx24123_readreg(state, 0x29) & 0x10; | |
775 | ||
776 | ||
777 | if (val) { | |
778 | printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__); | |
779 | return -ENOTSUPP; | |
780 | } | |
781 | ||
dce1dfc2 YP |
782 | /* wait for diseqc queue ready */ |
783 | cx24123_wait_for_diseqc(state); | |
784 | ||
a74b51fc VC |
785 | /* select tone mode */ |
786 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xf8); | |
787 | ||
788 | for (i = 0; i < cmd->msg_len; i++) | |
789 | cx24123_writereg(state, 0x2C + i, cmd->msg[i]); | |
790 | ||
791 | val = cx24123_readreg(state, 0x29); | |
792 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); | |
793 | ||
dce1dfc2 YP |
794 | /* wait for diseqc message to finish sending */ |
795 | cx24123_wait_for_diseqc(state); | |
a74b51fc VC |
796 | |
797 | return 0; | |
798 | } | |
799 | ||
800 | static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) | |
801 | { | |
802 | struct cx24123_state *state = fe->demodulator_priv; | |
803 | int val; | |
a74b51fc VC |
804 | |
805 | dprintk("%s:\n", __FUNCTION__); | |
806 | ||
807 | /* check if continuous tone has been stoped */ | |
808 | if (state->config->use_isl6421) | |
809 | val = cx24123_readlnbreg(state, 0x00) & 0x10; | |
810 | else | |
811 | val = cx24123_readreg(state, 0x29) & 0x10; | |
812 | ||
813 | ||
814 | if (val) { | |
815 | printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__); | |
816 | return -ENOTSUPP; | |
817 | } | |
818 | ||
dce1dfc2 YP |
819 | cx24123_wait_for_diseqc(state); |
820 | ||
a74b51fc VC |
821 | /* select tone mode */ |
822 | val = cx24123_readreg(state, 0x2a) & 0xf8; | |
823 | cx24123_writereg(state, 0x2a, val | 0x04); | |
824 | ||
825 | val = cx24123_readreg(state, 0x29); | |
826 | ||
827 | if (burst == SEC_MINI_A) | |
828 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); | |
829 | else if (burst == SEC_MINI_B) | |
830 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); | |
831 | else | |
832 | return -EINVAL; | |
833 | ||
dce1dfc2 | 834 | cx24123_wait_for_diseqc(state); |
a74b51fc VC |
835 | |
836 | return 0; | |
b79cb653 ST |
837 | } |
838 | ||
839 | static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status) | |
840 | { | |
841 | struct cx24123_state *state = fe->demodulator_priv; | |
842 | ||
843 | int sync = cx24123_readreg(state, 0x14); | |
844 | int lock = cx24123_readreg(state, 0x20); | |
845 | ||
846 | *status = 0; | |
847 | if (lock & 0x01) | |
a74b51fc VC |
848 | *status |= FE_HAS_SIGNAL; |
849 | if (sync & 0x02) | |
850 | *status |= FE_HAS_CARRIER; | |
b79cb653 ST |
851 | if (sync & 0x04) |
852 | *status |= FE_HAS_VITERBI; | |
853 | if (sync & 0x08) | |
a74b51fc | 854 | *status |= FE_HAS_SYNC; |
b79cb653 | 855 | if (sync & 0x80) |
a74b51fc | 856 | *status |= FE_HAS_LOCK; |
b79cb653 ST |
857 | |
858 | return 0; | |
859 | } | |
860 | ||
861 | /* | |
862 | * Configured to return the measurement of errors in blocks, because no UCBLOCKS value | |
863 | * is available, so this value doubles up to satisfy both measurements | |
864 | */ | |
865 | static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber) | |
866 | { | |
867 | struct cx24123_state *state = fe->demodulator_priv; | |
868 | ||
869 | state->lastber = | |
870 | ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | | |
871 | (cx24123_readreg(state, 0x1d) << 8 | | |
872 | cx24123_readreg(state, 0x1e)); | |
873 | ||
874 | /* Do the signal quality processing here, it's derived from the BER. */ | |
875 | /* Scale the BER from a 24bit to a SNR 16 bit where higher = better */ | |
876 | if (state->lastber < 5000) | |
877 | state->snr = 655*100; | |
878 | else if ( (state->lastber >= 5000) && (state->lastber < 55000) ) | |
879 | state->snr = 655*90; | |
880 | else if ( (state->lastber >= 55000) && (state->lastber < 150000) ) | |
881 | state->snr = 655*80; | |
882 | else if ( (state->lastber >= 150000) && (state->lastber < 250000) ) | |
883 | state->snr = 655*70; | |
884 | else if ( (state->lastber >= 250000) && (state->lastber < 450000) ) | |
885 | state->snr = 655*65; | |
886 | else | |
887 | state->snr = 0; | |
888 | ||
caf970e0 MCC |
889 | dprintk("%s: BER = %d, S/N index = %d\n",__FUNCTION__,state->lastber, state->snr); |
890 | ||
b79cb653 ST |
891 | *ber = state->lastber; |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
896 | static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength) | |
897 | { | |
898 | struct cx24123_state *state = fe->demodulator_priv; | |
899 | *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */ | |
900 | ||
caf970e0 MCC |
901 | dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength); |
902 | ||
b79cb653 ST |
903 | return 0; |
904 | } | |
905 | ||
906 | static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr) | |
907 | { | |
908 | struct cx24123_state *state = fe->demodulator_priv; | |
909 | *snr = state->snr; | |
910 | ||
caf970e0 MCC |
911 | dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr); |
912 | ||
b79cb653 ST |
913 | return 0; |
914 | } | |
915 | ||
916 | static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) | |
917 | { | |
918 | struct cx24123_state *state = fe->demodulator_priv; | |
919 | *ucblocks = state->lastber; | |
920 | ||
caf970e0 MCC |
921 | dprintk("%s: ucblocks (ber) = %d\n",__FUNCTION__,*ucblocks); |
922 | ||
b79cb653 ST |
923 | return 0; |
924 | } | |
925 | ||
926 | static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
927 | { | |
928 | struct cx24123_state *state = fe->demodulator_priv; | |
929 | ||
caf970e0 MCC |
930 | dprintk("%s: set_frontend\n",__FUNCTION__); |
931 | ||
b79cb653 ST |
932 | if (state->config->set_ts_params) |
933 | state->config->set_ts_params(fe, 0); | |
934 | ||
935 | state->currentfreq=p->frequency; | |
e3b152bc | 936 | state->currentsymbolrate = p->u.qpsk.symbol_rate; |
b79cb653 ST |
937 | |
938 | cx24123_set_inversion(state, p->inversion); | |
939 | cx24123_set_fec(state, p->u.qpsk.fec_inner); | |
940 | cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate); | |
941 | cx24123_pll_tune(fe, p); | |
942 | ||
943 | /* Enable automatic aquisition and reset cycle */ | |
e3b152bc | 944 | cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); |
b79cb653 ST |
945 | cx24123_writereg(state, 0x00, 0x10); |
946 | cx24123_writereg(state, 0x00, 0); | |
947 | ||
948 | return 0; | |
949 | } | |
950 | ||
951 | static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
952 | { | |
953 | struct cx24123_state *state = fe->demodulator_priv; | |
954 | ||
caf970e0 MCC |
955 | dprintk("%s: get_frontend\n",__FUNCTION__); |
956 | ||
b79cb653 ST |
957 | if (cx24123_get_inversion(state, &p->inversion) != 0) { |
958 | printk("%s: Failed to get inversion status\n",__FUNCTION__); | |
959 | return -EREMOTEIO; | |
960 | } | |
961 | if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) { | |
962 | printk("%s: Failed to get fec status\n",__FUNCTION__); | |
963 | return -EREMOTEIO; | |
964 | } | |
965 | p->frequency = state->currentfreq; | |
966 | p->u.qpsk.symbol_rate = state->currentsymbolrate; | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
971 | static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) | |
972 | { | |
973 | struct cx24123_state *state = fe->demodulator_priv; | |
974 | u8 val; | |
975 | ||
1c956a3a VC |
976 | switch (state->config->use_isl6421) { |
977 | case 1: | |
978 | ||
979 | val = cx24123_readlnbreg(state, 0x0); | |
b79cb653 | 980 | |
1c956a3a VC |
981 | switch (tone) { |
982 | case SEC_TONE_ON: | |
caf970e0 | 983 | dprintk("%s: isl6421 sec tone on\n",__FUNCTION__); |
1c956a3a VC |
984 | return cx24123_writelnbreg(state, 0x0, val | 0x10); |
985 | case SEC_TONE_OFF: | |
caf970e0 | 986 | dprintk("%s: isl6421 sec tone off\n",__FUNCTION__); |
1c956a3a VC |
987 | return cx24123_writelnbreg(state, 0x0, val & 0x2f); |
988 | default: | |
989 | printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone); | |
990 | return -EINVAL; | |
991 | } | |
992 | ||
993 | case 0: | |
994 | ||
995 | val = cx24123_readreg(state, 0x29); | |
996 | ||
997 | switch (tone) { | |
998 | case SEC_TONE_ON: | |
999 | dprintk("%s: setting tone on\n", __FUNCTION__); | |
1000 | return cx24123_writereg(state, 0x29, val | 0x10); | |
1001 | case SEC_TONE_OFF: | |
1002 | dprintk("%s: setting tone off\n",__FUNCTION__); | |
1003 | return cx24123_writereg(state, 0x29, val & 0xef); | |
1004 | default: | |
1005 | printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone); | |
1006 | return -EINVAL; | |
1007 | } | |
b79cb653 | 1008 | } |
1c956a3a VC |
1009 | |
1010 | return 0; | |
b79cb653 ST |
1011 | } |
1012 | ||
1013 | static void cx24123_release(struct dvb_frontend* fe) | |
1014 | { | |
1015 | struct cx24123_state* state = fe->demodulator_priv; | |
1016 | dprintk("%s\n",__FUNCTION__); | |
1017 | kfree(state); | |
1018 | } | |
1019 | ||
1020 | static struct dvb_frontend_ops cx24123_ops; | |
1021 | ||
e3b152bc JS |
1022 | struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, |
1023 | struct i2c_adapter* i2c) | |
b79cb653 ST |
1024 | { |
1025 | struct cx24123_state* state = NULL; | |
1026 | int ret; | |
1027 | ||
1028 | dprintk("%s\n",__FUNCTION__); | |
1029 | ||
1030 | /* allocate memory for the internal state */ | |
1031 | state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL); | |
1032 | if (state == NULL) { | |
1033 | printk("Unable to kmalloc\n"); | |
1034 | goto error; | |
1035 | } | |
1036 | ||
1037 | /* setup the state */ | |
1038 | state->config = config; | |
1039 | state->i2c = i2c; | |
1040 | memcpy(&state->ops, &cx24123_ops, sizeof(struct dvb_frontend_ops)); | |
1041 | state->lastber = 0; | |
1042 | state->snr = 0; | |
1043 | state->lnbreg = 0; | |
1044 | state->VCAarg = 0; | |
1045 | state->VGAarg = 0; | |
1046 | state->bandselectarg = 0; | |
1047 | state->pllarg = 0; | |
1048 | state->currentfreq = 0; | |
1049 | state->currentsymbolrate = 0; | |
1050 | ||
1051 | /* check if the demod is there */ | |
1052 | ret = cx24123_readreg(state, 0x00); | |
1053 | if ((ret != 0xd1) && (ret != 0xe1)) { | |
1054 | printk("Version != d1 or e1\n"); | |
1055 | goto error; | |
1056 | } | |
1057 | ||
1058 | /* create dvb_frontend */ | |
1059 | state->frontend.ops = &state->ops; | |
1060 | state->frontend.demodulator_priv = state; | |
1061 | return &state->frontend; | |
1062 | ||
1063 | error: | |
1064 | kfree(state); | |
1065 | ||
1066 | return NULL; | |
1067 | } | |
1068 | ||
1069 | static struct dvb_frontend_ops cx24123_ops = { | |
1070 | ||
1071 | .info = { | |
1072 | .name = "Conexant CX24123/CX24109", | |
1073 | .type = FE_QPSK, | |
1074 | .frequency_min = 950000, | |
1075 | .frequency_max = 2150000, | |
1076 | .frequency_stepsize = 1011, /* kHz for QPSK frontends */ | |
0e4558ab | 1077 | .frequency_tolerance = 5000, |
b79cb653 ST |
1078 | .symbol_rate_min = 1000000, |
1079 | .symbol_rate_max = 45000000, | |
1080 | .caps = FE_CAN_INVERSION_AUTO | | |
1081 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
0e4558ab YP |
1082 | FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | |
1083 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
b79cb653 ST |
1084 | FE_CAN_QPSK | FE_CAN_RECOVER |
1085 | }, | |
1086 | ||
1087 | .release = cx24123_release, | |
1088 | ||
1089 | .init = cx24123_initfe, | |
1090 | .set_frontend = cx24123_set_frontend, | |
1091 | .get_frontend = cx24123_get_frontend, | |
1092 | .read_status = cx24123_read_status, | |
1093 | .read_ber = cx24123_read_ber, | |
1094 | .read_signal_strength = cx24123_read_signal_strength, | |
1095 | .read_snr = cx24123_read_snr, | |
1096 | .read_ucblocks = cx24123_read_ucblocks, | |
1097 | .diseqc_send_master_cmd = cx24123_send_diseqc_msg, | |
a74b51fc | 1098 | .diseqc_send_burst = cx24123_diseqc_send_burst, |
b79cb653 ST |
1099 | .set_tone = cx24123_set_tone, |
1100 | .set_voltage = cx24123_set_voltage, | |
1101 | }; | |
1102 | ||
1103 | module_param(debug, int, 0644); | |
caf970e0 | 1104 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); |
b79cb653 | 1105 | |
70047f9c YP |
1106 | module_param(force_band, int, 0644); |
1107 | MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off)."); | |
1108 | ||
b79cb653 ST |
1109 | MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware"); |
1110 | MODULE_AUTHOR("Steven Toth"); | |
1111 | MODULE_LICENSE("GPL"); | |
1112 | ||
1113 | EXPORT_SYMBOL(cx24123_attach); |