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Commit | Line | Data |
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b79cb653 ST |
1 | /* |
2 | Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver | |
3 | ||
4 | Copyright (C) 2005 Steven Toth <stoth@hauppauge.com> | |
5 | ||
1c956a3a VC |
6 | Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc> |
7 | ||
b79cb653 ST |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #include <linux/slab.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/module.h> | |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/init.h> | |
28 | ||
29 | #include "dvb_frontend.h" | |
30 | #include "cx24123.h" | |
31 | ||
a74b51fc VC |
32 | #define XTAL 10111000 |
33 | ||
70047f9c | 34 | static int force_band; |
b79cb653 ST |
35 | static int debug; |
36 | #define dprintk(args...) \ | |
37 | do { \ | |
38 | if (debug) printk (KERN_DEBUG "cx24123: " args); \ | |
39 | } while (0) | |
40 | ||
e3b152bc JS |
41 | struct cx24123_state |
42 | { | |
b79cb653 | 43 | struct i2c_adapter* i2c; |
b79cb653 ST |
44 | const struct cx24123_config* config; |
45 | ||
46 | struct dvb_frontend frontend; | |
47 | ||
48 | u32 lastber; | |
49 | u16 snr; | |
b79cb653 ST |
50 | |
51 | /* Some PLL specifics for tuning */ | |
52 | u32 VCAarg; | |
53 | u32 VGAarg; | |
54 | u32 bandselectarg; | |
55 | u32 pllarg; | |
a74b51fc | 56 | u32 FILTune; |
b79cb653 ST |
57 | |
58 | /* The Demod/Tuner can't easily provide these, we cache them */ | |
59 | u32 currentfreq; | |
60 | u32 currentsymbolrate; | |
61 | }; | |
62 | ||
e3b152bc JS |
63 | /* Various tuner defaults need to be established for a given symbol rate Sps */ |
64 | static struct | |
65 | { | |
66 | u32 symbolrate_low; | |
67 | u32 symbolrate_high; | |
e3b152bc JS |
68 | u32 VCAprogdata; |
69 | u32 VGAprogdata; | |
a74b51fc | 70 | u32 FILTune; |
e3b152bc JS |
71 | } cx24123_AGC_vals[] = |
72 | { | |
73 | { | |
74 | .symbolrate_low = 1000000, | |
75 | .symbolrate_high = 4999999, | |
a74b51fc VC |
76 | /* the specs recommend other values for VGA offsets, |
77 | but tests show they are wrong */ | |
0e4558ab YP |
78 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
79 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x07, | |
80 | .FILTune = 0x27f /* 0.41 V */ | |
e3b152bc JS |
81 | }, |
82 | { | |
83 | .symbolrate_low = 5000000, | |
84 | .symbolrate_high = 14999999, | |
0e4558ab YP |
85 | .VGAprogdata = (1 << 19) | (0x180 << 9) | 0x1e0, |
86 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x1f, | |
a74b51fc | 87 | .FILTune = 0x317 /* 0.90 V */ |
e3b152bc JS |
88 | }, |
89 | { | |
90 | .symbolrate_low = 15000000, | |
91 | .symbolrate_high = 45000000, | |
0e4558ab YP |
92 | .VGAprogdata = (1 << 19) | (0x100 << 9) | 0x180, |
93 | .VCAprogdata = (2 << 19) | (0x07 << 9) | 0x3f, | |
94 | .FILTune = 0x145 /* 2.70 V */ | |
e3b152bc JS |
95 | }, |
96 | }; | |
97 | ||
98 | /* | |
99 | * Various tuner defaults need to be established for a given frequency kHz. | |
100 | * fixme: The bounds on the bands do not match the doc in real life. | |
101 | * fixme: Some of them have been moved, other might need adjustment. | |
102 | */ | |
103 | static struct | |
104 | { | |
105 | u32 freq_low; | |
106 | u32 freq_high; | |
e3b152bc | 107 | u32 VCOdivider; |
e3b152bc JS |
108 | u32 progdata; |
109 | } cx24123_bandselect_vals[] = | |
110 | { | |
70047f9c | 111 | /* band 1 */ |
e3b152bc JS |
112 | { |
113 | .freq_low = 950000, | |
e3b152bc | 114 | .freq_high = 1074999, |
e3b152bc | 115 | .VCOdivider = 4, |
70047f9c | 116 | .progdata = (0 << 19) | (0 << 9) | 0x40, |
e3b152bc | 117 | }, |
70047f9c YP |
118 | |
119 | /* band 2 */ | |
e3b152bc JS |
120 | { |
121 | .freq_low = 1075000, | |
70047f9c YP |
122 | .freq_high = 1177999, |
123 | .VCOdivider = 4, | |
124 | .progdata = (0 << 19) | (0 << 9) | 0x80, | |
e3b152bc | 125 | }, |
70047f9c YP |
126 | |
127 | /* band 3 */ | |
e3b152bc | 128 | { |
70047f9c YP |
129 | .freq_low = 1178000, |
130 | .freq_high = 1295999, | |
e3b152bc | 131 | .VCOdivider = 2, |
70047f9c | 132 | .progdata = (0 << 19) | (1 << 9) | 0x01, |
e3b152bc | 133 | }, |
70047f9c YP |
134 | |
135 | /* band 4 */ | |
e3b152bc | 136 | { |
70047f9c YP |
137 | .freq_low = 1296000, |
138 | .freq_high = 1431999, | |
e3b152bc | 139 | .VCOdivider = 2, |
70047f9c | 140 | .progdata = (0 << 19) | (1 << 9) | 0x02, |
e3b152bc | 141 | }, |
70047f9c YP |
142 | |
143 | /* band 5 */ | |
e3b152bc | 144 | { |
70047f9c YP |
145 | .freq_low = 1432000, |
146 | .freq_high = 1575999, | |
e3b152bc | 147 | .VCOdivider = 2, |
70047f9c | 148 | .progdata = (0 << 19) | (1 << 9) | 0x04, |
e3b152bc | 149 | }, |
70047f9c YP |
150 | |
151 | /* band 6 */ | |
e3b152bc | 152 | { |
70047f9c | 153 | .freq_low = 1576000, |
e3b152bc | 154 | .freq_high = 1717999, |
e3b152bc | 155 | .VCOdivider = 2, |
70047f9c | 156 | .progdata = (0 << 19) | (1 << 9) | 0x08, |
e3b152bc | 157 | }, |
70047f9c YP |
158 | |
159 | /* band 7 */ | |
e3b152bc JS |
160 | { |
161 | .freq_low = 1718000, | |
162 | .freq_high = 1855999, | |
e3b152bc | 163 | .VCOdivider = 2, |
70047f9c | 164 | .progdata = (0 << 19) | (1 << 9) | 0x10, |
e3b152bc | 165 | }, |
70047f9c YP |
166 | |
167 | /* band 8 */ | |
e3b152bc JS |
168 | { |
169 | .freq_low = 1856000, | |
170 | .freq_high = 2035999, | |
e3b152bc | 171 | .VCOdivider = 2, |
70047f9c | 172 | .progdata = (0 << 19) | (1 << 9) | 0x20, |
e3b152bc | 173 | }, |
70047f9c YP |
174 | |
175 | /* band 9 */ | |
e3b152bc JS |
176 | { |
177 | .freq_low = 2036000, | |
70047f9c | 178 | .freq_high = 2150000, |
e3b152bc | 179 | .VCOdivider = 2, |
70047f9c | 180 | .progdata = (0 << 19) | (1 << 9) | 0x40, |
e3b152bc JS |
181 | }, |
182 | }; | |
183 | ||
b79cb653 ST |
184 | static struct { |
185 | u8 reg; | |
186 | u8 data; | |
187 | } cx24123_regdata[] = | |
188 | { | |
189 | {0x00, 0x03}, /* Reset system */ | |
190 | {0x00, 0x00}, /* Clear reset */ | |
0e4558ab YP |
191 | {0x03, 0x07}, /* QPSK, DVB, Auto Acquisition (default) */ |
192 | {0x04, 0x10}, /* MPEG */ | |
193 | {0x05, 0x04}, /* MPEG */ | |
194 | {0x06, 0x31}, /* MPEG (default) */ | |
195 | {0x0b, 0x00}, /* Freq search start point (default) */ | |
196 | {0x0c, 0x00}, /* Demodulator sample gain (default) */ | |
197 | {0x0d, 0x02}, /* Frequency search range = Fsymbol / 4 (default) */ | |
198 | {0x0e, 0x03}, /* Default non-inverted, FEC 3/4 (default) */ | |
199 | {0x0f, 0xfe}, /* FEC search mask (all supported codes) */ | |
200 | {0x10, 0x01}, /* Default search inversion, no repeat (default) */ | |
201 | {0x16, 0x00}, /* Enable reading of frequency */ | |
202 | {0x17, 0x01}, /* Enable EsNO Ready Counter */ | |
203 | {0x1c, 0x80}, /* Enable error counter */ | |
204 | {0x20, 0x00}, /* Tuner burst clock rate = 500KHz */ | |
205 | {0x21, 0x15}, /* Tuner burst mode, word length = 0x15 */ | |
206 | {0x28, 0x00}, /* Enable FILTERV with positive pol., DiSEqC 2.x off */ | |
207 | {0x29, 0x00}, /* DiSEqC LNB_DC off */ | |
208 | {0x2a, 0xb0}, /* DiSEqC Parameters (default) */ | |
209 | {0x2b, 0x73}, /* DiSEqC Tone Frequency (default) */ | |
210 | {0x2c, 0x00}, /* DiSEqC Message (0x2c - 0x31) */ | |
b79cb653 ST |
211 | {0x2d, 0x00}, |
212 | {0x2e, 0x00}, | |
213 | {0x2f, 0x00}, | |
214 | {0x30, 0x00}, | |
215 | {0x31, 0x00}, | |
0e4558ab YP |
216 | {0x32, 0x8c}, /* DiSEqC Parameters (default) */ |
217 | {0x33, 0x00}, /* Interrupts off (0x33 - 0x34) */ | |
b79cb653 | 218 | {0x34, 0x00}, |
0e4558ab YP |
219 | {0x35, 0x03}, /* DiSEqC Tone Amplitude (default) */ |
220 | {0x36, 0x02}, /* DiSEqC Parameters (default) */ | |
221 | {0x37, 0x3a}, /* DiSEqC Parameters (default) */ | |
222 | {0x3a, 0x00}, /* Enable AGC accumulator (for signal strength) */ | |
223 | {0x44, 0x00}, /* Constellation (default) */ | |
224 | {0x45, 0x00}, /* Symbol count (default) */ | |
225 | {0x46, 0x0d}, /* Symbol rate estimator on (default) */ | |
226 | {0x56, 0x41}, /* Various (default) */ | |
227 | {0x57, 0xff}, /* Error Counter Window (default) */ | |
228 | {0x67, 0x83}, /* Non-DCII symbol clock */ | |
b79cb653 ST |
229 | }; |
230 | ||
231 | static int cx24123_writereg(struct cx24123_state* state, int reg, int data) | |
232 | { | |
233 | u8 buf[] = { reg, data }; | |
234 | struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; | |
235 | int err; | |
236 | ||
caf970e0 MCC |
237 | if (debug>1) |
238 | printk("cx24123: %s: write reg 0x%02x, value 0x%02x\n", | |
239 | __FUNCTION__,reg, data); | |
240 | ||
b79cb653 ST |
241 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
242 | printk("%s: writereg error(err == %i, reg == 0x%02x," | |
243 | " data == 0x%02x)\n", __FUNCTION__, err, reg, data); | |
244 | return -EREMOTEIO; | |
245 | } | |
246 | ||
247 | return 0; | |
248 | } | |
249 | ||
b79cb653 ST |
250 | static int cx24123_readreg(struct cx24123_state* state, u8 reg) |
251 | { | |
252 | int ret; | |
253 | u8 b0[] = { reg }; | |
254 | u8 b1[] = { 0 }; | |
255 | struct i2c_msg msg[] = { | |
256 | { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 }, | |
257 | { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } | |
258 | }; | |
259 | ||
260 | ret = i2c_transfer(state->i2c, msg, 2); | |
261 | ||
262 | if (ret != 2) { | |
263 | printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret); | |
264 | return ret; | |
265 | } | |
266 | ||
caf970e0 MCC |
267 | if (debug>1) |
268 | printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret); | |
269 | ||
b79cb653 ST |
270 | return b1[0]; |
271 | } | |
272 | ||
b79cb653 ST |
273 | static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion) |
274 | { | |
0e4558ab YP |
275 | u8 nom_reg = cx24123_readreg(state, 0x0e); |
276 | u8 auto_reg = cx24123_readreg(state, 0x10); | |
277 | ||
b79cb653 ST |
278 | switch (inversion) { |
279 | case INVERSION_OFF: | |
caf970e0 | 280 | dprintk("%s: inversion off\n",__FUNCTION__); |
0e4558ab YP |
281 | cx24123_writereg(state, 0x0e, nom_reg & ~0x80); |
282 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
283 | break; |
284 | case INVERSION_ON: | |
caf970e0 | 285 | dprintk("%s: inversion on\n",__FUNCTION__); |
0e4558ab YP |
286 | cx24123_writereg(state, 0x0e, nom_reg | 0x80); |
287 | cx24123_writereg(state, 0x10, auto_reg | 0x80); | |
b79cb653 ST |
288 | break; |
289 | case INVERSION_AUTO: | |
caf970e0 | 290 | dprintk("%s: inversion auto\n",__FUNCTION__); |
0e4558ab | 291 | cx24123_writereg(state, 0x10, auto_reg & ~0x80); |
b79cb653 ST |
292 | break; |
293 | default: | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
300 | static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion) | |
301 | { | |
302 | u8 val; | |
303 | ||
304 | val = cx24123_readreg(state, 0x1b) >> 7; | |
305 | ||
caf970e0 MCC |
306 | if (val == 0) { |
307 | dprintk("%s: read inversion off\n",__FUNCTION__); | |
e3b152bc | 308 | *inversion = INVERSION_OFF; |
caf970e0 MCC |
309 | } else { |
310 | dprintk("%s: read inversion on\n",__FUNCTION__); | |
e3b152bc | 311 | *inversion = INVERSION_ON; |
caf970e0 | 312 | } |
b79cb653 ST |
313 | |
314 | return 0; | |
315 | } | |
316 | ||
317 | static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec) | |
318 | { | |
0e4558ab YP |
319 | u8 nom_reg = cx24123_readreg(state, 0x0e) & ~0x07; |
320 | ||
b79cb653 | 321 | if ( (fec < FEC_NONE) || (fec > FEC_AUTO) ) |
e3b152bc | 322 | fec = FEC_AUTO; |
b79cb653 | 323 | |
b79cb653 | 324 | switch (fec) { |
b79cb653 | 325 | case FEC_1_2: |
caf970e0 | 326 | dprintk("%s: set FEC to 1/2\n",__FUNCTION__); |
0e4558ab YP |
327 | cx24123_writereg(state, 0x0e, nom_reg | 0x01); |
328 | cx24123_writereg(state, 0x0f, 0x02); | |
329 | break; | |
b79cb653 | 330 | case FEC_2_3: |
caf970e0 | 331 | dprintk("%s: set FEC to 2/3\n",__FUNCTION__); |
0e4558ab YP |
332 | cx24123_writereg(state, 0x0e, nom_reg | 0x02); |
333 | cx24123_writereg(state, 0x0f, 0x04); | |
334 | break; | |
b79cb653 | 335 | case FEC_3_4: |
caf970e0 | 336 | dprintk("%s: set FEC to 3/4\n",__FUNCTION__); |
0e4558ab YP |
337 | cx24123_writereg(state, 0x0e, nom_reg | 0x03); |
338 | cx24123_writereg(state, 0x0f, 0x08); | |
339 | break; | |
340 | case FEC_4_5: | |
caf970e0 | 341 | dprintk("%s: set FEC to 4/5\n",__FUNCTION__); |
0e4558ab YP |
342 | cx24123_writereg(state, 0x0e, nom_reg | 0x04); |
343 | cx24123_writereg(state, 0x0f, 0x10); | |
344 | break; | |
345 | case FEC_5_6: | |
caf970e0 | 346 | dprintk("%s: set FEC to 5/6\n",__FUNCTION__); |
0e4558ab YP |
347 | cx24123_writereg(state, 0x0e, nom_reg | 0x05); |
348 | cx24123_writereg(state, 0x0f, 0x20); | |
349 | break; | |
350 | case FEC_6_7: | |
351 | dprintk("%s: set FEC to 6/7\n",__FUNCTION__); | |
352 | cx24123_writereg(state, 0x0e, nom_reg | 0x06); | |
353 | cx24123_writereg(state, 0x0f, 0x40); | |
354 | break; | |
355 | case FEC_7_8: | |
356 | dprintk("%s: set FEC to 7/8\n",__FUNCTION__); | |
357 | cx24123_writereg(state, 0x0e, nom_reg | 0x07); | |
358 | cx24123_writereg(state, 0x0f, 0x80); | |
359 | break; | |
b79cb653 | 360 | case FEC_AUTO: |
caf970e0 | 361 | dprintk("%s: set FEC to auto\n",__FUNCTION__); |
0e4558ab YP |
362 | cx24123_writereg(state, 0x0f, 0xfe); |
363 | break; | |
b79cb653 ST |
364 | default: |
365 | return -EOPNOTSUPP; | |
366 | } | |
0e4558ab YP |
367 | |
368 | return 0; | |
b79cb653 ST |
369 | } |
370 | ||
371 | static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec) | |
372 | { | |
e3b152bc | 373 | int ret; |
b79cb653 | 374 | |
e3b152bc JS |
375 | ret = cx24123_readreg (state, 0x1b); |
376 | if (ret < 0) | |
377 | return ret; | |
a74b51fc VC |
378 | ret = ret & 0x07; |
379 | ||
380 | switch (ret) { | |
b79cb653 | 381 | case 1: |
e3b152bc JS |
382 | *fec = FEC_1_2; |
383 | break; | |
a74b51fc | 384 | case 2: |
e3b152bc JS |
385 | *fec = FEC_2_3; |
386 | break; | |
a74b51fc | 387 | case 3: |
e3b152bc JS |
388 | *fec = FEC_3_4; |
389 | break; | |
a74b51fc | 390 | case 4: |
e3b152bc JS |
391 | *fec = FEC_4_5; |
392 | break; | |
a74b51fc | 393 | case 5: |
e3b152bc JS |
394 | *fec = FEC_5_6; |
395 | break; | |
a74b51fc VC |
396 | case 6: |
397 | *fec = FEC_6_7; | |
398 | break; | |
b79cb653 | 399 | case 7: |
e3b152bc JS |
400 | *fec = FEC_7_8; |
401 | break; | |
b79cb653 | 402 | default: |
0e4558ab YP |
403 | /* this can happen when there's no lock */ |
404 | *fec = FEC_NONE; | |
b79cb653 ST |
405 | } |
406 | ||
e3b152bc | 407 | return 0; |
b79cb653 ST |
408 | } |
409 | ||
0e4558ab YP |
410 | /* Approximation of closest integer of log2(a/b). It actually gives the |
411 | lowest integer i such that 2^i >= round(a/b) */ | |
412 | static u32 cx24123_int_log2(u32 a, u32 b) | |
413 | { | |
414 | u32 exp, nearest = 0; | |
415 | u32 div = a / b; | |
416 | if(a % b >= b / 2) ++div; | |
417 | if(div < (1 << 31)) | |
418 | { | |
419 | for(exp = 1; div > exp; nearest++) | |
420 | exp += exp; | |
421 | } | |
422 | return nearest; | |
423 | } | |
424 | ||
b79cb653 ST |
425 | static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate) |
426 | { | |
0e4558ab | 427 | u32 tmp, sample_rate, ratio, sample_gain; |
a74b51fc VC |
428 | u8 pll_mult; |
429 | ||
430 | /* check if symbol rate is within limits */ | |
dea74869 PB |
431 | if ((srate > state->frontend.ops.info.symbol_rate_max) || |
432 | (srate < state->frontend.ops.info.symbol_rate_min)) | |
a74b51fc VC |
433 | return -EOPNOTSUPP;; |
434 | ||
435 | /* choose the sampling rate high enough for the required operation, | |
436 | while optimizing the power consumed by the demodulator */ | |
437 | if (srate < (XTAL*2)/2) | |
438 | pll_mult = 2; | |
439 | else if (srate < (XTAL*3)/2) | |
440 | pll_mult = 3; | |
441 | else if (srate < (XTAL*4)/2) | |
442 | pll_mult = 4; | |
443 | else if (srate < (XTAL*5)/2) | |
444 | pll_mult = 5; | |
445 | else if (srate < (XTAL*6)/2) | |
446 | pll_mult = 6; | |
447 | else if (srate < (XTAL*7)/2) | |
448 | pll_mult = 7; | |
449 | else if (srate < (XTAL*8)/2) | |
450 | pll_mult = 8; | |
451 | else | |
452 | pll_mult = 9; | |
453 | ||
454 | ||
455 | sample_rate = pll_mult * XTAL; | |
b79cb653 | 456 | |
a74b51fc VC |
457 | /* |
458 | SYSSymbolRate[21:0] = (srate << 23) / sample_rate | |
b79cb653 | 459 | |
a74b51fc VC |
460 | We have to use 32 bit unsigned arithmetic without precision loss. |
461 | The maximum srate is 45000000 or 0x02AEA540. This number has | |
462 | only 6 clear bits on top, hence we can shift it left only 6 bits | |
463 | at a time. Borrowed from cx24110.c | |
464 | */ | |
b79cb653 | 465 | |
a74b51fc VC |
466 | tmp = srate << 6; |
467 | ratio = tmp / sample_rate; | |
468 | ||
469 | tmp = (tmp % sample_rate) << 6; | |
470 | ratio = (ratio << 6) + (tmp / sample_rate); | |
471 | ||
472 | tmp = (tmp % sample_rate) << 6; | |
473 | ratio = (ratio << 6) + (tmp / sample_rate); | |
474 | ||
475 | tmp = (tmp % sample_rate) << 5; | |
476 | ratio = (ratio << 5) + (tmp / sample_rate); | |
477 | ||
478 | ||
479 | cx24123_writereg(state, 0x01, pll_mult * 6); | |
480 | ||
481 | cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f ); | |
482 | cx24123_writereg(state, 0x09, (ratio >> 8) & 0xff ); | |
483 | cx24123_writereg(state, 0x0a, (ratio ) & 0xff ); | |
484 | ||
0e4558ab YP |
485 | /* also set the demodulator sample gain */ |
486 | sample_gain = cx24123_int_log2(sample_rate, srate); | |
487 | tmp = cx24123_readreg(state, 0x0c) & ~0xe0; | |
488 | cx24123_writereg(state, 0x0c, tmp | sample_gain << 5); | |
489 | ||
490 | dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i sample_gain=%d\n", __FUNCTION__, srate, ratio, sample_rate, sample_gain); | |
b79cb653 ST |
491 | |
492 | return 0; | |
493 | } | |
494 | ||
495 | /* | |
496 | * Based on the required frequency and symbolrate, the tuner AGC has to be configured | |
497 | * and the correct band selected. Calculate those values | |
498 | */ | |
499 | static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
500 | { | |
501 | struct cx24123_state *state = fe->demodulator_priv; | |
e3b152bc JS |
502 | u32 ndiv = 0, adiv = 0, vco_div = 0; |
503 | int i = 0; | |
a74b51fc | 504 | int pump = 2; |
70047f9c YP |
505 | int band = 0; |
506 | int num_bands = sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); | |
b79cb653 ST |
507 | |
508 | /* Defaults for low freq, low rate */ | |
509 | state->VCAarg = cx24123_AGC_vals[0].VCAprogdata; | |
510 | state->VGAarg = cx24123_AGC_vals[0].VGAprogdata; | |
511 | state->bandselectarg = cx24123_bandselect_vals[0].progdata; | |
512 | vco_div = cx24123_bandselect_vals[0].VCOdivider; | |
513 | ||
a74b51fc | 514 | /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */ |
e3b152bc | 515 | for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++) |
b79cb653 ST |
516 | { |
517 | if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) && | |
a74b51fc | 518 | (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) { |
b79cb653 ST |
519 | state->VCAarg = cx24123_AGC_vals[i].VCAprogdata; |
520 | state->VGAarg = cx24123_AGC_vals[i].VGAprogdata; | |
a74b51fc | 521 | state->FILTune = cx24123_AGC_vals[i].FILTune; |
b79cb653 ST |
522 | } |
523 | } | |
524 | ||
70047f9c YP |
525 | /* determine the band to use */ |
526 | if(force_band < 1 || force_band > num_bands) | |
b79cb653 | 527 | { |
70047f9c YP |
528 | for (i = 0; i < num_bands; i++) |
529 | { | |
530 | if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) && | |
531 | (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) | |
532 | band = i; | |
b79cb653 ST |
533 | } |
534 | } | |
70047f9c YP |
535 | else |
536 | band = force_band - 1; | |
537 | ||
538 | state->bandselectarg = cx24123_bandselect_vals[band].progdata; | |
539 | vco_div = cx24123_bandselect_vals[band].VCOdivider; | |
540 | ||
541 | /* determine the charge pump current */ | |
542 | if ( p->frequency < (cx24123_bandselect_vals[band].freq_low + cx24123_bandselect_vals[band].freq_high)/2 ) | |
543 | pump = 0x01; | |
544 | else | |
545 | pump = 0x02; | |
b79cb653 ST |
546 | |
547 | /* Determine the N/A dividers for the requested lband freq (in kHz). */ | |
a74b51fc VC |
548 | /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */ |
549 | ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff; | |
550 | adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f; | |
b79cb653 ST |
551 | |
552 | if (adiv == 0) | |
a74b51fc | 553 | ndiv++; |
b79cb653 | 554 | |
a74b51fc VC |
555 | /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */ |
556 | state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv; | |
b79cb653 ST |
557 | |
558 | return 0; | |
559 | } | |
560 | ||
561 | /* | |
562 | * Tuner data is 21 bits long, must be left-aligned in data. | |
563 | * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip. | |
564 | */ | |
565 | static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data) | |
566 | { | |
567 | struct cx24123_state *state = fe->demodulator_priv; | |
0144f314 | 568 | unsigned long timeout; |
b79cb653 | 569 | |
caf970e0 MCC |
570 | dprintk("%s: pll writereg called, data=0x%08x\n",__FUNCTION__,data); |
571 | ||
b79cb653 ST |
572 | /* align the 21 bytes into to bit23 boundary */ |
573 | data = data << 3; | |
574 | ||
575 | /* Reset the demod pll word length to 0x15 bits */ | |
576 | cx24123_writereg(state, 0x21, 0x15); | |
577 | ||
b79cb653 | 578 | /* write the msb 8 bits, wait for the send to be completed */ |
0144f314 | 579 | timeout = jiffies + msecs_to_jiffies(40); |
e3b152bc | 580 | cx24123_writereg(state, 0x22, (data >> 16) & 0xff); |
0144f314 ST |
581 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
582 | if (time_after(jiffies, timeout)) { | |
583 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
584 | return -EREMOTEIO; |
585 | } | |
0144f314 | 586 | msleep(10); |
b79cb653 ST |
587 | } |
588 | ||
b79cb653 | 589 | /* send another 8 bytes, wait for the send to be completed */ |
0144f314 | 590 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 591 | cx24123_writereg(state, 0x22, (data>>8) & 0xff ); |
0144f314 ST |
592 | while ((cx24123_readreg(state, 0x20) & 0x40) == 0) { |
593 | if (time_after(jiffies, timeout)) { | |
594 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
595 | return -EREMOTEIO; |
596 | } | |
0144f314 | 597 | msleep(10); |
b79cb653 ST |
598 | } |
599 | ||
b79cb653 | 600 | /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */ |
0144f314 | 601 | timeout = jiffies + msecs_to_jiffies(40); |
b79cb653 | 602 | cx24123_writereg(state, 0x22, (data) & 0xff ); |
0144f314 ST |
603 | while ((cx24123_readreg(state, 0x20) & 0x80)) { |
604 | if (time_after(jiffies, timeout)) { | |
605 | printk("%s: demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__); | |
b79cb653 ST |
606 | return -EREMOTEIO; |
607 | } | |
0144f314 | 608 | msleep(10); |
b79cb653 ST |
609 | } |
610 | ||
611 | /* Trigger the demod to configure the tuner */ | |
612 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2); | |
613 | cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd); | |
614 | ||
615 | return 0; | |
616 | } | |
617 | ||
618 | static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
619 | { | |
620 | struct cx24123_state *state = fe->demodulator_priv; | |
a74b51fc VC |
621 | u8 val; |
622 | ||
623 | dprintk("frequency=%i\n", p->frequency); | |
b79cb653 | 624 | |
e3b152bc | 625 | if (cx24123_pll_calculate(fe, p) != 0) { |
b79cb653 ST |
626 | printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__); |
627 | return -EINVAL; | |
628 | } | |
629 | ||
630 | /* Write the new VCO/VGA */ | |
631 | cx24123_pll_writereg(fe, p, state->VCAarg); | |
632 | cx24123_pll_writereg(fe, p, state->VGAarg); | |
633 | ||
634 | /* Write the new bandselect and pll args */ | |
635 | cx24123_pll_writereg(fe, p, state->bandselectarg); | |
636 | cx24123_pll_writereg(fe, p, state->pllarg); | |
637 | ||
a74b51fc VC |
638 | /* set the FILTUNE voltage */ |
639 | val = cx24123_readreg(state, 0x28) & ~0x3; | |
640 | cx24123_writereg(state, 0x27, state->FILTune >> 2); | |
641 | cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3)); | |
642 | ||
caf970e0 MCC |
643 | dprintk("%s: pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg, |
644 | state->bandselectarg,state->pllarg); | |
645 | ||
b79cb653 ST |
646 | return 0; |
647 | } | |
648 | ||
649 | static int cx24123_initfe(struct dvb_frontend* fe) | |
650 | { | |
651 | struct cx24123_state *state = fe->demodulator_priv; | |
652 | int i; | |
653 | ||
caf970e0 MCC |
654 | dprintk("%s: init frontend\n",__FUNCTION__); |
655 | ||
b79cb653 | 656 | /* Configure the demod to a good set of defaults */ |
e3b152bc | 657 | for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++) |
b79cb653 ST |
658 | cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data); |
659 | ||
b79cb653 ST |
660 | return 0; |
661 | } | |
662 | ||
663 | static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage) | |
664 | { | |
665 | struct cx24123_state *state = fe->demodulator_priv; | |
666 | u8 val; | |
667 | ||
cd20ca9f | 668 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 669 | |
cd20ca9f AQ |
670 | switch (voltage) { |
671 | case SEC_VOLTAGE_13: | |
672 | dprintk("%s: setting voltage 13V\n", __FUNCTION__); | |
ccd214b2 | 673 | return cx24123_writereg(state, 0x29, val & 0x7f); |
cd20ca9f AQ |
674 | case SEC_VOLTAGE_18: |
675 | dprintk("%s: setting voltage 18V\n", __FUNCTION__); | |
ccd214b2 | 676 | return cx24123_writereg(state, 0x29, val | 0x80); |
cd20ca9f AQ |
677 | default: |
678 | return -EINVAL; | |
679 | }; | |
1c956a3a VC |
680 | |
681 | return 0; | |
b79cb653 ST |
682 | } |
683 | ||
dce1dfc2 YP |
684 | /* wait for diseqc queue to become ready (or timeout) */ |
685 | static void cx24123_wait_for_diseqc(struct cx24123_state *state) | |
686 | { | |
687 | unsigned long timeout = jiffies + msecs_to_jiffies(200); | |
688 | while (!(cx24123_readreg(state, 0x29) & 0x40)) { | |
689 | if(time_after(jiffies, timeout)) { | |
690 | printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__); | |
691 | break; | |
692 | } | |
693 | msleep(10); | |
694 | } | |
695 | } | |
696 | ||
a74b51fc | 697 | static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd) |
b79cb653 | 698 | { |
a74b51fc | 699 | struct cx24123_state *state = fe->demodulator_priv; |
cd20ca9f | 700 | int i, val, tone; |
a74b51fc VC |
701 | |
702 | dprintk("%s:\n",__FUNCTION__); | |
b79cb653 | 703 | |
cd20ca9f AQ |
704 | /* stop continuous tone if enabled */ |
705 | tone = cx24123_readreg(state, 0x29); | |
706 | if (tone & 0x10) | |
707 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 708 | |
dce1dfc2 YP |
709 | /* wait for diseqc queue ready */ |
710 | cx24123_wait_for_diseqc(state); | |
711 | ||
a74b51fc | 712 | /* select tone mode */ |
cd20ca9f | 713 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc VC |
714 | |
715 | for (i = 0; i < cmd->msg_len; i++) | |
716 | cx24123_writereg(state, 0x2C + i, cmd->msg[i]); | |
717 | ||
718 | val = cx24123_readreg(state, 0x29); | |
719 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); | |
720 | ||
dce1dfc2 YP |
721 | /* wait for diseqc message to finish sending */ |
722 | cx24123_wait_for_diseqc(state); | |
a74b51fc | 723 | |
cd20ca9f AQ |
724 | /* restart continuous tone if enabled */ |
725 | if (tone & 0x10) { | |
726 | cx24123_writereg(state, 0x29, tone & ~0x40); | |
727 | } | |
728 | ||
a74b51fc VC |
729 | return 0; |
730 | } | |
731 | ||
732 | static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst) | |
733 | { | |
734 | struct cx24123_state *state = fe->demodulator_priv; | |
cd20ca9f | 735 | int val, tone; |
a74b51fc VC |
736 | |
737 | dprintk("%s:\n", __FUNCTION__); | |
738 | ||
cd20ca9f AQ |
739 | /* stop continuous tone if enabled */ |
740 | tone = cx24123_readreg(state, 0x29); | |
741 | if (tone & 0x10) | |
742 | cx24123_writereg(state, 0x29, tone & ~0x50); | |
a74b51fc | 743 | |
cd20ca9f | 744 | /* wait for diseqc queue ready */ |
dce1dfc2 YP |
745 | cx24123_wait_for_diseqc(state); |
746 | ||
a74b51fc | 747 | /* select tone mode */ |
cd20ca9f AQ |
748 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) | 0x4); |
749 | msleep(30); | |
a74b51fc | 750 | val = cx24123_readreg(state, 0x29); |
a74b51fc VC |
751 | if (burst == SEC_MINI_A) |
752 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00)); | |
753 | else if (burst == SEC_MINI_B) | |
754 | cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08)); | |
755 | else | |
756 | return -EINVAL; | |
757 | ||
dce1dfc2 | 758 | cx24123_wait_for_diseqc(state); |
cd20ca9f | 759 | cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xfb); |
a74b51fc | 760 | |
cd20ca9f AQ |
761 | /* restart continuous tone if enabled */ |
762 | if (tone & 0x10) { | |
763 | cx24123_writereg(state, 0x29, tone & ~0x40); | |
764 | } | |
a74b51fc | 765 | return 0; |
b79cb653 ST |
766 | } |
767 | ||
768 | static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status) | |
769 | { | |
770 | struct cx24123_state *state = fe->demodulator_priv; | |
771 | ||
772 | int sync = cx24123_readreg(state, 0x14); | |
773 | int lock = cx24123_readreg(state, 0x20); | |
774 | ||
775 | *status = 0; | |
776 | if (lock & 0x01) | |
a74b51fc VC |
777 | *status |= FE_HAS_SIGNAL; |
778 | if (sync & 0x02) | |
779 | *status |= FE_HAS_CARRIER; | |
b79cb653 ST |
780 | if (sync & 0x04) |
781 | *status |= FE_HAS_VITERBI; | |
782 | if (sync & 0x08) | |
a74b51fc | 783 | *status |= FE_HAS_SYNC; |
b79cb653 | 784 | if (sync & 0x80) |
a74b51fc | 785 | *status |= FE_HAS_LOCK; |
b79cb653 ST |
786 | |
787 | return 0; | |
788 | } | |
789 | ||
790 | /* | |
791 | * Configured to return the measurement of errors in blocks, because no UCBLOCKS value | |
792 | * is available, so this value doubles up to satisfy both measurements | |
793 | */ | |
794 | static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber) | |
795 | { | |
796 | struct cx24123_state *state = fe->demodulator_priv; | |
797 | ||
798 | state->lastber = | |
799 | ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) | | |
800 | (cx24123_readreg(state, 0x1d) << 8 | | |
801 | cx24123_readreg(state, 0x1e)); | |
802 | ||
803 | /* Do the signal quality processing here, it's derived from the BER. */ | |
804 | /* Scale the BER from a 24bit to a SNR 16 bit where higher = better */ | |
805 | if (state->lastber < 5000) | |
806 | state->snr = 655*100; | |
807 | else if ( (state->lastber >= 5000) && (state->lastber < 55000) ) | |
808 | state->snr = 655*90; | |
809 | else if ( (state->lastber >= 55000) && (state->lastber < 150000) ) | |
810 | state->snr = 655*80; | |
811 | else if ( (state->lastber >= 150000) && (state->lastber < 250000) ) | |
812 | state->snr = 655*70; | |
813 | else if ( (state->lastber >= 250000) && (state->lastber < 450000) ) | |
814 | state->snr = 655*65; | |
815 | else | |
816 | state->snr = 0; | |
817 | ||
caf970e0 MCC |
818 | dprintk("%s: BER = %d, S/N index = %d\n",__FUNCTION__,state->lastber, state->snr); |
819 | ||
b79cb653 ST |
820 | *ber = state->lastber; |
821 | ||
822 | return 0; | |
823 | } | |
824 | ||
825 | static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength) | |
826 | { | |
827 | struct cx24123_state *state = fe->demodulator_priv; | |
828 | *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */ | |
829 | ||
caf970e0 MCC |
830 | dprintk("%s: Signal strength = %d\n",__FUNCTION__,*signal_strength); |
831 | ||
b79cb653 ST |
832 | return 0; |
833 | } | |
834 | ||
835 | static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr) | |
836 | { | |
837 | struct cx24123_state *state = fe->demodulator_priv; | |
838 | *snr = state->snr; | |
839 | ||
caf970e0 MCC |
840 | dprintk("%s: read S/N index = %d\n",__FUNCTION__,*snr); |
841 | ||
b79cb653 ST |
842 | return 0; |
843 | } | |
844 | ||
845 | static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) | |
846 | { | |
847 | struct cx24123_state *state = fe->demodulator_priv; | |
848 | *ucblocks = state->lastber; | |
849 | ||
caf970e0 MCC |
850 | dprintk("%s: ucblocks (ber) = %d\n",__FUNCTION__,*ucblocks); |
851 | ||
b79cb653 ST |
852 | return 0; |
853 | } | |
854 | ||
855 | static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
856 | { | |
857 | struct cx24123_state *state = fe->demodulator_priv; | |
858 | ||
caf970e0 MCC |
859 | dprintk("%s: set_frontend\n",__FUNCTION__); |
860 | ||
b79cb653 ST |
861 | if (state->config->set_ts_params) |
862 | state->config->set_ts_params(fe, 0); | |
863 | ||
864 | state->currentfreq=p->frequency; | |
e3b152bc | 865 | state->currentsymbolrate = p->u.qpsk.symbol_rate; |
b79cb653 ST |
866 | |
867 | cx24123_set_inversion(state, p->inversion); | |
868 | cx24123_set_fec(state, p->u.qpsk.fec_inner); | |
869 | cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate); | |
870 | cx24123_pll_tune(fe, p); | |
871 | ||
872 | /* Enable automatic aquisition and reset cycle */ | |
e3b152bc | 873 | cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07)); |
b79cb653 ST |
874 | cx24123_writereg(state, 0x00, 0x10); |
875 | cx24123_writereg(state, 0x00, 0); | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p) | |
881 | { | |
882 | struct cx24123_state *state = fe->demodulator_priv; | |
883 | ||
caf970e0 MCC |
884 | dprintk("%s: get_frontend\n",__FUNCTION__); |
885 | ||
b79cb653 ST |
886 | if (cx24123_get_inversion(state, &p->inversion) != 0) { |
887 | printk("%s: Failed to get inversion status\n",__FUNCTION__); | |
888 | return -EREMOTEIO; | |
889 | } | |
890 | if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) { | |
891 | printk("%s: Failed to get fec status\n",__FUNCTION__); | |
892 | return -EREMOTEIO; | |
893 | } | |
894 | p->frequency = state->currentfreq; | |
895 | p->u.qpsk.symbol_rate = state->currentsymbolrate; | |
896 | ||
897 | return 0; | |
898 | } | |
899 | ||
900 | static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone) | |
901 | { | |
902 | struct cx24123_state *state = fe->demodulator_priv; | |
903 | u8 val; | |
904 | ||
cd20ca9f AQ |
905 | /* wait for diseqc queue ready */ |
906 | cx24123_wait_for_diseqc(state); | |
1c956a3a | 907 | |
cd20ca9f | 908 | val = cx24123_readreg(state, 0x29) & ~0x40; |
1c956a3a | 909 | |
cd20ca9f AQ |
910 | switch (tone) { |
911 | case SEC_TONE_ON: | |
912 | dprintk("%s: setting tone on\n", __FUNCTION__); | |
913 | return cx24123_writereg(state, 0x29, val | 0x10); | |
914 | case SEC_TONE_OFF: | |
915 | dprintk("%s: setting tone off\n",__FUNCTION__); | |
916 | return cx24123_writereg(state, 0x29, val & 0xef); | |
917 | default: | |
918 | printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone); | |
919 | return -EINVAL; | |
b79cb653 | 920 | } |
1c956a3a VC |
921 | |
922 | return 0; | |
b79cb653 ST |
923 | } |
924 | ||
925 | static void cx24123_release(struct dvb_frontend* fe) | |
926 | { | |
927 | struct cx24123_state* state = fe->demodulator_priv; | |
928 | dprintk("%s\n",__FUNCTION__); | |
929 | kfree(state); | |
930 | } | |
931 | ||
932 | static struct dvb_frontend_ops cx24123_ops; | |
933 | ||
e3b152bc JS |
934 | struct dvb_frontend* cx24123_attach(const struct cx24123_config* config, |
935 | struct i2c_adapter* i2c) | |
b79cb653 ST |
936 | { |
937 | struct cx24123_state* state = NULL; | |
938 | int ret; | |
939 | ||
940 | dprintk("%s\n",__FUNCTION__); | |
941 | ||
942 | /* allocate memory for the internal state */ | |
943 | state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL); | |
944 | if (state == NULL) { | |
945 | printk("Unable to kmalloc\n"); | |
946 | goto error; | |
947 | } | |
948 | ||
949 | /* setup the state */ | |
950 | state->config = config; | |
951 | state->i2c = i2c; | |
b79cb653 ST |
952 | state->lastber = 0; |
953 | state->snr = 0; | |
b79cb653 ST |
954 | state->VCAarg = 0; |
955 | state->VGAarg = 0; | |
956 | state->bandselectarg = 0; | |
957 | state->pllarg = 0; | |
958 | state->currentfreq = 0; | |
959 | state->currentsymbolrate = 0; | |
960 | ||
961 | /* check if the demod is there */ | |
962 | ret = cx24123_readreg(state, 0x00); | |
963 | if ((ret != 0xd1) && (ret != 0xe1)) { | |
964 | printk("Version != d1 or e1\n"); | |
965 | goto error; | |
966 | } | |
967 | ||
968 | /* create dvb_frontend */ | |
dea74869 | 969 | memcpy(&state->frontend.ops, &cx24123_ops, sizeof(struct dvb_frontend_ops)); |
b79cb653 ST |
970 | state->frontend.demodulator_priv = state; |
971 | return &state->frontend; | |
972 | ||
973 | error: | |
974 | kfree(state); | |
975 | ||
976 | return NULL; | |
977 | } | |
978 | ||
979 | static struct dvb_frontend_ops cx24123_ops = { | |
980 | ||
981 | .info = { | |
982 | .name = "Conexant CX24123/CX24109", | |
983 | .type = FE_QPSK, | |
984 | .frequency_min = 950000, | |
985 | .frequency_max = 2150000, | |
986 | .frequency_stepsize = 1011, /* kHz for QPSK frontends */ | |
0e4558ab | 987 | .frequency_tolerance = 5000, |
b79cb653 ST |
988 | .symbol_rate_min = 1000000, |
989 | .symbol_rate_max = 45000000, | |
990 | .caps = FE_CAN_INVERSION_AUTO | | |
991 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | | |
0e4558ab YP |
992 | FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | |
993 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | | |
b79cb653 ST |
994 | FE_CAN_QPSK | FE_CAN_RECOVER |
995 | }, | |
996 | ||
997 | .release = cx24123_release, | |
998 | ||
999 | .init = cx24123_initfe, | |
1000 | .set_frontend = cx24123_set_frontend, | |
1001 | .get_frontend = cx24123_get_frontend, | |
1002 | .read_status = cx24123_read_status, | |
1003 | .read_ber = cx24123_read_ber, | |
1004 | .read_signal_strength = cx24123_read_signal_strength, | |
1005 | .read_snr = cx24123_read_snr, | |
1006 | .read_ucblocks = cx24123_read_ucblocks, | |
1007 | .diseqc_send_master_cmd = cx24123_send_diseqc_msg, | |
a74b51fc | 1008 | .diseqc_send_burst = cx24123_diseqc_send_burst, |
b79cb653 ST |
1009 | .set_tone = cx24123_set_tone, |
1010 | .set_voltage = cx24123_set_voltage, | |
1011 | }; | |
1012 | ||
1013 | module_param(debug, int, 0644); | |
caf970e0 | 1014 | MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)"); |
b79cb653 | 1015 | |
70047f9c YP |
1016 | module_param(force_band, int, 0644); |
1017 | MODULE_PARM_DESC(force_band, "Force a specific band select (1-9, default:off)."); | |
1018 | ||
b79cb653 ST |
1019 | MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware"); |
1020 | MODULE_AUTHOR("Steven Toth"); | |
1021 | MODULE_LICENSE("GPL"); | |
1022 | ||
1023 | EXPORT_SYMBOL(cx24123_attach); |