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[media] bt8xx: add support for PCI device ID 0x36c
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb / frontends / it913x-fe.c
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3dbbf82f
MP		 1/*
2 * Driver for it913x-fe Frontend
3 *
4 * with support for on chip it9137 integral tuner
5 *
6 * Copyright (C) 2011 Malcolm Priestley (tvboxspy@gmail.com)
7 * IT9137 Copyright (C) ITE Tech Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 *
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
23 */
24
25#include <linux/module.h>
26#include <linux/init.h>
27#include <linux/slab.h>
28#include <linux/types.h>
29
30#include "dvb_frontend.h"
31#include "it913x-fe.h"
32#include "it913x-fe-priv.h"
33
34static int it913x_debug;
35
36module_param_named(debug, it913x_debug, int, 0644);
37MODULE_PARM_DESC(debug, "set debugging level (1=info (or-able)).");
38
39#define dprintk(level, args...) do { \
40 if (level & it913x_debug) \
41 printk(KERN_DEBUG "it913x-fe: " args); \
42} while (0)
43
44#define deb_info(args...) dprintk(0x01, args)
45#define debug_data_snipet(level, name, p) \
46 dprintk(level, name" (%02x%02x%02x%02x%02x%02x%02x%02x)", \
47 *p, *(p+1), *(p+2), *(p+3), *(p+4), \
48 *(p+5), *(p+6), *(p+7));
49
50struct it913x_fe_state {
51 struct dvb_frontend frontend;
52 struct i2c_adapter *i2c_adap;
b7d425d3 53 struct ite_config *config;
3dbbf82f
MP		 54 u8 i2c_addr;
55 u32 frequency;
3dbbf82f
MP		 56 u32 crystalFrequency;
57 u32 adcFrequency;
58 u8 tuner_type;
59 struct adctable *table;
60 fe_status_t it913x_status;
7c2808e2 61 u16 tun_xtal;
62 u8 tun_fdiv;
63 u8 tun_clk_mode;
64 u32 tun_fn_min;
3dbbf82f
MP		 65};
66
67static int it913x_read_reg(struct it913x_fe_state *state,
68 u32 reg, u8 *data, u8 count)
69{
70 int ret;
71 u8 pro = PRO_DMOD; /* All reads from demodulator */
72 u8 b[4];
73 struct i2c_msg msg[2] = {
74 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
75 .buf = b, .len = sizeof(b) },
76 { .addr = state->i2c_addr + (pro << 1), .flags = I2C_M_RD,
77 .buf = data, .len = count }
78 };
79 b[0] = (u8) reg >> 24;
80 b[1] = (u8)(reg >> 16) & 0xff;
81 b[2] = (u8)(reg >> 8) & 0xff;
82 b[3] = (u8) reg & 0xff;
83
84 ret = i2c_transfer(state->i2c_adap, msg, 2);
85
86 return ret;
87}
88
89static int it913x_read_reg_u8(struct it913x_fe_state *state, u32 reg)
90{
91 int ret;
92 u8 b[1];
93 ret = it913x_read_reg(state, reg, &b[0], sizeof(b));
94 return (ret < 0) ? -ENODEV : b[0];
95}
96
97static int it913x_write(struct it913x_fe_state *state,
98 u8 pro, u32 reg, u8 buf[], u8 count)
99{
100 u8 b[256];
101 struct i2c_msg msg[1] = {
102 { .addr = state->i2c_addr + (pro << 1), .flags = 0,
103 .buf = b, .len = count + 4 }
104 };
105 int ret;
106
107 b[0] = (u8) reg >> 24;
108 b[1] = (u8)(reg >> 16) & 0xff;
109 b[2] = (u8)(reg >> 8) & 0xff;
110 b[3] = (u8) reg & 0xff;
111 memcpy(&b[4], buf, count);
112
113 ret = i2c_transfer(state->i2c_adap, msg, 1);
114
115 if (ret < 0)
116 return -EIO;
117
118 return 0;
119}
120
121static int it913x_write_reg(struct it913x_fe_state *state,
122 u8 pro, u32 reg, u32 data)
123{
124 int ret;
125 u8 b[4];
126 u8 s;
127
128 b[0] = data >> 24;
129 b[1] = (data >> 16) & 0xff;
130 b[2] = (data >> 8) & 0xff;
131 b[3] = data & 0xff;
132 /* expand write as needed */
133 if (data < 0x100)
134 s = 3;
135 else if (data < 0x1000)
136 s = 2;
137 else if (data < 0x100000)
138 s = 1;
139 else
140 s = 0;
141
142 ret = it913x_write(state, pro, reg, &b[s], sizeof(b) - s);
143
144 return ret;
145}
146
147static int it913x_fe_script_loader(struct it913x_fe_state *state,
148 struct it913xset *loadscript)
149{
150 int ret, i;
151 if (loadscript == NULL)
152 return -EINVAL;
153
154 for (i = 0; i < 1000; ++i) {
155 if (loadscript[i].pro == 0xff)
156 break;
157 ret = it913x_write(state, loadscript[i].pro,
158 loadscript[i].address,
159 loadscript[i].reg, loadscript[i].count);
160 if (ret < 0)
161 return -ENODEV;
162 }
163 return 0;
164}
165
7c2808e2 166static int it913x_init_tuner(struct it913x_fe_state *state)
167{
168 int ret, i, reg;
169 u8 val, nv_val;
170 u8 nv[] = {48, 32, 24, 16, 12, 8, 6, 4, 2};
171 u8 b[2];
172
173 reg = it913x_read_reg_u8(state, 0xec86);
174 switch (reg) {
175 case 0:
176 state->tun_clk_mode = reg;
177 state->tun_xtal = 2000;
178 state->tun_fdiv = 3;
179 val = 16;
180 break;
181 case -ENODEV:
182 return -ENODEV;
183 case 1:
184 default:
185 state->tun_clk_mode = reg;
186 state->tun_xtal = 640;
187 state->tun_fdiv = 1;
188 val = 6;
189 break;
190 }
191
192 reg = it913x_read_reg_u8(state, 0xed03);
193
194 if (reg < 0)
195 return -ENODEV;
196 else if (reg < sizeof(nv))
197 nv_val = nv[reg];
198 else
199 nv_val = 2;
200
201 for (i = 0; i < 50; i++) {
202 ret = it913x_read_reg(state, 0xed23, &b[0], sizeof(b));
203 reg = (b[1] << 8) + b[0];
204 if (reg > 0)
205 break;
206 if (ret < 0)
207 return -ENODEV;
208 udelay(2000);
209 }
210 state->tun_fn_min = state->tun_xtal * reg;
211 state->tun_fn_min /= (state->tun_fdiv * nv_val);
212 deb_info("Tuner fn_min %d", state->tun_fn_min);
213
b7d425d3
MP		 214 if (state->config->chip_ver > 1)
215 msleep(50);
216 else {
217 for (i = 0; i < 50; i++) {
218 reg = it913x_read_reg_u8(state, 0xec82);
219 if (reg > 0)
220 break;
221 if (reg < 0)
222 return -ENODEV;
223 udelay(2000);
224 }
7c2808e2 225 }
226
227 return it913x_write_reg(state, PRO_DMOD, 0xed81, val);
228}
229
3dbbf82f
MP		 230static int it9137_set_tuner(struct it913x_fe_state *state,
231 enum fe_bandwidth bandwidth, u32 frequency_m)
232{
233 struct it913xset *set_tuner = set_it9137_template;
7c2808e2 234 int ret, reg;
3dbbf82f 235 u32 frequency = frequency_m / 1000;
7c2808e2 236 u32 freq, temp_f, tmp;
237 u16 iqik_m_cal;
3dbbf82f
MP		 238 u16 n_div;
239 u8 n;
240 u8 l_band;
241 u8 lna_band;
242 u8 bw;
243
244 deb_info("Tuner Frequency %d Bandwidth %d", frequency, bandwidth);
245
246 if (frequency >= 51000 && frequency <= 440000) {
247 l_band = 0;
248 lna_band = 0;
249 } else if (frequency > 440000 && frequency <= 484000) {
250 l_band = 1;
251 lna_band = 1;
252 } else if (frequency > 484000 && frequency <= 533000) {
253 l_band = 1;
254 lna_band = 2;
255 } else if (frequency > 533000 && frequency <= 587000) {
256 l_band = 1;
257 lna_band = 3;
258 } else if (frequency > 587000 && frequency <= 645000) {
259 l_band = 1;
260 lna_band = 4;
261 } else if (frequency > 645000 && frequency <= 710000) {
262 l_band = 1;
263 lna_band = 5;
264 } else if (frequency > 710000 && frequency <= 782000) {
265 l_band = 1;
266 lna_band = 6;
267 } else if (frequency > 782000 && frequency <= 860000) {
268 l_band = 1;
269 lna_band = 7;
270 } else if (frequency > 1450000 && frequency <= 1492000) {
271 l_band = 1;
272 lna_band = 0;
273 } else if (frequency > 1660000 && frequency <= 1685000) {
274 l_band = 1;
275 lna_band = 1;
276 } else
277 return -EINVAL;
278 set_tuner[0].reg[0] = lna_band;
279
280 if (bandwidth == BANDWIDTH_5_MHZ)
281 bw = 0;
282 else if (bandwidth == BANDWIDTH_6_MHZ)
283 bw = 2;
284 else if (bandwidth == BANDWIDTH_7_MHZ)
285 bw = 4;
286 else if (bandwidth == BANDWIDTH_8_MHZ)
287 bw = 6;
288 else
289 bw = 6;
7c2808e2 290
3dbbf82f
MP		 291 set_tuner[1].reg[0] = bw;
292 set_tuner[2].reg[0] = 0xa0 | (l_band << 3);
293
7c2808e2 294 if (frequency > 53000 && frequency <= 74000) {
3dbbf82f
MP		 295 n_div = 48;
296 n = 0;
297 } else if (frequency > 74000 && frequency <= 111000) {
298 n_div = 32;
299 n = 1;
300 } else if (frequency > 111000 && frequency <= 148000) {
301 n_div = 24;
302 n = 2;
303 } else if (frequency > 148000 && frequency <= 222000) {
304 n_div = 16;
305 n = 3;
306 } else if (frequency > 222000 && frequency <= 296000) {
307 n_div = 12;
308 n = 4;
309 } else if (frequency > 296000 && frequency <= 445000) {
310 n_div = 8;
311 n = 5;
7c2808e2 312 } else if (frequency > 445000 && frequency <= state->tun_fn_min) {
3dbbf82f
MP		 313 n_div = 6;
314 n = 6;
7c2808e2 315 } else if (frequency > state->tun_fn_min && frequency <= 950000) {
3dbbf82f
MP		 316 n_div = 4;
317 n = 7;
318 } else if (frequency > 1450000 && frequency <= 1680000) {
319 n_div = 2;
320 n = 0;
321 } else
322 return -EINVAL;
323
7c2808e2 324 reg = it913x_read_reg_u8(state, 0xed81);
325 iqik_m_cal = (u16)reg * n_div;
3dbbf82f 326
7c2808e2 327 if (reg < 0x20) {
328 if (state->tun_clk_mode == 0)
329 iqik_m_cal = (iqik_m_cal * 9) >> 5;
330 else
331 iqik_m_cal >>= 1;
332 } else {
333 iqik_m_cal = 0x40 - iqik_m_cal;
334 if (state->tun_clk_mode == 0)
335 iqik_m_cal = ~((iqik_m_cal * 9) >> 5);
336 else
337 iqik_m_cal = ~(iqik_m_cal >> 1);
338 }
339
340 temp_f = frequency * (u32)n_div * (u32)state->tun_fdiv;
341 freq = temp_f / state->tun_xtal;
342 tmp = freq * state->tun_xtal;
343
344 if ((temp_f - tmp) >= (state->tun_xtal >> 1))
345 freq++;
3dbbf82f 346
3dbbf82f 347 freq += (u32) n << 13;
7c2808e2 348 /* Frequency OMEGA_IQIK_M_CAL_MID*/
349 temp_f = freq + (u32)iqik_m_cal;
3dbbf82f 350
7c2808e2 351 set_tuner[3].reg[0] = temp_f & 0xff;
352 set_tuner[4].reg[0] = (temp_f >> 8) & 0xff;
353
354 deb_info("High Frequency = %04x", temp_f);
355
356 /* Lower frequency */
357 set_tuner[5].reg[0] = freq & 0xff;
358 set_tuner[6].reg[0] = (freq >> 8) & 0xff;
359
360 deb_info("low Frequency = %04x", freq);
3dbbf82f
MP		 361
362 ret = it913x_fe_script_loader(state, set_tuner);
363
364 return (ret < 0) ? -ENODEV : 0;
3dbbf82f
MP		 365}
366
367static int it913x_fe_select_bw(struct it913x_fe_state *state,
368 enum fe_bandwidth bandwidth, u32 adcFrequency)
369{
370 int ret, i;
371 u8 buffer[256];
372 u32 coeff[8];
373 u16 bfsfcw_fftinx_ratio;
374 u16 fftinx_bfsfcw_ratio;
375 u8 count;
376 u8 bw;
377 u8 adcmultiplier;
378
379 deb_info("Bandwidth %d Adc %d", bandwidth, adcFrequency);
380
381 if (bandwidth == BANDWIDTH_5_MHZ)
382 bw = 3;
383 else if (bandwidth == BANDWIDTH_6_MHZ)
384 bw = 0;
385 else if (bandwidth == BANDWIDTH_7_MHZ)
386 bw = 1;
387 else if (bandwidth == BANDWIDTH_8_MHZ)
388 bw = 2;
389 else
390 bw = 2;
391
392 ret = it913x_write_reg(state, PRO_DMOD, REG_BW, bw);
393
394 if (state->table == NULL)
395 return -EINVAL;
396
397 /* In write order */
398 coeff[0] = state->table[bw].coeff_1_2048;
399 coeff[1] = state->table[bw].coeff_2_2k;
400 coeff[2] = state->table[bw].coeff_1_8191;
401 coeff[3] = state->table[bw].coeff_1_8192;
402 coeff[4] = state->table[bw].coeff_1_8193;
403 coeff[5] = state->table[bw].coeff_2_8k;
404 coeff[6] = state->table[bw].coeff_1_4096;
405 coeff[7] = state->table[bw].coeff_2_4k;
406 bfsfcw_fftinx_ratio = state->table[bw].bfsfcw_fftinx_ratio;
407 fftinx_bfsfcw_ratio = state->table[bw].fftinx_bfsfcw_ratio;
408
409 /* ADC multiplier */
410 ret = it913x_read_reg_u8(state, ADC_X_2);
411 if (ret < 0)
412 return -EINVAL;
413
414 adcmultiplier = ret;
415
416 count = 0;
417
418 /* Build Buffer for COEFF Registers */
419 for (i = 0; i < 8; i++) {
420 if (adcmultiplier == 1)
421 coeff[i] /= 2;
422 buffer[count++] = (coeff[i] >> 24) & 0x3;
423 buffer[count++] = (coeff[i] >> 16) & 0xff;
424 buffer[count++] = (coeff[i] >> 8) & 0xff;
425 buffer[count++] = coeff[i] & 0xff;
426 }
427
428 /* bfsfcw_fftinx_ratio register 0x21-0x22 */
429 buffer[count++] = bfsfcw_fftinx_ratio & 0xff;
430 buffer[count++] = (bfsfcw_fftinx_ratio >> 8) & 0xff;
431 /* fftinx_bfsfcw_ratio register 0x23-0x24 */
432 buffer[count++] = fftinx_bfsfcw_ratio & 0xff;
433 buffer[count++] = (fftinx_bfsfcw_ratio >> 8) & 0xff;
434 /* start at COEFF_1_2048 and write through to fftinx_bfsfcw_ratio*/
435 ret = it913x_write(state, PRO_DMOD, COEFF_1_2048, buffer, count);
436
437 for (i = 0; i < 42; i += 8)
438 debug_data_snipet(0x1, "Buffer", &buffer[i]);
439
440 return ret;
441}
442
443
444
445static int it913x_fe_read_status(struct dvb_frontend *fe, fe_status_t *status)
446{
447 struct it913x_fe_state *state = fe->demodulator_priv;
448 int ret, i;
449 fe_status_t old_status = state->it913x_status;
450 *status = 0;
451
452 if (state->it913x_status == 0) {
453 ret = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
454 if (ret == 0x1) {
455 *status |= FE_HAS_SIGNAL;
456 for (i = 0; i < 40; i++) {
457 ret = it913x_read_reg_u8(state, MP2IF_SYNC_LK);
458 if (ret == 0x1)
459 break;
460 msleep(25);
461 }
462 if (ret == 0x1)
463 *status |= FE_HAS_CARRIER
464 | FE_HAS_VITERBI
465 | FE_HAS_SYNC;
466 state->it913x_status = *status;
467 }
468 }
469
470 if (state->it913x_status & FE_HAS_SYNC) {
471 ret = it913x_read_reg_u8(state, TPSD_LOCK);
472 if (ret == 0x1)
473 *status |= FE_HAS_LOCK
474 | state->it913x_status;
475 else
476 state->it913x_status = 0;
477 if (old_status != state->it913x_status)
478 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, ret);
479 }
480
481 return 0;
482}
483
484static int it913x_fe_read_signal_strength(struct dvb_frontend *fe,
485 u16 *strength)
486{
487 struct it913x_fe_state *state = fe->demodulator_priv;
488 int ret = it913x_read_reg_u8(state, SIGNAL_LEVEL);
489 /*SIGNAL_LEVEL always returns 100%! so using FE_HAS_SIGNAL as switch*/
490 if (state->it913x_status & FE_HAS_SIGNAL)
491 ret = (ret * 0xff) / 0x64;
492 else
493 ret = 0x0;
494 ret |= ret << 0x8;
495 *strength = ret;
496 return 0;
497}
498
499static int it913x_fe_read_snr(struct dvb_frontend *fe, u16* snr)
500{
501 struct it913x_fe_state *state = fe->demodulator_priv;
502 int ret = it913x_read_reg_u8(state, SIGNAL_QUALITY);
503 ret = (ret * 0xff) / 0x64;
504 ret |= (ret << 0x8);
505 *snr = ~ret;
506 return 0;
507}
508
509static int it913x_fe_read_ber(struct dvb_frontend *fe, u32 *ber)
510{
511 *ber = 0;
512 return 0;
513}
514
515static int it913x_fe_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
516{
517 *ucblocks = 0;
518 return 0;
519}
520
521static int it913x_fe_get_frontend(struct dvb_frontend *fe,
522 struct dvb_frontend_parameters *p)
523{
524 struct it913x_fe_state *state = fe->demodulator_priv;
525 int ret;
526 u8 reg[8];
527
528 ret = it913x_read_reg(state, REG_TPSD_TX_MODE, reg, sizeof(reg));
529
530 if (reg[3] < 3)
531 p->u.ofdm.constellation = fe_con[reg[3]];
532
533 if (reg[0] < 3)
534 p->u.ofdm.transmission_mode = fe_mode[reg[0]];
535
536 if (reg[1] < 4)
537 p->u.ofdm.guard_interval = fe_gi[reg[1]];
538
539 if (reg[2] < 4)
540 p->u.ofdm.hierarchy_information = fe_hi[reg[2]];
541
542 p->u.ofdm.code_rate_HP = (reg[6] < 6) ? fe_code[reg[6]] : FEC_NONE;
543 p->u.ofdm.code_rate_LP = (reg[7] < 6) ? fe_code[reg[7]] : FEC_NONE;
544
545 return 0;
546}
547
548static int it913x_fe_set_frontend(struct dvb_frontend *fe,
549 struct dvb_frontend_parameters *p)
550{
551 struct it913x_fe_state *state = fe->demodulator_priv;
552 int ret, i;
553 u8 empty_ch, last_ch;
554
555 state->it913x_status = 0;
556
557 /* Set bw*/
558 ret = it913x_fe_select_bw(state, p->u.ofdm.bandwidth,
559 state->adcFrequency);
560
561 /* Training Mode Off */
562 ret = it913x_write_reg(state, PRO_LINK, TRAINING_MODE, 0x0);
563
564 /* Clear Empty Channel */
565 ret = it913x_write_reg(state, PRO_DMOD, EMPTY_CHANNEL_STATUS, 0x0);
566
567 /* Clear bits */
568 ret = it913x_write_reg(state, PRO_DMOD, MP2IF_SYNC_LK, 0x0);
569 /* LED on */
570 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
571 /* Select Band*/
572 if ((p->frequency >= 51000000) && (p->frequency <= 230000000))
573 i = 0;
574 else if ((p->frequency >= 350000000) && (p->frequency <= 900000000))
575 i = 1;
576 else if ((p->frequency >= 1450000000) && (p->frequency <= 1680000000))
577 i = 2;
578 else
579 return -EOPNOTSUPP;
580
581 ret = it913x_write_reg(state, PRO_DMOD, FREE_BAND, i);
582
583 deb_info("Frontend Set Tuner Type %02x", state->tuner_type);
584 switch (state->tuner_type) {
b7d425d3
MP		 585 case IT9135_38:
586 case IT9135_51:
587 case IT9135_52:
588 case IT9135_60:
589 case IT9135_61:
590 case IT9135_62:
3dbbf82f
MP		 591 ret = it9137_set_tuner(state,
592 p->u.ofdm.bandwidth, p->frequency);
593 break;
594 default:
595 if (fe->ops.tuner_ops.set_params) {
596 fe->ops.tuner_ops.set_params(fe, p);
597 if (fe->ops.i2c_gate_ctrl)
598 fe->ops.i2c_gate_ctrl(fe, 0);
599 }
600 break;
601 }
602 /* LED off */
603 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
604 /* Trigger ofsm */
605 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
606 last_ch = 2;
607 for (i = 0; i < 40; ++i) {
608 empty_ch = it913x_read_reg_u8(state, EMPTY_CHANNEL_STATUS);
609 if (last_ch == 1 && empty_ch == 1)
610 break;
611 if (last_ch == 2 && empty_ch == 2)
612 return 0;
613 last_ch = empty_ch;
614 msleep(25);
615 }
616 for (i = 0; i < 40; ++i) {
617 if (it913x_read_reg_u8(state, D_TPSD_LOCK) == 1)
618 break;
619 msleep(25);
620 }
621
622 state->frequency = p->frequency;
623 return 0;
624}
625
626static int it913x_fe_suspend(struct it913x_fe_state *state)
627{
628 int ret, i;
629 u8 b;
630
631 ret = it913x_write_reg(state, PRO_DMOD, SUSPEND_FLAG, 0x1);
632
633 ret |= it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x0);
634
635 for (i = 0; i < 128; i++) {
636 ret = it913x_read_reg(state, SUSPEND_FLAG, &b, 1);
637 if (ret < 0)
e3052885 638 return -ENODEV;
3dbbf82f
MP		 639 if (b == 0)
640 break;
641
642 }
643
644 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x8);
645 /* Turn LED off */
e3052885 646 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x0);
3dbbf82f 647
e3052885
MP		 648 ret |= it913x_fe_script_loader(state, it9137_tuner_off);
649
650 return (ret < 0) ? -ENODEV : 0;
3dbbf82f
MP		 651}
652
e3052885
MP		 653/* Power sequence */
654/* Power Up Tuner on -> Frontend suspend off -> Tuner clk on */
655/* Power Down Frontend suspend on -> Tuner clk off -> Tuner off */
656
3dbbf82f
MP		 657static int it913x_fe_sleep(struct dvb_frontend *fe)
658{
659 struct it913x_fe_state *state = fe->demodulator_priv;
660 return it913x_fe_suspend(state);
661}
662
3dbbf82f
MP		 663static u32 compute_div(u32 a, u32 b, u32 x)
664{
665 u32 res = 0;
666 u32 c = 0;
667 u32 i = 0;
668
669 if (a > b) {
670 c = a / b;
671 a = a - c * b;
672 }
673
674 for (i = 0; i < x; i++) {
675 if (a >= b) {
676 res += 1;
677 a -= b;
678 }
679 a <<= 1;
680 res <<= 1;
681 }
682
683 res = (c << x) + res;
684
685 return res;
686}
687
688static int it913x_fe_start(struct it913x_fe_state *state)
689{
b7d425d3 690 struct it913xset *set_lna;
3dbbf82f
MP		 691 struct it913xset *set_mode;
692 int ret;
b7d425d3 693 u8 adf = (state->config->adf & 0xf);
3dbbf82f
MP		 694 u32 adc, xtal;
695 u8 b[4];
696
b7d425d3
MP		 697 if (state->config->chip_ver == 1)
698 ret = it913x_init_tuner(state);
7c2808e2 699
2b3c13ec 700 if (adf < 10) {
3dbbf82f
MP		 701 state->crystalFrequency = fe_clockTable[adf].xtal ;
702 state->table = fe_clockTable[adf].table;
703 state->adcFrequency = state->table->adcFrequency;
704
705 adc = compute_div(state->adcFrequency, 1000000ul, 19ul);
706 xtal = compute_div(state->crystalFrequency, 1000000ul, 19ul);
707
708 } else
709 return -EINVAL;
710
711 deb_info("Xtal Freq :%d Adc Freq :%d Adc %08x Xtal %08x",
712 state->crystalFrequency, state->adcFrequency, adc, xtal);
713
714 /* Set LED indicator on GPIOH3 */
715 ret = it913x_write_reg(state, PRO_LINK, GPIOH3_EN, 0x1);
716 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_ON, 0x1);
717 ret |= it913x_write_reg(state, PRO_LINK, GPIOH3_O, 0x1);
718
3dbbf82f
MP		 719 ret |= it913x_write_reg(state, PRO_LINK, 0xf641, state->tuner_type);
720 ret |= it913x_write_reg(state, PRO_DMOD, 0xf5ca, 0x01);
721 ret |= it913x_write_reg(state, PRO_DMOD, 0xf715, 0x01);
722
723 b[0] = xtal & 0xff;
724 b[1] = (xtal >> 8) & 0xff;
725 b[2] = (xtal >> 16) & 0xff;
726 b[3] = (xtal >> 24);
727 ret |= it913x_write(state, PRO_DMOD, XTAL_CLK, b , 4);
728
729 b[0] = adc & 0xff;
730 b[1] = (adc >> 8) & 0xff;
731 b[2] = (adc >> 16) & 0xff;
732 ret |= it913x_write(state, PRO_DMOD, ADC_FREQ, b, 3);
b7d425d3
MP		 733 if (ret < 0)
734 return -ENODEV;
3dbbf82f 735
b7d425d3
MP		 736 /* v1 or v2 tuner script */
737 if (state->config->chip_ver > 1)
738 ret = it913x_fe_script_loader(state, it9135_v2);
739 else
740 ret = it913x_fe_script_loader(state, it9135_v1);
741 if (ret < 0)
742 return ret;
743
744 /* LNA Scripts */
3dbbf82f 745 switch (state->tuner_type) {
b7d425d3
MP		 746 case IT9135_51:
747 set_lna = it9135_51;
748 break;
749 case IT9135_52:
750 set_lna = it9135_52;
3dbbf82f 751 break;
b7d425d3
MP		 752 case IT9135_60:
753 set_lna = it9135_60;
754 break;
755 case IT9135_61:
756 set_lna = it9135_61;
757 break;
758 case IT9135_62:
759 set_lna = it9135_62;
760 break;
761 case IT9135_38:
3dbbf82f 762 default:
b7d425d3 763 set_lna = it9135_38;
3dbbf82f 764 }
b7d425d3
MP		 765 ret = it913x_fe_script_loader(state, set_lna);
766 if (ret < 0)
767 return ret;
768
769 if (state->config->chip_ver == 2) {
770 ret = it913x_write_reg(state, PRO_DMOD, TRIGGER_OFSM, 0x1);
771 ret |= it913x_write_reg(state, PRO_LINK, PADODPU, 0x0);
772 ret |= it913x_write_reg(state, PRO_LINK, AGC_O_D, 0x0);
773 ret |= it913x_init_tuner(state);
774 }
775 if (ret < 0)
776 return -ENODEV;
7c2808e2 777
3dbbf82f
MP		 778 /* Always solo frontend */
779 set_mode = set_solo_fe;
780 ret |= it913x_fe_script_loader(state, set_mode);
781
782 ret |= it913x_fe_suspend(state);
b7d425d3 783 return (ret < 0) ? -ENODEV : 0;
3dbbf82f
MP		 784}
785
786static int it913x_fe_init(struct dvb_frontend *fe)
787{
788 struct it913x_fe_state *state = fe->demodulator_priv;
3dbbf82f 789 int ret = 0;
e3052885
MP		 790 /* Power Up Tuner - common all versions */
791 ret = it913x_write_reg(state, PRO_DMOD, 0xec40, 0x1);
3dbbf82f 792
e3052885 793 ret |= it913x_write_reg(state, PRO_DMOD, AFE_MEM0, 0x0);
3dbbf82f
MP		 794
795 ret |= it913x_fe_script_loader(state, init_1);
796
b7d425d3 797 ret |= it913x_write_reg(state, PRO_DMOD, 0xfba8, 0x0);
e3052885 798
3dbbf82f
MP		 799 return (ret < 0) ? -ENODEV : 0;
800}
801
802static void it913x_fe_release(struct dvb_frontend *fe)
803{
804 struct it913x_fe_state *state = fe->demodulator_priv;
805 kfree(state);
806}
807
808static struct dvb_frontend_ops it913x_fe_ofdm_ops;
809
810struct dvb_frontend *it913x_fe_attach(struct i2c_adapter *i2c_adap,
b7d425d3 811 u8 i2c_addr, struct ite_config *config)
3dbbf82f
MP		 812{
813 struct it913x_fe_state *state = NULL;
814 int ret;
b7d425d3 815
3dbbf82f
MP		 816 /* allocate memory for the internal state */
817 state = kzalloc(sizeof(struct it913x_fe_state), GFP_KERNEL);
818 if (state == NULL)
b7d425d3
MP		 819 return NULL;
820 if (config == NULL)
3dbbf82f
MP		 821 goto error;
822
823 state->i2c_adap = i2c_adap;
824 state->i2c_addr = i2c_addr;
b7d425d3
MP		 825 state->config = config;
826
827 switch (state->config->tuner_id_0) {
828 case IT9135_51:
829 case IT9135_52:
830 case IT9135_60:
831 case IT9135_61:
832 case IT9135_62:
833 state->tuner_type = state->config->tuner_id_0;
834 break;
835 default:
836 case IT9135_38:
837 state->tuner_type = IT9135_38;
838 }
3dbbf82f
MP		 839
840 ret = it913x_fe_start(state);
841 if (ret < 0)
842 goto error;
843
844
845 /* create dvb_frontend */
846 memcpy(&state->frontend.ops, &it913x_fe_ofdm_ops,
847 sizeof(struct dvb_frontend_ops));
848 state->frontend.demodulator_priv = state;
849
850 return &state->frontend;
851error:
852 kfree(state);
853 return NULL;
854}
855EXPORT_SYMBOL(it913x_fe_attach);
856
857static struct dvb_frontend_ops it913x_fe_ofdm_ops = {
858
859 .info = {
860 .name = "it913x-fe DVB-T",
861 .type = FE_OFDM,
862 .frequency_min = 51000000,
863 .frequency_max = 1680000000,
864 .frequency_stepsize = 62500,
865 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
866 FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
867 FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
868 FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
869 FE_CAN_TRANSMISSION_MODE_AUTO |
870 FE_CAN_GUARD_INTERVAL_AUTO |
871 FE_CAN_HIERARCHY_AUTO,
872 },
873
874 .release = it913x_fe_release,
875
876 .init = it913x_fe_init,
877 .sleep = it913x_fe_sleep,
878
879 .set_frontend = it913x_fe_set_frontend,
880 .get_frontend = it913x_fe_get_frontend,
881
882 .read_status = it913x_fe_read_status,
883 .read_signal_strength = it913x_fe_read_signal_strength,
884 .read_snr = it913x_fe_read_snr,
885 .read_ber = it913x_fe_read_ber,
886 .read_ucblocks = it913x_fe_read_ucblocks,
887};
888
889MODULE_DESCRIPTION("it913x Frontend and it9137 tuner");
890MODULE_AUTHOR("Malcolm Priestley tvboxspy@gmail.com");
2b3c13ec 891MODULE_VERSION("1.09");
3dbbf82f 892MODULE_LICENSE("GPL");
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