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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[mirror_ubuntu-bionic-kernel.git] / drivers / media / dvb / frontends / lgdt3305.c
CommitLineData
cae78ed5
MK		 1/*
2 * Support for LGDT3305 - VSB/QAM
3 *
4 * Copyright (C) 2008, 2009 Michael Krufky <mkrufky@linuxtv.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
511da457 22#include <asm/div64.h>
cae78ed5 23#include <linux/dvb/frontend.h>
5a0e3ad6 24#include <linux/slab.h>
cae78ed5
MK		 25#include "dvb_math.h"
26#include "lgdt3305.h"
27
28static int debug;
29module_param(debug, int, 0644);
30MODULE_PARM_DESC(debug, "set debug level (info=1, reg=2 (or-able))");
31
32#define DBG_INFO 1
33#define DBG_REG 2
34
35#define lg_printk(kern, fmt, arg...) \
36 printk(kern "%s: " fmt, __func__, ##arg)
37
38#define lg_info(fmt, arg...) printk(KERN_INFO "lgdt3305: " fmt, ##arg)
39#define lg_warn(fmt, arg...) lg_printk(KERN_WARNING, fmt, ##arg)
40#define lg_err(fmt, arg...) lg_printk(KERN_ERR, fmt, ##arg)
41#define lg_dbg(fmt, arg...) if (debug & DBG_INFO) \
42 lg_printk(KERN_DEBUG, fmt, ##arg)
43#define lg_reg(fmt, arg...) if (debug & DBG_REG) \
44 lg_printk(KERN_DEBUG, fmt, ##arg)
45
46#define lg_fail(ret) \
47({ \
48 int __ret; \
49 __ret = (ret < 0); \
50 if (__ret) \
51 lg_err("error %d on line %d\n", ret, __LINE__); \
52 __ret; \
53})
54
55struct lgdt3305_state {
56 struct i2c_adapter *i2c_adap;
57 const struct lgdt3305_config *cfg;
58
59 struct dvb_frontend frontend;
60
61 fe_modulation_t current_modulation;
62 u32 current_frequency;
63 u32 snr;
64};
65
66/* ------------------------------------------------------------------------ */
67
68#define LGDT3305_GEN_CTRL_1 0x0000
69#define LGDT3305_GEN_CTRL_2 0x0001
70#define LGDT3305_GEN_CTRL_3 0x0002
71#define LGDT3305_GEN_STATUS 0x0003
72#define LGDT3305_GEN_CONTROL 0x0007
73#define LGDT3305_GEN_CTRL_4 0x000a
74#define LGDT3305_DGTL_AGC_REF_1 0x0012
75#define LGDT3305_DGTL_AGC_REF_2 0x0013
76#define LGDT3305_CR_CTR_FREQ_1 0x0106
77#define LGDT3305_CR_CTR_FREQ_2 0x0107
78#define LGDT3305_CR_CTR_FREQ_3 0x0108
79#define LGDT3305_CR_CTR_FREQ_4 0x0109
80#define LGDT3305_CR_MSE_1 0x011b
81#define LGDT3305_CR_MSE_2 0x011c
82#define LGDT3305_CR_LOCK_STATUS 0x011d
83#define LGDT3305_CR_CTRL_7 0x0126
84#define LGDT3305_AGC_POWER_REF_1 0x0300
85#define LGDT3305_AGC_POWER_REF_2 0x0301
86#define LGDT3305_AGC_DELAY_PT_1 0x0302
87#define LGDT3305_AGC_DELAY_PT_2 0x0303
88#define LGDT3305_RFAGC_LOOP_FLTR_BW_1 0x0306
89#define LGDT3305_RFAGC_LOOP_FLTR_BW_2 0x0307
90#define LGDT3305_IFBW_1 0x0308
91#define LGDT3305_IFBW_2 0x0309
92#define LGDT3305_AGC_CTRL_1 0x030c
93#define LGDT3305_AGC_CTRL_4 0x0314
94#define LGDT3305_EQ_MSE_1 0x0413
95#define LGDT3305_EQ_MSE_2 0x0414
96#define LGDT3305_EQ_MSE_3 0x0415
97#define LGDT3305_PT_MSE_1 0x0417
98#define LGDT3305_PT_MSE_2 0x0418
99#define LGDT3305_PT_MSE_3 0x0419
100#define LGDT3305_FEC_BLOCK_CTRL 0x0504
101#define LGDT3305_FEC_LOCK_STATUS 0x050a
102#define LGDT3305_FEC_PKT_ERR_1 0x050c
103#define LGDT3305_FEC_PKT_ERR_2 0x050d
104#define LGDT3305_TP_CTRL_1 0x050e
105#define LGDT3305_BERT_PERIOD 0x0801
106#define LGDT3305_BERT_ERROR_COUNT_1 0x080a
107#define LGDT3305_BERT_ERROR_COUNT_2 0x080b
108#define LGDT3305_BERT_ERROR_COUNT_3 0x080c
109#define LGDT3305_BERT_ERROR_COUNT_4 0x080d
110
111static int lgdt3305_write_reg(struct lgdt3305_state *state, u16 reg, u8 val)
112{
113 int ret;
114 u8 buf[] = { reg >> 8, reg & 0xff, val };
115 struct i2c_msg msg = {
116 .addr = state->cfg->i2c_addr, .flags = 0,
117 .buf = buf, .len = 3,
118 };
119
120 lg_reg("reg: 0x%04x, val: 0x%02x\n", reg, val);
121
122 ret = i2c_transfer(state->i2c_adap, &msg, 1);
123
124 if (ret != 1) {
125 lg_err("error (addr %02x %02x <- %02x, err = %i)\n",
126 msg.buf[0], msg.buf[1], msg.buf[2], ret);
127 if (ret < 0)
128 return ret;
129 else
130 return -EREMOTEIO;
131 }
132 return 0;
133}
134
135static int lgdt3305_read_reg(struct lgdt3305_state *state, u16 reg, u8 *val)
136{
137 int ret;
138 u8 reg_buf[] = { reg >> 8, reg & 0xff };
139 struct i2c_msg msg[] = {
140 { .addr = state->cfg->i2c_addr,
141 .flags = 0, .buf = reg_buf, .len = 2 },
142 { .addr = state->cfg->i2c_addr,
143 .flags = I2C_M_RD, .buf = val, .len = 1 },
144 };
145
146 lg_reg("reg: 0x%04x\n", reg);
147
148 ret = i2c_transfer(state->i2c_adap, msg, 2);
149
150 if (ret != 2) {
151 lg_err("error (addr %02x reg %04x error (ret == %i)\n",
152 state->cfg->i2c_addr, reg, ret);
153 if (ret < 0)
154 return ret;
155 else
156 return -EREMOTEIO;
157 }
158 return 0;
159}
160
161#define read_reg(state, reg) \
162({ \
163 u8 __val; \
164 int ret = lgdt3305_read_reg(state, reg, &__val); \
165 if (lg_fail(ret)) \
166 __val = 0; \
167 __val; \
168})
169
170static int lgdt3305_set_reg_bit(struct lgdt3305_state *state,
171 u16 reg, int bit, int onoff)
172{
173 u8 val;
174 int ret;
175
176 lg_reg("reg: 0x%04x, bit: %d, level: %d\n", reg, bit, onoff);
177
178 ret = lgdt3305_read_reg(state, reg, &val);
179 if (lg_fail(ret))
180 goto fail;
181
182 val &= ~(1 << bit);
183 val |= (onoff & 1) << bit;
184
185 ret = lgdt3305_write_reg(state, reg, val);
186fail:
187 return ret;
188}
189
190struct lgdt3305_reg {
191 u16 reg;
192 u8 val;
193};
194
195static int lgdt3305_write_regs(struct lgdt3305_state *state,
196 struct lgdt3305_reg *regs, int len)
197{
198 int i, ret;
199
200 lg_reg("writing %d registers...\n", len);
201
202 for (i = 0; i < len - 1; i++) {
203 ret = lgdt3305_write_reg(state, regs[i].reg, regs[i].val);
204 if (lg_fail(ret))
205 return ret;
206 }
207 return 0;
208}
209
210/* ------------------------------------------------------------------------ */
211
212static int lgdt3305_soft_reset(struct lgdt3305_state *state)
213{
214 int ret;
215
216 lg_dbg("\n");
217
218 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 0);
219 if (lg_fail(ret))
220 goto fail;
221
222 msleep(20);
223 ret = lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_3, 0, 1);
224fail:
225 return ret;
226}
227
228static inline int lgdt3305_mpeg_mode(struct lgdt3305_state *state,
229 enum lgdt3305_mpeg_mode mode)
230{
231 lg_dbg("(%d)\n", mode);
232 return lgdt3305_set_reg_bit(state, LGDT3305_TP_CTRL_1, 5, mode);
233}
234
235static int lgdt3305_mpeg_mode_polarity(struct lgdt3305_state *state,
236 enum lgdt3305_tp_clock_edge edge,
237 enum lgdt3305_tp_valid_polarity valid)
238{
239 u8 val;
240 int ret;
241
242 lg_dbg("edge = %d, valid = %d\n", edge, valid);
243
244 ret = lgdt3305_read_reg(state, LGDT3305_TP_CTRL_1, &val);
245 if (lg_fail(ret))
246 goto fail;
247
248 val &= ~0x09;
249
250 if (edge)
251 val |= 0x08;
252 if (valid)
253 val |= 0x01;
254
255 ret = lgdt3305_write_reg(state, LGDT3305_TP_CTRL_1, val);
256 if (lg_fail(ret))
257 goto fail;
258
259 ret = lgdt3305_soft_reset(state);
260fail:
261 return ret;
262}
263
264static int lgdt3305_set_modulation(struct lgdt3305_state *state,
265 struct dvb_frontend_parameters *param)
266{
267 u8 opermode;
268 int ret;
269
270 lg_dbg("\n");
271
272 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_1, &opermode);
273 if (lg_fail(ret))
274 goto fail;
275
276 opermode &= ~0x03;
277
278 switch (param->u.vsb.modulation) {
279 case VSB_8:
280 opermode |= 0x03;
281 break;
282 case QAM_64:
283 opermode |= 0x00;
284 break;
285 case QAM_256:
286 opermode |= 0x01;
287 break;
288 default:
289 return -EINVAL;
290 }
291 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_1, opermode);
292fail:
293 return ret;
294}
295
296static int lgdt3305_set_filter_extension(struct lgdt3305_state *state,
297 struct dvb_frontend_parameters *param)
298{
299 int val;
300
301 switch (param->u.vsb.modulation) {
302 case VSB_8:
303 val = 0;
304 break;
305 case QAM_64:
306 case QAM_256:
307 val = 1;
308 break;
309 default:
310 return -EINVAL;
311 }
312 lg_dbg("val = %d\n", val);
313
314 return lgdt3305_set_reg_bit(state, 0x043f, 2, val);
315}
316
317/* ------------------------------------------------------------------------ */
318
319static int lgdt3305_passband_digital_agc(struct lgdt3305_state *state,
320 struct dvb_frontend_parameters *param)
321{
322 u16 agc_ref;
323
324 switch (param->u.vsb.modulation) {
325 case VSB_8:
326 agc_ref = 0x32c4;
327 break;
328 case QAM_64:
329 agc_ref = 0x2a00;
330 break;
331 case QAM_256:
332 agc_ref = 0x2a80;
333 break;
334 default:
335 return -EINVAL;
336 }
337
338 lg_dbg("agc ref: 0x%04x\n", agc_ref);
339
340 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_1, agc_ref >> 8);
341 lgdt3305_write_reg(state, LGDT3305_DGTL_AGC_REF_2, agc_ref & 0xff);
342
343 return 0;
344}
345
346static int lgdt3305_rfagc_loop(struct lgdt3305_state *state,
347 struct dvb_frontend_parameters *param)
348{
349 u16 ifbw, rfbw, agcdelay;
350
351 switch (param->u.vsb.modulation) {
352 case VSB_8:
353 agcdelay = 0x04c0;
354 rfbw = 0x8000;
355 ifbw = 0x8000;
356 break;
357 case QAM_64:
358 case QAM_256:
359 agcdelay = 0x046b;
360 rfbw = 0x8889;
361 ifbw = 0x8888;
362 break;
363 default:
364 return -EINVAL;
365 }
366
367 if (state->cfg->rf_agc_loop) {
368 lg_dbg("agcdelay: 0x%04x, rfbw: 0x%04x\n", agcdelay, rfbw);
369
370 /* rf agc loop filter bandwidth */
371 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_1,
372 agcdelay >> 8);
373 lgdt3305_write_reg(state, LGDT3305_AGC_DELAY_PT_2,
374 agcdelay & 0xff);
375
376 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_1,
377 rfbw >> 8);
378 lgdt3305_write_reg(state, LGDT3305_RFAGC_LOOP_FLTR_BW_2,
379 rfbw & 0xff);
380 } else {
381 lg_dbg("ifbw: 0x%04x\n", ifbw);
382
383 /* if agc loop filter bandwidth */
384 lgdt3305_write_reg(state, LGDT3305_IFBW_1, ifbw >> 8);
385 lgdt3305_write_reg(state, LGDT3305_IFBW_2, ifbw & 0xff);
386 }
387
388 return 0;
389}
390
391static int lgdt3305_agc_setup(struct lgdt3305_state *state,
392 struct dvb_frontend_parameters *param)
393{
394 int lockdten, acqen;
395
396 switch (param->u.vsb.modulation) {
397 case VSB_8:
398 lockdten = 0;
399 acqen = 0;
400 break;
401 case QAM_64:
402 case QAM_256:
403 lockdten = 1;
404 acqen = 1;
405 break;
406 default:
407 return -EINVAL;
408 }
409
410 lg_dbg("lockdten = %d, acqen = %d\n", lockdten, acqen);
411
412 /* control agc function */
413 lgdt3305_write_reg(state, LGDT3305_AGC_CTRL_4, 0xe1 | lockdten << 1);
414 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 2, acqen);
415
416 return lgdt3305_rfagc_loop(state, param);
417}
418
419static int lgdt3305_set_agc_power_ref(struct lgdt3305_state *state,
420 struct dvb_frontend_parameters *param)
421{
422 u16 usref = 0;
423
424 switch (param->u.vsb.modulation) {
425 case VSB_8:
426 if (state->cfg->usref_8vsb)
427 usref = state->cfg->usref_8vsb;
428 break;
429 case QAM_64:
430 if (state->cfg->usref_qam64)
431 usref = state->cfg->usref_qam64;
432 break;
433 case QAM_256:
434 if (state->cfg->usref_qam256)
435 usref = state->cfg->usref_qam256;
436 break;
437 default:
438 return -EINVAL;
439 }
440
441 if (usref) {
442 lg_dbg("set manual mode: 0x%04x\n", usref);
443
444 lgdt3305_set_reg_bit(state, LGDT3305_AGC_CTRL_1, 3, 1);
445
446 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_1,
447 0xff & (usref >> 8));
448 lgdt3305_write_reg(state, LGDT3305_AGC_POWER_REF_2,
449 0xff & (usref >> 0));
450 }
451 return 0;
452}
453
454/* ------------------------------------------------------------------------ */
455
456static int lgdt3305_spectral_inversion(struct lgdt3305_state *state,
457 struct dvb_frontend_parameters *param,
458 int inversion)
459{
460 int ret;
461
462 lg_dbg("(%d)\n", inversion);
463
464 switch (param->u.vsb.modulation) {
465 case VSB_8:
466 ret = lgdt3305_write_reg(state, LGDT3305_CR_CTRL_7,
467 inversion ? 0xf9 : 0x79);
468 break;
469 case QAM_64:
470 case QAM_256:
471 ret = lgdt3305_write_reg(state, LGDT3305_FEC_BLOCK_CTRL,
472 inversion ? 0xfd : 0xff);
473 break;
474 default:
475 ret = -EINVAL;
476 }
477 return ret;
478}
479
480static int lgdt3305_set_if(struct lgdt3305_state *state,
481 struct dvb_frontend_parameters *param)
482{
483 u16 if_freq_khz;
484 u8 nco1, nco2, nco3, nco4;
485 u64 nco;
486
487 switch (param->u.vsb.modulation) {
488 case VSB_8:
489 if_freq_khz = state->cfg->vsb_if_khz;
490 break;
491 case QAM_64:
492 case QAM_256:
493 if_freq_khz = state->cfg->qam_if_khz;
494 break;
495 default:
496 return -EINVAL;
497 }
498
499 nco = if_freq_khz / 10;
500
cae78ed5
MK		 501 switch (param->u.vsb.modulation) {
502 case VSB_8:
cae78ed5 503 nco <<= 24;
511da457 504 do_div(nco, 625);
cae78ed5
MK		 505 break;
506 case QAM_64:
507 case QAM_256:
cae78ed5 508 nco <<= 28;
511da457 509 do_div(nco, 625);
cae78ed5
MK		 510 break;
511 default:
512 return -EINVAL;
513 }
514
515 nco1 = (nco >> 24) & 0x3f;
516 nco1 |= 0x40;
517 nco2 = (nco >> 16) & 0xff;
518 nco3 = (nco >> 8) & 0xff;
519 nco4 = nco & 0xff;
520
521 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_1, nco1);
522 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_2, nco2);
523 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_3, nco3);
524 lgdt3305_write_reg(state, LGDT3305_CR_CTR_FREQ_4, nco4);
525
526 lg_dbg("%d KHz -> [%02x%02x%02x%02x]\n",
527 if_freq_khz, nco1, nco2, nco3, nco4);
528
529 return 0;
530}
531
532/* ------------------------------------------------------------------------ */
533
534static int lgdt3305_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
535{
536 struct lgdt3305_state *state = fe->demodulator_priv;
537
538 if (state->cfg->deny_i2c_rptr)
539 return 0;
540
541 lg_dbg("(%d)\n", enable);
542
543 return lgdt3305_set_reg_bit(state, LGDT3305_GEN_CTRL_2, 5,
544 enable ? 0 : 1);
545}
546
547static int lgdt3305_sleep(struct dvb_frontend *fe)
548{
549 struct lgdt3305_state *state = fe->demodulator_priv;
550 u8 gen_ctrl_3, gen_ctrl_4;
551
552 lg_dbg("\n");
553
554 gen_ctrl_3 = read_reg(state, LGDT3305_GEN_CTRL_3);
555 gen_ctrl_4 = read_reg(state, LGDT3305_GEN_CTRL_4);
556
557 /* hold in software reset while sleeping */
558 gen_ctrl_3 &= ~0x01;
559 /* tristate the IF-AGC pin */
560 gen_ctrl_3 |= 0x02;
561 /* tristate the RF-AGC pin */
562 gen_ctrl_3 |= 0x04;
563
564 /* disable vsb/qam module */
565 gen_ctrl_4 &= ~0x01;
566 /* disable adc module */
567 gen_ctrl_4 &= ~0x02;
568
569 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_3, gen_ctrl_3);
570 lgdt3305_write_reg(state, LGDT3305_GEN_CTRL_4, gen_ctrl_4);
571
572 return 0;
573}
574
575static int lgdt3305_init(struct dvb_frontend *fe)
576{
577 struct lgdt3305_state *state = fe->demodulator_priv;
578 int ret;
579
580 static struct lgdt3305_reg lgdt3305_init_data[] = {
581 { .reg = LGDT3305_GEN_CTRL_1,
582 .val = 0x03, },
583 { .reg = LGDT3305_GEN_CTRL_2,
584 .val = 0xb0, },
585 { .reg = LGDT3305_GEN_CTRL_3,
586 .val = 0x01, },
587 { .reg = LGDT3305_GEN_CONTROL,
588 .val = 0x6f, },
589 { .reg = LGDT3305_GEN_CTRL_4,
590 .val = 0x03, },
591 { .reg = LGDT3305_DGTL_AGC_REF_1,
592 .val = 0x32, },
593 { .reg = LGDT3305_DGTL_AGC_REF_2,
594 .val = 0xc4, },
595 { .reg = LGDT3305_CR_CTR_FREQ_1,
596 .val = 0x00, },
597 { .reg = LGDT3305_CR_CTR_FREQ_2,
598 .val = 0x00, },
599 { .reg = LGDT3305_CR_CTR_FREQ_3,
600 .val = 0x00, },
601 { .reg = LGDT3305_CR_CTR_FREQ_4,
602 .val = 0x00, },
603 { .reg = LGDT3305_CR_CTRL_7,
604 .val = 0x79, },
605 { .reg = LGDT3305_AGC_POWER_REF_1,
606 .val = 0x32, },
607 { .reg = LGDT3305_AGC_POWER_REF_2,
608 .val = 0xc4, },
609 { .reg = LGDT3305_AGC_DELAY_PT_1,
610 .val = 0x0d, },
611 { .reg = LGDT3305_AGC_DELAY_PT_2,
612 .val = 0x30, },
613 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_1,
614 .val = 0x80, },
615 { .reg = LGDT3305_RFAGC_LOOP_FLTR_BW_2,
616 .val = 0x00, },
617 { .reg = LGDT3305_IFBW_1,
618 .val = 0x80, },
619 { .reg = LGDT3305_IFBW_2,
620 .val = 0x00, },
621 { .reg = LGDT3305_AGC_CTRL_1,
622 .val = 0x30, },
623 { .reg = LGDT3305_AGC_CTRL_4,
624 .val = 0x61, },
625 { .reg = LGDT3305_FEC_BLOCK_CTRL,
626 .val = 0xff, },
627 { .reg = LGDT3305_TP_CTRL_1,
628 .val = 0x1b, },
629 };
630
631 lg_dbg("\n");
632
633 ret = lgdt3305_write_regs(state, lgdt3305_init_data,
634 ARRAY_SIZE(lgdt3305_init_data));
635 if (lg_fail(ret))
636 goto fail;
637
638 ret = lgdt3305_soft_reset(state);
639fail:
640 return ret;
641}
642
643static int lgdt3305_set_parameters(struct dvb_frontend *fe,
644 struct dvb_frontend_parameters *param)
645{
646 struct lgdt3305_state *state = fe->demodulator_priv;
647 int ret;
648
649 lg_dbg("(%d, %d)\n", param->frequency, param->u.vsb.modulation);
650
651 if (fe->ops.tuner_ops.set_params) {
652 ret = fe->ops.tuner_ops.set_params(fe, param);
653 if (fe->ops.i2c_gate_ctrl)
654 fe->ops.i2c_gate_ctrl(fe, 0);
655 if (lg_fail(ret))
656 goto fail;
657 state->current_frequency = param->frequency;
658 }
659
660 ret = lgdt3305_set_modulation(state, param);
661 if (lg_fail(ret))
662 goto fail;
663
664 ret = lgdt3305_passband_digital_agc(state, param);
665 if (lg_fail(ret))
666 goto fail;
667 ret = lgdt3305_set_agc_power_ref(state, param);
668 if (lg_fail(ret))
669 goto fail;
670 ret = lgdt3305_agc_setup(state, param);
671 if (lg_fail(ret))
672 goto fail;
673
674 /* low if */
675 ret = lgdt3305_write_reg(state, LGDT3305_GEN_CONTROL, 0x2f);
676 if (lg_fail(ret))
677 goto fail;
678 ret = lgdt3305_set_reg_bit(state, LGDT3305_CR_CTR_FREQ_1, 6, 1);
679 if (lg_fail(ret))
680 goto fail;
681
682 ret = lgdt3305_set_if(state, param);
683 if (lg_fail(ret))
684 goto fail;
685 ret = lgdt3305_spectral_inversion(state, param,
686 state->cfg->spectral_inversion
687 ? 1 : 0);
688 if (lg_fail(ret))
689 goto fail;
690
691 ret = lgdt3305_set_filter_extension(state, param);
692 if (lg_fail(ret))
693 goto fail;
694
695 state->current_modulation = param->u.vsb.modulation;
696
697 ret = lgdt3305_mpeg_mode(state, state->cfg->mpeg_mode);
698 if (lg_fail(ret))
699 goto fail;
700
701 /* lgdt3305_mpeg_mode_polarity calls lgdt3305_soft_reset */
702 ret = lgdt3305_mpeg_mode_polarity(state,
703 state->cfg->tpclk_edge,
704 state->cfg->tpvalid_polarity);
705fail:
706 return ret;
707}
708
709static int lgdt3305_get_frontend(struct dvb_frontend *fe,
710 struct dvb_frontend_parameters *param)
711{
712 struct lgdt3305_state *state = fe->demodulator_priv;
713
714 lg_dbg("\n");
715
716 param->u.vsb.modulation = state->current_modulation;
717 param->frequency = state->current_frequency;
718 return 0;
719}
720
721/* ------------------------------------------------------------------------ */
722
723static int lgdt3305_read_cr_lock_status(struct lgdt3305_state *state,
724 int *locked)
725{
726 u8 val;
727 int ret;
728 char *cr_lock_state = "";
729
730 *locked = 0;
731
732 ret = lgdt3305_read_reg(state, LGDT3305_CR_LOCK_STATUS, &val);
733 if (lg_fail(ret))
734 goto fail;
735
736 switch (state->current_modulation) {
737 case QAM_256:
738 case QAM_64:
739 if (val & (1 << 1))
740 *locked = 1;
741
742 switch (val & 0x07) {
743 case 0:
744 cr_lock_state = "QAM UNLOCK";
745 break;
746 case 4:
747 cr_lock_state = "QAM 1stLock";
748 break;
749 case 6:
750 cr_lock_state = "QAM 2ndLock";
751 break;
752 case 7:
753 cr_lock_state = "QAM FinalLock";
754 break;
755 default:
756 cr_lock_state = "CLOCKQAM-INVALID!";
757 break;
758 }
759 break;
760 case VSB_8:
761 if (val & (1 << 7)) {
762 *locked = 1;
763 cr_lock_state = "CLOCKVSB";
764 }
765 break;
766 default:
767 ret = -EINVAL;
768 }
769 lg_dbg("(%d) %s\n", *locked, cr_lock_state);
770fail:
771 return ret;
772}
773
774static int lgdt3305_read_fec_lock_status(struct lgdt3305_state *state,
775 int *locked)
776{
777 u8 val;
778 int ret, mpeg_lock, fec_lock, viterbi_lock;
779
780 *locked = 0;
781
782 switch (state->current_modulation) {
783 case QAM_256:
784 case QAM_64:
785 ret = lgdt3305_read_reg(state,
786 LGDT3305_FEC_LOCK_STATUS, &val);
787 if (lg_fail(ret))
788 goto fail;
789
790 mpeg_lock = (val & (1 << 0)) ? 1 : 0;
791 fec_lock = (val & (1 << 2)) ? 1 : 0;
792 viterbi_lock = (val & (1 << 3)) ? 1 : 0;
793
794 *locked = mpeg_lock && fec_lock && viterbi_lock;
795
796 lg_dbg("(%d) %s%s%s\n", *locked,
797 mpeg_lock ? "mpeg lock " : "",
798 fec_lock ? "fec lock " : "",
799 viterbi_lock ? "viterbi lock" : "");
800 break;
801 case VSB_8:
802 default:
803 ret = -EINVAL;
804 }
805fail:
806 return ret;
807}
808
809static int lgdt3305_read_status(struct dvb_frontend *fe, fe_status_t *status)
810{
811 struct lgdt3305_state *state = fe->demodulator_priv;
812 u8 val;
813 int ret, signal, inlock, nofecerr, snrgood,
814 cr_lock, fec_lock, sync_lock;
815
816 *status = 0;
817
818 ret = lgdt3305_read_reg(state, LGDT3305_GEN_STATUS, &val);
819 if (lg_fail(ret))
820 goto fail;
821
822 signal = (val & (1 << 4)) ? 1 : 0;
823 inlock = (val & (1 << 3)) ? 0 : 1;
824 sync_lock = (val & (1 << 2)) ? 1 : 0;
825 nofecerr = (val & (1 << 1)) ? 1 : 0;
826 snrgood = (val & (1 << 0)) ? 1 : 0;
827
828 lg_dbg("%s%s%s%s%s\n",
829 signal ? "SIGNALEXIST " : "",
830 inlock ? "INLOCK " : "",
831 sync_lock ? "SYNCLOCK " : "",
832 nofecerr ? "NOFECERR " : "",
833 snrgood ? "SNRGOOD " : "");
834
835 ret = lgdt3305_read_cr_lock_status(state, &cr_lock);
836 if (lg_fail(ret))
837 goto fail;
838
839 if (signal)
840 *status |= FE_HAS_SIGNAL;
841 if (cr_lock)
842 *status |= FE_HAS_CARRIER;
843 if (nofecerr)
844 *status |= FE_HAS_VITERBI;
845 if (sync_lock)
846 *status |= FE_HAS_SYNC;
847
848 switch (state->current_modulation) {
849 case QAM_256:
850 case QAM_64:
851 ret = lgdt3305_read_fec_lock_status(state, &fec_lock);
852 if (lg_fail(ret))
853 goto fail;
854
855 if (fec_lock)
856 *status |= FE_HAS_LOCK;
857 break;
858 case VSB_8:
859 if (inlock)
860 *status |= FE_HAS_LOCK;
861 break;
862 default:
863 ret = -EINVAL;
864 }
865fail:
866 return ret;
867}
868
869/* ------------------------------------------------------------------------ */
870
871/* borrowed from lgdt330x.c */
872static u32 calculate_snr(u32 mse, u32 c)
873{
874 if (mse == 0) /* no signal */
875 return 0;
876
877 mse = intlog10(mse);
878 if (mse > c) {
879 /* Negative SNR, which is possible, but realisticly the
880 demod will lose lock before the signal gets this bad. The
881 API only allows for unsigned values, so just return 0 */
882 return 0;
883 }
884 return 10*(c - mse);
885}
886
887static int lgdt3305_read_snr(struct dvb_frontend *fe, u16 *snr)
888{
889 struct lgdt3305_state *state = fe->demodulator_priv;
890 u32 noise; /* noise value */
891 u32 c; /* per-modulation SNR calculation constant */
892
893 switch (state->current_modulation) {
894 case VSB_8:
895#ifdef USE_PTMSE
896 /* Use Phase Tracker Mean-Square Error Register */
897 /* SNR for ranges from -13.11 to +44.08 */
898 noise = ((read_reg(state, LGDT3305_PT_MSE_1) & 0x07) << 16) |
899 (read_reg(state, LGDT3305_PT_MSE_2) << 8) |
900 (read_reg(state, LGDT3305_PT_MSE_3) & 0xff);
901 c = 73957994; /* log10(25*32^2)*2^24 */
902#else
903 /* Use Equalizer Mean-Square Error Register */
904 /* SNR for ranges from -16.12 to +44.08 */
905 noise = ((read_reg(state, LGDT3305_EQ_MSE_1) & 0x0f) << 16) |
906 (read_reg(state, LGDT3305_EQ_MSE_2) << 8) |
907 (read_reg(state, LGDT3305_EQ_MSE_3) & 0xff);
908 c = 73957994; /* log10(25*32^2)*2^24 */
909#endif
910 break;
911 case QAM_64:
912 case QAM_256:
913 noise = (read_reg(state, LGDT3305_CR_MSE_1) << 8) |
914 (read_reg(state, LGDT3305_CR_MSE_2) & 0xff);
915
916 c = (state->current_modulation == QAM_64) ?
917 97939837 : 98026066;
918 /* log10(688128)*2^24 and log10(696320)*2^24 */
919 break;
920 default:
921 return -EINVAL;
922 }
923 state->snr = calculate_snr(noise, c);
60ce3c47 924 /* report SNR in dB * 10 */
cae78ed5
MK		 925 *snr = (state->snr / ((1 << 24) / 10));
926 lg_dbg("noise = 0x%08x, snr = %d.%02d dB\n", noise,
927 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
928
929 return 0;
930}
931
932static int lgdt3305_read_signal_strength(struct dvb_frontend *fe,
933 u16 *strength)
934{
935 /* borrowed from lgdt330x.c
936 *
937 * Calculate strength from SNR up to 35dB
938 * Even though the SNR can go higher than 35dB,
939 * there is some comfort factor in having a range of
940 * strong signals that can show at 100%
941 */
942 struct lgdt3305_state *state = fe->demodulator_priv;
943 u16 snr;
944 int ret;
945
946 *strength = 0;
947
948 ret = fe->ops.read_snr(fe, &snr);
949 if (lg_fail(ret))
950 goto fail;
951 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
952 /* scale the range 0 - 35*2^24 into 0 - 65535 */
953 if (state->snr >= 8960 * 0x10000)
954 *strength = 0xffff;
955 else
956 *strength = state->snr / 8960;
957fail:
958 return ret;
959}
960
961/* ------------------------------------------------------------------------ */
962
963static int lgdt3305_read_ber(struct dvb_frontend *fe, u32 *ber)
964{
965 *ber = 0;
966 return 0;
967}
968
969static int lgdt3305_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
970{
971 struct lgdt3305_state *state = fe->demodulator_priv;
972
973 *ucblocks =
974 (read_reg(state, LGDT3305_FEC_PKT_ERR_1) << 8) |
975 (read_reg(state, LGDT3305_FEC_PKT_ERR_2) & 0xff);
976
977 return 0;
978}
979
980static int lgdt3305_get_tune_settings(struct dvb_frontend *fe,
981 struct dvb_frontend_tune_settings
982 *fe_tune_settings)
983{
984 fe_tune_settings->min_delay_ms = 500;
985 lg_dbg("\n");
986 return 0;
987}
988
989static void lgdt3305_release(struct dvb_frontend *fe)
990{
991 struct lgdt3305_state *state = fe->demodulator_priv;
992 lg_dbg("\n");
993 kfree(state);
994}
995
996static struct dvb_frontend_ops lgdt3305_ops;
997
998struct dvb_frontend *lgdt3305_attach(const struct lgdt3305_config *config,
999 struct i2c_adapter *i2c_adap)
1000{
1001 struct lgdt3305_state *state = NULL;
1002 int ret;
1003 u8 val;
1004
1005 lg_dbg("(%d-%04x)\n",
1006 i2c_adap ? i2c_adapter_id(i2c_adap) : 0,
1007 config ? config->i2c_addr : 0);
1008
1009 state = kzalloc(sizeof(struct lgdt3305_state), GFP_KERNEL);
1010 if (state == NULL)
1011 goto fail;
1012
1013 state->cfg = config;
1014 state->i2c_adap = i2c_adap;
1015
1016 memcpy(&state->frontend.ops, &lgdt3305_ops,
1017 sizeof(struct dvb_frontend_ops));
1018 state->frontend.demodulator_priv = state;
1019
1020 /* verify that we're talking to a lg dt3305 */
1021 ret = lgdt3305_read_reg(state, LGDT3305_GEN_CTRL_2, &val);
1022 if ((lg_fail(ret)) | (val == 0))
1023 goto fail;
1024 ret = lgdt3305_write_reg(state, 0x0808, 0x80);
1025 if (lg_fail(ret))
1026 goto fail;
1027 ret = lgdt3305_read_reg(state, 0x0808, &val);
1028 if ((lg_fail(ret)) | (val != 0x80))
1029 goto fail;
1030 ret = lgdt3305_write_reg(state, 0x0808, 0x00);
1031 if (lg_fail(ret))
1032 goto fail;
1033
1034 state->current_frequency = -1;
1035 state->current_modulation = -1;
1036
1037 return &state->frontend;
1038fail:
1039 lg_warn("unable to detect LGDT3305 hardware\n");
cae78ed5
MK		 1040 kfree(state);
1041 return NULL;
1042}
1043EXPORT_SYMBOL(lgdt3305_attach);
1044
1045static struct dvb_frontend_ops lgdt3305_ops = {
1046 .info = {
1047 .name = "LG Electronics LGDT3305 VSB/QAM Frontend",
1048 .type = FE_ATSC,
1049 .frequency_min = 54000000,
1050 .frequency_max = 858000000,
1051 .frequency_stepsize = 62500,
1052 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
1053 },
1054 .i2c_gate_ctrl = lgdt3305_i2c_gate_ctrl,
1055 .init = lgdt3305_init,
1056 .sleep = lgdt3305_sleep,
1057 .set_frontend = lgdt3305_set_parameters,
1058 .get_frontend = lgdt3305_get_frontend,
1059 .get_tune_settings = lgdt3305_get_tune_settings,
1060 .read_status = lgdt3305_read_status,
1061 .read_ber = lgdt3305_read_ber,
1062 .read_signal_strength = lgdt3305_read_signal_strength,
1063 .read_snr = lgdt3305_read_snr,
1064 .read_ucblocks = lgdt3305_read_ucblocks,
1065 .release = lgdt3305_release,
1066};
1067
1068MODULE_DESCRIPTION("LG Electronics LGDT3305 ATSC/QAM-B Demodulator Driver");
1c12148b 1069MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
cae78ed5 1070MODULE_LICENSE("GPL");
0290152c 1071MODULE_VERSION("0.1");
cae78ed5
MK		 1072
1073/*
1074 * Local variables:
1075 * c-basic-offset: 8
1076 * End:
1077 */
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