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Commit | Line | Data |
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d8667cbb | 1 | /* |
1963c907 | 2 | * Support for LGDT3302 and LGDT3303 - VSB/QAM |
d8667cbb MM |
3 | * |
4 | * Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net> | |
5 | * | |
d8667cbb MM |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | */ | |
21 | ||
22 | /* | |
23 | * NOTES ABOUT THIS DRIVER | |
24 | * | |
1963c907 MK |
25 | * This Linux driver supports: |
26 | * DViCO FusionHDTV 3 Gold-Q | |
27 | * DViCO FusionHDTV 3 Gold-T | |
28 | * DViCO FusionHDTV 5 Gold | |
3cff00d9 | 29 | * DViCO FusionHDTV 5 Lite |
d8e6acf2 | 30 | * DViCO FusionHDTV 5 USB Gold |
c0b11b91 | 31 | * Air2PC/AirStar 2 ATSC 3rd generation (HD5000) |
20fe4f65 | 32 | * pcHDTV HD5500 |
d8667cbb | 33 | * |
d8667cbb MM |
34 | */ |
35 | ||
d8667cbb MM |
36 | #include <linux/kernel.h> |
37 | #include <linux/module.h> | |
38 | #include <linux/moduleparam.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/delay.h> | |
4e57b681 TS |
41 | #include <linux/string.h> |
42 | #include <linux/slab.h> | |
d8667cbb MM |
43 | #include <asm/byteorder.h> |
44 | ||
45 | #include "dvb_frontend.h" | |
19be685a | 46 | #include "dvb_math.h" |
6ddcc919 MK |
47 | #include "lgdt330x_priv.h" |
48 | #include "lgdt330x.h" | |
d8667cbb | 49 | |
19be685a TP |
50 | /* Use Equalizer Mean Squared Error instead of Phaser Tracker MSE */ |
51 | /* #define USE_EQMSE */ | |
52 | ||
d8667cbb MM |
53 | static int debug = 0; |
54 | module_param(debug, int, 0644); | |
6ddcc919 | 55 | MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off)."); |
d8667cbb MM |
56 | #define dprintk(args...) \ |
57 | do { \ | |
6ddcc919 | 58 | if (debug) printk(KERN_DEBUG "lgdt330x: " args); \ |
d8667cbb MM |
59 | } while (0) |
60 | ||
6ddcc919 | 61 | struct lgdt330x_state |
d8667cbb MM |
62 | { |
63 | struct i2c_adapter* i2c; | |
d8667cbb MM |
64 | |
65 | /* Configuration settings */ | |
6ddcc919 | 66 | const struct lgdt330x_config* config; |
d8667cbb MM |
67 | |
68 | struct dvb_frontend frontend; | |
69 | ||
70 | /* Demodulator private data */ | |
71 | fe_modulation_t current_modulation; | |
19be685a | 72 | u32 snr; /* Result of last SNR calculation */ |
d8667cbb MM |
73 | |
74 | /* Tuner private data */ | |
75 | u32 current_frequency; | |
76 | }; | |
77 | ||
1963c907 | 78 | static int i2c_write_demod_bytes (struct lgdt330x_state* state, |
dc9ca2af MK |
79 | u8 *buf, /* data bytes to send */ |
80 | int len /* number of bytes to send */ ) | |
d8667cbb | 81 | { |
b6aef071 | 82 | struct i2c_msg msg = |
1963c907 MK |
83 | { .addr = state->config->demod_address, |
84 | .flags = 0, | |
85 | .buf = buf, | |
86 | .len = 2 }; | |
b6aef071 | 87 | int i; |
1963c907 | 88 | int err; |
d8667cbb | 89 | |
1963c907 | 90 | for (i=0; i<len-1; i+=2){ |
d8667cbb | 91 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
1963c907 | 92 | printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __FUNCTION__, msg.buf[0], msg.buf[1], err); |
58ba006b MK |
93 | if (err < 0) |
94 | return err; | |
95 | else | |
96 | return -EREMOTEIO; | |
d8667cbb | 97 | } |
1963c907 | 98 | msg.buf += 2; |
d8667cbb MM |
99 | } |
100 | return 0; | |
101 | } | |
102 | ||
103 | /* | |
104 | * This routine writes the register (reg) to the demod bus | |
105 | * then reads the data returned for (len) bytes. | |
106 | */ | |
107 | ||
1963c907 | 108 | static u8 i2c_read_demod_bytes (struct lgdt330x_state* state, |
d8667cbb MM |
109 | enum I2C_REG reg, u8* buf, int len) |
110 | { | |
111 | u8 wr [] = { reg }; | |
112 | struct i2c_msg msg [] = { | |
113 | { .addr = state->config->demod_address, | |
114 | .flags = 0, .buf = wr, .len = 1 }, | |
115 | { .addr = state->config->demod_address, | |
116 | .flags = I2C_M_RD, .buf = buf, .len = len }, | |
117 | }; | |
118 | int ret; | |
119 | ret = i2c_transfer(state->i2c, msg, 2); | |
120 | if (ret != 2) { | |
6ddcc919 | 121 | printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __FUNCTION__, state->config->demod_address, reg, ret); |
d8667cbb MM |
122 | } else { |
123 | ret = 0; | |
124 | } | |
125 | return ret; | |
126 | } | |
127 | ||
128 | /* Software reset */ | |
1963c907 | 129 | static int lgdt3302_SwReset(struct lgdt330x_state* state) |
d8667cbb MM |
130 | { |
131 | u8 ret; | |
132 | u8 reset[] = { | |
133 | IRQ_MASK, | |
134 | 0x00 /* bit 6 is active low software reset | |
135 | * bits 5-0 are 1 to mask interrupts */ | |
136 | }; | |
137 | ||
1963c907 | 138 | ret = i2c_write_demod_bytes(state, |
dc9ca2af | 139 | reset, sizeof(reset)); |
d8667cbb | 140 | if (ret == 0) { |
1963c907 MK |
141 | |
142 | /* force reset high (inactive) and unmask interrupts */ | |
143 | reset[1] = 0x7f; | |
144 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 145 | reset, sizeof(reset)); |
d8667cbb | 146 | } |
d8667cbb MM |
147 | return ret; |
148 | } | |
149 | ||
1963c907 MK |
150 | static int lgdt3303_SwReset(struct lgdt330x_state* state) |
151 | { | |
152 | u8 ret; | |
153 | u8 reset[] = { | |
154 | 0x02, | |
155 | 0x00 /* bit 0 is active low software reset */ | |
156 | }; | |
157 | ||
158 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 159 | reset, sizeof(reset)); |
1963c907 MK |
160 | if (ret == 0) { |
161 | ||
162 | /* force reset high (inactive) */ | |
163 | reset[1] = 0x01; | |
164 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 165 | reset, sizeof(reset)); |
1963c907 MK |
166 | } |
167 | return ret; | |
168 | } | |
169 | ||
170 | static int lgdt330x_SwReset(struct lgdt330x_state* state) | |
171 | { | |
172 | switch (state->config->demod_chip) { | |
173 | case LGDT3302: | |
174 | return lgdt3302_SwReset(state); | |
175 | case LGDT3303: | |
176 | return lgdt3303_SwReset(state); | |
177 | default: | |
178 | return -ENODEV; | |
179 | } | |
180 | } | |
181 | ||
6ddcc919 | 182 | static int lgdt330x_init(struct dvb_frontend* fe) |
d8667cbb MM |
183 | { |
184 | /* Hardware reset is done using gpio[0] of cx23880x chip. | |
185 | * I'd like to do it here, but don't know how to find chip address. | |
186 | * cx88-cards.c arranges for the reset bit to be inactive (high). | |
187 | * Maybe there needs to be a callable function in cx88-core or | |
188 | * the caller of this function needs to do it. */ | |
189 | ||
1963c907 MK |
190 | /* |
191 | * Array of byte pairs <address, value> | |
192 | * to initialize each different chip | |
193 | */ | |
194 | static u8 lgdt3302_init_data[] = { | |
195 | /* Use 50MHz parameter values from spec sheet since xtal is 50 */ | |
196 | /* Change the value of NCOCTFV[25:0] of carrier | |
197 | recovery center frequency register */ | |
198 | VSB_CARRIER_FREQ0, 0x00, | |
199 | VSB_CARRIER_FREQ1, 0x87, | |
200 | VSB_CARRIER_FREQ2, 0x8e, | |
201 | VSB_CARRIER_FREQ3, 0x01, | |
202 | /* Change the TPCLK pin polarity | |
203 | data is valid on falling clock */ | |
204 | DEMUX_CONTROL, 0xfb, | |
205 | /* Change the value of IFBW[11:0] of | |
206 | AGC IF/RF loop filter bandwidth register */ | |
207 | AGC_RF_BANDWIDTH0, 0x40, | |
208 | AGC_RF_BANDWIDTH1, 0x93, | |
209 | AGC_RF_BANDWIDTH2, 0x00, | |
210 | /* Change the value of bit 6, 'nINAGCBY' and | |
211 | 'NSSEL[1:0] of ACG function control register 2 */ | |
212 | AGC_FUNC_CTRL2, 0xc6, | |
213 | /* Change the value of bit 6 'RFFIX' | |
214 | of AGC function control register 3 */ | |
215 | AGC_FUNC_CTRL3, 0x40, | |
216 | /* Set the value of 'INLVTHD' register 0x2a/0x2c | |
217 | to 0x7fe */ | |
218 | AGC_DELAY0, 0x07, | |
219 | AGC_DELAY2, 0xfe, | |
220 | /* Change the value of IAGCBW[15:8] | |
9aaeded7 | 221 | of inner AGC loop filter bandwidth */ |
1963c907 MK |
222 | AGC_LOOP_BANDWIDTH0, 0x08, |
223 | AGC_LOOP_BANDWIDTH1, 0x9a | |
224 | }; | |
225 | ||
226 | static u8 lgdt3303_init_data[] = { | |
227 | 0x4c, 0x14 | |
228 | }; | |
229 | ||
c0b11b91 MK |
230 | static u8 flip_lgdt3303_init_data[] = { |
231 | 0x4c, 0x14, | |
232 | 0x87, 0xf3 | |
233 | }; | |
234 | ||
1963c907 MK |
235 | struct lgdt330x_state* state = fe->demodulator_priv; |
236 | char *chip_name; | |
237 | int err; | |
238 | ||
239 | switch (state->config->demod_chip) { | |
240 | case LGDT3302: | |
241 | chip_name = "LGDT3302"; | |
242 | err = i2c_write_demod_bytes(state, lgdt3302_init_data, | |
dc9ca2af MK |
243 | sizeof(lgdt3302_init_data)); |
244 | break; | |
1963c907 MK |
245 | case LGDT3303: |
246 | chip_name = "LGDT3303"; | |
c0b11b91 MK |
247 | if (state->config->clock_polarity_flip) { |
248 | err = i2c_write_demod_bytes(state, flip_lgdt3303_init_data, | |
249 | sizeof(flip_lgdt3303_init_data)); | |
250 | } else { | |
251 | err = i2c_write_demod_bytes(state, lgdt3303_init_data, | |
252 | sizeof(lgdt3303_init_data)); | |
253 | } | |
dc9ca2af | 254 | break; |
1963c907 MK |
255 | default: |
256 | chip_name = "undefined"; | |
257 | printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n"); | |
258 | err = -ENODEV; | |
259 | } | |
260 | dprintk("%s entered as %s\n", __FUNCTION__, chip_name); | |
261 | if (err < 0) | |
262 | return err; | |
263 | return lgdt330x_SwReset(state); | |
d8667cbb MM |
264 | } |
265 | ||
6ddcc919 | 266 | static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber) |
d8667cbb | 267 | { |
1963c907 | 268 | *ber = 0; /* Not supplied by the demod chips */ |
d8667cbb MM |
269 | return 0; |
270 | } | |
271 | ||
6ddcc919 | 272 | static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) |
d8667cbb | 273 | { |
1963c907 MK |
274 | struct lgdt330x_state* state = fe->demodulator_priv; |
275 | int err; | |
d8667cbb MM |
276 | u8 buf[2]; |
277 | ||
1963c907 MK |
278 | switch (state->config->demod_chip) { |
279 | case LGDT3302: | |
280 | err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1, | |
dc9ca2af MK |
281 | buf, sizeof(buf)); |
282 | break; | |
1963c907 MK |
283 | case LGDT3303: |
284 | err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1, | |
dc9ca2af MK |
285 | buf, sizeof(buf)); |
286 | break; | |
1963c907 MK |
287 | default: |
288 | printk(KERN_WARNING | |
dc9ca2af | 289 | "Only LGDT3302 and LGDT3303 are supported chips.\n"); |
1963c907 MK |
290 | err = -ENODEV; |
291 | } | |
d8667cbb MM |
292 | |
293 | *ucblocks = (buf[0] << 8) | buf[1]; | |
294 | return 0; | |
295 | } | |
296 | ||
6ddcc919 | 297 | static int lgdt330x_set_parameters(struct dvb_frontend* fe, |
d8667cbb MM |
298 | struct dvb_frontend_parameters *param) |
299 | { | |
1963c907 MK |
300 | /* |
301 | * Array of byte pairs <address, value> | |
302 | * to initialize 8VSB for lgdt3303 chip 50 MHz IF | |
303 | */ | |
304 | static u8 lgdt3303_8vsb_44_data[] = { | |
305 | 0x04, 0x00, | |
306 | 0x0d, 0x40, | |
9101e622 MCC |
307 | 0x0e, 0x87, |
308 | 0x0f, 0x8e, | |
309 | 0x10, 0x01, | |
310 | 0x47, 0x8b }; | |
1963c907 MK |
311 | |
312 | /* | |
313 | * Array of byte pairs <address, value> | |
314 | * to initialize QAM for lgdt3303 chip | |
315 | */ | |
316 | static u8 lgdt3303_qam_data[] = { | |
317 | 0x04, 0x00, | |
318 | 0x0d, 0x00, | |
319 | 0x0e, 0x00, | |
320 | 0x0f, 0x00, | |
321 | 0x10, 0x00, | |
322 | 0x51, 0x63, | |
323 | 0x47, 0x66, | |
324 | 0x48, 0x66, | |
325 | 0x4d, 0x1a, | |
326 | 0x49, 0x08, | |
327 | 0x4a, 0x9b }; | |
328 | ||
329 | struct lgdt330x_state* state = fe->demodulator_priv; | |
d8667cbb | 330 | |
d8667cbb | 331 | static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 }; |
d8667cbb | 332 | |
1963c907 | 333 | int err; |
d8667cbb MM |
334 | /* Change only if we are actually changing the modulation */ |
335 | if (state->current_modulation != param->u.vsb.modulation) { | |
336 | switch(param->u.vsb.modulation) { | |
337 | case VSB_8: | |
338 | dprintk("%s: VSB_8 MODE\n", __FUNCTION__); | |
339 | ||
1963c907 MK |
340 | /* Select VSB mode */ |
341 | top_ctrl_cfg[1] = 0x03; | |
0ccef6db MK |
342 | |
343 | /* Select ANT connector if supported by card */ | |
344 | if (state->config->pll_rf_set) | |
345 | state->config->pll_rf_set(fe, 1); | |
1963c907 MK |
346 | |
347 | if (state->config->demod_chip == LGDT3303) { | |
348 | err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data, | |
dc9ca2af | 349 | sizeof(lgdt3303_8vsb_44_data)); |
1963c907 | 350 | } |
d8667cbb MM |
351 | break; |
352 | ||
353 | case QAM_64: | |
354 | dprintk("%s: QAM_64 MODE\n", __FUNCTION__); | |
355 | ||
1963c907 MK |
356 | /* Select QAM_64 mode */ |
357 | top_ctrl_cfg[1] = 0x00; | |
0ccef6db MK |
358 | |
359 | /* Select CABLE connector if supported by card */ | |
360 | if (state->config->pll_rf_set) | |
361 | state->config->pll_rf_set(fe, 0); | |
1963c907 MK |
362 | |
363 | if (state->config->demod_chip == LGDT3303) { | |
364 | err = i2c_write_demod_bytes(state, lgdt3303_qam_data, | |
365 | sizeof(lgdt3303_qam_data)); | |
366 | } | |
d8667cbb MM |
367 | break; |
368 | ||
369 | case QAM_256: | |
370 | dprintk("%s: QAM_256 MODE\n", __FUNCTION__); | |
371 | ||
1963c907 MK |
372 | /* Select QAM_256 mode */ |
373 | top_ctrl_cfg[1] = 0x01; | |
0ccef6db MK |
374 | |
375 | /* Select CABLE connector if supported by card */ | |
376 | if (state->config->pll_rf_set) | |
377 | state->config->pll_rf_set(fe, 0); | |
1963c907 MK |
378 | |
379 | if (state->config->demod_chip == LGDT3303) { | |
380 | err = i2c_write_demod_bytes(state, lgdt3303_qam_data, | |
381 | sizeof(lgdt3303_qam_data)); | |
382 | } | |
d8667cbb MM |
383 | break; |
384 | default: | |
6ddcc919 | 385 | printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __FUNCTION__, param->u.vsb.modulation); |
d8667cbb MM |
386 | return -1; |
387 | } | |
1963c907 MK |
388 | /* |
389 | * select serial or parallel MPEG harware interface | |
390 | * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303 | |
391 | * Parallel: 0x00 | |
392 | */ | |
393 | top_ctrl_cfg[1] |= state->config->serial_mpeg; | |
d8667cbb MM |
394 | |
395 | /* Select the requested mode */ | |
1963c907 | 396 | i2c_write_demod_bytes(state, top_ctrl_cfg, |
dc9ca2af MK |
397 | sizeof(top_ctrl_cfg)); |
398 | if (state->config->set_ts_params) | |
399 | state->config->set_ts_params(fe, 0); | |
d8667cbb MM |
400 | state->current_modulation = param->u.vsb.modulation; |
401 | } | |
d8667cbb | 402 | |
dc9ca2af | 403 | /* Tune to the specified frequency */ |
dea74869 PB |
404 | if (fe->ops.tuner_ops.set_params) { |
405 | fe->ops.tuner_ops.set_params(fe, param); | |
406 | if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); | |
02269f37 | 407 | } |
dc9ca2af MK |
408 | |
409 | /* Keep track of the new frequency */ | |
4302c15e MCC |
410 | /* FIXME this is the wrong way to do this... */ |
411 | /* The tuner is shared with the video4linux analog API */ | |
dc9ca2af MK |
412 | state->current_frequency = param->frequency; |
413 | ||
6ddcc919 | 414 | lgdt330x_SwReset(state); |
d8667cbb MM |
415 | return 0; |
416 | } | |
417 | ||
6ddcc919 | 418 | static int lgdt330x_get_frontend(struct dvb_frontend* fe, |
d8667cbb MM |
419 | struct dvb_frontend_parameters* param) |
420 | { | |
6ddcc919 | 421 | struct lgdt330x_state *state = fe->demodulator_priv; |
d8667cbb MM |
422 | param->frequency = state->current_frequency; |
423 | return 0; | |
424 | } | |
425 | ||
1963c907 | 426 | static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status) |
d8667cbb | 427 | { |
1963c907 | 428 | struct lgdt330x_state* state = fe->demodulator_priv; |
d8667cbb MM |
429 | u8 buf[3]; |
430 | ||
431 | *status = 0; /* Reset status result */ | |
432 | ||
08d80525 | 433 | /* AGC status register */ |
1963c907 | 434 | i2c_read_demod_bytes(state, AGC_STATUS, buf, 1); |
08d80525 MK |
435 | dprintk("%s: AGC_STATUS = 0x%02x\n", __FUNCTION__, buf[0]); |
436 | if ((buf[0] & 0x0c) == 0x8){ | |
437 | /* Test signal does not exist flag */ | |
438 | /* as well as the AGC lock flag. */ | |
439 | *status |= FE_HAS_SIGNAL; | |
08d80525 MK |
440 | } |
441 | ||
1963c907 MK |
442 | /* |
443 | * You must set the Mask bits to 1 in the IRQ_MASK in order | |
444 | * to see that status bit in the IRQ_STATUS register. | |
445 | * This is done in SwReset(); | |
446 | */ | |
d8667cbb | 447 | /* signal status */ |
1963c907 | 448 | i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf)); |
d8667cbb | 449 | dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __FUNCTION__, buf[0], buf[1], buf[2]); |
08d80525 | 450 | |
d8667cbb MM |
451 | |
452 | /* sync status */ | |
453 | if ((buf[2] & 0x03) == 0x01) { | |
454 | *status |= FE_HAS_SYNC; | |
455 | } | |
456 | ||
457 | /* FEC error status */ | |
458 | if ((buf[2] & 0x0c) == 0x08) { | |
459 | *status |= FE_HAS_LOCK; | |
460 | *status |= FE_HAS_VITERBI; | |
461 | } | |
462 | ||
d8667cbb | 463 | /* Carrier Recovery Lock Status Register */ |
1963c907 | 464 | i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); |
d8667cbb MM |
465 | dprintk("%s: CARRIER_LOCK = 0x%02x\n", __FUNCTION__, buf[0]); |
466 | switch (state->current_modulation) { | |
467 | case QAM_256: | |
468 | case QAM_64: | |
469 | /* Need to undestand why there are 3 lock levels here */ | |
470 | if ((buf[0] & 0x07) == 0x07) | |
471 | *status |= FE_HAS_CARRIER; | |
d8667cbb | 472 | break; |
d8667cbb MM |
473 | case VSB_8: |
474 | if ((buf[0] & 0x80) == 0x80) | |
475 | *status |= FE_HAS_CARRIER; | |
d8667cbb | 476 | break; |
d8667cbb | 477 | default: |
6ddcc919 | 478 | printk("KERN_WARNING lgdt330x: %s: Modulation set to unsupported value\n", __FUNCTION__); |
d8667cbb | 479 | } |
d8667cbb MM |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
1963c907 MK |
484 | static int lgdt3303_read_status(struct dvb_frontend* fe, fe_status_t* status) |
485 | { | |
486 | struct lgdt330x_state* state = fe->demodulator_priv; | |
487 | int err; | |
488 | u8 buf[3]; | |
489 | ||
490 | *status = 0; /* Reset status result */ | |
491 | ||
492 | /* lgdt3303 AGC status register */ | |
493 | err = i2c_read_demod_bytes(state, 0x58, buf, 1); | |
494 | if (err < 0) | |
495 | return err; | |
496 | ||
497 | dprintk("%s: AGC_STATUS = 0x%02x\n", __FUNCTION__, buf[0]); | |
498 | if ((buf[0] & 0x21) == 0x01){ | |
499 | /* Test input signal does not exist flag */ | |
500 | /* as well as the AGC lock flag. */ | |
501 | *status |= FE_HAS_SIGNAL; | |
1963c907 MK |
502 | } |
503 | ||
504 | /* Carrier Recovery Lock Status Register */ | |
505 | i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); | |
506 | dprintk("%s: CARRIER_LOCK = 0x%02x\n", __FUNCTION__, buf[0]); | |
507 | switch (state->current_modulation) { | |
508 | case QAM_256: | |
509 | case QAM_64: | |
510 | /* Need to undestand why there are 3 lock levels here */ | |
511 | if ((buf[0] & 0x07) == 0x07) | |
512 | *status |= FE_HAS_CARRIER; | |
513 | else | |
514 | break; | |
515 | i2c_read_demod_bytes(state, 0x8a, buf, 1); | |
516 | if ((buf[0] & 0x04) == 0x04) | |
517 | *status |= FE_HAS_SYNC; | |
518 | if ((buf[0] & 0x01) == 0x01) | |
519 | *status |= FE_HAS_LOCK; | |
520 | if ((buf[0] & 0x08) == 0x08) | |
521 | *status |= FE_HAS_VITERBI; | |
522 | break; | |
523 | case VSB_8: | |
524 | if ((buf[0] & 0x80) == 0x80) | |
525 | *status |= FE_HAS_CARRIER; | |
526 | else | |
527 | break; | |
528 | i2c_read_demod_bytes(state, 0x38, buf, 1); | |
529 | if ((buf[0] & 0x02) == 0x00) | |
530 | *status |= FE_HAS_SYNC; | |
531 | if ((buf[0] & 0x01) == 0x01) { | |
532 | *status |= FE_HAS_LOCK; | |
533 | *status |= FE_HAS_VITERBI; | |
534 | } | |
535 | break; | |
536 | default: | |
537 | printk("KERN_WARNING lgdt330x: %s: Modulation set to unsupported value\n", __FUNCTION__); | |
538 | } | |
539 | return 0; | |
540 | } | |
541 | ||
19be685a TP |
542 | /* Calculate SNR estimation (scaled by 2^24) |
543 | ||
544 | 8-VSB SNR equations from LGDT3302 and LGDT3303 datasheets, QAM | |
545 | equations from LGDT3303 datasheet. VSB is the same between the '02 | |
546 | and '03, so maybe QAM is too? Perhaps someone with a newer datasheet | |
547 | that has QAM information could verify? | |
548 | ||
549 | For 8-VSB: (two ways, take your pick) | |
550 | LGDT3302: | |
551 | SNR_EQ = 10 * log10(25 * 24^2 / EQ_MSE) | |
552 | LGDT3303: | |
553 | SNR_EQ = 10 * log10(25 * 32^2 / EQ_MSE) | |
554 | LGDT3302 & LGDT3303: | |
555 | SNR_PT = 10 * log10(25 * 32^2 / PT_MSE) (we use this one) | |
556 | For 64-QAM: | |
557 | SNR = 10 * log10( 688128 / MSEQAM) | |
558 | For 256-QAM: | |
559 | SNR = 10 * log10( 696320 / MSEQAM) | |
560 | ||
561 | We re-write the snr equation as: | |
562 | SNR * 2^24 = 10*(c - intlog10(MSE)) | |
563 | Where for 256-QAM, c = log10(696320) * 2^24, and so on. */ | |
564 | ||
565 | static u32 calculate_snr(u32 mse, u32 c) | |
d8667cbb | 566 | { |
19be685a TP |
567 | if (mse == 0) /* No signal */ |
568 | return 0; | |
569 | ||
570 | mse = intlog10(mse); | |
571 | if (mse > c) { | |
572 | /* Negative SNR, which is possible, but realisticly the | |
573 | demod will lose lock before the signal gets this bad. The | |
574 | API only allows for unsigned values, so just return 0 */ | |
575 | return 0; | |
576 | } | |
577 | return 10*(c - mse); | |
d8667cbb MM |
578 | } |
579 | ||
1963c907 | 580 | static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr) |
d8667cbb | 581 | { |
6ddcc919 | 582 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
19be685a TP |
583 | u8 buf[5]; /* read data buffer */ |
584 | u32 noise; /* noise value */ | |
585 | u32 c; /* per-modulation SNR calculation constant */ | |
d8667cbb | 586 | |
19be685a TP |
587 | switch(state->current_modulation) { |
588 | case VSB_8: | |
589 | i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5); | |
590 | #ifdef USE_EQMSE | |
591 | /* Use Equalizer Mean-Square Error Register */ | |
592 | /* SNR for ranges from -15.61 to +41.58 */ | |
d8667cbb | 593 | noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2]; |
19be685a | 594 | c = 69765745; /* log10(25*24^2)*2^24 */ |
d8667cbb | 595 | #else |
19be685a TP |
596 | /* Use Phase Tracker Mean-Square Error Register */ |
597 | /* SNR for ranges from -13.11 to +44.08 */ | |
d8667cbb | 598 | noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4]; |
19be685a TP |
599 | c = 73957994; /* log10(25*32^2)*2^24 */ |
600 | #endif | |
601 | break; | |
602 | case QAM_64: | |
603 | case QAM_256: | |
604 | i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2); | |
1963c907 | 605 | noise = ((buf[0] & 3) << 8) | buf[1]; |
19be685a TP |
606 | c = state->current_modulation == QAM_64 ? 97939837 : 98026066; |
607 | /* log10(688128)*2^24 and log10(696320)*2^24 */ | |
608 | break; | |
609 | default: | |
610 | printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n", | |
611 | __FUNCTION__); | |
612 | return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */ | |
d8667cbb MM |
613 | } |
614 | ||
19be685a TP |
615 | state->snr = calculate_snr(noise, c); |
616 | *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */ | |
d8667cbb | 617 | |
19be685a TP |
618 | dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __FUNCTION__, noise, |
619 | state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16); | |
d8667cbb MM |
620 | |
621 | return 0; | |
622 | } | |
623 | ||
1963c907 MK |
624 | static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr) |
625 | { | |
1963c907 | 626 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
19be685a TP |
627 | u8 buf[5]; /* read data buffer */ |
628 | u32 noise; /* noise value */ | |
629 | u32 c; /* per-modulation SNR calculation constant */ | |
1963c907 | 630 | |
19be685a TP |
631 | switch(state->current_modulation) { |
632 | case VSB_8: | |
633 | i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5); | |
634 | #ifdef USE_EQMSE | |
635 | /* Use Equalizer Mean-Square Error Register */ | |
636 | /* SNR for ranges from -16.12 to +44.08 */ | |
637 | noise = ((buf[0] & 0x78) << 13) | (buf[1] << 8) | buf[2]; | |
638 | c = 73957994; /* log10(25*32^2)*2^24 */ | |
639 | #else | |
640 | /* Use Phase Tracker Mean-Square Error Register */ | |
641 | /* SNR for ranges from -13.11 to +44.08 */ | |
1963c907 | 642 | noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4]; |
19be685a TP |
643 | c = 73957994; /* log10(25*32^2)*2^24 */ |
644 | #endif | |
645 | break; | |
646 | case QAM_64: | |
647 | case QAM_256: | |
648 | i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2); | |
1963c907 | 649 | noise = (buf[0] << 8) | buf[1]; |
19be685a TP |
650 | c = state->current_modulation == QAM_64 ? 97939837 : 98026066; |
651 | /* log10(688128)*2^24 and log10(696320)*2^24 */ | |
652 | break; | |
653 | default: | |
654 | printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n", | |
655 | __FUNCTION__); | |
656 | return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */ | |
1963c907 MK |
657 | } |
658 | ||
19be685a TP |
659 | state->snr = calculate_snr(noise, c); |
660 | *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */ | |
661 | ||
662 | dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __FUNCTION__, noise, | |
663 | state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16); | |
664 | ||
665 | return 0; | |
666 | } | |
667 | ||
668 | static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength) | |
669 | { | |
670 | /* Calculate Strength from SNR up to 35dB */ | |
671 | /* Even though the SNR can go higher than 35dB, there is some comfort */ | |
672 | /* factor in having a range of strong signals that can show at 100% */ | |
673 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; | |
674 | u16 snr; | |
675 | int ret; | |
1963c907 | 676 | |
19be685a TP |
677 | ret = fe->ops.read_snr(fe, &snr); |
678 | if (ret != 0) | |
679 | return ret; | |
680 | /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */ | |
681 | /* scale the range 0 - 35*2^24 into 0 - 65535 */ | |
682 | if (state->snr >= 8960 * 0x10000) | |
683 | *strength = 0xffff; | |
684 | else | |
685 | *strength = state->snr / 8960; | |
1963c907 MK |
686 | |
687 | return 0; | |
688 | } | |
689 | ||
6ddcc919 | 690 | static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings) |
d8667cbb MM |
691 | { |
692 | /* I have no idea about this - it may not be needed */ | |
693 | fe_tune_settings->min_delay_ms = 500; | |
694 | fe_tune_settings->step_size = 0; | |
695 | fe_tune_settings->max_drift = 0; | |
696 | return 0; | |
697 | } | |
698 | ||
6ddcc919 | 699 | static void lgdt330x_release(struct dvb_frontend* fe) |
d8667cbb | 700 | { |
6ddcc919 | 701 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
d8667cbb MM |
702 | kfree(state); |
703 | } | |
704 | ||
1963c907 MK |
705 | static struct dvb_frontend_ops lgdt3302_ops; |
706 | static struct dvb_frontend_ops lgdt3303_ops; | |
d8667cbb | 707 | |
6ddcc919 | 708 | struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config, |
d8667cbb MM |
709 | struct i2c_adapter* i2c) |
710 | { | |
6ddcc919 | 711 | struct lgdt330x_state* state = NULL; |
d8667cbb MM |
712 | u8 buf[1]; |
713 | ||
714 | /* Allocate memory for the internal state */ | |
7408187d | 715 | state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL); |
d8667cbb MM |
716 | if (state == NULL) |
717 | goto error; | |
d8667cbb MM |
718 | |
719 | /* Setup the state */ | |
720 | state->config = config; | |
721 | state->i2c = i2c; | |
dea74869 PB |
722 | |
723 | /* Create dvb_frontend */ | |
1963c907 MK |
724 | switch (config->demod_chip) { |
725 | case LGDT3302: | |
dea74869 | 726 | memcpy(&state->frontend.ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops)); |
1963c907 MK |
727 | break; |
728 | case LGDT3303: | |
dea74869 | 729 | memcpy(&state->frontend.ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops)); |
1963c907 MK |
730 | break; |
731 | default: | |
732 | goto error; | |
733 | } | |
dea74869 | 734 | state->frontend.demodulator_priv = state; |
1963c907 | 735 | |
d8667cbb | 736 | /* Verify communication with demod chip */ |
1963c907 | 737 | if (i2c_read_demod_bytes(state, 2, buf, 1)) |
d8667cbb MM |
738 | goto error; |
739 | ||
740 | state->current_frequency = -1; | |
741 | state->current_modulation = -1; | |
742 | ||
d8667cbb MM |
743 | return &state->frontend; |
744 | ||
745 | error: | |
2ea75330 | 746 | kfree(state); |
d8667cbb MM |
747 | dprintk("%s: ERROR\n",__FUNCTION__); |
748 | return NULL; | |
749 | } | |
750 | ||
1963c907 MK |
751 | static struct dvb_frontend_ops lgdt3302_ops = { |
752 | .info = { | |
e179d8b0 | 753 | .name= "LG Electronics LGDT3302 VSB/QAM Frontend", |
1963c907 MK |
754 | .type = FE_ATSC, |
755 | .frequency_min= 54000000, | |
756 | .frequency_max= 858000000, | |
757 | .frequency_stepsize= 62500, | |
66944e99 MK |
758 | .symbol_rate_min = 5056941, /* QAM 64 */ |
759 | .symbol_rate_max = 10762000, /* VSB 8 */ | |
1963c907 MK |
760 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB |
761 | }, | |
762 | .init = lgdt330x_init, | |
763 | .set_frontend = lgdt330x_set_parameters, | |
764 | .get_frontend = lgdt330x_get_frontend, | |
765 | .get_tune_settings = lgdt330x_get_tune_settings, | |
766 | .read_status = lgdt3302_read_status, | |
767 | .read_ber = lgdt330x_read_ber, | |
768 | .read_signal_strength = lgdt330x_read_signal_strength, | |
769 | .read_snr = lgdt3302_read_snr, | |
770 | .read_ucblocks = lgdt330x_read_ucblocks, | |
771 | .release = lgdt330x_release, | |
772 | }; | |
773 | ||
774 | static struct dvb_frontend_ops lgdt3303_ops = { | |
d8667cbb | 775 | .info = { |
1963c907 | 776 | .name= "LG Electronics LGDT3303 VSB/QAM Frontend", |
d8667cbb MM |
777 | .type = FE_ATSC, |
778 | .frequency_min= 54000000, | |
779 | .frequency_max= 858000000, | |
780 | .frequency_stepsize= 62500, | |
66944e99 MK |
781 | .symbol_rate_min = 5056941, /* QAM 64 */ |
782 | .symbol_rate_max = 10762000, /* VSB 8 */ | |
d8667cbb MM |
783 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB |
784 | }, | |
6ddcc919 MK |
785 | .init = lgdt330x_init, |
786 | .set_frontend = lgdt330x_set_parameters, | |
787 | .get_frontend = lgdt330x_get_frontend, | |
788 | .get_tune_settings = lgdt330x_get_tune_settings, | |
1963c907 | 789 | .read_status = lgdt3303_read_status, |
6ddcc919 MK |
790 | .read_ber = lgdt330x_read_ber, |
791 | .read_signal_strength = lgdt330x_read_signal_strength, | |
1963c907 | 792 | .read_snr = lgdt3303_read_snr, |
6ddcc919 MK |
793 | .read_ucblocks = lgdt330x_read_ucblocks, |
794 | .release = lgdt330x_release, | |
d8667cbb MM |
795 | }; |
796 | ||
1963c907 | 797 | MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); |
d8667cbb MM |
798 | MODULE_AUTHOR("Wilson Michaels"); |
799 | MODULE_LICENSE("GPL"); | |
800 | ||
6ddcc919 | 801 | EXPORT_SYMBOL(lgdt330x_attach); |
d8667cbb MM |
802 | |
803 | /* | |
804 | * Local variables: | |
805 | * c-basic-offset: 8 | |
d8667cbb MM |
806 | * End: |
807 | */ |