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Commit | Line | Data |
---|---|---|
d8667cbb | 1 | /* |
1963c907 | 2 | * Support for LGDT3302 and LGDT3303 - VSB/QAM |
d8667cbb MM |
3 | * |
4 | * Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net> | |
5 | * | |
d8667cbb MM |
6 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | * | |
20 | */ | |
21 | ||
22 | /* | |
23 | * NOTES ABOUT THIS DRIVER | |
24 | * | |
1963c907 MK |
25 | * This Linux driver supports: |
26 | * DViCO FusionHDTV 3 Gold-Q | |
27 | * DViCO FusionHDTV 3 Gold-T | |
28 | * DViCO FusionHDTV 5 Gold | |
3cff00d9 | 29 | * DViCO FusionHDTV 5 Lite |
d8e6acf2 | 30 | * DViCO FusionHDTV 5 USB Gold |
c0b11b91 | 31 | * Air2PC/AirStar 2 ATSC 3rd generation (HD5000) |
20fe4f65 | 32 | * pcHDTV HD5500 |
d8667cbb MM |
33 | * |
34 | * TODO: | |
1963c907 | 35 | * signal strength always returns 0. |
d8667cbb MM |
36 | * |
37 | */ | |
38 | ||
d8667cbb MM |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/moduleparam.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/delay.h> | |
4e57b681 TS |
44 | #include <linux/string.h> |
45 | #include <linux/slab.h> | |
d8667cbb MM |
46 | #include <asm/byteorder.h> |
47 | ||
48 | #include "dvb_frontend.h" | |
6ddcc919 MK |
49 | #include "lgdt330x_priv.h" |
50 | #include "lgdt330x.h" | |
d8667cbb MM |
51 | |
52 | static int debug = 0; | |
53 | module_param(debug, int, 0644); | |
6ddcc919 | 54 | MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off)."); |
d8667cbb MM |
55 | #define dprintk(args...) \ |
56 | do { \ | |
6ddcc919 | 57 | if (debug) printk(KERN_DEBUG "lgdt330x: " args); \ |
d8667cbb MM |
58 | } while (0) |
59 | ||
6ddcc919 | 60 | struct lgdt330x_state |
d8667cbb MM |
61 | { |
62 | struct i2c_adapter* i2c; | |
63 | struct dvb_frontend_ops ops; | |
64 | ||
65 | /* Configuration settings */ | |
6ddcc919 | 66 | const struct lgdt330x_config* config; |
d8667cbb MM |
67 | |
68 | struct dvb_frontend frontend; | |
69 | ||
70 | /* Demodulator private data */ | |
71 | fe_modulation_t current_modulation; | |
72 | ||
73 | /* Tuner private data */ | |
74 | u32 current_frequency; | |
75 | }; | |
76 | ||
1963c907 | 77 | static int i2c_write_demod_bytes (struct lgdt330x_state* state, |
dc9ca2af MK |
78 | u8 *buf, /* data bytes to send */ |
79 | int len /* number of bytes to send */ ) | |
d8667cbb | 80 | { |
b6aef071 | 81 | struct i2c_msg msg = |
1963c907 MK |
82 | { .addr = state->config->demod_address, |
83 | .flags = 0, | |
84 | .buf = buf, | |
85 | .len = 2 }; | |
b6aef071 | 86 | int i; |
1963c907 | 87 | int err; |
d8667cbb | 88 | |
1963c907 | 89 | for (i=0; i<len-1; i+=2){ |
d8667cbb | 90 | if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) { |
1963c907 | 91 | printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __FUNCTION__, msg.buf[0], msg.buf[1], err); |
58ba006b MK |
92 | if (err < 0) |
93 | return err; | |
94 | else | |
95 | return -EREMOTEIO; | |
d8667cbb | 96 | } |
1963c907 | 97 | msg.buf += 2; |
d8667cbb MM |
98 | } |
99 | return 0; | |
100 | } | |
101 | ||
102 | /* | |
103 | * This routine writes the register (reg) to the demod bus | |
104 | * then reads the data returned for (len) bytes. | |
105 | */ | |
106 | ||
1963c907 | 107 | static u8 i2c_read_demod_bytes (struct lgdt330x_state* state, |
d8667cbb MM |
108 | enum I2C_REG reg, u8* buf, int len) |
109 | { | |
110 | u8 wr [] = { reg }; | |
111 | struct i2c_msg msg [] = { | |
112 | { .addr = state->config->demod_address, | |
113 | .flags = 0, .buf = wr, .len = 1 }, | |
114 | { .addr = state->config->demod_address, | |
115 | .flags = I2C_M_RD, .buf = buf, .len = len }, | |
116 | }; | |
117 | int ret; | |
118 | ret = i2c_transfer(state->i2c, msg, 2); | |
119 | if (ret != 2) { | |
6ddcc919 | 120 | printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __FUNCTION__, state->config->demod_address, reg, ret); |
d8667cbb MM |
121 | } else { |
122 | ret = 0; | |
123 | } | |
124 | return ret; | |
125 | } | |
126 | ||
127 | /* Software reset */ | |
1963c907 | 128 | static int lgdt3302_SwReset(struct lgdt330x_state* state) |
d8667cbb MM |
129 | { |
130 | u8 ret; | |
131 | u8 reset[] = { | |
132 | IRQ_MASK, | |
133 | 0x00 /* bit 6 is active low software reset | |
134 | * bits 5-0 are 1 to mask interrupts */ | |
135 | }; | |
136 | ||
1963c907 | 137 | ret = i2c_write_demod_bytes(state, |
dc9ca2af | 138 | reset, sizeof(reset)); |
d8667cbb | 139 | if (ret == 0) { |
1963c907 MK |
140 | |
141 | /* force reset high (inactive) and unmask interrupts */ | |
142 | reset[1] = 0x7f; | |
143 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 144 | reset, sizeof(reset)); |
d8667cbb | 145 | } |
d8667cbb MM |
146 | return ret; |
147 | } | |
148 | ||
1963c907 MK |
149 | static int lgdt3303_SwReset(struct lgdt330x_state* state) |
150 | { | |
151 | u8 ret; | |
152 | u8 reset[] = { | |
153 | 0x02, | |
154 | 0x00 /* bit 0 is active low software reset */ | |
155 | }; | |
156 | ||
157 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 158 | reset, sizeof(reset)); |
1963c907 MK |
159 | if (ret == 0) { |
160 | ||
161 | /* force reset high (inactive) */ | |
162 | reset[1] = 0x01; | |
163 | ret = i2c_write_demod_bytes(state, | |
dc9ca2af | 164 | reset, sizeof(reset)); |
1963c907 MK |
165 | } |
166 | return ret; | |
167 | } | |
168 | ||
169 | static int lgdt330x_SwReset(struct lgdt330x_state* state) | |
170 | { | |
171 | switch (state->config->demod_chip) { | |
172 | case LGDT3302: | |
173 | return lgdt3302_SwReset(state); | |
174 | case LGDT3303: | |
175 | return lgdt3303_SwReset(state); | |
176 | default: | |
177 | return -ENODEV; | |
178 | } | |
179 | } | |
180 | ||
6ddcc919 | 181 | static int lgdt330x_init(struct dvb_frontend* fe) |
d8667cbb MM |
182 | { |
183 | /* Hardware reset is done using gpio[0] of cx23880x chip. | |
184 | * I'd like to do it here, but don't know how to find chip address. | |
185 | * cx88-cards.c arranges for the reset bit to be inactive (high). | |
186 | * Maybe there needs to be a callable function in cx88-core or | |
187 | * the caller of this function needs to do it. */ | |
188 | ||
1963c907 MK |
189 | /* |
190 | * Array of byte pairs <address, value> | |
191 | * to initialize each different chip | |
192 | */ | |
193 | static u8 lgdt3302_init_data[] = { | |
194 | /* Use 50MHz parameter values from spec sheet since xtal is 50 */ | |
195 | /* Change the value of NCOCTFV[25:0] of carrier | |
196 | recovery center frequency register */ | |
197 | VSB_CARRIER_FREQ0, 0x00, | |
198 | VSB_CARRIER_FREQ1, 0x87, | |
199 | VSB_CARRIER_FREQ2, 0x8e, | |
200 | VSB_CARRIER_FREQ3, 0x01, | |
201 | /* Change the TPCLK pin polarity | |
202 | data is valid on falling clock */ | |
203 | DEMUX_CONTROL, 0xfb, | |
204 | /* Change the value of IFBW[11:0] of | |
205 | AGC IF/RF loop filter bandwidth register */ | |
206 | AGC_RF_BANDWIDTH0, 0x40, | |
207 | AGC_RF_BANDWIDTH1, 0x93, | |
208 | AGC_RF_BANDWIDTH2, 0x00, | |
209 | /* Change the value of bit 6, 'nINAGCBY' and | |
210 | 'NSSEL[1:0] of ACG function control register 2 */ | |
211 | AGC_FUNC_CTRL2, 0xc6, | |
212 | /* Change the value of bit 6 'RFFIX' | |
213 | of AGC function control register 3 */ | |
214 | AGC_FUNC_CTRL3, 0x40, | |
215 | /* Set the value of 'INLVTHD' register 0x2a/0x2c | |
216 | to 0x7fe */ | |
217 | AGC_DELAY0, 0x07, | |
218 | AGC_DELAY2, 0xfe, | |
219 | /* Change the value of IAGCBW[15:8] | |
220 | of inner AGC loop filter bandwith */ | |
221 | AGC_LOOP_BANDWIDTH0, 0x08, | |
222 | AGC_LOOP_BANDWIDTH1, 0x9a | |
223 | }; | |
224 | ||
225 | static u8 lgdt3303_init_data[] = { | |
226 | 0x4c, 0x14 | |
227 | }; | |
228 | ||
c0b11b91 MK |
229 | static u8 flip_lgdt3303_init_data[] = { |
230 | 0x4c, 0x14, | |
231 | 0x87, 0xf3 | |
232 | }; | |
233 | ||
1963c907 MK |
234 | struct lgdt330x_state* state = fe->demodulator_priv; |
235 | char *chip_name; | |
236 | int err; | |
237 | ||
238 | switch (state->config->demod_chip) { | |
239 | case LGDT3302: | |
240 | chip_name = "LGDT3302"; | |
241 | err = i2c_write_demod_bytes(state, lgdt3302_init_data, | |
dc9ca2af MK |
242 | sizeof(lgdt3302_init_data)); |
243 | break; | |
1963c907 MK |
244 | case LGDT3303: |
245 | chip_name = "LGDT3303"; | |
c0b11b91 MK |
246 | if (state->config->clock_polarity_flip) { |
247 | err = i2c_write_demod_bytes(state, flip_lgdt3303_init_data, | |
248 | sizeof(flip_lgdt3303_init_data)); | |
249 | } else { | |
250 | err = i2c_write_demod_bytes(state, lgdt3303_init_data, | |
251 | sizeof(lgdt3303_init_data)); | |
252 | } | |
dc9ca2af | 253 | break; |
1963c907 MK |
254 | default: |
255 | chip_name = "undefined"; | |
256 | printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n"); | |
257 | err = -ENODEV; | |
258 | } | |
259 | dprintk("%s entered as %s\n", __FUNCTION__, chip_name); | |
260 | if (err < 0) | |
261 | return err; | |
262 | return lgdt330x_SwReset(state); | |
d8667cbb MM |
263 | } |
264 | ||
6ddcc919 | 265 | static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber) |
d8667cbb | 266 | { |
1963c907 | 267 | *ber = 0; /* Not supplied by the demod chips */ |
d8667cbb MM |
268 | return 0; |
269 | } | |
270 | ||
6ddcc919 | 271 | static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks) |
d8667cbb | 272 | { |
1963c907 MK |
273 | struct lgdt330x_state* state = fe->demodulator_priv; |
274 | int err; | |
d8667cbb MM |
275 | u8 buf[2]; |
276 | ||
1963c907 MK |
277 | switch (state->config->demod_chip) { |
278 | case LGDT3302: | |
279 | err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1, | |
dc9ca2af MK |
280 | buf, sizeof(buf)); |
281 | break; | |
1963c907 MK |
282 | case LGDT3303: |
283 | err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1, | |
dc9ca2af MK |
284 | buf, sizeof(buf)); |
285 | break; | |
1963c907 MK |
286 | default: |
287 | printk(KERN_WARNING | |
dc9ca2af | 288 | "Only LGDT3302 and LGDT3303 are supported chips.\n"); |
1963c907 MK |
289 | err = -ENODEV; |
290 | } | |
d8667cbb MM |
291 | |
292 | *ucblocks = (buf[0] << 8) | buf[1]; | |
293 | return 0; | |
294 | } | |
295 | ||
6ddcc919 | 296 | static int lgdt330x_set_parameters(struct dvb_frontend* fe, |
d8667cbb MM |
297 | struct dvb_frontend_parameters *param) |
298 | { | |
1963c907 MK |
299 | /* |
300 | * Array of byte pairs <address, value> | |
301 | * to initialize 8VSB for lgdt3303 chip 50 MHz IF | |
302 | */ | |
303 | static u8 lgdt3303_8vsb_44_data[] = { | |
304 | 0x04, 0x00, | |
305 | 0x0d, 0x40, | |
9101e622 MCC |
306 | 0x0e, 0x87, |
307 | 0x0f, 0x8e, | |
308 | 0x10, 0x01, | |
309 | 0x47, 0x8b }; | |
1963c907 MK |
310 | |
311 | /* | |
312 | * Array of byte pairs <address, value> | |
313 | * to initialize QAM for lgdt3303 chip | |
314 | */ | |
315 | static u8 lgdt3303_qam_data[] = { | |
316 | 0x04, 0x00, | |
317 | 0x0d, 0x00, | |
318 | 0x0e, 0x00, | |
319 | 0x0f, 0x00, | |
320 | 0x10, 0x00, | |
321 | 0x51, 0x63, | |
322 | 0x47, 0x66, | |
323 | 0x48, 0x66, | |
324 | 0x4d, 0x1a, | |
325 | 0x49, 0x08, | |
326 | 0x4a, 0x9b }; | |
327 | ||
328 | struct lgdt330x_state* state = fe->demodulator_priv; | |
d8667cbb | 329 | |
d8667cbb | 330 | static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 }; |
d8667cbb | 331 | |
1963c907 | 332 | int err; |
d8667cbb MM |
333 | /* Change only if we are actually changing the modulation */ |
334 | if (state->current_modulation != param->u.vsb.modulation) { | |
335 | switch(param->u.vsb.modulation) { | |
336 | case VSB_8: | |
337 | dprintk("%s: VSB_8 MODE\n", __FUNCTION__); | |
338 | ||
1963c907 MK |
339 | /* Select VSB mode */ |
340 | top_ctrl_cfg[1] = 0x03; | |
0ccef6db MK |
341 | |
342 | /* Select ANT connector if supported by card */ | |
343 | if (state->config->pll_rf_set) | |
344 | state->config->pll_rf_set(fe, 1); | |
1963c907 MK |
345 | |
346 | if (state->config->demod_chip == LGDT3303) { | |
347 | err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data, | |
dc9ca2af | 348 | sizeof(lgdt3303_8vsb_44_data)); |
1963c907 | 349 | } |
d8667cbb MM |
350 | break; |
351 | ||
352 | case QAM_64: | |
353 | dprintk("%s: QAM_64 MODE\n", __FUNCTION__); | |
354 | ||
1963c907 MK |
355 | /* Select QAM_64 mode */ |
356 | top_ctrl_cfg[1] = 0x00; | |
0ccef6db MK |
357 | |
358 | /* Select CABLE connector if supported by card */ | |
359 | if (state->config->pll_rf_set) | |
360 | state->config->pll_rf_set(fe, 0); | |
1963c907 MK |
361 | |
362 | if (state->config->demod_chip == LGDT3303) { | |
363 | err = i2c_write_demod_bytes(state, lgdt3303_qam_data, | |
364 | sizeof(lgdt3303_qam_data)); | |
365 | } | |
d8667cbb MM |
366 | break; |
367 | ||
368 | case QAM_256: | |
369 | dprintk("%s: QAM_256 MODE\n", __FUNCTION__); | |
370 | ||
1963c907 MK |
371 | /* Select QAM_256 mode */ |
372 | top_ctrl_cfg[1] = 0x01; | |
0ccef6db MK |
373 | |
374 | /* Select CABLE connector if supported by card */ | |
375 | if (state->config->pll_rf_set) | |
376 | state->config->pll_rf_set(fe, 0); | |
1963c907 MK |
377 | |
378 | if (state->config->demod_chip == LGDT3303) { | |
379 | err = i2c_write_demod_bytes(state, lgdt3303_qam_data, | |
380 | sizeof(lgdt3303_qam_data)); | |
381 | } | |
d8667cbb MM |
382 | break; |
383 | default: | |
6ddcc919 | 384 | printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __FUNCTION__, param->u.vsb.modulation); |
d8667cbb MM |
385 | return -1; |
386 | } | |
1963c907 MK |
387 | /* |
388 | * select serial or parallel MPEG harware interface | |
389 | * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303 | |
390 | * Parallel: 0x00 | |
391 | */ | |
392 | top_ctrl_cfg[1] |= state->config->serial_mpeg; | |
d8667cbb MM |
393 | |
394 | /* Select the requested mode */ | |
1963c907 | 395 | i2c_write_demod_bytes(state, top_ctrl_cfg, |
dc9ca2af MK |
396 | sizeof(top_ctrl_cfg)); |
397 | if (state->config->set_ts_params) | |
398 | state->config->set_ts_params(fe, 0); | |
d8667cbb MM |
399 | state->current_modulation = param->u.vsb.modulation; |
400 | } | |
d8667cbb | 401 | |
dc9ca2af MK |
402 | /* Tune to the specified frequency */ |
403 | if (state->config->pll_set) | |
1963c907 | 404 | state->config->pll_set(fe, param); |
dc9ca2af MK |
405 | |
406 | /* Keep track of the new frequency */ | |
4302c15e MCC |
407 | /* FIXME this is the wrong way to do this... */ |
408 | /* The tuner is shared with the video4linux analog API */ | |
dc9ca2af MK |
409 | state->current_frequency = param->frequency; |
410 | ||
6ddcc919 | 411 | lgdt330x_SwReset(state); |
d8667cbb MM |
412 | return 0; |
413 | } | |
414 | ||
6ddcc919 | 415 | static int lgdt330x_get_frontend(struct dvb_frontend* fe, |
d8667cbb MM |
416 | struct dvb_frontend_parameters* param) |
417 | { | |
6ddcc919 | 418 | struct lgdt330x_state *state = fe->demodulator_priv; |
d8667cbb MM |
419 | param->frequency = state->current_frequency; |
420 | return 0; | |
421 | } | |
422 | ||
1963c907 | 423 | static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status) |
d8667cbb | 424 | { |
1963c907 | 425 | struct lgdt330x_state* state = fe->demodulator_priv; |
d8667cbb MM |
426 | u8 buf[3]; |
427 | ||
428 | *status = 0; /* Reset status result */ | |
429 | ||
08d80525 | 430 | /* AGC status register */ |
1963c907 | 431 | i2c_read_demod_bytes(state, AGC_STATUS, buf, 1); |
08d80525 MK |
432 | dprintk("%s: AGC_STATUS = 0x%02x\n", __FUNCTION__, buf[0]); |
433 | if ((buf[0] & 0x0c) == 0x8){ | |
434 | /* Test signal does not exist flag */ | |
435 | /* as well as the AGC lock flag. */ | |
436 | *status |= FE_HAS_SIGNAL; | |
437 | } else { | |
438 | /* Without a signal all other status bits are meaningless */ | |
439 | return 0; | |
440 | } | |
441 | ||
1963c907 MK |
442 | /* |
443 | * You must set the Mask bits to 1 in the IRQ_MASK in order | |
444 | * to see that status bit in the IRQ_STATUS register. | |
445 | * This is done in SwReset(); | |
446 | */ | |
d8667cbb | 447 | /* signal status */ |
1963c907 | 448 | i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf)); |
d8667cbb | 449 | dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __FUNCTION__, buf[0], buf[1], buf[2]); |
08d80525 | 450 | |
d8667cbb MM |
451 | |
452 | /* sync status */ | |
453 | if ((buf[2] & 0x03) == 0x01) { | |
454 | *status |= FE_HAS_SYNC; | |
455 | } | |
456 | ||
457 | /* FEC error status */ | |
458 | if ((buf[2] & 0x0c) == 0x08) { | |
459 | *status |= FE_HAS_LOCK; | |
460 | *status |= FE_HAS_VITERBI; | |
461 | } | |
462 | ||
d8667cbb | 463 | /* Carrier Recovery Lock Status Register */ |
1963c907 | 464 | i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); |
d8667cbb MM |
465 | dprintk("%s: CARRIER_LOCK = 0x%02x\n", __FUNCTION__, buf[0]); |
466 | switch (state->current_modulation) { | |
467 | case QAM_256: | |
468 | case QAM_64: | |
469 | /* Need to undestand why there are 3 lock levels here */ | |
470 | if ((buf[0] & 0x07) == 0x07) | |
471 | *status |= FE_HAS_CARRIER; | |
d8667cbb | 472 | break; |
d8667cbb MM |
473 | case VSB_8: |
474 | if ((buf[0] & 0x80) == 0x80) | |
475 | *status |= FE_HAS_CARRIER; | |
d8667cbb | 476 | break; |
d8667cbb | 477 | default: |
6ddcc919 | 478 | printk("KERN_WARNING lgdt330x: %s: Modulation set to unsupported value\n", __FUNCTION__); |
d8667cbb | 479 | } |
d8667cbb MM |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
1963c907 MK |
484 | static int lgdt3303_read_status(struct dvb_frontend* fe, fe_status_t* status) |
485 | { | |
486 | struct lgdt330x_state* state = fe->demodulator_priv; | |
487 | int err; | |
488 | u8 buf[3]; | |
489 | ||
490 | *status = 0; /* Reset status result */ | |
491 | ||
492 | /* lgdt3303 AGC status register */ | |
493 | err = i2c_read_demod_bytes(state, 0x58, buf, 1); | |
494 | if (err < 0) | |
495 | return err; | |
496 | ||
497 | dprintk("%s: AGC_STATUS = 0x%02x\n", __FUNCTION__, buf[0]); | |
498 | if ((buf[0] & 0x21) == 0x01){ | |
499 | /* Test input signal does not exist flag */ | |
500 | /* as well as the AGC lock flag. */ | |
501 | *status |= FE_HAS_SIGNAL; | |
502 | } else { | |
503 | /* Without a signal all other status bits are meaningless */ | |
504 | return 0; | |
505 | } | |
506 | ||
507 | /* Carrier Recovery Lock Status Register */ | |
508 | i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1); | |
509 | dprintk("%s: CARRIER_LOCK = 0x%02x\n", __FUNCTION__, buf[0]); | |
510 | switch (state->current_modulation) { | |
511 | case QAM_256: | |
512 | case QAM_64: | |
513 | /* Need to undestand why there are 3 lock levels here */ | |
514 | if ((buf[0] & 0x07) == 0x07) | |
515 | *status |= FE_HAS_CARRIER; | |
516 | else | |
517 | break; | |
518 | i2c_read_demod_bytes(state, 0x8a, buf, 1); | |
519 | if ((buf[0] & 0x04) == 0x04) | |
520 | *status |= FE_HAS_SYNC; | |
521 | if ((buf[0] & 0x01) == 0x01) | |
522 | *status |= FE_HAS_LOCK; | |
523 | if ((buf[0] & 0x08) == 0x08) | |
524 | *status |= FE_HAS_VITERBI; | |
525 | break; | |
526 | case VSB_8: | |
527 | if ((buf[0] & 0x80) == 0x80) | |
528 | *status |= FE_HAS_CARRIER; | |
529 | else | |
530 | break; | |
531 | i2c_read_demod_bytes(state, 0x38, buf, 1); | |
532 | if ((buf[0] & 0x02) == 0x00) | |
533 | *status |= FE_HAS_SYNC; | |
534 | if ((buf[0] & 0x01) == 0x01) { | |
535 | *status |= FE_HAS_LOCK; | |
536 | *status |= FE_HAS_VITERBI; | |
537 | } | |
538 | break; | |
539 | default: | |
540 | printk("KERN_WARNING lgdt330x: %s: Modulation set to unsupported value\n", __FUNCTION__); | |
541 | } | |
542 | return 0; | |
543 | } | |
544 | ||
6ddcc919 | 545 | static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength) |
d8667cbb MM |
546 | { |
547 | /* not directly available. */ | |
1963c907 | 548 | *strength = 0; |
d8667cbb MM |
549 | return 0; |
550 | } | |
551 | ||
1963c907 | 552 | static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr) |
d8667cbb MM |
553 | { |
554 | #ifdef SNR_IN_DB | |
555 | /* | |
556 | * Spec sheet shows formula for SNR_EQ = 10 log10(25 * 24**2 / noise) | |
557 | * and SNR_PH = 10 log10(25 * 32**2 / noise) for equalizer and phase tracker | |
558 | * respectively. The following tables are built on these formulas. | |
559 | * The usual definition is SNR = 20 log10(signal/noise) | |
560 | * If the specification is wrong the value retuned is 1/2 the actual SNR in db. | |
561 | * | |
562 | * This table is a an ordered list of noise values computed by the | |
563 | * formula from the spec sheet such that the index into the table | |
564 | * starting at 43 or 45 is the SNR value in db. There are duplicate noise | |
565 | * value entries at the beginning because the SNR varies more than | |
566 | * 1 db for a change of 1 digit in noise at very small values of noise. | |
567 | * | |
568 | * Examples from SNR_EQ table: | |
569 | * noise SNR | |
570 | * 0 43 | |
571 | * 1 42 | |
572 | * 2 39 | |
573 | * 3 37 | |
574 | * 4 36 | |
575 | * 5 35 | |
576 | * 6 34 | |
577 | * 7 33 | |
578 | * 8 33 | |
579 | * 9 32 | |
580 | * 10 32 | |
581 | * 11 31 | |
582 | * 12 31 | |
583 | * 13 30 | |
584 | */ | |
585 | ||
586 | static const u32 SNR_EQ[] = | |
587 | { 1, 2, 2, 2, 3, 3, 4, 4, 5, 7, | |
588 | 9, 11, 13, 17, 21, 26, 33, 41, 52, 65, | |
589 | 81, 102, 129, 162, 204, 257, 323, 406, 511, 644, | |
590 | 810, 1020, 1284, 1616, 2035, 2561, 3224, 4059, 5110, 6433, | |
591 | 8098, 10195, 12835, 16158, 20341, 25608, 32238, 40585, 51094, 64323, | |
592 | 80978, 101945, 128341, 161571, 203406, 256073, 0x40000 | |
593 | }; | |
594 | ||
595 | static const u32 SNR_PH[] = | |
596 | { 1, 2, 2, 2, 3, 3, 4, 5, 6, 8, | |
597 | 10, 12, 15, 19, 23, 29, 37, 46, 58, 73, | |
598 | 91, 115, 144, 182, 229, 288, 362, 456, 574, 722, | |
599 | 909, 1144, 1440, 1813, 2282, 2873, 3617, 4553, 5732, 7216, | |
600 | 9084, 11436, 14396, 18124, 22817, 28724, 36161, 45524, 57312, 72151, | |
1963c907 | 601 | 90833, 114351, 143960, 181235, 228161, 0x080000 |
d8667cbb MM |
602 | }; |
603 | ||
604 | static u8 buf[5];/* read data buffer */ | |
605 | static u32 noise; /* noise value */ | |
606 | static u32 snr_db; /* index into SNR_EQ[] */ | |
6ddcc919 | 607 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
d8667cbb | 608 | |
1963c907 MK |
609 | /* read both equalizer and phase tracker noise data */ |
610 | i2c_read_demod_bytes(state, EQPH_ERR0, buf, sizeof(buf)); | |
d8667cbb MM |
611 | |
612 | if (state->current_modulation == VSB_8) { | |
613 | /* Equalizer Mean-Square Error Register for VSB */ | |
614 | noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2]; | |
615 | ||
616 | /* | |
617 | * Look up noise value in table. | |
618 | * A better search algorithm could be used... | |
619 | * watch out there are duplicate entries. | |
620 | */ | |
621 | for (snr_db = 0; snr_db < sizeof(SNR_EQ); snr_db++) { | |
622 | if (noise < SNR_EQ[snr_db]) { | |
623 | *snr = 43 - snr_db; | |
624 | break; | |
625 | } | |
626 | } | |
627 | } else { | |
628 | /* Phase Tracker Mean-Square Error Register for QAM */ | |
629 | noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4]; | |
630 | ||
631 | /* Look up noise value in table. */ | |
632 | for (snr_db = 0; snr_db < sizeof(SNR_PH); snr_db++) { | |
633 | if (noise < SNR_PH[snr_db]) { | |
634 | *snr = 45 - snr_db; | |
635 | break; | |
636 | } | |
637 | } | |
638 | } | |
639 | #else | |
640 | /* Return the raw noise value */ | |
641 | static u8 buf[5];/* read data buffer */ | |
642 | static u32 noise; /* noise value */ | |
6ddcc919 | 643 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
d8667cbb MM |
644 | |
645 | /* read both equalizer and pase tracker noise data */ | |
1963c907 | 646 | i2c_read_demod_bytes(state, EQPH_ERR0, buf, sizeof(buf)); |
d8667cbb MM |
647 | |
648 | if (state->current_modulation == VSB_8) { | |
1963c907 | 649 | /* Phase Tracker Mean-Square Error Register for VSB */ |
d8667cbb | 650 | noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4]; |
1963c907 MK |
651 | } else { |
652 | ||
653 | /* Carrier Recovery Mean-Square Error for QAM */ | |
654 | i2c_read_demod_bytes(state, 0x1a, buf, 2); | |
655 | noise = ((buf[0] & 3) << 8) | buf[1]; | |
d8667cbb MM |
656 | } |
657 | ||
658 | /* Small values for noise mean signal is better so invert noise */ | |
1963c907 | 659 | *snr = ~noise; |
d8667cbb MM |
660 | #endif |
661 | ||
662 | dprintk("%s: noise = 0x%05x, snr = %idb\n",__FUNCTION__, noise, *snr); | |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
1963c907 MK |
667 | static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr) |
668 | { | |
669 | /* Return the raw noise value */ | |
670 | static u8 buf[5];/* read data buffer */ | |
671 | static u32 noise; /* noise value */ | |
672 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; | |
673 | ||
674 | if (state->current_modulation == VSB_8) { | |
675 | ||
676 | /* Phase Tracker Mean-Square Error Register for VSB */ | |
677 | noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4]; | |
678 | } else { | |
679 | ||
680 | /* Carrier Recovery Mean-Square Error for QAM */ | |
681 | i2c_read_demod_bytes(state, 0x1a, buf, 2); | |
682 | noise = (buf[0] << 8) | buf[1]; | |
683 | } | |
684 | ||
685 | /* Small values for noise mean signal is better so invert noise */ | |
686 | *snr = ~noise; | |
687 | ||
688 | dprintk("%s: noise = 0x%05x, snr = %idb\n",__FUNCTION__, noise, *snr); | |
689 | ||
690 | return 0; | |
691 | } | |
692 | ||
6ddcc919 | 693 | static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings) |
d8667cbb MM |
694 | { |
695 | /* I have no idea about this - it may not be needed */ | |
696 | fe_tune_settings->min_delay_ms = 500; | |
697 | fe_tune_settings->step_size = 0; | |
698 | fe_tune_settings->max_drift = 0; | |
699 | return 0; | |
700 | } | |
701 | ||
6ddcc919 | 702 | static void lgdt330x_release(struct dvb_frontend* fe) |
d8667cbb | 703 | { |
6ddcc919 | 704 | struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv; |
d8667cbb MM |
705 | kfree(state); |
706 | } | |
707 | ||
1963c907 MK |
708 | static struct dvb_frontend_ops lgdt3302_ops; |
709 | static struct dvb_frontend_ops lgdt3303_ops; | |
d8667cbb | 710 | |
6ddcc919 | 711 | struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config, |
d8667cbb MM |
712 | struct i2c_adapter* i2c) |
713 | { | |
6ddcc919 | 714 | struct lgdt330x_state* state = NULL; |
d8667cbb MM |
715 | u8 buf[1]; |
716 | ||
717 | /* Allocate memory for the internal state */ | |
7408187d | 718 | state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL); |
d8667cbb MM |
719 | if (state == NULL) |
720 | goto error; | |
d8667cbb MM |
721 | |
722 | /* Setup the state */ | |
723 | state->config = config; | |
724 | state->i2c = i2c; | |
1963c907 MK |
725 | switch (config->demod_chip) { |
726 | case LGDT3302: | |
727 | memcpy(&state->ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops)); | |
728 | break; | |
729 | case LGDT3303: | |
730 | memcpy(&state->ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops)); | |
731 | break; | |
732 | default: | |
733 | goto error; | |
734 | } | |
735 | ||
d8667cbb | 736 | /* Verify communication with demod chip */ |
1963c907 | 737 | if (i2c_read_demod_bytes(state, 2, buf, 1)) |
d8667cbb MM |
738 | goto error; |
739 | ||
740 | state->current_frequency = -1; | |
741 | state->current_modulation = -1; | |
742 | ||
743 | /* Create dvb_frontend */ | |
744 | state->frontend.ops = &state->ops; | |
745 | state->frontend.demodulator_priv = state; | |
746 | return &state->frontend; | |
747 | ||
748 | error: | |
2ea75330 | 749 | kfree(state); |
d8667cbb MM |
750 | dprintk("%s: ERROR\n",__FUNCTION__); |
751 | return NULL; | |
752 | } | |
753 | ||
1963c907 MK |
754 | static struct dvb_frontend_ops lgdt3302_ops = { |
755 | .info = { | |
e179d8b0 | 756 | .name= "LG Electronics LGDT3302 VSB/QAM Frontend", |
1963c907 MK |
757 | .type = FE_ATSC, |
758 | .frequency_min= 54000000, | |
759 | .frequency_max= 858000000, | |
760 | .frequency_stepsize= 62500, | |
66944e99 MK |
761 | .symbol_rate_min = 5056941, /* QAM 64 */ |
762 | .symbol_rate_max = 10762000, /* VSB 8 */ | |
1963c907 MK |
763 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB |
764 | }, | |
765 | .init = lgdt330x_init, | |
766 | .set_frontend = lgdt330x_set_parameters, | |
767 | .get_frontend = lgdt330x_get_frontend, | |
768 | .get_tune_settings = lgdt330x_get_tune_settings, | |
769 | .read_status = lgdt3302_read_status, | |
770 | .read_ber = lgdt330x_read_ber, | |
771 | .read_signal_strength = lgdt330x_read_signal_strength, | |
772 | .read_snr = lgdt3302_read_snr, | |
773 | .read_ucblocks = lgdt330x_read_ucblocks, | |
774 | .release = lgdt330x_release, | |
775 | }; | |
776 | ||
777 | static struct dvb_frontend_ops lgdt3303_ops = { | |
d8667cbb | 778 | .info = { |
1963c907 | 779 | .name= "LG Electronics LGDT3303 VSB/QAM Frontend", |
d8667cbb MM |
780 | .type = FE_ATSC, |
781 | .frequency_min= 54000000, | |
782 | .frequency_max= 858000000, | |
783 | .frequency_stepsize= 62500, | |
66944e99 MK |
784 | .symbol_rate_min = 5056941, /* QAM 64 */ |
785 | .symbol_rate_max = 10762000, /* VSB 8 */ | |
d8667cbb MM |
786 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB |
787 | }, | |
6ddcc919 MK |
788 | .init = lgdt330x_init, |
789 | .set_frontend = lgdt330x_set_parameters, | |
790 | .get_frontend = lgdt330x_get_frontend, | |
791 | .get_tune_settings = lgdt330x_get_tune_settings, | |
1963c907 | 792 | .read_status = lgdt3303_read_status, |
6ddcc919 MK |
793 | .read_ber = lgdt330x_read_ber, |
794 | .read_signal_strength = lgdt330x_read_signal_strength, | |
1963c907 | 795 | .read_snr = lgdt3303_read_snr, |
6ddcc919 MK |
796 | .read_ucblocks = lgdt330x_read_ucblocks, |
797 | .release = lgdt330x_release, | |
d8667cbb MM |
798 | }; |
799 | ||
1963c907 | 800 | MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver"); |
d8667cbb MM |
801 | MODULE_AUTHOR("Wilson Michaels"); |
802 | MODULE_LICENSE("GPL"); | |
803 | ||
6ddcc919 | 804 | EXPORT_SYMBOL(lgdt330x_attach); |
d8667cbb MM |
805 | |
806 | /* | |
807 | * Local variables: | |
808 | * c-basic-offset: 8 | |
d8667cbb MM |
809 | * End: |
810 | */ |