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d8667cbb 1/*
1963c907 2 * Support for LGDT3302 and LGDT3303 - VSB/QAM
d8667cbb
MM
3 *
4 * Copyright (C) 2005 Wilson Michaels <wilsonmichaels@earthlink.net>
5 *
d8667cbb
MM
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 *
20 */
21
22/*
23 * NOTES ABOUT THIS DRIVER
24 *
1963c907
MK
25 * This Linux driver supports:
26 * DViCO FusionHDTV 3 Gold-Q
27 * DViCO FusionHDTV 3 Gold-T
28 * DViCO FusionHDTV 5 Gold
3cff00d9 29 * DViCO FusionHDTV 5 Lite
d8e6acf2 30 * DViCO FusionHDTV 5 USB Gold
c0b11b91 31 * Air2PC/AirStar 2 ATSC 3rd generation (HD5000)
20fe4f65 32 * pcHDTV HD5500
d8667cbb 33 *
d8667cbb
MM
34 */
35
d8667cbb
MM
36#include <linux/kernel.h>
37#include <linux/module.h>
d8667cbb
MM
38#include <linux/init.h>
39#include <linux/delay.h>
4e57b681
TS
40#include <linux/string.h>
41#include <linux/slab.h>
d8667cbb
MM
42#include <asm/byteorder.h>
43
44#include "dvb_frontend.h"
19be685a 45#include "dvb_math.h"
6ddcc919
MK
46#include "lgdt330x_priv.h"
47#include "lgdt330x.h"
d8667cbb 48
19be685a
TP
49/* Use Equalizer Mean Squared Error instead of Phaser Tracker MSE */
50/* #define USE_EQMSE */
51
ff699e6b 52static int debug;
d8667cbb 53module_param(debug, int, 0644);
6ddcc919 54MODULE_PARM_DESC(debug,"Turn on/off lgdt330x frontend debugging (default:off).");
d8667cbb
MM
55#define dprintk(args...) \
56do { \
6ddcc919 57if (debug) printk(KERN_DEBUG "lgdt330x: " args); \
d8667cbb
MM
58} while (0)
59
6ddcc919 60struct lgdt330x_state
d8667cbb
MM
61{
62 struct i2c_adapter* i2c;
d8667cbb
MM
63
64 /* Configuration settings */
6ddcc919 65 const struct lgdt330x_config* config;
d8667cbb
MM
66
67 struct dvb_frontend frontend;
68
69 /* Demodulator private data */
70 fe_modulation_t current_modulation;
19be685a 71 u32 snr; /* Result of last SNR calculation */
d8667cbb
MM
72
73 /* Tuner private data */
74 u32 current_frequency;
75};
76
1963c907 77static int i2c_write_demod_bytes (struct lgdt330x_state* state,
dc9ca2af
MK
78 u8 *buf, /* data bytes to send */
79 int len /* number of bytes to send */ )
d8667cbb 80{
b6aef071 81 struct i2c_msg msg =
1963c907
MK
82 { .addr = state->config->demod_address,
83 .flags = 0,
84 .buf = buf,
85 .len = 2 };
b6aef071 86 int i;
1963c907 87 int err;
d8667cbb 88
1963c907 89 for (i=0; i<len-1; i+=2){
d8667cbb 90 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
271ddbf7 91 printk(KERN_WARNING "lgdt330x: %s error (addr %02x <- %02x, err = %i)\n", __func__, msg.buf[0], msg.buf[1], err);
58ba006b
MK
92 if (err < 0)
93 return err;
94 else
95 return -EREMOTEIO;
d8667cbb 96 }
1963c907 97 msg.buf += 2;
d8667cbb
MM
98 }
99 return 0;
100}
101
102/*
103 * This routine writes the register (reg) to the demod bus
104 * then reads the data returned for (len) bytes.
105 */
106
1963c907 107static u8 i2c_read_demod_bytes (struct lgdt330x_state* state,
d8667cbb
MM
108 enum I2C_REG reg, u8* buf, int len)
109{
110 u8 wr [] = { reg };
111 struct i2c_msg msg [] = {
112 { .addr = state->config->demod_address,
113 .flags = 0, .buf = wr, .len = 1 },
114 { .addr = state->config->demod_address,
115 .flags = I2C_M_RD, .buf = buf, .len = len },
116 };
117 int ret;
118 ret = i2c_transfer(state->i2c, msg, 2);
119 if (ret != 2) {
271ddbf7 120 printk(KERN_WARNING "lgdt330x: %s: addr 0x%02x select 0x%02x error (ret == %i)\n", __func__, state->config->demod_address, reg, ret);
d8667cbb
MM
121 } else {
122 ret = 0;
123 }
124 return ret;
125}
126
127/* Software reset */
1963c907 128static int lgdt3302_SwReset(struct lgdt330x_state* state)
d8667cbb
MM
129{
130 u8 ret;
131 u8 reset[] = {
132 IRQ_MASK,
133 0x00 /* bit 6 is active low software reset
134 * bits 5-0 are 1 to mask interrupts */
135 };
136
1963c907 137 ret = i2c_write_demod_bytes(state,
dc9ca2af 138 reset, sizeof(reset));
d8667cbb 139 if (ret == 0) {
1963c907
MK
140
141 /* force reset high (inactive) and unmask interrupts */
142 reset[1] = 0x7f;
143 ret = i2c_write_demod_bytes(state,
dc9ca2af 144 reset, sizeof(reset));
d8667cbb 145 }
d8667cbb
MM
146 return ret;
147}
148
1963c907
MK
149static int lgdt3303_SwReset(struct lgdt330x_state* state)
150{
151 u8 ret;
152 u8 reset[] = {
153 0x02,
154 0x00 /* bit 0 is active low software reset */
155 };
156
157 ret = i2c_write_demod_bytes(state,
dc9ca2af 158 reset, sizeof(reset));
1963c907
MK
159 if (ret == 0) {
160
161 /* force reset high (inactive) */
162 reset[1] = 0x01;
163 ret = i2c_write_demod_bytes(state,
dc9ca2af 164 reset, sizeof(reset));
1963c907
MK
165 }
166 return ret;
167}
168
169static int lgdt330x_SwReset(struct lgdt330x_state* state)
170{
171 switch (state->config->demod_chip) {
172 case LGDT3302:
173 return lgdt3302_SwReset(state);
174 case LGDT3303:
175 return lgdt3303_SwReset(state);
176 default:
177 return -ENODEV;
178 }
179}
180
6ddcc919 181static int lgdt330x_init(struct dvb_frontend* fe)
d8667cbb
MM
182{
183 /* Hardware reset is done using gpio[0] of cx23880x chip.
184 * I'd like to do it here, but don't know how to find chip address.
185 * cx88-cards.c arranges for the reset bit to be inactive (high).
186 * Maybe there needs to be a callable function in cx88-core or
187 * the caller of this function needs to do it. */
188
1963c907
MK
189 /*
190 * Array of byte pairs <address, value>
191 * to initialize each different chip
192 */
193 static u8 lgdt3302_init_data[] = {
194 /* Use 50MHz parameter values from spec sheet since xtal is 50 */
195 /* Change the value of NCOCTFV[25:0] of carrier
196 recovery center frequency register */
197 VSB_CARRIER_FREQ0, 0x00,
198 VSB_CARRIER_FREQ1, 0x87,
199 VSB_CARRIER_FREQ2, 0x8e,
200 VSB_CARRIER_FREQ3, 0x01,
201 /* Change the TPCLK pin polarity
202 data is valid on falling clock */
203 DEMUX_CONTROL, 0xfb,
204 /* Change the value of IFBW[11:0] of
205 AGC IF/RF loop filter bandwidth register */
206 AGC_RF_BANDWIDTH0, 0x40,
207 AGC_RF_BANDWIDTH1, 0x93,
208 AGC_RF_BANDWIDTH2, 0x00,
209 /* Change the value of bit 6, 'nINAGCBY' and
210 'NSSEL[1:0] of ACG function control register 2 */
211 AGC_FUNC_CTRL2, 0xc6,
212 /* Change the value of bit 6 'RFFIX'
213 of AGC function control register 3 */
214 AGC_FUNC_CTRL3, 0x40,
215 /* Set the value of 'INLVTHD' register 0x2a/0x2c
216 to 0x7fe */
217 AGC_DELAY0, 0x07,
218 AGC_DELAY2, 0xfe,
219 /* Change the value of IAGCBW[15:8]
9aaeded7 220 of inner AGC loop filter bandwidth */
1963c907
MK
221 AGC_LOOP_BANDWIDTH0, 0x08,
222 AGC_LOOP_BANDWIDTH1, 0x9a
223 };
224
225 static u8 lgdt3303_init_data[] = {
226 0x4c, 0x14
227 };
228
c0f4c0ad 229 static u8 flip_1_lgdt3303_init_data[] = {
c0b11b91
MK
230 0x4c, 0x14,
231 0x87, 0xf3
232 };
233
c0f4c0ad
MK
234 static u8 flip_2_lgdt3303_init_data[] = {
235 0x4c, 0x14,
236 0x87, 0xda
237 };
238
1963c907
MK
239 struct lgdt330x_state* state = fe->demodulator_priv;
240 char *chip_name;
241 int err;
242
243 switch (state->config->demod_chip) {
244 case LGDT3302:
245 chip_name = "LGDT3302";
246 err = i2c_write_demod_bytes(state, lgdt3302_init_data,
dc9ca2af
MK
247 sizeof(lgdt3302_init_data));
248 break;
1963c907
MK
249 case LGDT3303:
250 chip_name = "LGDT3303";
c0f4c0ad
MK
251 switch (state->config->clock_polarity_flip) {
252 case 2:
253 err = i2c_write_demod_bytes(state,
254 flip_2_lgdt3303_init_data,
255 sizeof(flip_2_lgdt3303_init_data));
256 break;
257 case 1:
258 err = i2c_write_demod_bytes(state,
259 flip_1_lgdt3303_init_data,
260 sizeof(flip_1_lgdt3303_init_data));
261 break;
262 case 0:
263 default:
c0b11b91
MK
264 err = i2c_write_demod_bytes(state, lgdt3303_init_data,
265 sizeof(lgdt3303_init_data));
266 }
dc9ca2af 267 break;
1963c907
MK
268 default:
269 chip_name = "undefined";
270 printk (KERN_WARNING "Only LGDT3302 and LGDT3303 are supported chips.\n");
271 err = -ENODEV;
272 }
271ddbf7 273 dprintk("%s entered as %s\n", __func__, chip_name);
1963c907
MK
274 if (err < 0)
275 return err;
276 return lgdt330x_SwReset(state);
d8667cbb
MM
277}
278
6ddcc919 279static int lgdt330x_read_ber(struct dvb_frontend* fe, u32* ber)
d8667cbb 280{
1963c907 281 *ber = 0; /* Not supplied by the demod chips */
d8667cbb
MM
282 return 0;
283}
284
6ddcc919 285static int lgdt330x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
d8667cbb 286{
1963c907
MK
287 struct lgdt330x_state* state = fe->demodulator_priv;
288 int err;
d8667cbb
MM
289 u8 buf[2];
290
1963c907
MK
291 switch (state->config->demod_chip) {
292 case LGDT3302:
293 err = i2c_read_demod_bytes(state, LGDT3302_PACKET_ERR_COUNTER1,
dc9ca2af
MK
294 buf, sizeof(buf));
295 break;
1963c907
MK
296 case LGDT3303:
297 err = i2c_read_demod_bytes(state, LGDT3303_PACKET_ERR_COUNTER1,
dc9ca2af
MK
298 buf, sizeof(buf));
299 break;
1963c907
MK
300 default:
301 printk(KERN_WARNING
dc9ca2af 302 "Only LGDT3302 and LGDT3303 are supported chips.\n");
1963c907
MK
303 err = -ENODEV;
304 }
d8667cbb
MM
305
306 *ucblocks = (buf[0] << 8) | buf[1];
307 return 0;
308}
309
6ddcc919 310static int lgdt330x_set_parameters(struct dvb_frontend* fe,
d8667cbb
MM
311 struct dvb_frontend_parameters *param)
312{
1963c907
MK
313 /*
314 * Array of byte pairs <address, value>
315 * to initialize 8VSB for lgdt3303 chip 50 MHz IF
316 */
317 static u8 lgdt3303_8vsb_44_data[] = {
318 0x04, 0x00,
319 0x0d, 0x40,
0b6389ff
MK
320 0x0e, 0x87,
321 0x0f, 0x8e,
322 0x10, 0x01,
323 0x47, 0x8b };
1963c907
MK
324
325 /*
326 * Array of byte pairs <address, value>
327 * to initialize QAM for lgdt3303 chip
328 */
329 static u8 lgdt3303_qam_data[] = {
330 0x04, 0x00,
331 0x0d, 0x00,
332 0x0e, 0x00,
333 0x0f, 0x00,
334 0x10, 0x00,
335 0x51, 0x63,
336 0x47, 0x66,
337 0x48, 0x66,
338 0x4d, 0x1a,
339 0x49, 0x08,
340 0x4a, 0x9b };
341
342 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb 343
d8667cbb 344 static u8 top_ctrl_cfg[] = { TOP_CONTROL, 0x03 };
d8667cbb 345
1963c907 346 int err;
d8667cbb
MM
347 /* Change only if we are actually changing the modulation */
348 if (state->current_modulation != param->u.vsb.modulation) {
349 switch(param->u.vsb.modulation) {
350 case VSB_8:
271ddbf7 351 dprintk("%s: VSB_8 MODE\n", __func__);
d8667cbb 352
1963c907
MK
353 /* Select VSB mode */
354 top_ctrl_cfg[1] = 0x03;
0ccef6db
MK
355
356 /* Select ANT connector if supported by card */
357 if (state->config->pll_rf_set)
358 state->config->pll_rf_set(fe, 1);
1963c907
MK
359
360 if (state->config->demod_chip == LGDT3303) {
361 err = i2c_write_demod_bytes(state, lgdt3303_8vsb_44_data,
dc9ca2af 362 sizeof(lgdt3303_8vsb_44_data));
1963c907 363 }
d8667cbb
MM
364 break;
365
366 case QAM_64:
271ddbf7 367 dprintk("%s: QAM_64 MODE\n", __func__);
d8667cbb 368
1963c907
MK
369 /* Select QAM_64 mode */
370 top_ctrl_cfg[1] = 0x00;
0ccef6db
MK
371
372 /* Select CABLE connector if supported by card */
373 if (state->config->pll_rf_set)
374 state->config->pll_rf_set(fe, 0);
1963c907
MK
375
376 if (state->config->demod_chip == LGDT3303) {
377 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
378 sizeof(lgdt3303_qam_data));
379 }
d8667cbb
MM
380 break;
381
382 case QAM_256:
271ddbf7 383 dprintk("%s: QAM_256 MODE\n", __func__);
d8667cbb 384
1963c907
MK
385 /* Select QAM_256 mode */
386 top_ctrl_cfg[1] = 0x01;
0ccef6db
MK
387
388 /* Select CABLE connector if supported by card */
389 if (state->config->pll_rf_set)
390 state->config->pll_rf_set(fe, 0);
1963c907
MK
391
392 if (state->config->demod_chip == LGDT3303) {
393 err = i2c_write_demod_bytes(state, lgdt3303_qam_data,
394 sizeof(lgdt3303_qam_data));
395 }
d8667cbb
MM
396 break;
397 default:
271ddbf7 398 printk(KERN_WARNING "lgdt330x: %s: Modulation type(%d) UNSUPPORTED\n", __func__, param->u.vsb.modulation);
d8667cbb
MM
399 return -1;
400 }
1963c907
MK
401 /*
402 * select serial or parallel MPEG harware interface
403 * Serial: 0x04 for LGDT3302 or 0x40 for LGDT3303
404 * Parallel: 0x00
405 */
406 top_ctrl_cfg[1] |= state->config->serial_mpeg;
d8667cbb
MM
407
408 /* Select the requested mode */
1963c907 409 i2c_write_demod_bytes(state, top_ctrl_cfg,
dc9ca2af
MK
410 sizeof(top_ctrl_cfg));
411 if (state->config->set_ts_params)
412 state->config->set_ts_params(fe, 0);
d8667cbb
MM
413 state->current_modulation = param->u.vsb.modulation;
414 }
d8667cbb 415
dc9ca2af 416 /* Tune to the specified frequency */
dea74869
PB
417 if (fe->ops.tuner_ops.set_params) {
418 fe->ops.tuner_ops.set_params(fe, param);
419 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
02269f37 420 }
dc9ca2af
MK
421
422 /* Keep track of the new frequency */
4302c15e
MCC
423 /* FIXME this is the wrong way to do this... */
424 /* The tuner is shared with the video4linux analog API */
dc9ca2af
MK
425 state->current_frequency = param->frequency;
426
6ddcc919 427 lgdt330x_SwReset(state);
d8667cbb
MM
428 return 0;
429}
430
6ddcc919 431static int lgdt330x_get_frontend(struct dvb_frontend* fe,
d8667cbb
MM
432 struct dvb_frontend_parameters* param)
433{
6ddcc919 434 struct lgdt330x_state *state = fe->demodulator_priv;
d8667cbb
MM
435 param->frequency = state->current_frequency;
436 return 0;
437}
438
1963c907 439static int lgdt3302_read_status(struct dvb_frontend* fe, fe_status_t* status)
d8667cbb 440{
1963c907 441 struct lgdt330x_state* state = fe->demodulator_priv;
d8667cbb
MM
442 u8 buf[3];
443
444 *status = 0; /* Reset status result */
445
08d80525 446 /* AGC status register */
1963c907 447 i2c_read_demod_bytes(state, AGC_STATUS, buf, 1);
271ddbf7 448 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
08d80525
MK
449 if ((buf[0] & 0x0c) == 0x8){
450 /* Test signal does not exist flag */
451 /* as well as the AGC lock flag. */
452 *status |= FE_HAS_SIGNAL;
08d80525
MK
453 }
454
1963c907
MK
455 /*
456 * You must set the Mask bits to 1 in the IRQ_MASK in order
457 * to see that status bit in the IRQ_STATUS register.
458 * This is done in SwReset();
459 */
d8667cbb 460 /* signal status */
1963c907 461 i2c_read_demod_bytes(state, TOP_CONTROL, buf, sizeof(buf));
271ddbf7 462 dprintk("%s: TOP_CONTROL = 0x%02x, IRO_MASK = 0x%02x, IRQ_STATUS = 0x%02x\n", __func__, buf[0], buf[1], buf[2]);
08d80525 463
d8667cbb
MM
464
465 /* sync status */
466 if ((buf[2] & 0x03) == 0x01) {
467 *status |= FE_HAS_SYNC;
468 }
469
470 /* FEC error status */
471 if ((buf[2] & 0x0c) == 0x08) {
472 *status |= FE_HAS_LOCK;
473 *status |= FE_HAS_VITERBI;
474 }
475
d8667cbb 476 /* Carrier Recovery Lock Status Register */
1963c907 477 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 478 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
d8667cbb
MM
479 switch (state->current_modulation) {
480 case QAM_256:
481 case QAM_64:
af901ca1 482 /* Need to understand why there are 3 lock levels here */
d8667cbb
MM
483 if ((buf[0] & 0x07) == 0x07)
484 *status |= FE_HAS_CARRIER;
d8667cbb 485 break;
d8667cbb
MM
486 case VSB_8:
487 if ((buf[0] & 0x80) == 0x80)
488 *status |= FE_HAS_CARRIER;
d8667cbb 489 break;
d8667cbb 490 default:
271ddbf7 491 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
d8667cbb 492 }
d8667cbb
MM
493
494 return 0;
495}
496
1963c907
MK
497static int lgdt3303_read_status(struct dvb_frontend* fe, fe_status_t* status)
498{
499 struct lgdt330x_state* state = fe->demodulator_priv;
500 int err;
501 u8 buf[3];
502
503 *status = 0; /* Reset status result */
504
505 /* lgdt3303 AGC status register */
506 err = i2c_read_demod_bytes(state, 0x58, buf, 1);
507 if (err < 0)
508 return err;
509
271ddbf7 510 dprintk("%s: AGC_STATUS = 0x%02x\n", __func__, buf[0]);
1963c907
MK
511 if ((buf[0] & 0x21) == 0x01){
512 /* Test input signal does not exist flag */
513 /* as well as the AGC lock flag. */
514 *status |= FE_HAS_SIGNAL;
1963c907
MK
515 }
516
517 /* Carrier Recovery Lock Status Register */
518 i2c_read_demod_bytes(state, CARRIER_LOCK, buf, 1);
271ddbf7 519 dprintk("%s: CARRIER_LOCK = 0x%02x\n", __func__, buf[0]);
1963c907
MK
520 switch (state->current_modulation) {
521 case QAM_256:
522 case QAM_64:
af901ca1 523 /* Need to understand why there are 3 lock levels here */
1963c907
MK
524 if ((buf[0] & 0x07) == 0x07)
525 *status |= FE_HAS_CARRIER;
526 else
527 break;
528 i2c_read_demod_bytes(state, 0x8a, buf, 1);
529 if ((buf[0] & 0x04) == 0x04)
530 *status |= FE_HAS_SYNC;
531 if ((buf[0] & 0x01) == 0x01)
532 *status |= FE_HAS_LOCK;
533 if ((buf[0] & 0x08) == 0x08)
534 *status |= FE_HAS_VITERBI;
535 break;
536 case VSB_8:
537 if ((buf[0] & 0x80) == 0x80)
538 *status |= FE_HAS_CARRIER;
539 else
540 break;
541 i2c_read_demod_bytes(state, 0x38, buf, 1);
542 if ((buf[0] & 0x02) == 0x00)
543 *status |= FE_HAS_SYNC;
544 if ((buf[0] & 0x01) == 0x01) {
545 *status |= FE_HAS_LOCK;
546 *status |= FE_HAS_VITERBI;
547 }
548 break;
549 default:
271ddbf7 550 printk(KERN_WARNING "lgdt330x: %s: Modulation set to unsupported value\n", __func__);
1963c907
MK
551 }
552 return 0;
553}
554
19be685a
TP
555/* Calculate SNR estimation (scaled by 2^24)
556
557 8-VSB SNR equations from LGDT3302 and LGDT3303 datasheets, QAM
558 equations from LGDT3303 datasheet. VSB is the same between the '02
559 and '03, so maybe QAM is too? Perhaps someone with a newer datasheet
560 that has QAM information could verify?
561
562 For 8-VSB: (two ways, take your pick)
563 LGDT3302:
564 SNR_EQ = 10 * log10(25 * 24^2 / EQ_MSE)
565 LGDT3303:
566 SNR_EQ = 10 * log10(25 * 32^2 / EQ_MSE)
567 LGDT3302 & LGDT3303:
568 SNR_PT = 10 * log10(25 * 32^2 / PT_MSE) (we use this one)
569 For 64-QAM:
570 SNR = 10 * log10( 688128 / MSEQAM)
571 For 256-QAM:
572 SNR = 10 * log10( 696320 / MSEQAM)
573
574 We re-write the snr equation as:
575 SNR * 2^24 = 10*(c - intlog10(MSE))
576 Where for 256-QAM, c = log10(696320) * 2^24, and so on. */
577
578static u32 calculate_snr(u32 mse, u32 c)
d8667cbb 579{
19be685a
TP
580 if (mse == 0) /* No signal */
581 return 0;
582
583 mse = intlog10(mse);
584 if (mse > c) {
585 /* Negative SNR, which is possible, but realisticly the
586 demod will lose lock before the signal gets this bad. The
587 API only allows for unsigned values, so just return 0 */
588 return 0;
589 }
590 return 10*(c - mse);
d8667cbb
MM
591}
592
1963c907 593static int lgdt3302_read_snr(struct dvb_frontend* fe, u16* snr)
d8667cbb 594{
6ddcc919 595 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
596 u8 buf[5]; /* read data buffer */
597 u32 noise; /* noise value */
598 u32 c; /* per-modulation SNR calculation constant */
d8667cbb 599
19be685a
TP
600 switch(state->current_modulation) {
601 case VSB_8:
602 i2c_read_demod_bytes(state, LGDT3302_EQPH_ERR0, buf, 5);
603#ifdef USE_EQMSE
604 /* Use Equalizer Mean-Square Error Register */
605 /* SNR for ranges from -15.61 to +41.58 */
d8667cbb 606 noise = ((buf[0] & 7) << 16) | (buf[1] << 8) | buf[2];
19be685a 607 c = 69765745; /* log10(25*24^2)*2^24 */
d8667cbb 608#else
19be685a
TP
609 /* Use Phase Tracker Mean-Square Error Register */
610 /* SNR for ranges from -13.11 to +44.08 */
d8667cbb 611 noise = ((buf[0] & 7<<3) << 13) | (buf[3] << 8) | buf[4];
19be685a
TP
612 c = 73957994; /* log10(25*32^2)*2^24 */
613#endif
614 break;
615 case QAM_64:
616 case QAM_256:
617 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 618 noise = ((buf[0] & 3) << 8) | buf[1];
19be685a
TP
619 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
620 /* log10(688128)*2^24 and log10(696320)*2^24 */
621 break;
622 default:
623 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 624 __func__);
19be685a 625 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
d8667cbb
MM
626 }
627
19be685a
TP
628 state->snr = calculate_snr(noise, c);
629 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
d8667cbb 630
271ddbf7 631 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a 632 state->snr >> 24, (((state->snr>>8) & 0xffff) * 100) >> 16);
d8667cbb
MM
633
634 return 0;
635}
636
1963c907
MK
637static int lgdt3303_read_snr(struct dvb_frontend* fe, u16* snr)
638{
1963c907 639 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
19be685a
TP
640 u8 buf[5]; /* read data buffer */
641 u32 noise; /* noise value */
642 u32 c; /* per-modulation SNR calculation constant */
1963c907 643
19be685a
TP
644 switch(state->current_modulation) {
645 case VSB_8:
646 i2c_read_demod_bytes(state, LGDT3303_EQPH_ERR0, buf, 5);
647#ifdef USE_EQMSE
648 /* Use Equalizer Mean-Square Error Register */
649 /* SNR for ranges from -16.12 to +44.08 */
650 noise = ((buf[0] & 0x78) << 13) | (buf[1] << 8) | buf[2];
651 c = 73957994; /* log10(25*32^2)*2^24 */
652#else
653 /* Use Phase Tracker Mean-Square Error Register */
654 /* SNR for ranges from -13.11 to +44.08 */
1963c907 655 noise = ((buf[0] & 7) << 16) | (buf[3] << 8) | buf[4];
19be685a
TP
656 c = 73957994; /* log10(25*32^2)*2^24 */
657#endif
658 break;
659 case QAM_64:
660 case QAM_256:
661 i2c_read_demod_bytes(state, CARRIER_MSEQAM1, buf, 2);
1963c907 662 noise = (buf[0] << 8) | buf[1];
19be685a
TP
663 c = state->current_modulation == QAM_64 ? 97939837 : 98026066;
664 /* log10(688128)*2^24 and log10(696320)*2^24 */
665 break;
666 default:
667 printk(KERN_ERR "lgdt330x: %s: Modulation set to unsupported value\n",
271ddbf7 668 __func__);
19be685a 669 return -EREMOTEIO; /* return -EDRIVER_IS_GIBBERED; */
1963c907
MK
670 }
671
19be685a
TP
672 state->snr = calculate_snr(noise, c);
673 *snr = (state->snr) >> 16; /* Convert from 8.24 fixed-point to 8.8 */
674
271ddbf7 675 dprintk("%s: noise = 0x%08x, snr = %d.%02d dB\n", __func__, noise,
19be685a
TP
676 state->snr >> 24, (((state->snr >> 8) & 0xffff) * 100) >> 16);
677
678 return 0;
679}
680
681static int lgdt330x_read_signal_strength(struct dvb_frontend* fe, u16* strength)
682{
683 /* Calculate Strength from SNR up to 35dB */
684 /* Even though the SNR can go higher than 35dB, there is some comfort */
685 /* factor in having a range of strong signals that can show at 100% */
686 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
687 u16 snr;
688 int ret;
1963c907 689
19be685a
TP
690 ret = fe->ops.read_snr(fe, &snr);
691 if (ret != 0)
692 return ret;
693 /* Rather than use the 8.8 value snr, use state->snr which is 8.24 */
694 /* scale the range 0 - 35*2^24 into 0 - 65535 */
695 if (state->snr >= 8960 * 0x10000)
696 *strength = 0xffff;
697 else
698 *strength = state->snr / 8960;
1963c907
MK
699
700 return 0;
701}
702
6ddcc919 703static int lgdt330x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
d8667cbb
MM
704{
705 /* I have no idea about this - it may not be needed */
706 fe_tune_settings->min_delay_ms = 500;
707 fe_tune_settings->step_size = 0;
708 fe_tune_settings->max_drift = 0;
709 return 0;
710}
711
6ddcc919 712static void lgdt330x_release(struct dvb_frontend* fe)
d8667cbb 713{
6ddcc919 714 struct lgdt330x_state* state = (struct lgdt330x_state*) fe->demodulator_priv;
d8667cbb
MM
715 kfree(state);
716}
717
1963c907
MK
718static struct dvb_frontend_ops lgdt3302_ops;
719static struct dvb_frontend_ops lgdt3303_ops;
d8667cbb 720
6ddcc919 721struct dvb_frontend* lgdt330x_attach(const struct lgdt330x_config* config,
d8667cbb
MM
722 struct i2c_adapter* i2c)
723{
6ddcc919 724 struct lgdt330x_state* state = NULL;
d8667cbb
MM
725 u8 buf[1];
726
727 /* Allocate memory for the internal state */
7408187d 728 state = kzalloc(sizeof(struct lgdt330x_state), GFP_KERNEL);
d8667cbb
MM
729 if (state == NULL)
730 goto error;
d8667cbb
MM
731
732 /* Setup the state */
733 state->config = config;
734 state->i2c = i2c;
dea74869
PB
735
736 /* Create dvb_frontend */
1963c907
MK
737 switch (config->demod_chip) {
738 case LGDT3302:
dea74869 739 memcpy(&state->frontend.ops, &lgdt3302_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
740 break;
741 case LGDT3303:
dea74869 742 memcpy(&state->frontend.ops, &lgdt3303_ops, sizeof(struct dvb_frontend_ops));
1963c907
MK
743 break;
744 default:
745 goto error;
746 }
dea74869 747 state->frontend.demodulator_priv = state;
1963c907 748
d8667cbb 749 /* Verify communication with demod chip */
1963c907 750 if (i2c_read_demod_bytes(state, 2, buf, 1))
d8667cbb
MM
751 goto error;
752
753 state->current_frequency = -1;
754 state->current_modulation = -1;
755
d8667cbb
MM
756 return &state->frontend;
757
758error:
2ea75330 759 kfree(state);
271ddbf7 760 dprintk("%s: ERROR\n",__func__);
d8667cbb
MM
761 return NULL;
762}
763
1963c907
MK
764static struct dvb_frontend_ops lgdt3302_ops = {
765 .info = {
e179d8b0 766 .name= "LG Electronics LGDT3302 VSB/QAM Frontend",
1963c907
MK
767 .type = FE_ATSC,
768 .frequency_min= 54000000,
769 .frequency_max= 858000000,
770 .frequency_stepsize= 62500,
66944e99
MK
771 .symbol_rate_min = 5056941, /* QAM 64 */
772 .symbol_rate_max = 10762000, /* VSB 8 */
1963c907
MK
773 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
774 },
775 .init = lgdt330x_init,
776 .set_frontend = lgdt330x_set_parameters,
777 .get_frontend = lgdt330x_get_frontend,
778 .get_tune_settings = lgdt330x_get_tune_settings,
779 .read_status = lgdt3302_read_status,
780 .read_ber = lgdt330x_read_ber,
781 .read_signal_strength = lgdt330x_read_signal_strength,
782 .read_snr = lgdt3302_read_snr,
783 .read_ucblocks = lgdt330x_read_ucblocks,
784 .release = lgdt330x_release,
785};
786
787static struct dvb_frontend_ops lgdt3303_ops = {
d8667cbb 788 .info = {
1963c907 789 .name= "LG Electronics LGDT3303 VSB/QAM Frontend",
d8667cbb
MM
790 .type = FE_ATSC,
791 .frequency_min= 54000000,
792 .frequency_max= 858000000,
793 .frequency_stepsize= 62500,
66944e99
MK
794 .symbol_rate_min = 5056941, /* QAM 64 */
795 .symbol_rate_max = 10762000, /* VSB 8 */
d8667cbb
MM
796 .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB
797 },
6ddcc919
MK
798 .init = lgdt330x_init,
799 .set_frontend = lgdt330x_set_parameters,
800 .get_frontend = lgdt330x_get_frontend,
801 .get_tune_settings = lgdt330x_get_tune_settings,
1963c907 802 .read_status = lgdt3303_read_status,
6ddcc919
MK
803 .read_ber = lgdt330x_read_ber,
804 .read_signal_strength = lgdt330x_read_signal_strength,
1963c907 805 .read_snr = lgdt3303_read_snr,
6ddcc919
MK
806 .read_ucblocks = lgdt330x_read_ucblocks,
807 .release = lgdt330x_release,
d8667cbb
MM
808};
809
1963c907 810MODULE_DESCRIPTION("LGDT330X (ATSC 8VSB & ITU-T J.83 AnnexB 64/256 QAM) Demodulator Driver");
d8667cbb
MM
811MODULE_AUTHOR("Wilson Michaels");
812MODULE_LICENSE("GPL");
813
6ddcc919 814EXPORT_SYMBOL(lgdt330x_attach);
d8667cbb
MM
815
816/*
817 * Local variables:
818 * c-basic-offset: 8
d8667cbb
MM
819 * End:
820 */