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Commit | Line | Data |
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8b4f1d03 ST |
1 | /* |
2 | Samsung S5H1411 VSB/QAM demodulator driver | |
3 | ||
6d897616 | 4 | Copyright (C) 2008 Steven Toth <stoth@linuxtv.org> |
8b4f1d03 ST |
5 | |
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | */ | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/string.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/delay.h> | |
28 | #include "dvb_frontend.h" | |
8b4f1d03 ST |
29 | #include "s5h1411.h" |
30 | ||
31 | struct s5h1411_state { | |
32 | ||
33 | struct i2c_adapter *i2c; | |
34 | ||
35 | /* configuration settings */ | |
36 | const struct s5h1411_config *config; | |
37 | ||
38 | struct dvb_frontend frontend; | |
39 | ||
40 | fe_modulation_t current_modulation; | |
41 | ||
42 | u32 current_frequency; | |
43 | int if_freq; | |
44 | ||
45 | u8 inversion; | |
46 | }; | |
47 | ||
48 | static int debug; | |
49 | ||
50 | #define dprintk(arg...) do { \ | |
51 | if (debug) \ | |
52 | printk(arg); \ | |
53 | } while (0) | |
54 | ||
55 | /* Register values to initialise the demod, defaults to VSB */ | |
56 | static struct init_tab { | |
57 | u8 addr; | |
58 | u8 reg; | |
59 | u16 data; | |
60 | } init_tab[] = { | |
61 | { S5H1411_I2C_TOP_ADDR, 0x00, 0x0071, }, | |
62 | { S5H1411_I2C_TOP_ADDR, 0x08, 0x0047, }, | |
63 | { S5H1411_I2C_TOP_ADDR, 0x1c, 0x0400, }, | |
64 | { S5H1411_I2C_TOP_ADDR, 0x1e, 0x0370, }, | |
f4ef033e | 65 | { S5H1411_I2C_TOP_ADDR, 0x1f, 0x342c, }, |
8b4f1d03 ST |
66 | { S5H1411_I2C_TOP_ADDR, 0x24, 0x0231, }, |
67 | { S5H1411_I2C_TOP_ADDR, 0x25, 0x1011, }, | |
68 | { S5H1411_I2C_TOP_ADDR, 0x26, 0x0f07, }, | |
69 | { S5H1411_I2C_TOP_ADDR, 0x27, 0x0f04, }, | |
70 | { S5H1411_I2C_TOP_ADDR, 0x28, 0x070f, }, | |
71 | { S5H1411_I2C_TOP_ADDR, 0x29, 0x2820, }, | |
72 | { S5H1411_I2C_TOP_ADDR, 0x2a, 0x102e, }, | |
73 | { S5H1411_I2C_TOP_ADDR, 0x2b, 0x0220, }, | |
74 | { S5H1411_I2C_TOP_ADDR, 0x2e, 0x0d0e, }, | |
75 | { S5H1411_I2C_TOP_ADDR, 0x2f, 0x1013, }, | |
76 | { S5H1411_I2C_TOP_ADDR, 0x31, 0x171b, }, | |
77 | { S5H1411_I2C_TOP_ADDR, 0x32, 0x0e0f, }, | |
78 | { S5H1411_I2C_TOP_ADDR, 0x33, 0x0f10, }, | |
79 | { S5H1411_I2C_TOP_ADDR, 0x34, 0x170e, }, | |
80 | { S5H1411_I2C_TOP_ADDR, 0x35, 0x4b10, }, | |
81 | { S5H1411_I2C_TOP_ADDR, 0x36, 0x0f17, }, | |
82 | { S5H1411_I2C_TOP_ADDR, 0x3c, 0x1577, }, | |
83 | { S5H1411_I2C_TOP_ADDR, 0x3d, 0x081a, }, | |
84 | { S5H1411_I2C_TOP_ADDR, 0x3e, 0x77ee, }, | |
85 | { S5H1411_I2C_TOP_ADDR, 0x40, 0x1e09, }, | |
86 | { S5H1411_I2C_TOP_ADDR, 0x41, 0x0f0c, }, | |
87 | { S5H1411_I2C_TOP_ADDR, 0x42, 0x1f10, }, | |
88 | { S5H1411_I2C_TOP_ADDR, 0x4d, 0x0509, }, | |
89 | { S5H1411_I2C_TOP_ADDR, 0x4e, 0x0a00, }, | |
90 | { S5H1411_I2C_TOP_ADDR, 0x50, 0x0000, }, | |
91 | { S5H1411_I2C_TOP_ADDR, 0x5b, 0x0000, }, | |
92 | { S5H1411_I2C_TOP_ADDR, 0x5c, 0x0008, }, | |
93 | { S5H1411_I2C_TOP_ADDR, 0x57, 0x1101, }, | |
94 | { S5H1411_I2C_TOP_ADDR, 0x65, 0x007c, }, | |
95 | { S5H1411_I2C_TOP_ADDR, 0x68, 0x0512, }, | |
96 | { S5H1411_I2C_TOP_ADDR, 0x69, 0x0258, }, | |
97 | { S5H1411_I2C_TOP_ADDR, 0x70, 0x0004, }, | |
98 | { S5H1411_I2C_TOP_ADDR, 0x71, 0x0007, }, | |
99 | { S5H1411_I2C_TOP_ADDR, 0x76, 0x00a9, }, | |
100 | { S5H1411_I2C_TOP_ADDR, 0x78, 0x3141, }, | |
101 | { S5H1411_I2C_TOP_ADDR, 0x7a, 0x3141, }, | |
102 | { S5H1411_I2C_TOP_ADDR, 0xb3, 0x8003, }, | |
8b4f1d03 ST |
103 | { S5H1411_I2C_TOP_ADDR, 0xb5, 0xa6bb, }, |
104 | { S5H1411_I2C_TOP_ADDR, 0xb6, 0x0609, }, | |
105 | { S5H1411_I2C_TOP_ADDR, 0xb7, 0x2f06, }, | |
106 | { S5H1411_I2C_TOP_ADDR, 0xb8, 0x003f, }, | |
107 | { S5H1411_I2C_TOP_ADDR, 0xb9, 0x2700, }, | |
108 | { S5H1411_I2C_TOP_ADDR, 0xba, 0xfac8, }, | |
109 | { S5H1411_I2C_TOP_ADDR, 0xbe, 0x1003, }, | |
110 | { S5H1411_I2C_TOP_ADDR, 0xbf, 0x103f, }, | |
111 | { S5H1411_I2C_TOP_ADDR, 0xce, 0x2000, }, | |
112 | { S5H1411_I2C_TOP_ADDR, 0xcf, 0x0800, }, | |
113 | { S5H1411_I2C_TOP_ADDR, 0xd0, 0x0800, }, | |
114 | { S5H1411_I2C_TOP_ADDR, 0xd1, 0x0400, }, | |
115 | { S5H1411_I2C_TOP_ADDR, 0xd2, 0x0800, }, | |
116 | { S5H1411_I2C_TOP_ADDR, 0xd3, 0x2000, }, | |
117 | { S5H1411_I2C_TOP_ADDR, 0xd4, 0x3000, }, | |
118 | { S5H1411_I2C_TOP_ADDR, 0xdb, 0x4a9b, }, | |
119 | { S5H1411_I2C_TOP_ADDR, 0xdc, 0x1000, }, | |
120 | { S5H1411_I2C_TOP_ADDR, 0xde, 0x0001, }, | |
121 | { S5H1411_I2C_TOP_ADDR, 0xdf, 0x0000, }, | |
122 | { S5H1411_I2C_TOP_ADDR, 0xe3, 0x0301, }, | |
123 | { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0000, }, | |
124 | { S5H1411_I2C_QAM_ADDR, 0xf3, 0x0001, }, | |
125 | { S5H1411_I2C_QAM_ADDR, 0x08, 0x0600, }, | |
126 | { S5H1411_I2C_QAM_ADDR, 0x18, 0x4201, }, | |
127 | { S5H1411_I2C_QAM_ADDR, 0x1e, 0x6476, }, | |
128 | { S5H1411_I2C_QAM_ADDR, 0x21, 0x0830, }, | |
129 | { S5H1411_I2C_QAM_ADDR, 0x0c, 0x5679, }, | |
130 | { S5H1411_I2C_QAM_ADDR, 0x0d, 0x579b, }, | |
131 | { S5H1411_I2C_QAM_ADDR, 0x24, 0x0102, }, | |
132 | { S5H1411_I2C_QAM_ADDR, 0x31, 0x7488, }, | |
133 | { S5H1411_I2C_QAM_ADDR, 0x32, 0x0a08, }, | |
134 | { S5H1411_I2C_QAM_ADDR, 0x3d, 0x8689, }, | |
135 | { S5H1411_I2C_QAM_ADDR, 0x49, 0x0048, }, | |
136 | { S5H1411_I2C_QAM_ADDR, 0x57, 0x2012, }, | |
137 | { S5H1411_I2C_QAM_ADDR, 0x5d, 0x7676, }, | |
138 | { S5H1411_I2C_QAM_ADDR, 0x04, 0x0400, }, | |
139 | { S5H1411_I2C_QAM_ADDR, 0x58, 0x00c0, }, | |
140 | { S5H1411_I2C_QAM_ADDR, 0x5b, 0x0100, }, | |
141 | }; | |
142 | ||
143 | /* VSB SNR lookup table */ | |
144 | static struct vsb_snr_tab { | |
145 | u16 val; | |
146 | u16 data; | |
147 | } vsb_snr_tab[] = { | |
148 | { 0x39f, 300, }, | |
149 | { 0x39b, 295, }, | |
150 | { 0x397, 290, }, | |
151 | { 0x394, 285, }, | |
152 | { 0x38f, 280, }, | |
153 | { 0x38b, 275, }, | |
154 | { 0x387, 270, }, | |
155 | { 0x382, 265, }, | |
156 | { 0x37d, 260, }, | |
157 | { 0x377, 255, }, | |
158 | { 0x370, 250, }, | |
159 | { 0x36a, 245, }, | |
160 | { 0x364, 240, }, | |
161 | { 0x35b, 235, }, | |
162 | { 0x353, 230, }, | |
163 | { 0x349, 225, }, | |
164 | { 0x340, 320, }, | |
165 | { 0x337, 215, }, | |
166 | { 0x327, 210, }, | |
167 | { 0x31b, 205, }, | |
168 | { 0x310, 200, }, | |
169 | { 0x302, 195, }, | |
170 | { 0x2f3, 190, }, | |
171 | { 0x2e4, 185, }, | |
172 | { 0x2d7, 180, }, | |
173 | { 0x2cd, 175, }, | |
174 | { 0x2bb, 170, }, | |
175 | { 0x2a9, 165, }, | |
176 | { 0x29e, 160, }, | |
177 | { 0x284, 155, }, | |
178 | { 0x27a, 150, }, | |
179 | { 0x260, 145, }, | |
180 | { 0x23a, 140, }, | |
181 | { 0x224, 135, }, | |
182 | { 0x213, 130, }, | |
183 | { 0x204, 125, }, | |
184 | { 0x1fe, 120, }, | |
185 | { 0, 0, }, | |
186 | }; | |
187 | ||
188 | /* QAM64 SNR lookup table */ | |
189 | static struct qam64_snr_tab { | |
190 | u16 val; | |
191 | u16 data; | |
192 | } qam64_snr_tab[] = { | |
193 | { 0x0001, 0, }, | |
194 | { 0x0af0, 300, }, | |
195 | { 0x0d80, 290, }, | |
196 | { 0x10a0, 280, }, | |
197 | { 0x14b5, 270, }, | |
198 | { 0x1590, 268, }, | |
199 | { 0x1680, 266, }, | |
200 | { 0x17b0, 264, }, | |
201 | { 0x18c0, 262, }, | |
202 | { 0x19b0, 260, }, | |
203 | { 0x1ad0, 258, }, | |
204 | { 0x1d00, 256, }, | |
205 | { 0x1da0, 254, }, | |
206 | { 0x1ef0, 252, }, | |
207 | { 0x2050, 250, }, | |
208 | { 0x20f0, 249, }, | |
209 | { 0x21d0, 248, }, | |
210 | { 0x22b0, 247, }, | |
211 | { 0x23a0, 246, }, | |
212 | { 0x2470, 245, }, | |
213 | { 0x24f0, 244, }, | |
214 | { 0x25a0, 243, }, | |
215 | { 0x26c0, 242, }, | |
216 | { 0x27b0, 241, }, | |
217 | { 0x28d0, 240, }, | |
218 | { 0x29b0, 239, }, | |
219 | { 0x2ad0, 238, }, | |
220 | { 0x2ba0, 237, }, | |
221 | { 0x2c80, 236, }, | |
222 | { 0x2d20, 235, }, | |
223 | { 0x2e00, 234, }, | |
224 | { 0x2f10, 233, }, | |
225 | { 0x3050, 232, }, | |
226 | { 0x3190, 231, }, | |
227 | { 0x3300, 230, }, | |
228 | { 0x3340, 229, }, | |
229 | { 0x3200, 228, }, | |
230 | { 0x3550, 227, }, | |
231 | { 0x3610, 226, }, | |
232 | { 0x3600, 225, }, | |
233 | { 0x3700, 224, }, | |
234 | { 0x3800, 223, }, | |
235 | { 0x3920, 222, }, | |
236 | { 0x3a20, 221, }, | |
237 | { 0x3b30, 220, }, | |
238 | { 0x3d00, 219, }, | |
239 | { 0x3e00, 218, }, | |
240 | { 0x4000, 217, }, | |
241 | { 0x4100, 216, }, | |
242 | { 0x4300, 215, }, | |
243 | { 0x4400, 214, }, | |
244 | { 0x4600, 213, }, | |
245 | { 0x4700, 212, }, | |
246 | { 0x4800, 211, }, | |
247 | { 0x4a00, 210, }, | |
248 | { 0x4b00, 209, }, | |
249 | { 0x4d00, 208, }, | |
250 | { 0x4f00, 207, }, | |
251 | { 0x5050, 206, }, | |
252 | { 0x5200, 205, }, | |
253 | { 0x53c0, 204, }, | |
254 | { 0x5450, 203, }, | |
255 | { 0x5650, 202, }, | |
256 | { 0x5820, 201, }, | |
257 | { 0x6000, 200, }, | |
258 | { 0xffff, 0, }, | |
259 | }; | |
260 | ||
261 | /* QAM256 SNR lookup table */ | |
262 | static struct qam256_snr_tab { | |
263 | u16 val; | |
264 | u16 data; | |
265 | } qam256_snr_tab[] = { | |
266 | { 0x0001, 0, }, | |
267 | { 0x0970, 400, }, | |
268 | { 0x0a90, 390, }, | |
269 | { 0x0b90, 380, }, | |
270 | { 0x0d90, 370, }, | |
271 | { 0x0ff0, 360, }, | |
272 | { 0x1240, 350, }, | |
273 | { 0x1345, 348, }, | |
274 | { 0x13c0, 346, }, | |
275 | { 0x14c0, 344, }, | |
276 | { 0x1500, 342, }, | |
277 | { 0x1610, 340, }, | |
278 | { 0x1700, 338, }, | |
279 | { 0x1800, 336, }, | |
280 | { 0x18b0, 334, }, | |
281 | { 0x1900, 332, }, | |
282 | { 0x1ab0, 330, }, | |
283 | { 0x1bc0, 328, }, | |
284 | { 0x1cb0, 326, }, | |
285 | { 0x1db0, 324, }, | |
286 | { 0x1eb0, 322, }, | |
287 | { 0x2030, 320, }, | |
288 | { 0x2200, 318, }, | |
289 | { 0x2280, 316, }, | |
290 | { 0x2410, 314, }, | |
291 | { 0x25b0, 312, }, | |
292 | { 0x27a0, 310, }, | |
293 | { 0x2840, 308, }, | |
294 | { 0x29d0, 306, }, | |
295 | { 0x2b10, 304, }, | |
296 | { 0x2d30, 302, }, | |
297 | { 0x2f20, 300, }, | |
298 | { 0x30c0, 298, }, | |
299 | { 0x3260, 297, }, | |
300 | { 0x32c0, 296, }, | |
301 | { 0x3300, 295, }, | |
302 | { 0x33b0, 294, }, | |
303 | { 0x34b0, 293, }, | |
304 | { 0x35a0, 292, }, | |
305 | { 0x3650, 291, }, | |
306 | { 0x3800, 290, }, | |
307 | { 0x3900, 289, }, | |
308 | { 0x3a50, 288, }, | |
309 | { 0x3b30, 287, }, | |
310 | { 0x3cb0, 286, }, | |
311 | { 0x3e20, 285, }, | |
312 | { 0x3fa0, 284, }, | |
313 | { 0x40a0, 283, }, | |
314 | { 0x41c0, 282, }, | |
315 | { 0x42f0, 281, }, | |
316 | { 0x44a0, 280, }, | |
317 | { 0x4600, 279, }, | |
318 | { 0x47b0, 278, }, | |
319 | { 0x4900, 277, }, | |
320 | { 0x4a00, 276, }, | |
321 | { 0x4ba0, 275, }, | |
322 | { 0x4d00, 274, }, | |
323 | { 0x4f00, 273, }, | |
324 | { 0x5000, 272, }, | |
325 | { 0x51f0, 272, }, | |
326 | { 0x53a0, 270, }, | |
327 | { 0x5520, 269, }, | |
328 | { 0x5700, 268, }, | |
329 | { 0x5800, 267, }, | |
330 | { 0x5a00, 266, }, | |
331 | { 0x5c00, 265, }, | |
332 | { 0x5d00, 264, }, | |
333 | { 0x5f00, 263, }, | |
334 | { 0x6000, 262, }, | |
335 | { 0x6200, 261, }, | |
336 | { 0x6400, 260, }, | |
337 | { 0xffff, 0, }, | |
338 | }; | |
339 | ||
340 | /* 8 bit registers, 16 bit values */ | |
341 | static int s5h1411_writereg(struct s5h1411_state *state, | |
342 | u8 addr, u8 reg, u16 data) | |
343 | { | |
344 | int ret; | |
b431c616 | 345 | u8 buf[] = { reg, data >> 8, data & 0xff }; |
8b4f1d03 ST |
346 | |
347 | struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 3 }; | |
348 | ||
349 | ret = i2c_transfer(state->i2c, &msg, 1); | |
350 | ||
351 | if (ret != 1) | |
352 | printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, " | |
353 | "ret == %i)\n", __func__, addr, reg, data, ret); | |
354 | ||
355 | return (ret != 1) ? -1 : 0; | |
356 | } | |
357 | ||
358 | static u16 s5h1411_readreg(struct s5h1411_state *state, u8 addr, u8 reg) | |
359 | { | |
360 | int ret; | |
b431c616 ST |
361 | u8 b0[] = { reg }; |
362 | u8 b1[] = { 0, 0 }; | |
8b4f1d03 | 363 | |
b431c616 | 364 | struct i2c_msg msg[] = { |
8b4f1d03 ST |
365 | { .addr = addr, .flags = 0, .buf = b0, .len = 1 }, |
366 | { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 2 } }; | |
367 | ||
368 | ret = i2c_transfer(state->i2c, msg, 2); | |
369 | ||
370 | if (ret != 2) | |
371 | printk(KERN_ERR "%s: readreg error (ret == %i)\n", | |
372 | __func__, ret); | |
373 | return (b1[0] << 8) | b1[1]; | |
374 | } | |
375 | ||
376 | static int s5h1411_softreset(struct dvb_frontend *fe) | |
377 | { | |
378 | struct s5h1411_state *state = fe->demodulator_priv; | |
379 | ||
380 | dprintk("%s()\n", __func__); | |
381 | ||
382 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 0); | |
383 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf7, 1); | |
384 | return 0; | |
385 | } | |
386 | ||
387 | static int s5h1411_set_if_freq(struct dvb_frontend *fe, int KHz) | |
388 | { | |
389 | struct s5h1411_state *state = fe->demodulator_priv; | |
390 | ||
391 | dprintk("%s(%d KHz)\n", __func__, KHz); | |
392 | ||
393 | switch (KHz) { | |
394 | case 3250: | |
c96de519 | 395 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x10d5); |
8b4f1d03 ST |
396 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x5342); |
397 | s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x10d9); | |
398 | break; | |
399 | case 3500: | |
400 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1225); | |
401 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x1e96); | |
402 | s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1225); | |
403 | break; | |
404 | case 4000: | |
405 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x14bc); | |
406 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0xb53e); | |
407 | s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x14bd); | |
408 | break; | |
409 | default: | |
410 | dprintk("%s(%d KHz) Invalid, defaulting to 5380\n", | |
411 | __func__, KHz); | |
412 | /* no break, need to continue */ | |
413 | case 5380: | |
414 | case 44000: | |
415 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x38, 0x1be4); | |
416 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x39, 0x3655); | |
417 | s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x2c, 0x1be4); | |
418 | break; | |
419 | } | |
420 | ||
421 | state->if_freq = KHz; | |
422 | ||
423 | return 0; | |
424 | } | |
425 | ||
426 | static int s5h1411_set_mpeg_timing(struct dvb_frontend *fe, int mode) | |
427 | { | |
428 | struct s5h1411_state *state = fe->demodulator_priv; | |
429 | u16 val; | |
430 | ||
431 | dprintk("%s(%d)\n", __func__, mode); | |
432 | ||
433 | val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbe) & 0xcfff; | |
434 | switch (mode) { | |
435 | case S5H1411_MPEGTIMING_CONTINOUS_INVERTING_CLOCK: | |
436 | val |= 0x0000; | |
437 | break; | |
438 | case S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK: | |
439 | dprintk("%s(%d) Mode1 or Defaulting\n", __func__, mode); | |
440 | val |= 0x1000; | |
441 | break; | |
442 | case S5H1411_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK: | |
443 | val |= 0x2000; | |
444 | break; | |
445 | case S5H1411_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK: | |
446 | val |= 0x3000; | |
447 | break; | |
448 | default: | |
449 | return -EINVAL; | |
450 | } | |
451 | ||
452 | /* Configure MPEG Signal Timing charactistics */ | |
453 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbe, val); | |
454 | } | |
455 | ||
456 | static int s5h1411_set_spectralinversion(struct dvb_frontend *fe, int inversion) | |
457 | { | |
458 | struct s5h1411_state *state = fe->demodulator_priv; | |
459 | u16 val; | |
460 | ||
461 | dprintk("%s(%d)\n", __func__, inversion); | |
462 | val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x24) & ~0x1000; | |
463 | ||
464 | if (inversion == 1) | |
465 | val |= 0x1000; /* Inverted */ | |
8b4f1d03 ST |
466 | |
467 | state->inversion = inversion; | |
468 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x24, val); | |
469 | } | |
470 | ||
1af46b45 ST |
471 | static int s5h1411_set_serialmode(struct dvb_frontend *fe, int serial) |
472 | { | |
473 | struct s5h1411_state *state = fe->demodulator_priv; | |
474 | u16 val; | |
475 | ||
476 | dprintk("%s(%d)\n", __func__, serial); | |
477 | val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xbd) & ~0x100; | |
478 | ||
479 | if (serial == 1) | |
480 | val |= 0x100; | |
481 | ||
482 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xbd, val); | |
483 | } | |
484 | ||
8b4f1d03 ST |
485 | static int s5h1411_enable_modulation(struct dvb_frontend *fe, |
486 | fe_modulation_t m) | |
487 | { | |
488 | struct s5h1411_state *state = fe->demodulator_priv; | |
489 | ||
490 | dprintk("%s(0x%08x)\n", __func__, m); | |
491 | ||
492 | switch (m) { | |
493 | case VSB_8: | |
494 | dprintk("%s() VSB_8\n", __func__); | |
495 | s5h1411_set_if_freq(fe, state->config->vsb_if); | |
496 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x71); | |
497 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x00); | |
498 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0xf1); | |
499 | break; | |
500 | case QAM_64: | |
501 | case QAM_256: | |
5ca947a9 | 502 | case QAM_AUTO: |
8b4f1d03 ST |
503 | dprintk("%s() QAM_AUTO (64/256)\n", __func__); |
504 | s5h1411_set_if_freq(fe, state->config->qam_if); | |
505 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0x00, 0x0171); | |
506 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf6, 0x0001); | |
507 | s5h1411_writereg(state, S5H1411_I2C_QAM_ADDR, 0x16, 0x1101); | |
508 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xcd, 0x00f0); | |
509 | break; | |
510 | default: | |
511 | dprintk("%s() Invalid modulation\n", __func__); | |
512 | return -EINVAL; | |
513 | } | |
514 | ||
515 | state->current_modulation = m; | |
516 | s5h1411_softreset(fe); | |
517 | ||
518 | return 0; | |
519 | } | |
520 | ||
521 | static int s5h1411_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) | |
522 | { | |
523 | struct s5h1411_state *state = fe->demodulator_priv; | |
524 | ||
525 | dprintk("%s(%d)\n", __func__, enable); | |
526 | ||
527 | if (enable) | |
528 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); | |
529 | else | |
530 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 0); | |
531 | } | |
532 | ||
533 | static int s5h1411_set_gpio(struct dvb_frontend *fe, int enable) | |
534 | { | |
535 | struct s5h1411_state *state = fe->demodulator_priv; | |
536 | u16 val; | |
537 | ||
538 | dprintk("%s(%d)\n", __func__, enable); | |
539 | ||
540 | val = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xe0) & ~0x02; | |
541 | ||
542 | if (enable) | |
543 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, | |
544 | val | 0x02); | |
545 | else | |
546 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xe0, val); | |
547 | } | |
548 | ||
549 | static int s5h1411_sleep(struct dvb_frontend *fe, int enable) | |
550 | { | |
551 | struct s5h1411_state *state = fe->demodulator_priv; | |
552 | ||
553 | dprintk("%s(%d)\n", __func__, enable); | |
554 | ||
555 | if (enable) | |
556 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 1); | |
557 | else { | |
558 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf4, 0); | |
559 | s5h1411_softreset(fe); | |
560 | } | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | static int s5h1411_register_reset(struct dvb_frontend *fe) | |
566 | { | |
567 | struct s5h1411_state *state = fe->demodulator_priv; | |
568 | ||
569 | dprintk("%s()\n", __func__); | |
570 | ||
571 | return s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf3, 0); | |
572 | } | |
573 | ||
574 | /* Talk to the demod, set the FEC, GUARD, QAM settings etc */ | |
575 | static int s5h1411_set_frontend(struct dvb_frontend *fe, | |
576 | struct dvb_frontend_parameters *p) | |
577 | { | |
578 | struct s5h1411_state *state = fe->demodulator_priv; | |
579 | ||
580 | dprintk("%s(frequency=%d)\n", __func__, p->frequency); | |
581 | ||
582 | s5h1411_softreset(fe); | |
583 | ||
584 | state->current_frequency = p->frequency; | |
585 | ||
586 | s5h1411_enable_modulation(fe, p->u.vsb.modulation); | |
587 | ||
588 | /* Allow the demod to settle */ | |
589 | msleep(100); | |
590 | ||
591 | if (fe->ops.tuner_ops.set_params) { | |
592 | if (fe->ops.i2c_gate_ctrl) | |
593 | fe->ops.i2c_gate_ctrl(fe, 1); | |
594 | ||
595 | fe->ops.tuner_ops.set_params(fe, p); | |
596 | ||
597 | if (fe->ops.i2c_gate_ctrl) | |
598 | fe->ops.i2c_gate_ctrl(fe, 0); | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | /* Reset the demod hardware and reset all of the configuration registers | |
605 | to a default state. */ | |
606 | static int s5h1411_init(struct dvb_frontend *fe) | |
607 | { | |
608 | struct s5h1411_state *state = fe->demodulator_priv; | |
609 | int i; | |
610 | ||
611 | dprintk("%s()\n", __func__); | |
612 | ||
613 | s5h1411_sleep(fe, 0); | |
614 | s5h1411_register_reset(fe); | |
615 | ||
616 | for (i = 0; i < ARRAY_SIZE(init_tab); i++) | |
617 | s5h1411_writereg(state, init_tab[i].addr, | |
618 | init_tab[i].reg, | |
619 | init_tab[i].data); | |
620 | ||
621 | /* The datasheet says that after initialisation, VSB is default */ | |
622 | state->current_modulation = VSB_8; | |
623 | ||
624 | if (state->config->output_mode == S5H1411_SERIAL_OUTPUT) | |
625 | /* Serial */ | |
1af46b45 | 626 | s5h1411_set_serialmode(fe, 1); |
8b4f1d03 ST |
627 | else |
628 | /* Parallel */ | |
1af46b45 | 629 | s5h1411_set_serialmode(fe, 0); |
8b4f1d03 ST |
630 | |
631 | s5h1411_set_spectralinversion(fe, state->config->inversion); | |
632 | s5h1411_set_if_freq(fe, state->config->vsb_if); | |
633 | s5h1411_set_gpio(fe, state->config->gpio); | |
634 | s5h1411_set_mpeg_timing(fe, state->config->mpeg_timing); | |
635 | s5h1411_softreset(fe); | |
636 | ||
637 | /* Note: Leaving the I2C gate closed. */ | |
638 | s5h1411_i2c_gate_ctrl(fe, 0); | |
639 | ||
640 | return 0; | |
641 | } | |
642 | ||
643 | static int s5h1411_read_status(struct dvb_frontend *fe, fe_status_t *status) | |
644 | { | |
645 | struct s5h1411_state *state = fe->demodulator_priv; | |
646 | u16 reg; | |
647 | u32 tuner_status = 0; | |
648 | ||
649 | *status = 0; | |
650 | ||
e16c63de | 651 | /* Register F2 bit 15 = Master Lock, removed */ |
8b4f1d03 ST |
652 | |
653 | switch (state->current_modulation) { | |
654 | case QAM_64: | |
655 | case QAM_256: | |
656 | reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf0); | |
e16c63de ST |
657 | if (reg & 0x10) /* QAM FEC Lock */ |
658 | *status |= FE_HAS_SYNC | FE_HAS_LOCK; | |
659 | if (reg & 0x100) /* QAM EQ Lock */ | |
660 | *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL; | |
661 | ||
8b4f1d03 ST |
662 | break; |
663 | case VSB_8: | |
8b4f1d03 | 664 | reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf2); |
e16c63de ST |
665 | if (reg & 0x1000) /* FEC Lock */ |
666 | *status |= FE_HAS_SYNC | FE_HAS_LOCK; | |
667 | if (reg & 0x2000) /* EQ Lock */ | |
668 | *status |= FE_HAS_VITERBI | FE_HAS_CARRIER | FE_HAS_SIGNAL; | |
669 | ||
670 | reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x53); | |
671 | if (reg & 0x1) /* AFC Lock */ | |
672 | *status |= FE_HAS_SIGNAL; | |
673 | ||
8b4f1d03 ST |
674 | break; |
675 | default: | |
676 | return -EINVAL; | |
677 | } | |
678 | ||
679 | switch (state->config->status_mode) { | |
680 | case S5H1411_DEMODLOCKING: | |
681 | if (*status & FE_HAS_VITERBI) | |
682 | *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; | |
683 | break; | |
684 | case S5H1411_TUNERLOCKING: | |
685 | /* Get the tuner status */ | |
686 | if (fe->ops.tuner_ops.get_status) { | |
687 | if (fe->ops.i2c_gate_ctrl) | |
688 | fe->ops.i2c_gate_ctrl(fe, 1); | |
689 | ||
690 | fe->ops.tuner_ops.get_status(fe, &tuner_status); | |
691 | ||
692 | if (fe->ops.i2c_gate_ctrl) | |
693 | fe->ops.i2c_gate_ctrl(fe, 0); | |
694 | } | |
695 | if (tuner_status) | |
696 | *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL; | |
697 | break; | |
698 | } | |
699 | ||
700 | dprintk("%s() status 0x%08x\n", __func__, *status); | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
705 | static int s5h1411_qam256_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v) | |
706 | { | |
707 | int i, ret = -EINVAL; | |
708 | dprintk("%s()\n", __func__); | |
709 | ||
710 | for (i = 0; i < ARRAY_SIZE(qam256_snr_tab); i++) { | |
711 | if (v < qam256_snr_tab[i].val) { | |
712 | *snr = qam256_snr_tab[i].data; | |
713 | ret = 0; | |
714 | break; | |
715 | } | |
716 | } | |
717 | return ret; | |
718 | } | |
719 | ||
720 | static int s5h1411_qam64_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v) | |
721 | { | |
722 | int i, ret = -EINVAL; | |
723 | dprintk("%s()\n", __func__); | |
724 | ||
725 | for (i = 0; i < ARRAY_SIZE(qam64_snr_tab); i++) { | |
726 | if (v < qam64_snr_tab[i].val) { | |
727 | *snr = qam64_snr_tab[i].data; | |
728 | ret = 0; | |
729 | break; | |
730 | } | |
731 | } | |
732 | return ret; | |
733 | } | |
734 | ||
735 | static int s5h1411_vsb_lookup_snr(struct dvb_frontend *fe, u16 *snr, u16 v) | |
736 | { | |
737 | int i, ret = -EINVAL; | |
738 | dprintk("%s()\n", __func__); | |
739 | ||
740 | for (i = 0; i < ARRAY_SIZE(vsb_snr_tab); i++) { | |
741 | if (v > vsb_snr_tab[i].val) { | |
742 | *snr = vsb_snr_tab[i].data; | |
743 | ret = 0; | |
744 | break; | |
745 | } | |
746 | } | |
747 | dprintk("%s() snr=%d\n", __func__, *snr); | |
748 | return ret; | |
749 | } | |
750 | ||
751 | static int s5h1411_read_snr(struct dvb_frontend *fe, u16 *snr) | |
752 | { | |
753 | struct s5h1411_state *state = fe->demodulator_priv; | |
754 | u16 reg; | |
755 | dprintk("%s()\n", __func__); | |
756 | ||
757 | switch (state->current_modulation) { | |
758 | case QAM_64: | |
759 | reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); | |
760 | return s5h1411_qam64_lookup_snr(fe, snr, reg); | |
761 | case QAM_256: | |
762 | reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xf1); | |
763 | return s5h1411_qam256_lookup_snr(fe, snr, reg); | |
764 | case VSB_8: | |
765 | reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, | |
766 | 0xf2) & 0x3ff; | |
767 | return s5h1411_vsb_lookup_snr(fe, snr, reg); | |
768 | default: | |
769 | break; | |
770 | } | |
771 | ||
772 | return -EINVAL; | |
773 | } | |
774 | ||
775 | static int s5h1411_read_signal_strength(struct dvb_frontend *fe, | |
776 | u16 *signal_strength) | |
777 | { | |
778 | return s5h1411_read_snr(fe, signal_strength); | |
779 | } | |
780 | ||
781 | static int s5h1411_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |
782 | { | |
783 | struct s5h1411_state *state = fe->demodulator_priv; | |
784 | ||
785 | *ucblocks = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0xc9); | |
786 | ||
787 | return 0; | |
788 | } | |
789 | ||
790 | static int s5h1411_read_ber(struct dvb_frontend *fe, u32 *ber) | |
791 | { | |
792 | return s5h1411_read_ucblocks(fe, ber); | |
793 | } | |
794 | ||
795 | static int s5h1411_get_frontend(struct dvb_frontend *fe, | |
796 | struct dvb_frontend_parameters *p) | |
797 | { | |
798 | struct s5h1411_state *state = fe->demodulator_priv; | |
799 | ||
800 | p->frequency = state->current_frequency; | |
801 | p->u.vsb.modulation = state->current_modulation; | |
802 | ||
803 | return 0; | |
804 | } | |
805 | ||
806 | static int s5h1411_get_tune_settings(struct dvb_frontend *fe, | |
807 | struct dvb_frontend_tune_settings *tune) | |
808 | { | |
809 | tune->min_delay_ms = 1000; | |
810 | return 0; | |
811 | } | |
812 | ||
813 | static void s5h1411_release(struct dvb_frontend *fe) | |
814 | { | |
815 | struct s5h1411_state *state = fe->demodulator_priv; | |
816 | kfree(state); | |
817 | } | |
818 | ||
819 | static struct dvb_frontend_ops s5h1411_ops; | |
820 | ||
821 | struct dvb_frontend *s5h1411_attach(const struct s5h1411_config *config, | |
822 | struct i2c_adapter *i2c) | |
823 | { | |
824 | struct s5h1411_state *state = NULL; | |
825 | u16 reg; | |
826 | ||
827 | /* allocate memory for the internal state */ | |
828 | state = kmalloc(sizeof(struct s5h1411_state), GFP_KERNEL); | |
829 | if (state == NULL) | |
830 | goto error; | |
831 | ||
832 | /* setup the state */ | |
833 | state->config = config; | |
834 | state->i2c = i2c; | |
835 | state->current_modulation = VSB_8; | |
836 | state->inversion = state->config->inversion; | |
837 | ||
838 | /* check if the demod exists */ | |
839 | reg = s5h1411_readreg(state, S5H1411_I2C_TOP_ADDR, 0x05); | |
840 | if (reg != 0x0066) | |
841 | goto error; | |
842 | ||
843 | /* create dvb_frontend */ | |
844 | memcpy(&state->frontend.ops, &s5h1411_ops, | |
845 | sizeof(struct dvb_frontend_ops)); | |
846 | ||
847 | state->frontend.demodulator_priv = state; | |
848 | ||
849 | if (s5h1411_init(&state->frontend) != 0) { | |
850 | printk(KERN_ERR "%s: Failed to initialize correctly\n", | |
851 | __func__); | |
852 | goto error; | |
853 | } | |
854 | ||
855 | /* Note: Leaving the I2C gate open here. */ | |
856 | s5h1411_writereg(state, S5H1411_I2C_TOP_ADDR, 0xf5, 1); | |
857 | ||
858 | return &state->frontend; | |
859 | ||
860 | error: | |
861 | kfree(state); | |
862 | return NULL; | |
863 | } | |
864 | EXPORT_SYMBOL(s5h1411_attach); | |
865 | ||
866 | static struct dvb_frontend_ops s5h1411_ops = { | |
867 | ||
868 | .info = { | |
869 | .name = "Samsung S5H1411 QAM/8VSB Frontend", | |
870 | .type = FE_ATSC, | |
871 | .frequency_min = 54000000, | |
872 | .frequency_max = 858000000, | |
873 | .frequency_stepsize = 62500, | |
874 | .caps = FE_CAN_QAM_64 | FE_CAN_QAM_256 | FE_CAN_8VSB | |
875 | }, | |
876 | ||
877 | .init = s5h1411_init, | |
878 | .i2c_gate_ctrl = s5h1411_i2c_gate_ctrl, | |
879 | .set_frontend = s5h1411_set_frontend, | |
880 | .get_frontend = s5h1411_get_frontend, | |
881 | .get_tune_settings = s5h1411_get_tune_settings, | |
882 | .read_status = s5h1411_read_status, | |
883 | .read_ber = s5h1411_read_ber, | |
884 | .read_signal_strength = s5h1411_read_signal_strength, | |
885 | .read_snr = s5h1411_read_snr, | |
886 | .read_ucblocks = s5h1411_read_ucblocks, | |
887 | .release = s5h1411_release, | |
888 | }; | |
889 | ||
890 | module_param(debug, int, 0644); | |
891 | MODULE_PARM_DESC(debug, "Enable verbose debug messages"); | |
892 | ||
893 | MODULE_DESCRIPTION("Samsung S5H1411 QAM-B/ATSC Demodulator driver"); | |
894 | MODULE_AUTHOR("Steven Toth"); | |
895 | MODULE_LICENSE("GPL"); | |
896 | ||
897 | /* | |
898 | * Local variables: | |
899 | * c-basic-offset: 8 | |
900 | */ |