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[PATCH] Remove duplicate code in signal.c
[mirror_ubuntu-artful-kernel.git] / drivers / media / dvb / frontends / s5h1420.c
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96bf2f2b
AQ		 1/*
2Driver for Samsung S5H1420 QPSK Demodulator
3
4Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
5
6This program is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 2 of the License, or
9(at your option) any later version.
10
11This program is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this program; if not, write to the Free Software
19Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20
21*/
22
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/string.h>
27#include <linux/slab.h>
28#include <linux/delay.h>
29
30#include "dvb_frontend.h"
31#include "s5h1420.h"
32
33
34
35#define TONE_FREQ 22000
36
37struct s5h1420_state {
38 struct i2c_adapter* i2c;
39 struct dvb_frontend_ops ops;
40 const struct s5h1420_config* config;
41 struct dvb_frontend frontend;
42
43 u8 postlocked:1;
44 u32 fclk;
45 u32 tunedfreq;
46 fe_code_rate_t fec_inner;
47 u32 symbol_rate;
48};
49
50static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
a9d6a80b
AQ		 51static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
52 struct dvb_frontend_tune_settings* fesettings);
96bf2f2b
AQ		 53
54
55static int debug = 0;
56#define dprintk if (debug) printk
57
58static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
59{
60 u8 buf [] = { reg, data };
61 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
62 int err;
63
64 if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
65 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __FUNCTION__, err, reg, data);
66 return -EREMOTEIO;
67 }
68
69 return 0;
70}
71
72static u8 s5h1420_readreg (struct s5h1420_state* state, u8 reg)
73{
74 int ret;
75 u8 b0 [] = { reg };
76 u8 b1 [] = { 0 };
77 struct i2c_msg msg1 = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 };
78 struct i2c_msg msg2 = { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 };
79
80 if ((ret = i2c_transfer (state->i2c, &msg1, 1)) != 1)
81 return ret;
82
83 if ((ret = i2c_transfer (state->i2c, &msg2, 1)) != 1)
84 return ret;
85
86 return b1[0];
87}
88
89static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
90{
91 struct s5h1420_state* state = fe->demodulator_priv;
92
93 switch(voltage) {
94 case SEC_VOLTAGE_13:
a9d6a80b
AQ		 95 s5h1420_writereg(state, 0x3c,
96 (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
96bf2f2b
AQ		 97 break;
98
99 case SEC_VOLTAGE_18:
100 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
101 break;
102
103 case SEC_VOLTAGE_OFF:
104 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
105 break;
106 }
107
108 return 0;
109}
110
111static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
112{
113 struct s5h1420_state* state = fe->demodulator_priv;
114
115 switch(tone) {
116 case SEC_TONE_ON:
a9d6a80b
AQ		 117 s5h1420_writereg(state, 0x3b,
118 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
96bf2f2b
AQ		 119 break;
120
121 case SEC_TONE_OFF:
a9d6a80b
AQ		 122 s5h1420_writereg(state, 0x3b,
123 (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
96bf2f2b
AQ		 124 break;
125 }
126
127 return 0;
128}
129
a9d6a80b
AQ		 130static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
131 struct dvb_diseqc_master_cmd* cmd)
96bf2f2b
AQ		 132{
133 struct s5h1420_state* state = fe->demodulator_priv;
134 u8 val;
135 int i;
136 unsigned long timeout;
137 int result = 0;
138
a9d6a80b
AQ		 139 if (cmd->msg_len > 8)
140 return -EINVAL;
141
96bf2f2b
AQ		 142 /* setup for DISEQC */
143 val = s5h1420_readreg(state, 0x3b);
144 s5h1420_writereg(state, 0x3b, 0x02);
145 msleep(15);
146
147 /* write the DISEQC command bytes */
148 for(i=0; i< cmd->msg_len; i++) {
a9d6a80b 149 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
96bf2f2b
AQ		 150 }
151
152 /* kick off transmission */
a9d6a80b
AQ		 153 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
154 ((cmd->msg_len-1) << 4) | 0x08);
96bf2f2b
AQ		 155
156 /* wait for transmission to complete */
157 timeout = jiffies + ((100*HZ) / 1000);
158 while(time_before(jiffies, timeout)) {
a9d6a80b 159 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
96bf2f2b
AQ		 160 break;
161
162 msleep(5);
163 }
164 if (time_after(jiffies, timeout))
165 result = -ETIMEDOUT;
166
167 /* restore original settings */
168 s5h1420_writereg(state, 0x3b, val);
169 msleep(15);
170 return result;
171}
172
a9d6a80b
AQ		 173static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
174 struct dvb_diseqc_slave_reply* reply)
96bf2f2b
AQ		 175{
176 struct s5h1420_state* state = fe->demodulator_priv;
177 u8 val;
178 int i;
179 int length;
180 unsigned long timeout;
181 int result = 0;
182
183 /* setup for DISEQC recieve */
184 val = s5h1420_readreg(state, 0x3b);
185 s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
186 msleep(15);
187
188 /* wait for reception to complete */
189 timeout = jiffies + ((reply->timeout*HZ) / 1000);
190 while(time_before(jiffies, timeout)) {
191 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
192 break;
193
194 msleep(5);
195 }
196 if (time_after(jiffies, timeout)) {
197 result = -ETIMEDOUT;
198 goto exit;
199 }
200
201 /* check error flag - FIXME: not sure what this does - docs do not describe
202 * beyond "error flag for diseqc receive data :( */
203 if (s5h1420_readreg(state, 0x49)) {
204 result = -EIO;
205 goto exit;
206 }
207
208 /* check length */
209 length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
210 if (length > sizeof(reply->msg)) {
211 result = -EOVERFLOW;
212 goto exit;
213 }
214 reply->msg_len = length;
215
216 /* extract data */
217 for(i=0; i< length; i++) {
a9d6a80b 218 reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
96bf2f2b
AQ		 219 }
220
221exit:
222 /* restore original settings */
223 s5h1420_writereg(state, 0x3b, val);
224 msleep(15);
225 return result;
226}
227
228static int s5h1420_send_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd)
229{
230 struct s5h1420_state* state = fe->demodulator_priv;
231 u8 val;
232 int result = 0;
233 unsigned long timeout;
234
235 /* setup for tone burst */
236 val = s5h1420_readreg(state, 0x3b);
237 s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
238
239 /* set value for B position if requested */
240 if (minicmd == SEC_MINI_B) {
241 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
242 }
243 msleep(15);
244
245 /* start transmission */
246 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
247
248 /* wait for transmission to complete */
a9d6a80b 249 timeout = jiffies + ((100*HZ) / 1000);
96bf2f2b
AQ		 250 while(time_before(jiffies, timeout)) {
251 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
252 break;
253
254 msleep(5);
255 }
256 if (time_after(jiffies, timeout))
257 result = -ETIMEDOUT;
258
259 /* restore original settings */
260 s5h1420_writereg(state, 0x3b, val);
261 msleep(15);
262 return result;
263}
264
265static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state)
266{
267 u8 val;
268 fe_status_t status = 0;
269
270 val = s5h1420_readreg(state, 0x14);
271 if (val & 0x02)
a9d6a80b 272 status |= FE_HAS_SIGNAL;
96bf2f2b 273 if (val & 0x01)
a9d6a80b 274 status |= FE_HAS_CARRIER;
96bf2f2b
AQ		 275 val = s5h1420_readreg(state, 0x36);
276 if (val & 0x01)
277 status |= FE_HAS_VITERBI;
278 if (val & 0x20)
279 status |= FE_HAS_SYNC;
280 if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
281 status |= FE_HAS_LOCK;
282
283 return status;
284}
285
286static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
287{
288 struct s5h1420_state* state = fe->demodulator_priv;
289 u8 val;
290
291 if (status == NULL)
292 return -EINVAL;
293
294 /* determine lock state */
295 *status = s5h1420_get_status_bits(state);
296
a9d6a80b
AQ		 297 /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
298 the inversion, wait a bit and check again */
96bf2f2b
AQ		 299 if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {
300 val = s5h1420_readreg(state, 0x32);
301 if ((val & 0x07) == 0x03) {
302 if (val & 0x08)
303 s5h1420_writereg(state, 0x31, 0x13);
304 else
305 s5h1420_writereg(state, 0x31, 0x1b);
306
307 /* wait a bit then update lock status */
308 mdelay(200);
309 *status = s5h1420_get_status_bits(state);
310 }
311 }
312
313 /* perform post lock setup */
314 if ((*status & FE_HAS_LOCK) && (!state->postlocked)) {
315
316 /* calculate the data rate */
317 u32 tmp = s5h1420_getsymbolrate(state);
318 switch(s5h1420_readreg(state, 0x32) & 0x07) {
319 case 0:
320 tmp = (tmp * 2 * 1) / 2;
321 break;
322
323 case 1:
324 tmp = (tmp * 2 * 2) / 3;
325 break;
326
327 case 2:
328 tmp = (tmp * 2 * 3) / 4;
329 break;
330
331 case 3:
332 tmp = (tmp * 2 * 5) / 6;
333 break;
334
335 case 4:
336 tmp = (tmp * 2 * 6) / 7;
337 break;
338
339 case 5:
340 tmp = (tmp * 2 * 7) / 8;
341 break;
342 }
a9d6a80b
AQ		 343 if (tmp == 0) {
344 printk("s5h1420: avoided division by 0\n");
345 tmp = 1;
346 }
96bf2f2b
AQ		 347 tmp = state->fclk / tmp;
348
349 /* set the MPEG_CLK_INTL for the calculated data rate */
350 if (tmp < 4)
351 val = 0x00;
352 else if (tmp < 8)
353 val = 0x01;
354 else if (tmp < 12)
355 val = 0x02;
356 else if (tmp < 16)
357 val = 0x03;
358 else if (tmp < 24)
359 val = 0x04;
360 else if (tmp < 32)
361 val = 0x05;
362 else
363 val = 0x06;
364 s5h1420_writereg(state, 0x22, val);
365
366 /* DC freeze */
367 s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01);
368
369 /* kicker disable + remove DC offset */
370 s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f);
371
372 /* post-lock processing has been done! */
373 state->postlocked = 1;
374 }
375
376 return 0;
377}
378
379static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
380{
381 struct s5h1420_state* state = fe->demodulator_priv;
382
383 s5h1420_writereg(state, 0x46, 0x1d);
384 mdelay(25);
a9d6a80b
AQ		 385
386 *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
387
388 return 0;
96bf2f2b
AQ		 389}
390
391static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
392{
393 struct s5h1420_state* state = fe->demodulator_priv;
394
a9d6a80b 395 u8 val = s5h1420_readreg(state, 0x15);
96bf2f2b 396
a9d6a80b
AQ		 397 *strength = (u16) ((val << 8) | val);
398
399 return 0;
96bf2f2b
AQ		 400}
401
402static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
403{
404 struct s5h1420_state* state = fe->demodulator_priv;
405
406 s5h1420_writereg(state, 0x46, 0x1f);
407 mdelay(25);
a9d6a80b
AQ		 408
409 *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
410
411 return 0;
96bf2f2b
AQ		 412}
413
414static void s5h1420_reset(struct s5h1420_state* state)
415{
416 s5h1420_writereg (state, 0x01, 0x08);
417 s5h1420_writereg (state, 0x01, 0x00);
418 udelay(10);
419}
420
a9d6a80b
AQ		 421static void s5h1420_setsymbolrate(struct s5h1420_state* state,
422 struct dvb_frontend_parameters *p)
96bf2f2b
AQ		 423{
424 u64 val;
425
a9d6a80b 426 val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
96bf2f2b
AQ		 427 if (p->u.qpsk.symbol_rate <= 21000000) {
428 val *= 2;
429 }
430 do_div(val, (state->fclk / 1000));
431
432 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0x7f);
433 s5h1420_writereg(state, 0x11, val >> 16);
434 s5h1420_writereg(state, 0x12, val >> 8);
435 s5h1420_writereg(state, 0x13, val & 0xff);
436 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x80);
437}
438
439static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
440{
a9d6a80b 441 u64 val = 0;
96bf2f2b
AQ		 442 int sampling = 2;
443
444 if (s5h1420_readreg(state, 0x05) & 0x2)
445 sampling = 1;
446
447 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
448 val = s5h1420_readreg(state, 0x11) << 16;
449 val |= s5h1420_readreg(state, 0x12) << 8;
450 val |= s5h1420_readreg(state, 0x13);
451 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
452
a9d6a80b 453 val *= (state->fclk / 1000ULL);
96bf2f2b
AQ		 454 do_div(val, ((1<<24) * sampling));
455
a9d6a80b 456 return (u32) (val * 1000ULL);
96bf2f2b
AQ		 457}
458
459static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
460{
461 int val;
462
463 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
464 * divide fclk by 1000000 to get the correct value. */
465 val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
466
467 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0xbf);
468 s5h1420_writereg(state, 0x0e, val >> 16);
469 s5h1420_writereg(state, 0x0f, val >> 8);
470 s5h1420_writereg(state, 0x10, val & 0xff);
471 s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x40);
472}
473
474static int s5h1420_getfreqoffset(struct s5h1420_state* state)
475{
476 int val;
477
478 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
479 val = s5h1420_readreg(state, 0x0e) << 16;
480 val |= s5h1420_readreg(state, 0x0f) << 8;
481 val |= s5h1420_readreg(state, 0x10);
482 s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
483
484 if (val & 0x800000)
485 val |= 0xff000000;
486
487 /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
488 * divide fclk by 1000000 to get the correct value. */
a9d6a80b 489 val = (((-val) * (state->fclk/1000000)) / (1<<24));
96bf2f2b
AQ		 490
491 return val;
492}
493
a9d6a80b
AQ		 494static void s5h1420_setfec_inversion(struct s5h1420_state* state,
495 struct dvb_frontend_parameters *p)
96bf2f2b 496{
a9d6a80b
AQ		 497 u8 inversion = 0;
498
499 if (p->inversion == INVERSION_OFF) {
500 inversion = state->config->invert ? 0x08 : 0;
501 } else if (p->inversion == INVERSION_ON) {
502 inversion = state->config->invert ? 0 : 0x08;
503 }
504
96bf2f2b 505 if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
96bf2f2b 506 s5h1420_writereg(state, 0x30, 0x3f);
a9d6a80b 507 s5h1420_writereg(state, 0x31, 0x00 | inversion);
96bf2f2b
AQ		 508 } else {
509 switch(p->u.qpsk.fec_inner) {
510 case FEC_1_2:
96bf2f2b 511 s5h1420_writereg(state, 0x30, 0x01);
a9d6a80b 512 s5h1420_writereg(state, 0x31, 0x10 | inversion);
96bf2f2b
AQ		 513 break;
514
515 case FEC_2_3:
96bf2f2b 516 s5h1420_writereg(state, 0x30, 0x02);
a9d6a80b 517 s5h1420_writereg(state, 0x31, 0x11 | inversion);
96bf2f2b
AQ		 518 break;
519
520 case FEC_3_4:
96bf2f2b 521 s5h1420_writereg(state, 0x30, 0x04);
a9d6a80b
AQ		 522 s5h1420_writereg(state, 0x31, 0x12 | inversion);
523 break;
96bf2f2b
AQ		 524
525 case FEC_5_6:
96bf2f2b 526 s5h1420_writereg(state, 0x30, 0x08);
a9d6a80b 527 s5h1420_writereg(state, 0x31, 0x13 | inversion);
96bf2f2b
AQ		 528 break;
529
530 case FEC_6_7:
96bf2f2b 531 s5h1420_writereg(state, 0x30, 0x10);
a9d6a80b 532 s5h1420_writereg(state, 0x31, 0x14 | inversion);
96bf2f2b
AQ		 533 break;
534
535 case FEC_7_8:
96bf2f2b 536 s5h1420_writereg(state, 0x30, 0x20);
a9d6a80b 537 s5h1420_writereg(state, 0x31, 0x15 | inversion);
96bf2f2b
AQ		 538 break;
539
540 default:
541 return;
542 }
543 }
544}
545
546static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
547{
548 switch(s5h1420_readreg(state, 0x32) & 0x07) {
549 case 0:
550 return FEC_1_2;
551
552 case 1:
553 return FEC_2_3;
554
555 case 2:
556 return FEC_3_4;
557
558 case 3:
559 return FEC_5_6;
560
561 case 4:
562 return FEC_6_7;
563
564 case 5:
565 return FEC_7_8;
566 }
567
568 return FEC_NONE;
569}
570
96bf2f2b
AQ		 571static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
572{
573 if (s5h1420_readreg(state, 0x32) & 0x08)
574 return INVERSION_ON;
575
576 return INVERSION_OFF;
577}
578
a9d6a80b
AQ		 579static int s5h1420_set_frontend(struct dvb_frontend* fe,
580 struct dvb_frontend_parameters *p)
96bf2f2b
AQ		 581{
582 struct s5h1420_state* state = fe->demodulator_priv;
a9d6a80b 583 int frequency_delta;
96bf2f2b 584 struct dvb_frontend_tune_settings fesettings;
a9d6a80b 585 u32 tmp;
96bf2f2b
AQ		 586
587 /* check if we should do a fast-tune */
588 memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
589 s5h1420_get_tune_settings(fe, &fesettings);
590 frequency_delta = p->frequency - state->tunedfreq;
a9d6a80b
AQ		 591 if ((frequency_delta > -fesettings.max_drift) &&
592 (frequency_delta < fesettings.max_drift) &&
96bf2f2b
AQ		 593 (frequency_delta != 0) &&
594 (state->fec_inner == p->u.qpsk.fec_inner) &&
595 (state->symbol_rate == p->u.qpsk.symbol_rate)) {
596
a9d6a80b
AQ		 597 if (state->config->pll_set) {
598 s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
599 state->config->pll_set(fe, p, &tmp);
600 s5h1420_setfreqoffset(state, p->frequency - tmp);
601 }
96bf2f2b
AQ		 602 return 0;
603 }
604
605 /* first of all, software reset */
606 s5h1420_reset(state);
607
96bf2f2b
AQ		 608 /* set s5h1420 fclk PLL according to desired symbol rate */
609 if (p->u.qpsk.symbol_rate > 28000000) {
610 state->fclk = 88000000;
611 s5h1420_writereg(state, 0x03, 0x50);
612 s5h1420_writereg(state, 0x04, 0x40);
613 s5h1420_writereg(state, 0x05, 0xae);
614 } else if (p->u.qpsk.symbol_rate > 21000000) {
615 state->fclk = 59000000;
616 s5h1420_writereg(state, 0x03, 0x33);
617 s5h1420_writereg(state, 0x04, 0x40);
618 s5h1420_writereg(state, 0x05, 0xae);
619 } else {
620 state->fclk = 88000000;
621 s5h1420_writereg(state, 0x03, 0x50);
622 s5h1420_writereg(state, 0x04, 0x40);
623 s5h1420_writereg(state, 0x05, 0xac);
624 }
625
626 /* set misc registers */
627 s5h1420_writereg(state, 0x02, 0x00);
a9d6a80b 628 s5h1420_writereg(state, 0x06, 0x00);
96bf2f2b 629 s5h1420_writereg(state, 0x07, 0xb0);
a9d6a80b 630 s5h1420_writereg(state, 0x0a, 0xe7);
96bf2f2b
AQ		 631 s5h1420_writereg(state, 0x0b, 0x78);
632 s5h1420_writereg(state, 0x0c, 0x48);
633 s5h1420_writereg(state, 0x0d, 0x6b);
634 s5h1420_writereg(state, 0x2e, 0x8e);
635 s5h1420_writereg(state, 0x35, 0x33);
636 s5h1420_writereg(state, 0x38, 0x01);
637 s5h1420_writereg(state, 0x39, 0x7d);
638 s5h1420_writereg(state, 0x3a, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
639 s5h1420_writereg(state, 0x3c, 0x00);
640 s5h1420_writereg(state, 0x45, 0x61);
641 s5h1420_writereg(state, 0x46, 0x1d);
642
643 /* start QPSK */
644 s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
645
a9d6a80b
AQ		 646 /* set tuner PLL */
647 if (state->config->pll_set) {
648 s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
649 state->config->pll_set(fe, p, &tmp);
650 s5h1420_setfreqoffset(state, 0);
651 }
96bf2f2b
AQ		 652
653 /* set the reset of the parameters */
654 s5h1420_setsymbolrate(state, p);
a9d6a80b 655 s5h1420_setfec_inversion(state, p);
96bf2f2b
AQ		 656
657 state->fec_inner = p->u.qpsk.fec_inner;
658 state->symbol_rate = p->u.qpsk.symbol_rate;
659 state->postlocked = 0;
a9d6a80b 660 state->tunedfreq = p->frequency;
96bf2f2b
AQ		 661 return 0;
662}
663
a9d6a80b
AQ		 664static int s5h1420_get_frontend(struct dvb_frontend* fe,
665 struct dvb_frontend_parameters *p)
96bf2f2b
AQ		 666{
667 struct s5h1420_state* state = fe->demodulator_priv;
668
669 p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
670 p->inversion = s5h1420_getinversion(state);
671 p->u.qpsk.symbol_rate = s5h1420_getsymbolrate(state);
672 p->u.qpsk.fec_inner = s5h1420_getfec(state);
673
674 return 0;
675}
676
a9d6a80b
AQ		 677static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
678 struct dvb_frontend_tune_settings* fesettings)
96bf2f2b
AQ		 679{
680 if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) {
681 fesettings->min_delay_ms = 50;
682 fesettings->step_size = 2000;
683 fesettings->max_drift = 8000;
684 } else if (fesettings->parameters.u.qpsk.symbol_rate > 12000000) {
685 fesettings->min_delay_ms = 100;
686 fesettings->step_size = 1500;
687 fesettings->max_drift = 9000;
688 } else if (fesettings->parameters.u.qpsk.symbol_rate > 8000000) {
689 fesettings->min_delay_ms = 100;
690 fesettings->step_size = 1000;
691 fesettings->max_drift = 8000;
692 } else if (fesettings->parameters.u.qpsk.symbol_rate > 4000000) {
693 fesettings->min_delay_ms = 100;
694 fesettings->step_size = 500;
695 fesettings->max_drift = 7000;
696 } else if (fesettings->parameters.u.qpsk.symbol_rate > 2000000) {
697 fesettings->min_delay_ms = 200;
698 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
699 fesettings->max_drift = 14 * fesettings->step_size;
700 } else {
701 fesettings->min_delay_ms = 200;
702 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
703 fesettings->max_drift = 18 * fesettings->step_size;
704 }
705
706 return 0;
707}
708
709static int s5h1420_init (struct dvb_frontend* fe)
710{
711 struct s5h1420_state* state = fe->demodulator_priv;
712
713 /* disable power down and do reset */
714 s5h1420_writereg(state, 0x02, 0x10);
715 msleep(10);
716 s5h1420_reset(state);
717
718 /* init PLL */
719 if (state->config->pll_init) {
720 s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
721 state->config->pll_init(fe);
722 s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
723 }
724
725 return 0;
726}
727
728static int s5h1420_sleep(struct dvb_frontend* fe)
729{
730 struct s5h1420_state* state = fe->demodulator_priv;
731
732 return s5h1420_writereg(state, 0x02, 0x12);
733}
734
735static void s5h1420_release(struct dvb_frontend* fe)
736{
737 struct s5h1420_state* state = fe->demodulator_priv;
738 kfree(state);
739}
740
741static struct dvb_frontend_ops s5h1420_ops;
742
a9d6a80b
AQ		 743struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
744 struct i2c_adapter* i2c)
96bf2f2b
AQ		 745{
746 struct s5h1420_state* state = NULL;
747 u8 identity;
748
749 /* allocate memory for the internal state */
750 state = kmalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
751 if (state == NULL)
752 goto error;
753
754 /* setup the state */
755 state->config = config;
756 state->i2c = i2c;
757 memcpy(&state->ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
758 state->postlocked = 0;
759 state->fclk = 88000000;
760 state->tunedfreq = 0;
761 state->fec_inner = FEC_NONE;
762 state->symbol_rate = 0;
763
764 /* check if the demod is there + identify it */
765 identity = s5h1420_readreg(state, 0x00);
766 if (identity != 0x03)
767 goto error;
768
769 /* create dvb_frontend */
770 state->frontend.ops = &state->ops;
771 state->frontend.demodulator_priv = state;
772 return &state->frontend;
773
774error:
775 kfree(state);
776 return NULL;
777}
778
779static struct dvb_frontend_ops s5h1420_ops = {
780
781 .info = {
782 .name = "Samsung S5H1420 DVB-S",
783 .type = FE_QPSK,
784 .frequency_min = 950000,
785 .frequency_max = 2150000,
786 .frequency_stepsize = 125, /* kHz for QPSK frontends */
787 .frequency_tolerance = 29500,
788 .symbol_rate_min = 1000000,
789 .symbol_rate_max = 45000000,
790 /* .symbol_rate_tolerance = ???,*/
791 .caps = FE_CAN_INVERSION_AUTO |
792 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
793 FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
794 FE_CAN_QPSK
795 },
796
797 .release = s5h1420_release,
798
799 .init = s5h1420_init,
800 .sleep = s5h1420_sleep,
801
802 .set_frontend = s5h1420_set_frontend,
803 .get_frontend = s5h1420_get_frontend,
804 .get_tune_settings = s5h1420_get_tune_settings,
805
806 .read_status = s5h1420_read_status,
807 .read_ber = s5h1420_read_ber,
808 .read_signal_strength = s5h1420_read_signal_strength,
809 .read_ucblocks = s5h1420_read_ucblocks,
810
811 .diseqc_send_master_cmd = s5h1420_send_master_cmd,
812 .diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
813 .diseqc_send_burst = s5h1420_send_burst,
814 .set_tone = s5h1420_set_tone,
815 .set_voltage = s5h1420_set_voltage,
816};
817
818module_param(debug, int, 0644);
819
820MODULE_DESCRIPTION("Samsung S5H1420 DVB-S Demodulator driver");
821MODULE_AUTHOR("Andrew de Quincey");
822MODULE_LICENSE("GPL");
823
824EXPORT_SYMBOL(s5h1420_attach);
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